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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
f3705136 | 26 | #include <linux/cpu.h> |
e9e2cdb4 | 27 | #include <linux/clockchips.h> |
d36b49b9 | 28 | #include <linux/acpi_pmtmr.h> |
6eb0a0fd | 29 | #include <linux/module.h> |
ad62ca2b | 30 | #include <linux/dmi.h> |
1da177e4 LT |
31 | |
32 | #include <asm/atomic.h> | |
33 | #include <asm/smp.h> | |
34 | #include <asm/mtrr.h> | |
35 | #include <asm/mpspec.h> | |
36 | #include <asm/desc.h> | |
37 | #include <asm/arch_hooks.h> | |
38 | #include <asm/hpet.h> | |
306e440d | 39 | #include <asm/i8253.h> |
3e4ff115 | 40 | #include <asm/nmi.h> |
1da177e4 LT |
41 | |
42 | #include <mach_apic.h> | |
382dbd07 | 43 | #include <mach_apicdef.h> |
6eb0a0fd | 44 | #include <mach_ipi.h> |
1da177e4 | 45 | |
e05d723f TG |
46 | /* |
47 | * Sanity check | |
48 | */ | |
ff8a03a6 | 49 | #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F) |
e05d723f TG |
50 | # error SPURIOUS_APIC_VECTOR definition error |
51 | #endif | |
52 | ||
8f6e2ca9 AS |
53 | unsigned long mp_lapic_addr; |
54 | ||
9635b47d EB |
55 | /* |
56 | * Knob to control our willingness to enable the local APIC. | |
e05d723f | 57 | * |
914bebfa | 58 | * +1=force-enable |
9635b47d | 59 | */ |
914bebfa YL |
60 | static int force_enable_local_apic; |
61 | int disable_apic; | |
9635b47d | 62 | |
aa276e1c | 63 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ |
36fef094 | 64 | static int disable_apic_timer __cpuinitdata; |
e585bef8 TG |
65 | /* Local APIC timer works in C2 */ |
66 | int local_apic_timer_c2_ok; | |
67 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
e9e2cdb4 | 68 | |
ce178331 AM |
69 | int first_system_vector = 0xfe; |
70 | ||
71 | char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE}; | |
72 | ||
1da177e4 | 73 | /* |
e05d723f | 74 | * Debug level, exported for io_apic.c |
1da177e4 | 75 | */ |
baa13188 | 76 | unsigned int apic_verbosity; |
1da177e4 | 77 | |
f3918352 AS |
78 | int pic_mode; |
79 | ||
bab4b27c AS |
80 | /* Have we found an MP table */ |
81 | int smp_found_config; | |
82 | ||
746f2eb7 CG |
83 | static struct resource lapic_resource = { |
84 | .name = "Local APIC", | |
85 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
86 | }; | |
87 | ||
e9e2cdb4 | 88 | static unsigned int calibration_result; |
1da177e4 | 89 | |
e9e2cdb4 TG |
90 | static int lapic_next_event(unsigned long delta, |
91 | struct clock_event_device *evt); | |
92 | static void lapic_timer_setup(enum clock_event_mode mode, | |
93 | struct clock_event_device *evt); | |
94 | static void lapic_timer_broadcast(cpumask_t mask); | |
95 | static void apic_pm_activate(void); | |
e05d723f | 96 | |
e9e2cdb4 TG |
97 | /* |
98 | * The local apic timer can be used for any function which is CPU local. | |
99 | */ | |
100 | static struct clock_event_device lapic_clockevent = { | |
101 | .name = "lapic", | |
102 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
d36b49b9 | 103 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, |
e9e2cdb4 TG |
104 | .shift = 32, |
105 | .set_mode = lapic_timer_setup, | |
106 | .set_next_event = lapic_next_event, | |
107 | .broadcast = lapic_timer_broadcast, | |
108 | .rating = 100, | |
109 | .irq = -1, | |
110 | }; | |
111 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
e05d723f TG |
112 | |
113 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ | |
114 | static int enabled_via_apicbase; | |
115 | ||
d3432896 | 116 | static unsigned long apic_phys; |
b6c80513 CG |
117 | unsigned int __cpuinitdata maxcpus = NR_CPUS; |
118 | ||
d3432896 | 119 | |
e05d723f TG |
120 | /* |
121 | * Get the LAPIC version | |
122 | */ | |
123 | static inline int lapic_get_version(void) | |
95d769aa | 124 | { |
e05d723f | 125 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
95d769aa AK |
126 | } |
127 | ||
1da177e4 | 128 | /* |
ab4a574e | 129 | * Check, if the APIC is integrated or a separate chip |
1da177e4 | 130 | */ |
e05d723f | 131 | static inline int lapic_is_integrated(void) |
1da177e4 | 132 | { |
9c803869 CG |
133 | #ifdef CONFIG_X86_64 |
134 | return 1; | |
135 | #else | |
e05d723f | 136 | return APIC_INTEGRATED(lapic_get_version()); |
9c803869 | 137 | #endif |
1da177e4 LT |
138 | } |
139 | ||
e05d723f TG |
140 | /* |
141 | * Check, whether this is a modern or a first generation APIC | |
142 | */ | |
143 | static int modern_apic(void) | |
1da177e4 | 144 | { |
e05d723f TG |
145 | /* AMD systems use old APIC versions, so check the CPU */ |
146 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
147 | boot_cpu_data.x86 >= 0xf) | |
148 | return 1; | |
149 | return lapic_get_version() >= 0x14; | |
1da177e4 LT |
150 | } |
151 | ||
9a8f0e6b SS |
152 | /* |
153 | * Paravirt kernels also might be using these below ops. So we still | |
154 | * use generic apic_read()/apic_write(), which might be pointing to different | |
155 | * ops in PARAVIRT case. | |
156 | */ | |
c535b6a1 | 157 | void xapic_wait_icr_idle(void) |
f2b218dd FLV |
158 | { |
159 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
160 | cpu_relax(); | |
161 | } | |
162 | ||
c535b6a1 | 163 | u32 safe_xapic_wait_icr_idle(void) |
f2b218dd | 164 | { |
42e0a9aa | 165 | u32 send_status; |
f2b218dd FLV |
166 | int timeout; |
167 | ||
168 | timeout = 0; | |
169 | do { | |
170 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
171 | if (!send_status) | |
172 | break; | |
173 | udelay(100); | |
174 | } while (timeout++ < 1000); | |
175 | ||
176 | return send_status; | |
177 | } | |
178 | ||
c535b6a1 YL |
179 | void xapic_icr_write(u32 low, u32 id) |
180 | { | |
f586bf7d SS |
181 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
182 | apic_write(APIC_ICR, low); | |
c535b6a1 YL |
183 | } |
184 | ||
185 | u64 xapic_icr_read(void) | |
186 | { | |
187 | u32 icr1, icr2; | |
188 | ||
189 | icr2 = apic_read(APIC_ICR2); | |
190 | icr1 = apic_read(APIC_ICR); | |
191 | ||
192 | return icr1 | ((u64)icr2 << 32); | |
193 | } | |
194 | ||
195 | static struct apic_ops xapic_ops = { | |
196 | .read = native_apic_mem_read, | |
197 | .write = native_apic_mem_write, | |
c535b6a1 YL |
198 | .icr_read = xapic_icr_read, |
199 | .icr_write = xapic_icr_write, | |
200 | .wait_icr_idle = xapic_wait_icr_idle, | |
201 | .safe_wait_icr_idle = safe_xapic_wait_icr_idle, | |
202 | }; | |
203 | ||
204 | struct apic_ops __read_mostly *apic_ops = &xapic_ops; | |
205 | EXPORT_SYMBOL_GPL(apic_ops); | |
206 | ||
e05d723f TG |
207 | /** |
208 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
209 | */ | |
e9427101 | 210 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 211 | { |
d4c63ec0 | 212 | unsigned int v; |
1da177e4 | 213 | |
d4c63ec0 CG |
214 | /* unmask and set to NMI */ |
215 | v = APIC_DM_NMI; | |
216 | ||
217 | /* Level triggered for 82489DX (32bit mode) */ | |
e05d723f | 218 | if (!lapic_is_integrated()) |
1da177e4 | 219 | v |= APIC_LVT_LEVEL_TRIGGER; |
d4c63ec0 | 220 | |
593f4a78 | 221 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
222 | } |
223 | ||
e05d723f TG |
224 | /** |
225 | * get_physical_broadcast - Get number of physical broadcast IDs | |
226 | */ | |
1da177e4 LT |
227 | int get_physical_broadcast(void) |
228 | { | |
e05d723f | 229 | return modern_apic() ? 0xff : 0xf; |
1da177e4 LT |
230 | } |
231 | ||
e05d723f TG |
232 | /** |
233 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
234 | */ | |
235 | int lapic_get_maxlvt(void) | |
1da177e4 | 236 | { |
36a028de | 237 | unsigned int v; |
1da177e4 | 238 | |
36a028de CG |
239 | v = apic_read(APIC_LVR); |
240 | /* | |
241 | * - we always have APIC integrated on 64bit mode | |
242 | * - 82489DXs do not report # of LVT entries | |
243 | */ | |
e05d723f | 244 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; |
1da177e4 LT |
245 | } |
246 | ||
e05d723f TG |
247 | /* |
248 | * Local APIC timer | |
249 | */ | |
250 | ||
c40aaec6 CG |
251 | /* Clock divisor */ |
252 | #ifdef CONFG_X86_64 | |
253 | #define APIC_DIVISOR 1 | |
254 | #else | |
d36b49b9 | 255 | #define APIC_DIVISOR 16 |
c40aaec6 | 256 | #endif |
e05d723f TG |
257 | |
258 | /* | |
259 | * This function sets up the local APIC timer, with a timeout of | |
260 | * 'clocks' APIC bus clock. During calibration we actually call | |
261 | * this function twice on the boot CPU, once with a bogus timeout | |
262 | * value, second time for real. The other (noncalibrating) CPUs | |
263 | * call this function only once, with the real, calibrated value. | |
274cfe59 CG |
264 | * |
265 | * We do reads before writes even if unnecessary, to get around the | |
266 | * P5 APIC double write bug. | |
e05d723f | 267 | */ |
e9e2cdb4 | 268 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 269 | { |
e05d723f | 270 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 271 | |
e9e2cdb4 TG |
272 | lvtt_value = LOCAL_TIMER_VECTOR; |
273 | if (!oneshot) | |
274 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
e05d723f TG |
275 | if (!lapic_is_integrated()) |
276 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
277 | ||
e9e2cdb4 | 278 | if (!irqen) |
e05d723f TG |
279 | lvtt_value |= APIC_LVT_MASKED; |
280 | ||
593f4a78 | 281 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
282 | |
283 | /* | |
e05d723f | 284 | * Divide PICLK by 16 |
1da177e4 | 285 | */ |
e05d723f | 286 | tmp_value = apic_read(APIC_TDCR); |
593f4a78 | 287 | apic_write(APIC_TDCR, |
c40aaec6 CG |
288 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | |
289 | APIC_TDR_DIV_16); | |
1da177e4 | 290 | |
e9e2cdb4 | 291 | if (!oneshot) |
593f4a78 | 292 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
e9e2cdb4 TG |
293 | } |
294 | ||
274cfe59 CG |
295 | /* |
296 | * Setup extended LVT, AMD specific (K8, family 10h) | |
297 | * | |
298 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
299 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
300 | */ | |
301 | ||
302 | #define APIC_EILVT_LVTOFF_MCE 0 | |
303 | #define APIC_EILVT_LVTOFF_IBS 1 | |
304 | ||
305 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
306 | { | |
307 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; | |
308 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; | |
309 | ||
310 | apic_write(reg, v); | |
311 | } | |
312 | ||
313 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) | |
314 | { | |
315 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
316 | return APIC_EILVT_LVTOFF_MCE; | |
317 | } | |
318 | ||
319 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
320 | { | |
321 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
322 | return APIC_EILVT_LVTOFF_IBS; | |
323 | } | |
324 | ||
e9e2cdb4 TG |
325 | /* |
326 | * Program the next event, relative to now | |
327 | */ | |
328 | static int lapic_next_event(unsigned long delta, | |
329 | struct clock_event_device *evt) | |
330 | { | |
593f4a78 | 331 | apic_write(APIC_TMICT, delta); |
e9e2cdb4 | 332 | return 0; |
1da177e4 LT |
333 | } |
334 | ||
e9e2cdb4 TG |
335 | /* |
336 | * Setup the lapic timer in periodic or oneshot mode | |
337 | */ | |
338 | static void lapic_timer_setup(enum clock_event_mode mode, | |
339 | struct clock_event_device *evt) | |
1da177e4 | 340 | { |
e05d723f | 341 | unsigned long flags; |
e9e2cdb4 | 342 | unsigned int v; |
e05d723f | 343 | |
274cfe59 | 344 | /* Lapic used as dummy for broadcast ? */ |
64e474d1 | 345 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) |
d36b49b9 TG |
346 | return; |
347 | ||
e05d723f | 348 | local_irq_save(flags); |
1da177e4 | 349 | |
e9e2cdb4 TG |
350 | switch (mode) { |
351 | case CLOCK_EVT_MODE_PERIODIC: | |
352 | case CLOCK_EVT_MODE_ONESHOT: | |
353 | __setup_APIC_LVTT(calibration_result, | |
354 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
355 | break; | |
356 | case CLOCK_EVT_MODE_UNUSED: | |
357 | case CLOCK_EVT_MODE_SHUTDOWN: | |
358 | v = apic_read(APIC_LVTT); | |
359 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
593f4a78 | 360 | apic_write(APIC_LVTT, v); |
e9e2cdb4 | 361 | break; |
18de5bc4 TG |
362 | case CLOCK_EVT_MODE_RESUME: |
363 | /* Nothing to do here */ | |
364 | break; | |
e9e2cdb4 | 365 | } |
e05d723f TG |
366 | |
367 | local_irq_restore(flags); | |
368 | } | |
369 | ||
e9e2cdb4 TG |
370 | /* |
371 | * Local APIC timer broadcast function | |
372 | */ | |
373 | static void lapic_timer_broadcast(cpumask_t mask) | |
374 | { | |
375 | #ifdef CONFIG_SMP | |
376 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
377 | #endif | |
378 | } | |
379 | ||
380 | /* | |
381 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
382 | * of the boot CPU and register the clock event in the framework. | |
383 | */ | |
384 | static void __devinit setup_APIC_timer(void) | |
385 | { | |
386 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
387 | ||
388 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); | |
389 | levt->cpumask = cpumask_of_cpu(smp_processor_id()); | |
390 | ||
391 | clockevents_register_device(levt); | |
392 | } | |
393 | ||
e05d723f | 394 | /* |
d36b49b9 TG |
395 | * In this functions we calibrate APIC bus clocks to the external timer. |
396 | * | |
397 | * We want to do the calibration only once since we want to have local timer | |
398 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus | |
399 | * frequency. | |
400 | * | |
401 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
402 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
403 | * readout is broken, so it never gets out of the wait loop again. This was | |
404 | * also reported by others. | |
e05d723f | 405 | * |
d36b49b9 TG |
406 | * Monitoring the jiffies value is inaccurate and the clockevents |
407 | * infrastructure allows us to do a simple substitution of the interrupt | |
408 | * handler. | |
e9e2cdb4 | 409 | * |
d36b49b9 TG |
410 | * The calibration routine also uses the pm_timer when possible, as the PIT |
411 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
412 | * back to normal later in the boot process). | |
e05d723f TG |
413 | */ |
414 | ||
d36b49b9 | 415 | #define LAPIC_CAL_LOOPS (HZ/10) |
e05d723f | 416 | |
f5352fd0 | 417 | static __initdata int lapic_cal_loops = -1; |
d36b49b9 TG |
418 | static __initdata long lapic_cal_t1, lapic_cal_t2; |
419 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
420 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; | |
421 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; | |
1da177e4 | 422 | |
d36b49b9 TG |
423 | /* |
424 | * Temporary interrupt handler. | |
425 | */ | |
426 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
427 | { | |
428 | unsigned long long tsc = 0; | |
429 | long tapic = apic_read(APIC_TMCCT); | |
430 | unsigned long pm = acpi_pm_read_early(); | |
1da177e4 | 431 | |
d36b49b9 TG |
432 | if (cpu_has_tsc) |
433 | rdtscll(tsc); | |
434 | ||
435 | switch (lapic_cal_loops++) { | |
436 | case 0: | |
437 | lapic_cal_t1 = tapic; | |
438 | lapic_cal_tsc1 = tsc; | |
439 | lapic_cal_pm1 = pm; | |
440 | lapic_cal_j1 = jiffies; | |
441 | break; | |
e05d723f | 442 | |
d36b49b9 TG |
443 | case LAPIC_CAL_LOOPS: |
444 | lapic_cal_t2 = tapic; | |
445 | lapic_cal_tsc2 = tsc; | |
446 | if (pm < lapic_cal_pm1) | |
447 | pm += ACPI_PM_OVRRUN; | |
448 | lapic_cal_pm2 = pm; | |
449 | lapic_cal_j2 = jiffies; | |
450 | break; | |
451 | } | |
452 | } | |
1da177e4 | 453 | |
836c129d | 454 | static int __init calibrate_APIC_clock(void) |
d36b49b9 TG |
455 | { |
456 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
457 | const long pm_100ms = PMTMR_TICKS_PER_SEC/10; | |
458 | const long pm_thresh = pm_100ms/100; | |
459 | void (*real_handler)(struct clock_event_device *dev); | |
460 | unsigned long deltaj; | |
461 | long delta, deltapm; | |
ca1b940c | 462 | int pm_referenced = 0; |
1da177e4 | 463 | |
d36b49b9 TG |
464 | local_irq_disable(); |
465 | ||
466 | /* Replace the global interrupt handler */ | |
467 | real_handler = global_clock_event->event_handler; | |
468 | global_clock_event->event_handler = lapic_cal_handler; | |
1da177e4 | 469 | |
1da177e4 | 470 | /* |
d36b49b9 TG |
471 | * Setup the APIC counter to 1e9. There is no way the lapic |
472 | * can underflow in the 100ms detection time frame | |
1da177e4 | 473 | */ |
d36b49b9 | 474 | __setup_APIC_LVTT(1000000000, 0, 0); |
1da177e4 | 475 | |
d36b49b9 TG |
476 | /* Let the interrupts run */ |
477 | local_irq_enable(); | |
478 | ||
ca1b940c TG |
479 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) |
480 | cpu_relax(); | |
d36b49b9 TG |
481 | |
482 | local_irq_disable(); | |
483 | ||
484 | /* Restore the real event handler */ | |
485 | global_clock_event->event_handler = real_handler; | |
486 | ||
487 | /* Build delta t1-t2 as apic timer counts down */ | |
488 | delta = lapic_cal_t1 - lapic_cal_t2; | |
489 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); | |
490 | ||
491 | /* Check, if the PM timer is available */ | |
492 | deltapm = lapic_cal_pm2 - lapic_cal_pm1; | |
493 | apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm); | |
494 | ||
495 | if (deltapm) { | |
496 | unsigned long mult; | |
497 | u64 res; | |
498 | ||
499 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
500 | ||
501 | if (deltapm > (pm_100ms - pm_thresh) && | |
502 | deltapm < (pm_100ms + pm_thresh)) { | |
503 | apic_printk(APIC_VERBOSE, "... PM timer result ok\n"); | |
504 | } else { | |
505 | res = (((u64) deltapm) * mult) >> 22; | |
506 | do_div(res, 1000000); | |
507 | printk(KERN_WARNING "APIC calibration not consistent " | |
508 | "with PM Timer: %ldms instead of 100ms\n", | |
509 | (long)res); | |
510 | /* Correct the lapic counter value */ | |
ff8a03a6 | 511 | res = (((u64) delta) * pm_100ms); |
d36b49b9 TG |
512 | do_div(res, deltapm); |
513 | printk(KERN_INFO "APIC delta adjusted to PM-Timer: " | |
514 | "%lu (%ld)\n", (unsigned long) res, delta); | |
515 | delta = (long) res; | |
516 | } | |
ca1b940c | 517 | pm_referenced = 1; |
d36b49b9 | 518 | } |
e05d723f | 519 | |
e9e2cdb4 | 520 | /* Calculate the scaled math multiplication factor */ |
877084fb AM |
521 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, |
522 | lapic_clockevent.shift); | |
e9e2cdb4 TG |
523 | lapic_clockevent.max_delta_ns = |
524 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
525 | lapic_clockevent.min_delta_ns = | |
526 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
527 | ||
d36b49b9 TG |
528 | calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; |
529 | ||
530 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); | |
e9e2cdb4 | 531 | apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult); |
d36b49b9 TG |
532 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", |
533 | calibration_result); | |
e9e2cdb4 | 534 | |
d36b49b9 TG |
535 | if (cpu_has_tsc) { |
536 | delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); | |
e05d723f | 537 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " |
d36b49b9 TG |
538 | "%ld.%04ld MHz.\n", |
539 | (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ), | |
540 | (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
541 | } | |
e05d723f TG |
542 | |
543 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
d36b49b9 TG |
544 | "%u.%04u MHz.\n", |
545 | calibration_result / (1000000 / HZ), | |
546 | calibration_result % (1000000 / HZ)); | |
e05d723f | 547 | |
c2b84b30 TG |
548 | /* |
549 | * Do a sanity check on the APIC calibration result | |
550 | */ | |
551 | if (calibration_result < (1000000 / HZ)) { | |
552 | local_irq_enable(); | |
553 | printk(KERN_WARNING | |
554 | "APIC frequency too slow, disabling apic timer\n"); | |
836c129d | 555 | return -1; |
c2b84b30 TG |
556 | } |
557 | ||
64e474d1 | 558 | levt->features &= ~CLOCK_EVT_FEAT_DUMMY; |
836c129d | 559 | |
ca1b940c TG |
560 | /* We trust the pm timer based calibration */ |
561 | if (!pm_referenced) { | |
562 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); | |
d36b49b9 | 563 | |
ca1b940c TG |
564 | /* |
565 | * Setup the apic timer manually | |
566 | */ | |
567 | levt->event_handler = lapic_cal_handler; | |
568 | lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); | |
569 | lapic_cal_loops = -1; | |
d36b49b9 | 570 | |
ca1b940c TG |
571 | /* Let the interrupts run */ |
572 | local_irq_enable(); | |
d36b49b9 | 573 | |
f5352fd0 | 574 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) |
ca1b940c | 575 | cpu_relax(); |
d36b49b9 | 576 | |
ca1b940c | 577 | local_irq_disable(); |
d36b49b9 | 578 | |
ca1b940c TG |
579 | /* Stop the lapic timer */ |
580 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); | |
d36b49b9 | 581 | |
ca1b940c | 582 | local_irq_enable(); |
d36b49b9 | 583 | |
ca1b940c TG |
584 | /* Jiffies delta */ |
585 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
586 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | |
d36b49b9 | 587 | |
d36b49b9 | 588 | /* Check, if the jiffies result is consistent */ |
ca1b940c | 589 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) |
d36b49b9 | 590 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); |
ca1b940c | 591 | else |
64e474d1 | 592 | levt->features |= CLOCK_EVT_FEAT_DUMMY; |
4edc5db8 IM |
593 | } else |
594 | local_irq_enable(); | |
e05d723f | 595 | |
64e474d1 | 596 | if (levt->features & CLOCK_EVT_FEAT_DUMMY) { |
d36b49b9 TG |
597 | printk(KERN_WARNING |
598 | "APIC timer disabled due to verification failure.\n"); | |
836c129d CG |
599 | return -1; |
600 | } | |
601 | ||
602 | return 0; | |
603 | } | |
604 | ||
605 | /* | |
606 | * Setup the boot APIC | |
607 | * | |
608 | * Calibrate and verify the result. | |
609 | */ | |
610 | void __init setup_boot_APIC_clock(void) | |
611 | { | |
612 | /* | |
613 | * The local apic timer can be disabled via the kernel | |
614 | * commandline or from the CPU detection code. Register the lapic | |
615 | * timer as a dummy clock event source on SMP systems, so the | |
616 | * broadcast mechanism is used. On UP systems simply ignore it. | |
617 | */ | |
36fef094 | 618 | if (disable_apic_timer) { |
f1ee3789 | 619 | printk(KERN_INFO "Disabling APIC timer\n"); |
d36b49b9 | 620 | /* No broadcast on UP ! */ |
836c129d CG |
621 | if (num_possible_cpus() > 1) { |
622 | lapic_clockevent.mult = 1; | |
623 | setup_APIC_timer(); | |
624 | } | |
625 | return; | |
a5f5e43e | 626 | } |
d36b49b9 | 627 | |
836c129d CG |
628 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
629 | "calibrating APIC timer ...\n"); | |
630 | ||
631 | if (calibrate_APIC_clock()) { | |
632 | /* No broadcast on UP ! */ | |
633 | if (num_possible_cpus() > 1) | |
634 | setup_APIC_timer(); | |
635 | return; | |
636 | } | |
637 | ||
638 | /* | |
639 | * If nmi_watchdog is set to IO_APIC, we need the | |
640 | * PIT/HPET going. Otherwise register lapic as a dummy | |
641 | * device. | |
642 | */ | |
643 | if (nmi_watchdog != NMI_IO_APIC) | |
644 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
645 | else | |
646 | printk(KERN_WARNING "APIC timer registered as dummy," | |
647 | " due to nmi_watchdog=%d!\n", nmi_watchdog); | |
648 | ||
d36b49b9 TG |
649 | /* Setup the lapic or request the broadcast */ |
650 | setup_APIC_timer(); | |
e05d723f | 651 | } |
1da177e4 | 652 | |
e05d723f TG |
653 | void __devinit setup_secondary_APIC_clock(void) |
654 | { | |
e9e2cdb4 | 655 | setup_APIC_timer(); |
e05d723f | 656 | } |
1da177e4 | 657 | |
e05d723f | 658 | /* |
e9e2cdb4 | 659 | * The guts of the apic timer interrupt |
e05d723f | 660 | */ |
e9e2cdb4 | 661 | static void local_apic_timer_interrupt(void) |
e05d723f | 662 | { |
e9e2cdb4 TG |
663 | int cpu = smp_processor_id(); |
664 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
1da177e4 LT |
665 | |
666 | /* | |
d36b49b9 TG |
667 | * Normally we should not be here till LAPIC has been initialized but |
668 | * in some cases like kdump, its possible that there is a pending LAPIC | |
669 | * timer interrupt from previous kernel's context and is delivered in | |
670 | * new kernel the moment interrupts are enabled. | |
e05d723f | 671 | * |
d36b49b9 TG |
672 | * Interrupts are enabled early and LAPIC is setup much later, hence |
673 | * its possible that when we get here evt->event_handler is NULL. | |
674 | * Check for event_handler being NULL and discard the interrupt as | |
675 | * spurious. | |
1da177e4 | 676 | */ |
e9e2cdb4 TG |
677 | if (!evt->event_handler) { |
678 | printk(KERN_WARNING | |
679 | "Spurious LAPIC timer interrupt on cpu %d\n", cpu); | |
680 | /* Switch it off */ | |
681 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
682 | return; | |
683 | } | |
684 | ||
0e078e2f TG |
685 | /* |
686 | * the NMI deadlock-detector uses this. | |
687 | */ | |
0b23e8cf CG |
688 | #ifdef CONFIG_X86_64 |
689 | add_pda(apic_timer_irqs, 1); | |
690 | #else | |
e9e2cdb4 | 691 | per_cpu(irq_stat, cpu).apic_timer_irqs++; |
0b23e8cf | 692 | #endif |
e9e2cdb4 TG |
693 | |
694 | evt->event_handler(evt); | |
e05d723f TG |
695 | } |
696 | ||
697 | /* | |
698 | * Local APIC timer interrupt. This is the most natural way for doing | |
699 | * local interrupts, but local timer interrupts can be emulated by | |
700 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
701 | * | |
702 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
703 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
704 | */ | |
75604d7f | 705 | void smp_apic_timer_interrupt(struct pt_regs *regs) |
e05d723f TG |
706 | { |
707 | struct pt_regs *old_regs = set_irq_regs(regs); | |
1da177e4 LT |
708 | |
709 | /* | |
e05d723f TG |
710 | * NOTE! We'd better ACK the irq immediately, |
711 | * because timer handling can be slow. | |
1da177e4 | 712 | */ |
e05d723f | 713 | ack_APIC_irq(); |
1a75a3f0 | 714 | /* |
e05d723f TG |
715 | * update_process_times() expects us to have done irq_enter(). |
716 | * Besides, if we don't timer interrupts ignore the global | |
717 | * interrupt lock, which is the WrongThing (tm) to do. | |
1a75a3f0 | 718 | */ |
e05d723f | 719 | irq_enter(); |
e9e2cdb4 | 720 | local_apic_timer_interrupt(); |
e05d723f | 721 | irq_exit(); |
1a75a3f0 | 722 | |
e9e2cdb4 | 723 | set_irq_regs(old_regs); |
e05d723f TG |
724 | } |
725 | ||
726 | int setup_profiling_timer(unsigned int multiplier) | |
727 | { | |
728 | return -EINVAL; | |
729 | } | |
730 | ||
731 | /* | |
732 | * Local APIC start and shutdown | |
733 | */ | |
734 | ||
735 | /** | |
736 | * clear_local_APIC - shutdown the local APIC | |
737 | * | |
738 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
739 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
740 | * leftovers during boot. | |
741 | */ | |
742 | void clear_local_APIC(void) | |
743 | { | |
d3432896 | 744 | int maxlvt; |
0e078e2f | 745 | u32 v; |
1da177e4 | 746 | |
d3432896 AK |
747 | /* APIC hasn't been mapped yet */ |
748 | if (!apic_phys) | |
749 | return; | |
750 | ||
751 | maxlvt = lapic_get_maxlvt(); | |
1da177e4 | 752 | /* |
e05d723f TG |
753 | * Masking an LVT entry can trigger a local APIC error |
754 | * if the vector is zero. Mask LVTERR first to prevent this. | |
1da177e4 | 755 | */ |
e05d723f TG |
756 | if (maxlvt >= 3) { |
757 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
593f4a78 | 758 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); |
e05d723f | 759 | } |
1da177e4 | 760 | /* |
e05d723f TG |
761 | * Careful: we have to set masks only first to deassert |
762 | * any level-triggered sources. | |
1da177e4 | 763 | */ |
e05d723f | 764 | v = apic_read(APIC_LVTT); |
593f4a78 | 765 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); |
e05d723f | 766 | v = apic_read(APIC_LVT0); |
593f4a78 | 767 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
e05d723f | 768 | v = apic_read(APIC_LVT1); |
593f4a78 | 769 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); |
e05d723f TG |
770 | if (maxlvt >= 4) { |
771 | v = apic_read(APIC_LVTPC); | |
593f4a78 | 772 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); |
1da177e4 | 773 | } |
1da177e4 | 774 | |
e05d723f | 775 | /* lets not touch this if we didn't frob it */ |
6764014b | 776 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL) |
e05d723f TG |
777 | if (maxlvt >= 5) { |
778 | v = apic_read(APIC_LVTTHMR); | |
593f4a78 | 779 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); |
e05d723f TG |
780 | } |
781 | #endif | |
1da177e4 | 782 | /* |
e05d723f | 783 | * Clean APIC state for other OSs: |
1da177e4 | 784 | */ |
593f4a78 MR |
785 | apic_write(APIC_LVTT, APIC_LVT_MASKED); |
786 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
787 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
e05d723f | 788 | if (maxlvt >= 3) |
593f4a78 | 789 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); |
e05d723f | 790 | if (maxlvt >= 4) |
593f4a78 | 791 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); |
1da177e4 | 792 | |
e05d723f TG |
793 | /* Integrated APIC (!82489DX) ? */ |
794 | if (lapic_is_integrated()) { | |
1da177e4 | 795 | if (maxlvt > 3) |
e05d723f | 796 | /* Clear ESR due to Pentium errata 3AP and 11AP */ |
1da177e4 | 797 | apic_write(APIC_ESR, 0); |
e05d723f | 798 | apic_read(APIC_ESR); |
1da177e4 | 799 | } |
e05d723f | 800 | } |
1da177e4 | 801 | |
e05d723f TG |
802 | /** |
803 | * disable_local_APIC - clear and disable the local APIC | |
804 | */ | |
805 | void disable_local_APIC(void) | |
806 | { | |
990b183e | 807 | unsigned int value; |
e05d723f TG |
808 | |
809 | clear_local_APIC(); | |
810 | ||
811 | /* | |
812 | * Disable APIC (implies clearing of registers | |
813 | * for 82489DX!). | |
814 | */ | |
815 | value = apic_read(APIC_SPIV); | |
816 | value &= ~APIC_SPIV_APIC_ENABLED; | |
593f4a78 | 817 | apic_write(APIC_SPIV, value); |
e05d723f | 818 | |
990b183e | 819 | #ifdef CONFIG_X86_32 |
e05d723f TG |
820 | /* |
821 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
822 | * restore the disabled state. | |
823 | */ | |
824 | if (enabled_via_apicbase) { | |
825 | unsigned int l, h; | |
826 | ||
827 | rdmsr(MSR_IA32_APICBASE, l, h); | |
828 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
829 | wrmsr(MSR_IA32_APICBASE, l, h); | |
830 | } | |
990b183e | 831 | #endif |
1da177e4 LT |
832 | } |
833 | ||
834 | /* | |
e05d723f TG |
835 | * If Linux enabled the LAPIC against the BIOS default disable it down before |
836 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
837 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
77f72b19 | 838 | * for the case where Linux didn't enable the LAPIC. |
1da177e4 LT |
839 | */ |
840 | void lapic_shutdown(void) | |
841 | { | |
67963132 MS |
842 | unsigned long flags; |
843 | ||
77f72b19 | 844 | if (!cpu_has_apic) |
1da177e4 LT |
845 | return; |
846 | ||
67963132 | 847 | local_irq_save(flags); |
77f72b19 | 848 | |
fe4024dc CG |
849 | #ifdef CONFIG_X86_32 |
850 | if (!enabled_via_apicbase) | |
9ce122c6 | 851 | clear_local_APIC(); |
fe4024dc CG |
852 | else |
853 | #endif | |
854 | disable_local_APIC(); | |
855 | ||
77f72b19 | 856 | |
67963132 | 857 | local_irq_restore(flags); |
1da177e4 LT |
858 | } |
859 | ||
e05d723f TG |
860 | /* |
861 | * This is to verify that we're looking at a real local APIC. | |
862 | * Check these against your board if the CPUs aren't getting | |
863 | * started for no apparent reason. | |
864 | */ | |
865 | int __init verify_local_APIC(void) | |
1da177e4 | 866 | { |
e05d723f | 867 | unsigned int reg0, reg1; |
1da177e4 | 868 | |
e05d723f TG |
869 | /* |
870 | * The version register is read-only in a real APIC. | |
871 | */ | |
872 | reg0 = apic_read(APIC_LVR); | |
873 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
874 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
875 | reg1 = apic_read(APIC_LVR); | |
876 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
877 | ||
878 | /* | |
879 | * The two version reads above should print the same | |
880 | * numbers. If the second one is different, then we | |
881 | * poke at a non-APIC. | |
882 | */ | |
883 | if (reg1 != reg0) | |
1da177e4 LT |
884 | return 0; |
885 | ||
e05d723f TG |
886 | /* |
887 | * Check if the version looks reasonably. | |
888 | */ | |
889 | reg1 = GET_APIC_VERSION(reg0); | |
890 | if (reg1 == 0x00 || reg1 == 0xff) | |
891 | return 0; | |
892 | reg1 = lapic_get_maxlvt(); | |
893 | if (reg1 < 0x02 || reg1 == 0xff) | |
894 | return 0; | |
f990fff4 | 895 | |
e05d723f TG |
896 | /* |
897 | * The ID register is read/write in a real APIC. | |
898 | */ | |
899 | reg0 = apic_read(APIC_ID); | |
900 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); | |
c93baa1a CG |
901 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); |
902 | reg1 = apic_read(APIC_ID); | |
903 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); | |
904 | apic_write(APIC_ID, reg0); | |
905 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
906 | return 0; | |
e05d723f TG |
907 | |
908 | /* | |
909 | * The next two are just to see if we have sane values. | |
910 | * They're only really relevant if we're in Virtual Wire | |
911 | * compatibility mode, but most boxes are anymore. | |
912 | */ | |
913 | reg0 = apic_read(APIC_LVT0); | |
914 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); | |
915 | reg1 = apic_read(APIC_LVT1); | |
916 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
917 | ||
918 | return 1; | |
1da177e4 LT |
919 | } |
920 | ||
e05d723f TG |
921 | /** |
922 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
923 | */ | |
924 | void __init sync_Arb_IDs(void) | |
1da177e4 | 925 | { |
e05d723f TG |
926 | /* |
927 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
928 | * needed on AMD. | |
929 | */ | |
f44d9efd | 930 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
e05d723f | 931 | return; |
6f6da97f | 932 | |
e05d723f TG |
933 | /* |
934 | * Wait for idle. | |
935 | */ | |
936 | apic_wait_icr_idle(); | |
1da177e4 | 937 | |
e05d723f | 938 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); |
6f6da97f CG |
939 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
940 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
e05d723f | 941 | } |
1da177e4 | 942 | |
e05d723f TG |
943 | /* |
944 | * An initial setup of the virtual wire mode. | |
945 | */ | |
946 | void __init init_bsp_APIC(void) | |
947 | { | |
638c0411 | 948 | unsigned int value; |
f990fff4 | 949 | |
e05d723f TG |
950 | /* |
951 | * Don't do the setup now if we have a SMP BIOS as the | |
952 | * through-I/O-APIC virtual wire mode might be active. | |
953 | */ | |
954 | if (smp_found_config || !cpu_has_apic) | |
955 | return; | |
1da177e4 LT |
956 | |
957 | /* | |
e05d723f | 958 | * Do not trust the local APIC being empty at bootup. |
1da177e4 | 959 | */ |
e05d723f | 960 | clear_local_APIC(); |
1da177e4 | 961 | |
e05d723f TG |
962 | /* |
963 | * Enable APIC. | |
964 | */ | |
965 | value = apic_read(APIC_SPIV); | |
966 | value &= ~APIC_VECTOR_MASK; | |
967 | value |= APIC_SPIV_APIC_ENABLED; | |
968 | ||
638c0411 | 969 | #ifdef CONFIG_X86_32 |
e05d723f TG |
970 | /* This bit is reserved on P4/Xeon and should be cleared */ |
971 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
972 | (boot_cpu_data.x86 == 15)) | |
973 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
974 | else | |
638c0411 | 975 | #endif |
e05d723f TG |
976 | value |= APIC_SPIV_FOCUS_DISABLED; |
977 | value |= SPURIOUS_APIC_VECTOR; | |
593f4a78 | 978 | apic_write(APIC_SPIV, value); |
e05d723f TG |
979 | |
980 | /* | |
981 | * Set up the virtual wire mode. | |
982 | */ | |
593f4a78 | 983 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
e05d723f TG |
984 | value = APIC_DM_NMI; |
985 | if (!lapic_is_integrated()) /* 82489DX */ | |
986 | value |= APIC_LVT_LEVEL_TRIGGER; | |
593f4a78 | 987 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
988 | } |
989 | ||
a4928cff | 990 | static void __cpuinit lapic_setup_esr(void) |
df7939ae GOC |
991 | { |
992 | unsigned long oldvalue, value, maxlvt; | |
993 | if (lapic_is_integrated() && !esr_disable) { | |
c43da2f5 CG |
994 | if (esr_disable) { |
995 | /* | |
996 | * Something untraceable is creating bad interrupts on | |
997 | * secondary quads ... for the moment, just leave the | |
998 | * ESR disabled - we can't do anything useful with the | |
999 | * errors anyway - mbligh | |
1000 | */ | |
1001 | printk(KERN_INFO "Leaving ESR disabled.\n"); | |
1002 | return; | |
1003 | } | |
df7939ae GOC |
1004 | /* !82489DX */ |
1005 | maxlvt = lapic_get_maxlvt(); | |
1006 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1007 | apic_write(APIC_ESR, 0); | |
1008 | oldvalue = apic_read(APIC_ESR); | |
1009 | ||
1010 | /* enables sending errors */ | |
1011 | value = ERROR_APIC_VECTOR; | |
593f4a78 | 1012 | apic_write(APIC_LVTERR, value); |
df7939ae GOC |
1013 | /* |
1014 | * spec says clear errors after enabling vector. | |
1015 | */ | |
1016 | if (maxlvt > 3) | |
1017 | apic_write(APIC_ESR, 0); | |
1018 | value = apic_read(APIC_ESR); | |
1019 | if (value != oldvalue) | |
1020 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
1021 | "vector: 0x%08lx after: 0x%08lx\n", | |
1022 | oldvalue, value); | |
1023 | } else { | |
c43da2f5 | 1024 | printk(KERN_INFO "No ESR for 82489DX.\n"); |
df7939ae GOC |
1025 | } |
1026 | } | |
1027 | ||
1028 | ||
e05d723f TG |
1029 | /** |
1030 | * setup_local_APIC - setup the local APIC | |
1da177e4 | 1031 | */ |
d5337983 | 1032 | void __cpuinit setup_local_APIC(void) |
e05d723f | 1033 | { |
df7939ae | 1034 | unsigned long value, integrated; |
e05d723f | 1035 | int i, j; |
1da177e4 | 1036 | |
e05d723f TG |
1037 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ |
1038 | if (esr_disable) { | |
1039 | apic_write(APIC_ESR, 0); | |
1040 | apic_write(APIC_ESR, 0); | |
1041 | apic_write(APIC_ESR, 0); | |
1042 | apic_write(APIC_ESR, 0); | |
1043 | } | |
1da177e4 | 1044 | |
e05d723f | 1045 | integrated = lapic_is_integrated(); |
1da177e4 | 1046 | |
e05d723f TG |
1047 | /* |
1048 | * Double-check whether this APIC is really registered. | |
1049 | */ | |
1050 | if (!apic_id_registered()) | |
22d5c67c | 1051 | WARN_ON_ONCE(1); |
1da177e4 | 1052 | |
e05d723f TG |
1053 | /* |
1054 | * Intel recommends to set DFR, LDR and TPR before enabling | |
1055 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
1056 | * document number 292116). So here it goes... | |
1057 | */ | |
1058 | init_apic_ldr(); | |
1da177e4 | 1059 | |
e05d723f TG |
1060 | /* |
1061 | * Set Task Priority to 'accept all'. We never change this | |
1062 | * later on. | |
1063 | */ | |
1064 | value = apic_read(APIC_TASKPRI); | |
1065 | value &= ~APIC_TPRI_MASK; | |
593f4a78 | 1066 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 1067 | |
e05d723f TG |
1068 | /* |
1069 | * After a crash, we no longer service the interrupts and a pending | |
1070 | * interrupt from previous kernel might still have ISR bit set. | |
1071 | * | |
1072 | * Most probably by now CPU has serviced that pending interrupt and | |
1073 | * it might not have done the ack_APIC_irq() because it thought, | |
1074 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
1075 | * does not clear the ISR bit and cpu thinks it has already serivced | |
1076 | * the interrupt. Hence a vector might get locked. It was noticed | |
1077 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
1078 | */ | |
1079 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
1080 | value = apic_read(APIC_ISR + i*0x10); | |
1081 | for (j = 31; j >= 0; j--) { | |
1082 | if (value & (1<<j)) | |
1083 | ack_APIC_irq(); | |
1084 | } | |
1085 | } | |
1da177e4 | 1086 | |
e05d723f TG |
1087 | /* |
1088 | * Now that we are all set up, enable the APIC | |
1089 | */ | |
1090 | value = apic_read(APIC_SPIV); | |
1091 | value &= ~APIC_VECTOR_MASK; | |
1092 | /* | |
1093 | * Enable APIC | |
1094 | */ | |
1095 | value |= APIC_SPIV_APIC_ENABLED; | |
1da177e4 | 1096 | |
e05d723f TG |
1097 | /* |
1098 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1099 | * certain networking cards. If high frequency interrupts are | |
1100 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1101 | * entry is masked/unmasked at a high rate as well then sooner or | |
1102 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1103 | * from the device. If focus CPU is disabled then the hang goes | |
1104 | * away, oh well :-( | |
1105 | * | |
1106 | * [ This bug can be reproduced easily with a level-triggered | |
1107 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1108 | * BX chipset. ] | |
1109 | */ | |
1110 | /* | |
1111 | * Actually disabling the focus CPU check just makes the hang less | |
1112 | * frequent as it makes the interrupt distributon model be more | |
1113 | * like LRU than MRU (the short-term load is more even across CPUs). | |
1114 | * See also the comment in end_level_ioapic_irq(). --macro | |
1115 | */ | |
1da177e4 | 1116 | |
e05d723f TG |
1117 | /* Enable focus processor (bit==0) */ |
1118 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 1119 | |
e05d723f TG |
1120 | /* |
1121 | * Set spurious IRQ vector | |
1122 | */ | |
1123 | value |= SPURIOUS_APIC_VECTOR; | |
593f4a78 | 1124 | apic_write(APIC_SPIV, value); |
e05d723f TG |
1125 | |
1126 | /* | |
1127 | * Set up LVT0, LVT1: | |
1128 | * | |
1129 | * set up through-local-APIC on the BP's LINT0. This is not | |
27b46d76 | 1130 | * strictly necessary in pure symmetric-IO mode, but sometimes |
e05d723f TG |
1131 | * we delegate interrupts to the 8259A. |
1132 | */ | |
1133 | /* | |
1134 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1135 | */ | |
1136 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
1137 | if (!smp_processor_id() && (pic_mode || !value)) { | |
1138 | value = APIC_DM_EXTINT; | |
1139 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", | |
1140 | smp_processor_id()); | |
1141 | } else { | |
1142 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
1143 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", | |
1144 | smp_processor_id()); | |
1145 | } | |
593f4a78 | 1146 | apic_write(APIC_LVT0, value); |
e05d723f TG |
1147 | |
1148 | /* | |
1149 | * only the BP should see the LINT1 NMI signal, obviously. | |
1150 | */ | |
1151 | if (!smp_processor_id()) | |
1152 | value = APIC_DM_NMI; | |
1153 | else | |
1154 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
1155 | if (!integrated) /* 82489DX */ | |
1156 | value |= APIC_LVT_LEVEL_TRIGGER; | |
593f4a78 | 1157 | apic_write(APIC_LVT1, value); |
ac60aae5 | 1158 | } |
e05d723f | 1159 | |
ac60aae5 GOC |
1160 | void __cpuinit end_local_APIC_setup(void) |
1161 | { | |
ac60aae5 | 1162 | lapic_setup_esr(); |
fa6b95fc CG |
1163 | |
1164 | #ifdef CONFIG_X86_32 | |
1165 | unsigned int value; | |
e9e2cdb4 TG |
1166 | /* Disable the local apic timer */ |
1167 | value = apic_read(APIC_LVTT); | |
1168 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
593f4a78 | 1169 | apic_write(APIC_LVTT, value); |
fa6b95fc | 1170 | #endif |
e9e2cdb4 | 1171 | |
e05d723f TG |
1172 | setup_apic_nmi_watchdog(NULL); |
1173 | apic_pm_activate(); | |
1da177e4 LT |
1174 | } |
1175 | ||
e05d723f TG |
1176 | /* |
1177 | * Detect and initialize APIC | |
1178 | */ | |
e83a5fdc | 1179 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1180 | { |
1181 | u32 h, l, features; | |
1da177e4 LT |
1182 | |
1183 | /* Disabled by kernel option? */ | |
914bebfa | 1184 | if (disable_apic) |
1da177e4 LT |
1185 | return -1; |
1186 | ||
1da177e4 LT |
1187 | switch (boot_cpu_data.x86_vendor) { |
1188 | case X86_VENDOR_AMD: | |
1189 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
e05d723f | 1190 | (boot_cpu_data.x86 == 15)) |
1da177e4 LT |
1191 | break; |
1192 | goto no_apic; | |
1193 | case X86_VENDOR_INTEL: | |
1194 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
1195 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
1196 | break; | |
1197 | goto no_apic; | |
1198 | default: | |
1199 | goto no_apic; | |
1200 | } | |
1201 | ||
1202 | if (!cpu_has_apic) { | |
1203 | /* | |
e05d723f TG |
1204 | * Over-ride BIOS and try to enable the local APIC only if |
1205 | * "lapic" specified. | |
1da177e4 | 1206 | */ |
914bebfa | 1207 | if (!force_enable_local_apic) { |
e05d723f | 1208 | printk(KERN_INFO "Local APIC disabled by BIOS -- " |
1da177e4 LT |
1209 | "you can enable it with \"lapic\"\n"); |
1210 | return -1; | |
1211 | } | |
1212 | /* | |
e05d723f TG |
1213 | * Some BIOSes disable the local APIC in the APIC_BASE |
1214 | * MSR. This can only be done in software for Intel P6 or later | |
1215 | * and AMD K7 (Model > 1) or later. | |
1da177e4 LT |
1216 | */ |
1217 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1218 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
e05d723f TG |
1219 | printk(KERN_INFO |
1220 | "Local APIC disabled by BIOS -- reenabling.\n"); | |
1da177e4 LT |
1221 | l &= ~MSR_IA32_APICBASE_BASE; |
1222 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; | |
1223 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1224 | enabled_via_apicbase = 1; | |
1225 | } | |
1226 | } | |
1227 | /* | |
1228 | * The APIC feature bit should now be enabled | |
1229 | * in `cpuid' | |
1230 | */ | |
1231 | features = cpuid_edx(1); | |
1232 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
e05d723f | 1233 | printk(KERN_WARNING "Could not enable APIC!\n"); |
1da177e4 LT |
1234 | return -1; |
1235 | } | |
53756d37 | 1236 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
1da177e4 LT |
1237 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; |
1238 | ||
1239 | /* The BIOS may have set up the APIC at some other address */ | |
1240 | rdmsr(MSR_IA32_APICBASE, l, h); | |
e05d723f TG |
1241 | if (l & MSR_IA32_APICBASE_ENABLE) |
1242 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
1da177e4 | 1243 | |
e05d723f | 1244 | printk(KERN_INFO "Found and enabled local APIC!\n"); |
1da177e4 | 1245 | |
e05d723f | 1246 | apic_pm_activate(); |
1da177e4 | 1247 | |
e05d723f | 1248 | return 0; |
1da177e4 | 1249 | |
e05d723f TG |
1250 | no_apic: |
1251 | printk(KERN_INFO "No local APIC present or hardware disabled\n"); | |
1252 | return -1; | |
1253 | } | |
1da177e4 | 1254 | |
e05d723f TG |
1255 | /** |
1256 | * init_apic_mappings - initialize APIC mappings | |
1257 | */ | |
1258 | void __init init_apic_mappings(void) | |
1da177e4 | 1259 | { |
1da177e4 | 1260 | /* |
e05d723f TG |
1261 | * If no local APIC can be found then set up a fake all |
1262 | * zeroes page to simulate the local APIC and another | |
1263 | * one for the IO-APIC. | |
1da177e4 | 1264 | */ |
e05d723f TG |
1265 | if (!smp_found_config && detect_init_APIC()) { |
1266 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1267 | apic_phys = __pa(apic_phys); | |
1268 | } else | |
1269 | apic_phys = mp_lapic_addr; | |
1da177e4 | 1270 | |
e05d723f TG |
1271 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); |
1272 | printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE, | |
1273 | apic_phys); | |
1da177e4 | 1274 | |
e05d723f TG |
1275 | /* |
1276 | * Fetch the APIC ID of the BSP in case we have a | |
1277 | * default configuration (or the MP table is broken). | |
1278 | */ | |
1279 | if (boot_cpu_physical_apicid == -1U) | |
4c9961d5 | 1280 | boot_cpu_physical_apicid = read_apic_id(); |
1da177e4 | 1281 | |
1da177e4 LT |
1282 | } |
1283 | ||
e05d723f TG |
1284 | /* |
1285 | * This initializes the IO-APIC and APIC hardware if this is | |
1286 | * a UP kernel. | |
1287 | */ | |
e81b2c62 AS |
1288 | |
1289 | int apic_version[MAX_APICS]; | |
1290 | ||
e83a5fdc | 1291 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1292 | { |
e05d723f TG |
1293 | if (!smp_found_config && !cpu_has_apic) |
1294 | return -1; | |
6eb0a0fd | 1295 | |
e05d723f TG |
1296 | /* |
1297 | * Complain if the BIOS pretends there is one. | |
1298 | */ | |
1299 | if (!cpu_has_apic && | |
1300 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
1301 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1302 | boot_cpu_physical_apicid); | |
53756d37 | 1303 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
e05d723f | 1304 | return -1; |
6eb0a0fd | 1305 | } |
6eb0a0fd | 1306 | |
e05d723f | 1307 | verify_local_APIC(); |
6eb0a0fd | 1308 | |
e05d723f | 1309 | connect_bsp_APIC(); |
6eb0a0fd | 1310 | |
e05d723f TG |
1311 | /* |
1312 | * Hack: In case of kdump, after a crash, kernel might be booting | |
1313 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
1314 | * might be zero if read from MP tables. Get it from LAPIC. | |
1315 | */ | |
1316 | #ifdef CONFIG_CRASH_DUMP | |
4c9961d5 | 1317 | boot_cpu_physical_apicid = read_apic_id(); |
e05d723f | 1318 | #endif |
b6df1b8b | 1319 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
1da177e4 | 1320 | |
e05d723f | 1321 | setup_local_APIC(); |
1da177e4 | 1322 | |
acae7d90 MR |
1323 | #ifdef CONFIG_X86_IO_APIC |
1324 | if (!smp_found_config || skip_ioapic_setup || !nr_ioapics) | |
1325 | #endif | |
1326 | localise_nmi_watchdog(); | |
ac60aae5 | 1327 | end_local_APIC_setup(); |
e05d723f TG |
1328 | #ifdef CONFIG_X86_IO_APIC |
1329 | if (smp_found_config) | |
1330 | if (!skip_ioapic_setup && nr_ioapics) | |
1331 | setup_IO_APIC(); | |
1da177e4 | 1332 | #endif |
e05d723f | 1333 | setup_boot_clock(); |
1da177e4 | 1334 | |
e05d723f | 1335 | return 0; |
1da177e4 LT |
1336 | } |
1337 | ||
e05d723f TG |
1338 | /* |
1339 | * Local APIC interrupts | |
1340 | */ | |
1341 | ||
1da177e4 LT |
1342 | /* |
1343 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1344 | */ | |
e9e2cdb4 | 1345 | void smp_spurious_interrupt(struct pt_regs *regs) |
1da177e4 LT |
1346 | { |
1347 | unsigned long v; | |
1348 | ||
1349 | irq_enter(); | |
1350 | /* | |
1351 | * Check if this really is a spurious interrupt and ACK it | |
1352 | * if it is a vectored one. Just in case... | |
1353 | * Spurious interrupts should not be ACKed. | |
1354 | */ | |
1355 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); | |
1356 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1357 | ack_APIC_irq(); | |
1358 | ||
1359 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ | |
e05d723f TG |
1360 | printk(KERN_INFO "spurious APIC interrupt on CPU#%d, " |
1361 | "should never happen.\n", smp_processor_id()); | |
38e760a1 | 1362 | __get_cpu_var(irq_stat).irq_spurious_count++; |
1da177e4 LT |
1363 | irq_exit(); |
1364 | } | |
1365 | ||
1366 | /* | |
1367 | * This interrupt should never happen with our APIC/SMP architecture | |
1368 | */ | |
e9e2cdb4 | 1369 | void smp_error_interrupt(struct pt_regs *regs) |
1da177e4 LT |
1370 | { |
1371 | unsigned long v, v1; | |
1372 | ||
1373 | irq_enter(); | |
1374 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1375 | v = apic_read(APIC_ESR); | |
1376 | apic_write(APIC_ESR, 0); | |
1377 | v1 = apic_read(APIC_ESR); | |
1378 | ack_APIC_irq(); | |
1379 | atomic_inc(&irq_err_count); | |
1380 | ||
1381 | /* Here is what the APIC error bits mean: | |
1382 | 0: Send CS error | |
1383 | 1: Receive CS error | |
1384 | 2: Send accept error | |
1385 | 3: Receive accept error | |
1386 | 4: Reserved | |
1387 | 5: Send illegal vector | |
1388 | 6: Received illegal vector | |
1389 | 7: Illegal register address | |
1390 | */ | |
ff8a03a6 | 1391 | printk(KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n", |
e05d723f | 1392 | smp_processor_id(), v , v1); |
1da177e4 LT |
1393 | irq_exit(); |
1394 | } | |
1395 | ||
e05d723f TG |
1396 | /** |
1397 | * connect_bsp_APIC - attach the APIC to the interrupt system | |
1398 | */ | |
1399 | void __init connect_bsp_APIC(void) | |
1400 | { | |
36c9d674 | 1401 | #ifdef CONFIG_X86_32 |
e05d723f TG |
1402 | if (pic_mode) { |
1403 | /* | |
1404 | * Do not trust the local APIC being empty at bootup. | |
1405 | */ | |
1406 | clear_local_APIC(); | |
1407 | /* | |
1408 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1409 | * local APIC to INT and NMI lines. | |
1410 | */ | |
1411 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1412 | "enabling APIC mode.\n"); | |
1413 | outb(0x70, 0x22); | |
1414 | outb(0x01, 0x23); | |
1da177e4 | 1415 | } |
36c9d674 | 1416 | #endif |
e05d723f TG |
1417 | enable_apic_mode(); |
1418 | } | |
1da177e4 | 1419 | |
e05d723f TG |
1420 | /** |
1421 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1422 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1423 | * | |
1424 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1425 | * APIC is disabled. | |
1426 | */ | |
1427 | void disconnect_bsp_APIC(int virt_wire_setup) | |
1428 | { | |
c177b0bc | 1429 | #ifdef CONFIG_X86_32 |
e05d723f TG |
1430 | if (pic_mode) { |
1431 | /* | |
1432 | * Put the board back into PIC mode (has an effect only on | |
1433 | * certain older boards). Note that APIC interrupts, including | |
1434 | * IPIs, won't work beyond this point! The only exception are | |
1435 | * INIT IPIs. | |
1436 | */ | |
1437 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1438 | "entering PIC mode.\n"); | |
1439 | outb(0x70, 0x22); | |
1440 | outb(0x00, 0x23); | |
c177b0bc CG |
1441 | return; |
1442 | } | |
1443 | #endif | |
1da177e4 | 1444 | |
c177b0bc CG |
1445 | /* Go back to Virtual Wire compatibility mode */ |
1446 | unsigned int value; | |
1da177e4 | 1447 | |
c177b0bc CG |
1448 | /* For the spurious interrupt use vector F, and enable it */ |
1449 | value = apic_read(APIC_SPIV); | |
1450 | value &= ~APIC_VECTOR_MASK; | |
1451 | value |= APIC_SPIV_APIC_ENABLED; | |
1452 | value |= 0xf; | |
1453 | apic_write(APIC_SPIV, value); | |
1da177e4 | 1454 | |
c177b0bc | 1455 | if (!virt_wire_setup) { |
e05d723f | 1456 | /* |
c177b0bc CG |
1457 | * For LVT0 make it edge triggered, active high, |
1458 | * external and enabled | |
e05d723f | 1459 | */ |
c177b0bc CG |
1460 | value = apic_read(APIC_LVT0); |
1461 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
e05d723f TG |
1462 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | |
1463 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1464 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
c177b0bc CG |
1465 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); |
1466 | apic_write(APIC_LVT0, value); | |
1467 | } else { | |
1468 | /* Disable LVT0 */ | |
1469 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
e05d723f | 1470 | } |
c177b0bc CG |
1471 | |
1472 | /* | |
1473 | * For LVT1 make it edge triggered, active high, | |
1474 | * nmi and enabled | |
1475 | */ | |
1476 | value = apic_read(APIC_LVT1); | |
1477 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1478 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1479 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1480 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1481 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1482 | apic_write(APIC_LVT1, value); | |
e05d723f | 1483 | } |
1da177e4 | 1484 | |
903dcb5a AS |
1485 | void __cpuinit generic_processor_info(int apicid, int version) |
1486 | { | |
1487 | int cpu; | |
1488 | cpumask_t tmp_map; | |
903dcb5a AS |
1489 | |
1490 | /* | |
1491 | * Validate version | |
1492 | */ | |
1493 | if (version == 0x0) { | |
1494 | printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! " | |
1495 | "fixing up to 0x10. (tell your hw vendor)\n", | |
1496 | version); | |
1497 | version = 0x10; | |
1498 | } | |
1499 | apic_version[apicid] = version; | |
1500 | ||
903dcb5a AS |
1501 | if (num_processors >= NR_CPUS) { |
1502 | printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." | |
1503 | " Processor ignored.\n", NR_CPUS); | |
1504 | return; | |
1505 | } | |
1506 | ||
1507 | if (num_processors >= maxcpus) { | |
1508 | printk(KERN_WARNING "WARNING: maxcpus limit of %i reached." | |
1509 | " Processor ignored.\n", maxcpus); | |
1510 | return; | |
1511 | } | |
1512 | ||
1513 | num_processors++; | |
1514 | cpus_complement(tmp_map, cpu_present_map); | |
1515 | cpu = first_cpu(tmp_map); | |
1516 | ||
1b313f4a CG |
1517 | physid_set(apicid, phys_cpu_present_map); |
1518 | if (apicid == boot_cpu_physical_apicid) { | |
903dcb5a AS |
1519 | /* |
1520 | * x86_bios_cpu_apicid is required to have processors listed | |
1521 | * in same order as logical cpu numbers. Hence the first | |
1522 | * entry is BSP, and so on. | |
1523 | */ | |
1524 | cpu = 0; | |
1b313f4a | 1525 | } |
e0da3364 YL |
1526 | if (apicid > max_physical_apicid) |
1527 | max_physical_apicid = apicid; | |
1528 | ||
1b313f4a | 1529 | #ifdef CONFIG_X86_32 |
903dcb5a AS |
1530 | /* |
1531 | * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y | |
1532 | * but we need to work other dependencies like SMP_SUSPEND etc | |
1533 | * before this can be done without some confusion. | |
1534 | * if (CPU_HOTPLUG_ENABLED || num_processors > 8) | |
1535 | * - Ashok Raj <ashok.raj@intel.com> | |
1536 | */ | |
e0da3364 | 1537 | if (max_physical_apicid >= 8) { |
903dcb5a AS |
1538 | switch (boot_cpu_data.x86_vendor) { |
1539 | case X86_VENDOR_INTEL: | |
1540 | if (!APIC_XAPIC(version)) { | |
1541 | def_to_bigsmp = 0; | |
1542 | break; | |
1543 | } | |
1544 | /* If P4 and above fall through */ | |
1545 | case X86_VENDOR_AMD: | |
1546 | def_to_bigsmp = 1; | |
1547 | } | |
1548 | } | |
1b313f4a CG |
1549 | #endif |
1550 | ||
1551 | #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64) | |
903dcb5a | 1552 | /* are we being called early in kernel startup? */ |
23ca4bba MT |
1553 | if (early_per_cpu_ptr(x86_cpu_to_apicid)) { |
1554 | u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid); | |
1555 | u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); | |
903dcb5a AS |
1556 | |
1557 | cpu_to_apicid[cpu] = apicid; | |
1558 | bios_cpu_apicid[cpu] = apicid; | |
1559 | } else { | |
1560 | per_cpu(x86_cpu_to_apicid, cpu) = apicid; | |
1561 | per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1562 | } | |
1563 | #endif | |
1b313f4a | 1564 | |
903dcb5a AS |
1565 | cpu_set(cpu, cpu_possible_map); |
1566 | cpu_set(cpu, cpu_present_map); | |
1567 | } | |
1568 | ||
e05d723f TG |
1569 | /* |
1570 | * Power management | |
1571 | */ | |
1572 | #ifdef CONFIG_PM | |
1573 | ||
1574 | static struct { | |
274cfe59 CG |
1575 | /* |
1576 | * 'active' is true if the local APIC was enabled by us and | |
1577 | * not the BIOS; this signifies that we are also responsible | |
1578 | * for disabling it before entering apm/acpi suspend | |
1579 | */ | |
e05d723f TG |
1580 | int active; |
1581 | /* r/w apic fields */ | |
1582 | unsigned int apic_id; | |
1583 | unsigned int apic_taskpri; | |
1584 | unsigned int apic_ldr; | |
1585 | unsigned int apic_dfr; | |
1586 | unsigned int apic_spiv; | |
1587 | unsigned int apic_lvtt; | |
1588 | unsigned int apic_lvtpc; | |
1589 | unsigned int apic_lvt0; | |
1590 | unsigned int apic_lvt1; | |
1591 | unsigned int apic_lvterr; | |
1592 | unsigned int apic_tmict; | |
1593 | unsigned int apic_tdcr; | |
1594 | unsigned int apic_thmr; | |
1595 | } apic_pm_state; | |
1596 | ||
1597 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1598 | { | |
1599 | unsigned long flags; | |
1600 | int maxlvt; | |
1601 | ||
1602 | if (!apic_pm_state.active) | |
1603 | return 0; | |
1604 | ||
1605 | maxlvt = lapic_get_maxlvt(); | |
1606 | ||
1607 | apic_pm_state.apic_id = apic_read(APIC_ID); | |
1608 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); | |
1609 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1610 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1611 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1612 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1613 | if (maxlvt >= 4) | |
1614 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1615 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1616 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1617 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1618 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1619 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
24968cfd | 1620 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
e05d723f TG |
1621 | if (maxlvt >= 5) |
1622 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1da177e4 | 1623 | #endif |
1e4c85f9 | 1624 | |
e05d723f TG |
1625 | local_irq_save(flags); |
1626 | disable_local_APIC(); | |
1627 | local_irq_restore(flags); | |
1e4c85f9 | 1628 | return 0; |
1da177e4 | 1629 | } |
1a3f239d | 1630 | |
e05d723f | 1631 | static int lapic_resume(struct sys_device *dev) |
1a3f239d | 1632 | { |
e05d723f TG |
1633 | unsigned int l, h; |
1634 | unsigned long flags; | |
1635 | int maxlvt; | |
1636 | ||
1637 | if (!apic_pm_state.active) | |
1638 | return 0; | |
1639 | ||
1640 | maxlvt = lapic_get_maxlvt(); | |
1641 | ||
1642 | local_irq_save(flags); | |
1643 | ||
92206c90 CG |
1644 | #ifdef CONFIG_X86_64 |
1645 | if (x2apic) | |
1646 | enable_x2apic(); | |
1647 | else | |
1648 | #endif | |
1649 | /* | |
1650 | * Make sure the APICBASE points to the right address | |
1651 | * | |
1652 | * FIXME! This will be wrong if we ever support suspend on | |
1653 | * SMP! We'll need to do this as part of the CPU restore! | |
1654 | */ | |
1655 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1656 | l &= ~MSR_IA32_APICBASE_BASE; | |
1657 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
1658 | wrmsr(MSR_IA32_APICBASE, l, h); | |
e05d723f TG |
1659 | |
1660 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); | |
1661 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
1662 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
1663 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
1664 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
1665 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
1666 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
1667 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
92206c90 | 1668 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
e05d723f TG |
1669 | if (maxlvt >= 5) |
1670 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
1671 | #endif | |
1672 | if (maxlvt >= 4) | |
1673 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
1674 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
1675 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
1676 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
1677 | apic_write(APIC_ESR, 0); | |
1678 | apic_read(APIC_ESR); | |
1679 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
1680 | apic_write(APIC_ESR, 0); | |
1681 | apic_read(APIC_ESR); | |
92206c90 | 1682 | |
e05d723f | 1683 | local_irq_restore(flags); |
92206c90 | 1684 | |
1a3f239d RR |
1685 | return 0; |
1686 | } | |
1a3f239d | 1687 | |
e05d723f TG |
1688 | /* |
1689 | * This device has no shutdown method - fully functioning local APICs | |
1690 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
1691 | */ | |
1692 | ||
1693 | static struct sysdev_class lapic_sysclass = { | |
af5ca3f4 | 1694 | .name = "lapic", |
e05d723f TG |
1695 | .resume = lapic_resume, |
1696 | .suspend = lapic_suspend, | |
1697 | }; | |
1698 | ||
1699 | static struct sys_device device_lapic = { | |
1700 | .id = 0, | |
1701 | .cls = &lapic_sysclass, | |
1702 | }; | |
1703 | ||
1704 | static void __devinit apic_pm_activate(void) | |
1a3f239d | 1705 | { |
e05d723f | 1706 | apic_pm_state.active = 1; |
1a3f239d | 1707 | } |
1a3f239d | 1708 | |
e05d723f TG |
1709 | static int __init init_lapic_sysfs(void) |
1710 | { | |
1711 | int error; | |
1712 | ||
1713 | if (!cpu_has_apic) | |
1714 | return 0; | |
1715 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
1716 | ||
1717 | error = sysdev_class_register(&lapic_sysclass); | |
1718 | if (!error) | |
1719 | error = sysdev_register(&device_lapic); | |
1720 | return error; | |
1721 | } | |
1722 | device_initcall(init_lapic_sysfs); | |
1723 | ||
1724 | #else /* CONFIG_PM */ | |
1725 | ||
1726 | static void apic_pm_activate(void) { } | |
1727 | ||
1728 | #endif /* CONFIG_PM */ | |
0e078e2f TG |
1729 | |
1730 | /* | |
1731 | * APIC command line parameters | |
1732 | */ | |
1733 | static int __init parse_lapic(char *arg) | |
1734 | { | |
914bebfa | 1735 | force_enable_local_apic = 1; |
0e078e2f TG |
1736 | return 0; |
1737 | } | |
1738 | early_param("lapic", parse_lapic); | |
1739 | ||
1740 | static int __init parse_nolapic(char *arg) | |
1741 | { | |
914bebfa | 1742 | disable_apic = 1; |
9175fc06 | 1743 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
0e078e2f TG |
1744 | return 0; |
1745 | } | |
1746 | early_param("nolapic", parse_nolapic); | |
1747 | ||
36fef094 | 1748 | static int __init parse_disable_apic_timer(char *arg) |
0e078e2f | 1749 | { |
36fef094 | 1750 | disable_apic_timer = 1; |
0e078e2f TG |
1751 | return 0; |
1752 | } | |
36fef094 CG |
1753 | early_param("noapictimer", parse_disable_apic_timer); |
1754 | ||
1755 | static int __init parse_nolapic_timer(char *arg) | |
1756 | { | |
1757 | disable_apic_timer = 1; | |
1758 | return 0; | |
1759 | } | |
1760 | early_param("nolapic_timer", parse_nolapic_timer); | |
0e078e2f TG |
1761 | |
1762 | static int __init parse_lapic_timer_c2_ok(char *arg) | |
1763 | { | |
1764 | local_apic_timer_c2_ok = 1; | |
1765 | return 0; | |
1766 | } | |
1767 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
1768 | ||
48d97cb6 | 1769 | static int __init apic_set_verbosity(char *arg) |
0e078e2f | 1770 | { |
79af9bec CG |
1771 | if (!arg) { |
1772 | #ifdef CONFIG_X86_64 | |
1773 | skip_ioapic_setup = 0; | |
1774 | ioapic_force = 1; | |
1775 | return 0; | |
1776 | #endif | |
48d97cb6 | 1777 | return -EINVAL; |
79af9bec | 1778 | } |
48d97cb6 | 1779 | |
79af9bec | 1780 | if (strcmp("debug", arg) == 0) |
0e078e2f | 1781 | apic_verbosity = APIC_DEBUG; |
79af9bec | 1782 | else if (strcmp("verbose", arg) == 0) |
0e078e2f | 1783 | apic_verbosity = APIC_VERBOSE; |
79af9bec CG |
1784 | else { |
1785 | printk(KERN_WARNING "APIC Verbosity level %s not recognised" | |
1786 | " use apic=verbose or apic=debug\n", arg); | |
1787 | return -EINVAL; | |
1788 | } | |
48d97cb6 | 1789 | |
fb6bef80 | 1790 | return 0; |
0e078e2f | 1791 | } |
fb6bef80 | 1792 | early_param("apic", apic_set_verbosity); |
0e078e2f | 1793 | |
746f2eb7 CG |
1794 | static int __init lapic_insert_resource(void) |
1795 | { | |
1796 | if (!apic_phys) | |
1797 | return -1; | |
1798 | ||
1799 | /* Put local APIC into the resource map. */ | |
1800 | lapic_resource.start = apic_phys; | |
1801 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
1802 | insert_resource(&iomem_resource, &lapic_resource); | |
1803 | ||
1804 | return 0; | |
1805 | } | |
1806 | ||
1807 | /* | |
1808 | * need call insert after e820_reserve_resources() | |
1809 | * that is using request_resource | |
1810 | */ | |
1811 | late_initcall(lapic_insert_resource); |