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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
39928722 | 26 | #include <linux/ioport.h> |
ba7eda4c | 27 | #include <linux/clockchips.h> |
70a20025 | 28 | #include <linux/acpi_pmtmr.h> |
e83a5fdc | 29 | #include <linux/module.h> |
6e1cb38a | 30 | #include <linux/dmar.h> |
1da177e4 LT |
31 | |
32 | #include <asm/atomic.h> | |
33 | #include <asm/smp.h> | |
34 | #include <asm/mtrr.h> | |
35 | #include <asm/mpspec.h> | |
e83a5fdc | 36 | #include <asm/hpet.h> |
1da177e4 | 37 | #include <asm/pgalloc.h> |
75152114 | 38 | #include <asm/nmi.h> |
95833c83 | 39 | #include <asm/idle.h> |
73dea47f AK |
40 | #include <asm/proto.h> |
41 | #include <asm/timex.h> | |
2c8c0e6b | 42 | #include <asm/apic.h> |
6e1cb38a | 43 | #include <asm/i8259.h> |
1da177e4 | 44 | |
5af5573e | 45 | #include <mach_ipi.h> |
dd46e3ca | 46 | #include <mach_apic.h> |
5af5573e | 47 | |
36fef094 | 48 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ |
aa276e1c | 49 | static int disable_apic_timer __cpuinitdata; |
bc1d99c1 | 50 | static int apic_calibrate_pmtmr __initdata; |
0e078e2f | 51 | int disable_apic; |
6e1cb38a | 52 | int disable_x2apic; |
89027d35 | 53 | int x2apic; |
1da177e4 | 54 | |
6e1cb38a SS |
55 | /* x2apic enabled before OS handover */ |
56 | int x2apic_preenabled; | |
57 | ||
e83a5fdc | 58 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
59 | int local_apic_timer_c2_ok; |
60 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
61 | ||
e83a5fdc HS |
62 | /* |
63 | * Debug level, exported for io_apic.c | |
64 | */ | |
baa13188 | 65 | unsigned int apic_verbosity; |
e83a5fdc | 66 | |
bab4b27c AS |
67 | /* Have we found an MP table */ |
68 | int smp_found_config; | |
69 | ||
39928722 AD |
70 | static struct resource lapic_resource = { |
71 | .name = "Local APIC", | |
72 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
73 | }; | |
74 | ||
d03030e9 TG |
75 | static unsigned int calibration_result; |
76 | ||
ba7eda4c TG |
77 | static int lapic_next_event(unsigned long delta, |
78 | struct clock_event_device *evt); | |
79 | static void lapic_timer_setup(enum clock_event_mode mode, | |
80 | struct clock_event_device *evt); | |
ba7eda4c | 81 | static void lapic_timer_broadcast(cpumask_t mask); |
0e078e2f | 82 | static void apic_pm_activate(void); |
ba7eda4c TG |
83 | |
84 | static struct clock_event_device lapic_clockevent = { | |
85 | .name = "lapic", | |
86 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
87 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
88 | .shift = 32, | |
89 | .set_mode = lapic_timer_setup, | |
90 | .set_next_event = lapic_next_event, | |
91 | .broadcast = lapic_timer_broadcast, | |
92 | .rating = 100, | |
93 | .irq = -1, | |
94 | }; | |
95 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
96 | ||
d3432896 AK |
97 | static unsigned long apic_phys; |
98 | ||
3f530709 AS |
99 | unsigned long mp_lapic_addr; |
100 | ||
be8a5685 | 101 | unsigned int __cpuinitdata maxcpus = NR_CPUS; |
0e078e2f TG |
102 | /* |
103 | * Get the LAPIC version | |
104 | */ | |
105 | static inline int lapic_get_version(void) | |
ba7eda4c | 106 | { |
0e078e2f | 107 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
108 | } |
109 | ||
0e078e2f TG |
110 | /* |
111 | * Check, if the APIC is integrated or a seperate chip | |
112 | */ | |
113 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 114 | { |
0e078e2f | 115 | return 1; |
ba7eda4c TG |
116 | } |
117 | ||
118 | /* | |
0e078e2f | 119 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 120 | */ |
0e078e2f | 121 | static int modern_apic(void) |
ba7eda4c | 122 | { |
0e078e2f TG |
123 | /* AMD systems use old APIC versions, so check the CPU */ |
124 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
125 | boot_cpu_data.x86 >= 0xf) | |
126 | return 1; | |
127 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
128 | } |
129 | ||
1b374e4d | 130 | void xapic_wait_icr_idle(void) |
8339e9fb FLV |
131 | { |
132 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
133 | cpu_relax(); | |
134 | } | |
135 | ||
1b374e4d | 136 | u32 safe_xapic_wait_icr_idle(void) |
8339e9fb | 137 | { |
3c6bb07a | 138 | u32 send_status; |
8339e9fb FLV |
139 | int timeout; |
140 | ||
141 | timeout = 0; | |
142 | do { | |
143 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
144 | if (!send_status) | |
145 | break; | |
146 | udelay(100); | |
147 | } while (timeout++ < 1000); | |
148 | ||
149 | return send_status; | |
150 | } | |
151 | ||
1b374e4d SS |
152 | void xapic_icr_write(u32 low, u32 id) |
153 | { | |
ed4e5ec1 | 154 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
1b374e4d SS |
155 | apic_write(APIC_ICR, low); |
156 | } | |
157 | ||
158 | u64 xapic_icr_read(void) | |
159 | { | |
160 | u32 icr1, icr2; | |
161 | ||
162 | icr2 = apic_read(APIC_ICR2); | |
163 | icr1 = apic_read(APIC_ICR); | |
164 | ||
165 | return (icr1 | ((u64)icr2 << 32)); | |
166 | } | |
167 | ||
168 | static struct apic_ops xapic_ops = { | |
169 | .read = native_apic_mem_read, | |
170 | .write = native_apic_mem_write, | |
1b374e4d SS |
171 | .icr_read = xapic_icr_read, |
172 | .icr_write = xapic_icr_write, | |
173 | .wait_icr_idle = xapic_wait_icr_idle, | |
174 | .safe_wait_icr_idle = safe_xapic_wait_icr_idle, | |
175 | }; | |
176 | ||
177 | struct apic_ops __read_mostly *apic_ops = &xapic_ops; | |
178 | ||
179 | EXPORT_SYMBOL_GPL(apic_ops); | |
180 | ||
13c88fb5 SS |
181 | static void x2apic_wait_icr_idle(void) |
182 | { | |
183 | /* no need to wait for icr idle in x2apic */ | |
184 | return; | |
185 | } | |
186 | ||
187 | static u32 safe_x2apic_wait_icr_idle(void) | |
188 | { | |
189 | /* no need to wait for icr idle in x2apic */ | |
190 | return 0; | |
191 | } | |
192 | ||
193 | void x2apic_icr_write(u32 low, u32 id) | |
194 | { | |
195 | wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); | |
196 | } | |
197 | ||
198 | u64 x2apic_icr_read(void) | |
199 | { | |
200 | unsigned long val; | |
201 | ||
202 | rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); | |
203 | return val; | |
204 | } | |
205 | ||
206 | static struct apic_ops x2apic_ops = { | |
207 | .read = native_apic_msr_read, | |
208 | .write = native_apic_msr_write, | |
13c88fb5 SS |
209 | .icr_read = x2apic_icr_read, |
210 | .icr_write = x2apic_icr_write, | |
211 | .wait_icr_idle = x2apic_wait_icr_idle, | |
212 | .safe_wait_icr_idle = safe_x2apic_wait_icr_idle, | |
213 | }; | |
214 | ||
0e078e2f TG |
215 | /** |
216 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
217 | */ | |
e9427101 | 218 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 219 | { |
11a8e778 | 220 | unsigned int v; |
6935d1f9 TG |
221 | |
222 | /* unmask and set to NMI */ | |
223 | v = APIC_DM_NMI; | |
d4c63ec0 CG |
224 | |
225 | /* Level triggered for 82489DX (32bit mode) */ | |
226 | if (!lapic_is_integrated()) | |
227 | v |= APIC_LVT_LEVEL_TRIGGER; | |
228 | ||
11a8e778 | 229 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
230 | } |
231 | ||
0e078e2f TG |
232 | /** |
233 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
234 | */ | |
37e650c7 | 235 | int lapic_get_maxlvt(void) |
1da177e4 | 236 | { |
36a028de | 237 | unsigned int v; |
1da177e4 LT |
238 | |
239 | v = apic_read(APIC_LVR); | |
36a028de CG |
240 | /* |
241 | * - we always have APIC integrated on 64bit mode | |
242 | * - 82489DXs do not report # of LVT entries | |
243 | */ | |
244 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; | |
1da177e4 LT |
245 | } |
246 | ||
f07f4f90 CG |
247 | /* Clock divisor is set to 1 */ |
248 | #define APIC_DIVISOR 1 | |
249 | ||
0e078e2f TG |
250 | /* |
251 | * This function sets up the local APIC timer, with a timeout of | |
252 | * 'clocks' APIC bus clock. During calibration we actually call | |
253 | * this function twice on the boot CPU, once with a bogus timeout | |
254 | * value, second time for real. The other (noncalibrating) CPUs | |
255 | * call this function only once, with the real, calibrated value. | |
256 | * | |
257 | * We do reads before writes even if unnecessary, to get around the | |
258 | * P5 APIC double write bug. | |
259 | */ | |
260 | ||
261 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) | |
1da177e4 | 262 | { |
0e078e2f | 263 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 264 | |
0e078e2f TG |
265 | lvtt_value = LOCAL_TIMER_VECTOR; |
266 | if (!oneshot) | |
267 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
f07f4f90 CG |
268 | if (!lapic_is_integrated()) |
269 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
270 | ||
0e078e2f TG |
271 | if (!irqen) |
272 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 273 | |
0e078e2f | 274 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
275 | |
276 | /* | |
0e078e2f | 277 | * Divide PICLK by 16 |
1da177e4 | 278 | */ |
0e078e2f TG |
279 | tmp_value = apic_read(APIC_TDCR); |
280 | apic_write(APIC_TDCR, (tmp_value | |
281 | & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | |
282 | | APIC_TDR_DIV_16); | |
283 | ||
284 | if (!oneshot) | |
f07f4f90 | 285 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
1da177e4 LT |
286 | } |
287 | ||
0e078e2f | 288 | /* |
7b83dae7 RR |
289 | * Setup extended LVT, AMD specific (K8, family 10h) |
290 | * | |
291 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
292 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
0e078e2f | 293 | */ |
7b83dae7 RR |
294 | |
295 | #define APIC_EILVT_LVTOFF_MCE 0 | |
296 | #define APIC_EILVT_LVTOFF_IBS 1 | |
297 | ||
298 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
1da177e4 | 299 | { |
7b83dae7 | 300 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; |
0e078e2f | 301 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; |
a8fcf1a2 | 302 | |
0e078e2f | 303 | apic_write(reg, v); |
1da177e4 LT |
304 | } |
305 | ||
7b83dae7 RR |
306 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) |
307 | { | |
308 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
309 | return APIC_EILVT_LVTOFF_MCE; | |
310 | } | |
311 | ||
312 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
313 | { | |
314 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
315 | return APIC_EILVT_LVTOFF_IBS; | |
316 | } | |
317 | ||
0e078e2f TG |
318 | /* |
319 | * Program the next event, relative to now | |
320 | */ | |
321 | static int lapic_next_event(unsigned long delta, | |
322 | struct clock_event_device *evt) | |
1da177e4 | 323 | { |
0e078e2f TG |
324 | apic_write(APIC_TMICT, delta); |
325 | return 0; | |
1da177e4 LT |
326 | } |
327 | ||
0e078e2f TG |
328 | /* |
329 | * Setup the lapic timer in periodic or oneshot mode | |
330 | */ | |
331 | static void lapic_timer_setup(enum clock_event_mode mode, | |
332 | struct clock_event_device *evt) | |
9b7711f0 HS |
333 | { |
334 | unsigned long flags; | |
0e078e2f | 335 | unsigned int v; |
9b7711f0 | 336 | |
0e078e2f TG |
337 | /* Lapic used as dummy for broadcast ? */ |
338 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
9b7711f0 HS |
339 | return; |
340 | ||
341 | local_irq_save(flags); | |
342 | ||
0e078e2f TG |
343 | switch (mode) { |
344 | case CLOCK_EVT_MODE_PERIODIC: | |
345 | case CLOCK_EVT_MODE_ONESHOT: | |
346 | __setup_APIC_LVTT(calibration_result, | |
347 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
348 | break; | |
349 | case CLOCK_EVT_MODE_UNUSED: | |
350 | case CLOCK_EVT_MODE_SHUTDOWN: | |
351 | v = apic_read(APIC_LVTT); | |
352 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
353 | apic_write(APIC_LVTT, v); | |
354 | break; | |
355 | case CLOCK_EVT_MODE_RESUME: | |
356 | /* Nothing to do here */ | |
357 | break; | |
358 | } | |
9b7711f0 HS |
359 | |
360 | local_irq_restore(flags); | |
361 | } | |
362 | ||
1da177e4 | 363 | /* |
0e078e2f | 364 | * Local APIC timer broadcast function |
1da177e4 | 365 | */ |
0e078e2f | 366 | static void lapic_timer_broadcast(cpumask_t mask) |
1da177e4 | 367 | { |
0e078e2f TG |
368 | #ifdef CONFIG_SMP |
369 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
370 | #endif | |
371 | } | |
1da177e4 | 372 | |
0e078e2f TG |
373 | /* |
374 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
375 | * of the boot CPU and register the clock event in the framework. | |
376 | */ | |
377 | static void setup_APIC_timer(void) | |
378 | { | |
379 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
1da177e4 | 380 | |
0e078e2f TG |
381 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
382 | levt->cpumask = cpumask_of_cpu(smp_processor_id()); | |
1da177e4 | 383 | |
0e078e2f TG |
384 | clockevents_register_device(levt); |
385 | } | |
1da177e4 | 386 | |
0e078e2f TG |
387 | /* |
388 | * In this function we calibrate APIC bus clocks to the external | |
389 | * timer. Unfortunately we cannot use jiffies and the timer irq | |
390 | * to calibrate, since some later bootup code depends on getting | |
391 | * the first irq? Ugh. | |
392 | * | |
393 | * We want to do the calibration only once since we | |
394 | * want to have local timer irqs syncron. CPUs connected | |
395 | * by the same APIC bus have the very same bus frequency. | |
396 | * And we want to have irqs off anyways, no accidental | |
397 | * APIC irq that way. | |
398 | */ | |
399 | ||
400 | #define TICK_COUNT 100000000 | |
401 | ||
89b3b1f4 | 402 | static int __init calibrate_APIC_clock(void) |
0e078e2f TG |
403 | { |
404 | unsigned apic, apic_start; | |
405 | unsigned long tsc, tsc_start; | |
406 | int result; | |
407 | ||
408 | local_irq_disable(); | |
409 | ||
410 | /* | |
411 | * Put whatever arbitrary (but long enough) timeout | |
412 | * value into the APIC clock, we just want to get the | |
413 | * counter running for calibration. | |
414 | * | |
415 | * No interrupt enable ! | |
416 | */ | |
417 | __setup_APIC_LVTT(250000000, 0, 0); | |
418 | ||
419 | apic_start = apic_read(APIC_TMCCT); | |
420 | #ifdef CONFIG_X86_PM_TIMER | |
421 | if (apic_calibrate_pmtmr && pmtmr_ioport) { | |
422 | pmtimer_wait(5000); /* 5ms wait */ | |
423 | apic = apic_read(APIC_TMCCT); | |
424 | result = (apic_start - apic) * 1000L / 5; | |
425 | } else | |
426 | #endif | |
427 | { | |
428 | rdtscll(tsc_start); | |
429 | ||
430 | do { | |
431 | apic = apic_read(APIC_TMCCT); | |
432 | rdtscll(tsc); | |
433 | } while ((tsc - tsc_start) < TICK_COUNT && | |
434 | (apic_start - apic) < TICK_COUNT); | |
435 | ||
436 | result = (apic_start - apic) * 1000L * tsc_khz / | |
437 | (tsc - tsc_start); | |
438 | } | |
439 | ||
440 | local_irq_enable(); | |
441 | ||
442 | printk(KERN_DEBUG "APIC timer calibration result %d\n", result); | |
443 | ||
444 | printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n", | |
445 | result / 1000 / 1000, result / 1000 % 1000); | |
446 | ||
447 | /* Calculate the scaled math multiplication factor */ | |
877084fb AM |
448 | lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC, |
449 | lapic_clockevent.shift); | |
0e078e2f TG |
450 | lapic_clockevent.max_delta_ns = |
451 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
452 | lapic_clockevent.min_delta_ns = | |
453 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
454 | ||
f07f4f90 | 455 | calibration_result = (result * APIC_DIVISOR) / HZ; |
89b3b1f4 CG |
456 | |
457 | /* | |
458 | * Do a sanity check on the APIC calibration result | |
459 | */ | |
460 | if (calibration_result < (1000000 / HZ)) { | |
461 | printk(KERN_WARNING | |
462 | "APIC frequency too slow, disabling apic timer\n"); | |
463 | return -1; | |
464 | } | |
465 | ||
466 | return 0; | |
0e078e2f TG |
467 | } |
468 | ||
e83a5fdc HS |
469 | /* |
470 | * Setup the boot APIC | |
471 | * | |
472 | * Calibrate and verify the result. | |
473 | */ | |
0e078e2f TG |
474 | void __init setup_boot_APIC_clock(void) |
475 | { | |
476 | /* | |
477 | * The local apic timer can be disabled via the kernel commandline. | |
478 | * Register the lapic timer as a dummy clock event source on SMP | |
479 | * systems, so the broadcast mechanism is used. On UP systems simply | |
480 | * ignore it. | |
481 | */ | |
482 | if (disable_apic_timer) { | |
483 | printk(KERN_INFO "Disabling APIC timer\n"); | |
484 | /* No broadcast on UP ! */ | |
9d09951d TG |
485 | if (num_possible_cpus() > 1) { |
486 | lapic_clockevent.mult = 1; | |
0e078e2f | 487 | setup_APIC_timer(); |
9d09951d | 488 | } |
0e078e2f TG |
489 | return; |
490 | } | |
491 | ||
492 | printk(KERN_INFO "Using local APIC timer interrupts.\n"); | |
89b3b1f4 | 493 | if (calibrate_APIC_clock()) { |
c2b84b30 TG |
494 | /* No broadcast on UP ! */ |
495 | if (num_possible_cpus() > 1) | |
496 | setup_APIC_timer(); | |
497 | return; | |
498 | } | |
499 | ||
0e078e2f TG |
500 | /* |
501 | * If nmi_watchdog is set to IO_APIC, we need the | |
502 | * PIT/HPET going. Otherwise register lapic as a dummy | |
503 | * device. | |
504 | */ | |
505 | if (nmi_watchdog != NMI_IO_APIC) | |
506 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
507 | else | |
508 | printk(KERN_WARNING "APIC timer registered as dummy," | |
116f570e | 509 | " due to nmi_watchdog=%d!\n", nmi_watchdog); |
0e078e2f TG |
510 | |
511 | setup_APIC_timer(); | |
512 | } | |
513 | ||
0e078e2f TG |
514 | void __cpuinit setup_secondary_APIC_clock(void) |
515 | { | |
0e078e2f TG |
516 | setup_APIC_timer(); |
517 | } | |
518 | ||
519 | /* | |
520 | * The guts of the apic timer interrupt | |
521 | */ | |
522 | static void local_apic_timer_interrupt(void) | |
523 | { | |
524 | int cpu = smp_processor_id(); | |
525 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
526 | ||
527 | /* | |
528 | * Normally we should not be here till LAPIC has been initialized but | |
529 | * in some cases like kdump, its possible that there is a pending LAPIC | |
530 | * timer interrupt from previous kernel's context and is delivered in | |
531 | * new kernel the moment interrupts are enabled. | |
532 | * | |
533 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
534 | * its possible that when we get here evt->event_handler is NULL. | |
535 | * Check for event_handler being NULL and discard the interrupt as | |
536 | * spurious. | |
537 | */ | |
538 | if (!evt->event_handler) { | |
539 | printk(KERN_WARNING | |
540 | "Spurious LAPIC timer interrupt on cpu %d\n", cpu); | |
541 | /* Switch it off */ | |
542 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
543 | return; | |
544 | } | |
545 | ||
546 | /* | |
547 | * the NMI deadlock-detector uses this. | |
548 | */ | |
549 | add_pda(apic_timer_irqs, 1); | |
550 | ||
551 | evt->event_handler(evt); | |
552 | } | |
553 | ||
554 | /* | |
555 | * Local APIC timer interrupt. This is the most natural way for doing | |
556 | * local interrupts, but local timer interrupts can be emulated by | |
557 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
558 | * | |
559 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
560 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
561 | */ | |
562 | void smp_apic_timer_interrupt(struct pt_regs *regs) | |
563 | { | |
564 | struct pt_regs *old_regs = set_irq_regs(regs); | |
565 | ||
566 | /* | |
567 | * NOTE! We'd better ACK the irq immediately, | |
568 | * because timer handling can be slow. | |
569 | */ | |
570 | ack_APIC_irq(); | |
571 | /* | |
572 | * update_process_times() expects us to have done irq_enter(). | |
573 | * Besides, if we don't timer interrupts ignore the global | |
574 | * interrupt lock, which is the WrongThing (tm) to do. | |
575 | */ | |
576 | exit_idle(); | |
577 | irq_enter(); | |
578 | local_apic_timer_interrupt(); | |
579 | irq_exit(); | |
580 | set_irq_regs(old_regs); | |
581 | } | |
582 | ||
583 | int setup_profiling_timer(unsigned int multiplier) | |
584 | { | |
585 | return -EINVAL; | |
586 | } | |
587 | ||
588 | ||
589 | /* | |
590 | * Local APIC start and shutdown | |
591 | */ | |
592 | ||
593 | /** | |
594 | * clear_local_APIC - shutdown the local APIC | |
595 | * | |
596 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
597 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
598 | * leftovers during boot. | |
599 | */ | |
600 | void clear_local_APIC(void) | |
601 | { | |
2584a82d | 602 | int maxlvt; |
0e078e2f TG |
603 | u32 v; |
604 | ||
d3432896 AK |
605 | /* APIC hasn't been mapped yet */ |
606 | if (!apic_phys) | |
607 | return; | |
608 | ||
609 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
610 | /* |
611 | * Masking an LVT entry can trigger a local APIC error | |
612 | * if the vector is zero. Mask LVTERR first to prevent this. | |
613 | */ | |
614 | if (maxlvt >= 3) { | |
615 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
616 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
617 | } | |
618 | /* | |
619 | * Careful: we have to set masks only first to deassert | |
620 | * any level-triggered sources. | |
621 | */ | |
622 | v = apic_read(APIC_LVTT); | |
623 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
624 | v = apic_read(APIC_LVT0); | |
625 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
626 | v = apic_read(APIC_LVT1); | |
627 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
628 | if (maxlvt >= 4) { | |
629 | v = apic_read(APIC_LVTPC); | |
630 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
631 | } | |
632 | ||
633 | /* | |
634 | * Clean APIC state for other OSs: | |
635 | */ | |
636 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
637 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
638 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
639 | if (maxlvt >= 3) | |
640 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
641 | if (maxlvt >= 4) | |
642 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
643 | apic_write(APIC_ESR, 0); | |
644 | apic_read(APIC_ESR); | |
645 | } | |
646 | ||
647 | /** | |
648 | * disable_local_APIC - clear and disable the local APIC | |
649 | */ | |
650 | void disable_local_APIC(void) | |
651 | { | |
652 | unsigned int value; | |
653 | ||
654 | clear_local_APIC(); | |
655 | ||
656 | /* | |
657 | * Disable APIC (implies clearing of registers | |
658 | * for 82489DX!). | |
659 | */ | |
660 | value = apic_read(APIC_SPIV); | |
661 | value &= ~APIC_SPIV_APIC_ENABLED; | |
662 | apic_write(APIC_SPIV, value); | |
663 | } | |
664 | ||
665 | void lapic_shutdown(void) | |
666 | { | |
667 | unsigned long flags; | |
668 | ||
669 | if (!cpu_has_apic) | |
670 | return; | |
671 | ||
672 | local_irq_save(flags); | |
673 | ||
674 | disable_local_APIC(); | |
675 | ||
676 | local_irq_restore(flags); | |
677 | } | |
678 | ||
679 | /* | |
680 | * This is to verify that we're looking at a real local APIC. | |
681 | * Check these against your board if the CPUs aren't getting | |
682 | * started for no apparent reason. | |
683 | */ | |
684 | int __init verify_local_APIC(void) | |
685 | { | |
686 | unsigned int reg0, reg1; | |
687 | ||
688 | /* | |
689 | * The version register is read-only in a real APIC. | |
690 | */ | |
691 | reg0 = apic_read(APIC_LVR); | |
692 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
693 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
694 | reg1 = apic_read(APIC_LVR); | |
695 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
696 | ||
697 | /* | |
698 | * The two version reads above should print the same | |
699 | * numbers. If the second one is different, then we | |
700 | * poke at a non-APIC. | |
701 | */ | |
702 | if (reg1 != reg0) | |
703 | return 0; | |
704 | ||
705 | /* | |
706 | * Check if the version looks reasonably. | |
707 | */ | |
708 | reg1 = GET_APIC_VERSION(reg0); | |
709 | if (reg1 == 0x00 || reg1 == 0xff) | |
710 | return 0; | |
711 | reg1 = lapic_get_maxlvt(); | |
712 | if (reg1 < 0x02 || reg1 == 0xff) | |
713 | return 0; | |
714 | ||
715 | /* | |
716 | * The ID register is read/write in a real APIC. | |
717 | */ | |
2d7a66d0 | 718 | reg0 = apic_read(APIC_ID); |
0e078e2f TG |
719 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
720 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); | |
2d7a66d0 | 721 | reg1 = apic_read(APIC_ID); |
0e078e2f TG |
722 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); |
723 | apic_write(APIC_ID, reg0); | |
724 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
725 | return 0; | |
726 | ||
727 | /* | |
1da177e4 LT |
728 | * The next two are just to see if we have sane values. |
729 | * They're only really relevant if we're in Virtual Wire | |
730 | * compatibility mode, but most boxes are anymore. | |
731 | */ | |
732 | reg0 = apic_read(APIC_LVT0); | |
0e078e2f | 733 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
1da177e4 LT |
734 | reg1 = apic_read(APIC_LVT1); |
735 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
736 | ||
737 | return 1; | |
738 | } | |
739 | ||
0e078e2f TG |
740 | /** |
741 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
742 | */ | |
1da177e4 LT |
743 | void __init sync_Arb_IDs(void) |
744 | { | |
296cb951 CG |
745 | /* |
746 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
747 | * needed on AMD. | |
748 | */ | |
749 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
1da177e4 LT |
750 | return; |
751 | ||
752 | /* | |
753 | * Wait for idle. | |
754 | */ | |
755 | apic_wait_icr_idle(); | |
756 | ||
757 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
296cb951 | 758 | apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG | APIC_DM_INIT); |
1da177e4 LT |
759 | } |
760 | ||
1da177e4 LT |
761 | /* |
762 | * An initial setup of the virtual wire mode. | |
763 | */ | |
764 | void __init init_bsp_APIC(void) | |
765 | { | |
11a8e778 | 766 | unsigned int value; |
1da177e4 LT |
767 | |
768 | /* | |
769 | * Don't do the setup now if we have a SMP BIOS as the | |
770 | * through-I/O-APIC virtual wire mode might be active. | |
771 | */ | |
772 | if (smp_found_config || !cpu_has_apic) | |
773 | return; | |
774 | ||
775 | value = apic_read(APIC_LVR); | |
1da177e4 LT |
776 | |
777 | /* | |
778 | * Do not trust the local APIC being empty at bootup. | |
779 | */ | |
780 | clear_local_APIC(); | |
781 | ||
782 | /* | |
783 | * Enable APIC. | |
784 | */ | |
785 | value = apic_read(APIC_SPIV); | |
786 | value &= ~APIC_VECTOR_MASK; | |
787 | value |= APIC_SPIV_APIC_ENABLED; | |
788 | value |= APIC_SPIV_FOCUS_DISABLED; | |
789 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 790 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
791 | |
792 | /* | |
793 | * Set up the virtual wire mode. | |
794 | */ | |
11a8e778 | 795 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 796 | value = APIC_DM_NMI; |
11a8e778 | 797 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
798 | } |
799 | ||
0e078e2f TG |
800 | /** |
801 | * setup_local_APIC - setup the local APIC | |
802 | */ | |
803 | void __cpuinit setup_local_APIC(void) | |
1da177e4 | 804 | { |
739f33b3 | 805 | unsigned int value; |
da7ed9f9 | 806 | int i, j; |
1da177e4 | 807 | |
ac23d4ee | 808 | preempt_disable(); |
1da177e4 | 809 | value = apic_read(APIC_LVR); |
1da177e4 | 810 | |
fe7414a2 | 811 | BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f); |
1da177e4 LT |
812 | |
813 | /* | |
814 | * Double-check whether this APIC is really registered. | |
815 | * This is meaningless in clustered apic mode, so we skip it. | |
816 | */ | |
817 | if (!apic_id_registered()) | |
818 | BUG(); | |
819 | ||
820 | /* | |
821 | * Intel recommends to set DFR, LDR and TPR before enabling | |
822 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
823 | * document number 292116). So here it goes... | |
824 | */ | |
825 | init_apic_ldr(); | |
826 | ||
827 | /* | |
828 | * Set Task Priority to 'accept all'. We never change this | |
829 | * later on. | |
830 | */ | |
831 | value = apic_read(APIC_TASKPRI); | |
832 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 833 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 834 | |
da7ed9f9 VG |
835 | /* |
836 | * After a crash, we no longer service the interrupts and a pending | |
837 | * interrupt from previous kernel might still have ISR bit set. | |
838 | * | |
839 | * Most probably by now CPU has serviced that pending interrupt and | |
840 | * it might not have done the ack_APIC_irq() because it thought, | |
841 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
842 | * does not clear the ISR bit and cpu thinks it has already serivced | |
843 | * the interrupt. Hence a vector might get locked. It was noticed | |
844 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
845 | */ | |
846 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
847 | value = apic_read(APIC_ISR + i*0x10); | |
848 | for (j = 31; j >= 0; j--) { | |
849 | if (value & (1<<j)) | |
850 | ack_APIC_irq(); | |
851 | } | |
852 | } | |
853 | ||
1da177e4 LT |
854 | /* |
855 | * Now that we are all set up, enable the APIC | |
856 | */ | |
857 | value = apic_read(APIC_SPIV); | |
858 | value &= ~APIC_VECTOR_MASK; | |
859 | /* | |
860 | * Enable APIC | |
861 | */ | |
862 | value |= APIC_SPIV_APIC_ENABLED; | |
863 | ||
3f14c746 AK |
864 | /* We always use processor focus */ |
865 | ||
1da177e4 LT |
866 | /* |
867 | * Set spurious IRQ vector | |
868 | */ | |
869 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 870 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
871 | |
872 | /* | |
873 | * Set up LVT0, LVT1: | |
874 | * | |
875 | * set up through-local-APIC on the BP's LINT0. This is not | |
876 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
877 | * we delegate interrupts to the 8259A. | |
878 | */ | |
879 | /* | |
880 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
881 | */ | |
882 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
a8fcf1a2 | 883 | if (!smp_processor_id() && !value) { |
1da177e4 | 884 | value = APIC_DM_EXTINT; |
bc1d99c1 CW |
885 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", |
886 | smp_processor_id()); | |
1da177e4 LT |
887 | } else { |
888 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
bc1d99c1 CW |
889 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
890 | smp_processor_id()); | |
1da177e4 | 891 | } |
11a8e778 | 892 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
893 | |
894 | /* | |
895 | * only the BP should see the LINT1 NMI signal, obviously. | |
896 | */ | |
897 | if (!smp_processor_id()) | |
898 | value = APIC_DM_NMI; | |
899 | else | |
900 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
11a8e778 | 901 | apic_write(APIC_LVT1, value); |
ac23d4ee | 902 | preempt_enable(); |
739f33b3 | 903 | } |
1da177e4 | 904 | |
a4928cff | 905 | static void __cpuinit lapic_setup_esr(void) |
739f33b3 AK |
906 | { |
907 | unsigned maxlvt = lapic_get_maxlvt(); | |
908 | ||
909 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR); | |
1c69524c | 910 | /* |
739f33b3 | 911 | * spec says clear errors after enabling vector. |
1c69524c | 912 | */ |
739f33b3 AK |
913 | if (maxlvt > 3) |
914 | apic_write(APIC_ESR, 0); | |
915 | } | |
1da177e4 | 916 | |
739f33b3 AK |
917 | void __cpuinit end_local_APIC_setup(void) |
918 | { | |
919 | lapic_setup_esr(); | |
f2802e7f | 920 | setup_apic_nmi_watchdog(NULL); |
0e078e2f | 921 | apic_pm_activate(); |
1da177e4 | 922 | } |
1da177e4 | 923 | |
6e1cb38a SS |
924 | void check_x2apic(void) |
925 | { | |
926 | int msr, msr2; | |
927 | ||
928 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
929 | ||
930 | if (msr & X2APIC_ENABLE) { | |
931 | printk("x2apic enabled by BIOS, switching to x2apic ops\n"); | |
932 | x2apic_preenabled = x2apic = 1; | |
933 | apic_ops = &x2apic_ops; | |
934 | } | |
935 | } | |
936 | ||
937 | void enable_x2apic(void) | |
938 | { | |
939 | int msr, msr2; | |
940 | ||
941 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
942 | if (!(msr & X2APIC_ENABLE)) { | |
943 | printk("Enabling x2apic\n"); | |
944 | wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); | |
945 | } | |
946 | } | |
947 | ||
948 | void enable_IR_x2apic(void) | |
949 | { | |
950 | #ifdef CONFIG_INTR_REMAP | |
951 | int ret; | |
952 | unsigned long flags; | |
953 | ||
954 | if (!cpu_has_x2apic) | |
955 | return; | |
956 | ||
957 | if (!x2apic_preenabled && disable_x2apic) { | |
958 | printk(KERN_INFO | |
959 | "Skipped enabling x2apic and Interrupt-remapping " | |
960 | "because of nox2apic\n"); | |
961 | return; | |
962 | } | |
963 | ||
964 | if (x2apic_preenabled && disable_x2apic) | |
965 | panic("Bios already enabled x2apic, can't enforce nox2apic"); | |
966 | ||
967 | if (!x2apic_preenabled && skip_ioapic_setup) { | |
968 | printk(KERN_INFO | |
969 | "Skipped enabling x2apic and Interrupt-remapping " | |
970 | "because of skipping io-apic setup\n"); | |
971 | return; | |
972 | } | |
973 | ||
974 | ret = dmar_table_init(); | |
975 | if (ret) { | |
976 | printk(KERN_INFO | |
977 | "dmar_table_init() failed with %d:\n", ret); | |
978 | ||
979 | if (x2apic_preenabled) | |
980 | panic("x2apic enabled by bios. But IR enabling failed"); | |
981 | else | |
982 | printk(KERN_INFO | |
983 | "Not enabling x2apic,Intr-remapping\n"); | |
984 | return; | |
985 | } | |
986 | ||
987 | local_irq_save(flags); | |
988 | mask_8259A(); | |
989 | save_mask_IO_APIC_setup(); | |
990 | ||
991 | ret = enable_intr_remapping(1); | |
992 | ||
993 | if (ret && x2apic_preenabled) { | |
994 | local_irq_restore(flags); | |
995 | panic("x2apic enabled by bios. But IR enabling failed"); | |
996 | } | |
997 | ||
998 | if (ret) | |
999 | goto end; | |
1000 | ||
1001 | if (!x2apic) { | |
1002 | x2apic = 1; | |
1003 | apic_ops = &x2apic_ops; | |
1004 | enable_x2apic(); | |
1005 | } | |
1006 | end: | |
1007 | if (ret) | |
1008 | /* | |
1009 | * IR enabling failed | |
1010 | */ | |
1011 | restore_IO_APIC_setup(); | |
1012 | else | |
1013 | reinit_intr_remapped_IO_APIC(x2apic_preenabled); | |
1014 | ||
1015 | unmask_8259A(); | |
1016 | local_irq_restore(flags); | |
1017 | ||
1018 | if (!ret) { | |
1019 | if (!x2apic_preenabled) | |
1020 | printk(KERN_INFO | |
1021 | "Enabled x2apic and interrupt-remapping\n"); | |
1022 | else | |
1023 | printk(KERN_INFO | |
1024 | "Enabled Interrupt-remapping\n"); | |
1025 | } else | |
1026 | printk(KERN_ERR | |
1027 | "Failed to enable Interrupt-remapping and x2apic\n"); | |
1028 | #else | |
1029 | if (!cpu_has_x2apic) | |
1030 | return; | |
1031 | ||
1032 | if (x2apic_preenabled) | |
1033 | panic("x2apic enabled prior OS handover," | |
1034 | " enable CONFIG_INTR_REMAP"); | |
1035 | ||
1036 | printk(KERN_INFO "Enable CONFIG_INTR_REMAP for enabling intr-remapping " | |
1037 | " and x2apic\n"); | |
1038 | #endif | |
1039 | ||
1040 | return; | |
1041 | } | |
1042 | ||
1da177e4 LT |
1043 | /* |
1044 | * Detect and enable local APICs on non-SMP boards. | |
1045 | * Original code written by Keir Fraser. | |
1046 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 1047 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 1048 | */ |
0e078e2f | 1049 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1050 | { |
1051 | if (!cpu_has_apic) { | |
1052 | printk(KERN_INFO "No local APIC present\n"); | |
1053 | return -1; | |
1054 | } | |
1055 | ||
1056 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
c70dcb74 | 1057 | boot_cpu_physical_apicid = 0; |
1da177e4 LT |
1058 | return 0; |
1059 | } | |
1060 | ||
8643f9d0 YL |
1061 | void __init early_init_lapic_mapping(void) |
1062 | { | |
431ee79d | 1063 | unsigned long phys_addr; |
8643f9d0 YL |
1064 | |
1065 | /* | |
1066 | * If no local APIC can be found then go out | |
1067 | * : it means there is no mpatable and MADT | |
1068 | */ | |
1069 | if (!smp_found_config) | |
1070 | return; | |
1071 | ||
431ee79d | 1072 | phys_addr = mp_lapic_addr; |
8643f9d0 | 1073 | |
431ee79d | 1074 | set_fixmap_nocache(FIX_APIC_BASE, phys_addr); |
8643f9d0 | 1075 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
431ee79d | 1076 | APIC_BASE, phys_addr); |
8643f9d0 YL |
1077 | |
1078 | /* | |
1079 | * Fetch the APIC ID of the BSP in case we have a | |
1080 | * default configuration (or the MP table is broken). | |
1081 | */ | |
4c9961d5 | 1082 | boot_cpu_physical_apicid = read_apic_id(); |
8643f9d0 YL |
1083 | } |
1084 | ||
0e078e2f TG |
1085 | /** |
1086 | * init_apic_mappings - initialize APIC mappings | |
1087 | */ | |
1da177e4 LT |
1088 | void __init init_apic_mappings(void) |
1089 | { | |
6e1cb38a | 1090 | if (x2apic) { |
4c9961d5 | 1091 | boot_cpu_physical_apicid = read_apic_id(); |
6e1cb38a SS |
1092 | return; |
1093 | } | |
1094 | ||
1da177e4 LT |
1095 | /* |
1096 | * If no local APIC can be found then set up a fake all | |
1097 | * zeroes page to simulate the local APIC and another | |
1098 | * one for the IO-APIC. | |
1099 | */ | |
1100 | if (!smp_found_config && detect_init_APIC()) { | |
1101 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1102 | apic_phys = __pa(apic_phys); | |
1103 | } else | |
1104 | apic_phys = mp_lapic_addr; | |
1105 | ||
1106 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
7ffeeb1e YL |
1107 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
1108 | APIC_BASE, apic_phys); | |
1da177e4 LT |
1109 | |
1110 | /* | |
1111 | * Fetch the APIC ID of the BSP in case we have a | |
1112 | * default configuration (or the MP table is broken). | |
1113 | */ | |
4c9961d5 | 1114 | boot_cpu_physical_apicid = read_apic_id(); |
1da177e4 LT |
1115 | } |
1116 | ||
1117 | /* | |
0e078e2f TG |
1118 | * This initializes the IO-APIC and APIC hardware if this is |
1119 | * a UP kernel. | |
1da177e4 | 1120 | */ |
0e078e2f | 1121 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1122 | { |
0e078e2f TG |
1123 | if (disable_apic) { |
1124 | printk(KERN_INFO "Apic disabled\n"); | |
1125 | return -1; | |
1126 | } | |
1127 | if (!cpu_has_apic) { | |
1128 | disable_apic = 1; | |
1129 | printk(KERN_INFO "Apic disabled by BIOS\n"); | |
1130 | return -1; | |
1131 | } | |
1da177e4 | 1132 | |
6e1cb38a SS |
1133 | enable_IR_x2apic(); |
1134 | setup_apic_routing(); | |
1135 | ||
0e078e2f | 1136 | verify_local_APIC(); |
1da177e4 | 1137 | |
b5841765 GC |
1138 | connect_bsp_APIC(); |
1139 | ||
b6df1b8b | 1140 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
c70dcb74 | 1141 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); |
1da177e4 | 1142 | |
0e078e2f | 1143 | setup_local_APIC(); |
1da177e4 | 1144 | |
739f33b3 AK |
1145 | /* |
1146 | * Now enable IO-APICs, actually call clear_IO_APIC | |
1147 | * We need clear_IO_APIC before enabling vector on BP | |
1148 | */ | |
1149 | if (!skip_ioapic_setup && nr_ioapics) | |
1150 | enable_IO_APIC(); | |
1151 | ||
acae7d90 MR |
1152 | if (!smp_found_config || skip_ioapic_setup || !nr_ioapics) |
1153 | localise_nmi_watchdog(); | |
739f33b3 AK |
1154 | end_local_APIC_setup(); |
1155 | ||
0e078e2f TG |
1156 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
1157 | setup_IO_APIC(); | |
1158 | else | |
1159 | nr_ioapics = 0; | |
1160 | setup_boot_APIC_clock(); | |
1161 | check_nmi_watchdog(); | |
1162 | return 0; | |
1da177e4 LT |
1163 | } |
1164 | ||
1165 | /* | |
0e078e2f | 1166 | * Local APIC interrupts |
1da177e4 LT |
1167 | */ |
1168 | ||
0e078e2f TG |
1169 | /* |
1170 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1171 | */ | |
1172 | asmlinkage void smp_spurious_interrupt(void) | |
1da177e4 | 1173 | { |
0e078e2f TG |
1174 | unsigned int v; |
1175 | exit_idle(); | |
1176 | irq_enter(); | |
1da177e4 | 1177 | /* |
0e078e2f TG |
1178 | * Check if this really is a spurious interrupt and ACK it |
1179 | * if it is a vectored one. Just in case... | |
1180 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 1181 | */ |
0e078e2f TG |
1182 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
1183 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1184 | ack_APIC_irq(); | |
c4d58cbd | 1185 | |
0e078e2f TG |
1186 | add_pda(irq_spurious_count, 1); |
1187 | irq_exit(); | |
1188 | } | |
1da177e4 | 1189 | |
0e078e2f TG |
1190 | /* |
1191 | * This interrupt should never happen with our APIC/SMP architecture | |
1192 | */ | |
1193 | asmlinkage void smp_error_interrupt(void) | |
1194 | { | |
1195 | unsigned int v, v1; | |
1da177e4 | 1196 | |
0e078e2f TG |
1197 | exit_idle(); |
1198 | irq_enter(); | |
1199 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1200 | v = apic_read(APIC_ESR); | |
1201 | apic_write(APIC_ESR, 0); | |
1202 | v1 = apic_read(APIC_ESR); | |
1203 | ack_APIC_irq(); | |
1204 | atomic_inc(&irq_err_count); | |
ba7eda4c | 1205 | |
0e078e2f TG |
1206 | /* Here is what the APIC error bits mean: |
1207 | 0: Send CS error | |
1208 | 1: Receive CS error | |
1209 | 2: Send accept error | |
1210 | 3: Receive accept error | |
1211 | 4: Reserved | |
1212 | 5: Send illegal vector | |
1213 | 6: Received illegal vector | |
1214 | 7: Illegal register address | |
1215 | */ | |
1216 | printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n", | |
1217 | smp_processor_id(), v , v1); | |
1218 | irq_exit(); | |
1da177e4 LT |
1219 | } |
1220 | ||
b5841765 GC |
1221 | /** |
1222 | * * connect_bsp_APIC - attach the APIC to the interrupt system | |
1223 | * */ | |
1224 | void __init connect_bsp_APIC(void) | |
1225 | { | |
1226 | enable_apic_mode(); | |
1227 | } | |
1228 | ||
0e078e2f | 1229 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 1230 | { |
0e078e2f TG |
1231 | /* Go back to Virtual Wire compatibility mode */ |
1232 | unsigned long value; | |
1da177e4 | 1233 | |
0e078e2f TG |
1234 | /* For the spurious interrupt use vector F, and enable it */ |
1235 | value = apic_read(APIC_SPIV); | |
1236 | value &= ~APIC_VECTOR_MASK; | |
1237 | value |= APIC_SPIV_APIC_ENABLED; | |
1238 | value |= 0xf; | |
1239 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 1240 | |
0e078e2f TG |
1241 | if (!virt_wire_setup) { |
1242 | /* | |
1243 | * For LVT0 make it edge triggered, active high, | |
1244 | * external and enabled | |
1245 | */ | |
1246 | value = apic_read(APIC_LVT0); | |
1247 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1248 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1249 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1250 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1251 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1252 | apic_write(APIC_LVT0, value); | |
1253 | } else { | |
1254 | /* Disable LVT0 */ | |
1255 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1256 | } | |
b8ce3359 | 1257 | |
0e078e2f TG |
1258 | /* For LVT1 make it edge triggered, active high, nmi and enabled */ |
1259 | value = apic_read(APIC_LVT1); | |
1260 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1261 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1262 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1263 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1264 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1265 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
1266 | } |
1267 | ||
be8a5685 AS |
1268 | void __cpuinit generic_processor_info(int apicid, int version) |
1269 | { | |
1270 | int cpu; | |
1271 | cpumask_t tmp_map; | |
1272 | ||
1273 | if (num_processors >= NR_CPUS) { | |
1274 | printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." | |
1275 | " Processor ignored.\n", NR_CPUS); | |
1276 | return; | |
1277 | } | |
1278 | ||
1279 | if (num_processors >= maxcpus) { | |
1280 | printk(KERN_WARNING "WARNING: maxcpus limit of %i reached." | |
1281 | " Processor ignored.\n", maxcpus); | |
1282 | return; | |
1283 | } | |
1284 | ||
1285 | num_processors++; | |
1286 | cpus_complement(tmp_map, cpu_present_map); | |
1287 | cpu = first_cpu(tmp_map); | |
1288 | ||
1289 | physid_set(apicid, phys_cpu_present_map); | |
1290 | if (apicid == boot_cpu_physical_apicid) { | |
1291 | /* | |
1292 | * x86_bios_cpu_apicid is required to have processors listed | |
1293 | * in same order as logical cpu numbers. Hence the first | |
1294 | * entry is BSP, and so on. | |
1295 | */ | |
1296 | cpu = 0; | |
1297 | } | |
e0da3364 YL |
1298 | if (apicid > max_physical_apicid) |
1299 | max_physical_apicid = apicid; | |
1300 | ||
be8a5685 | 1301 | /* are we being called early in kernel startup? */ |
23ca4bba MT |
1302 | if (early_per_cpu_ptr(x86_cpu_to_apicid)) { |
1303 | u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid); | |
1304 | u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); | |
be8a5685 AS |
1305 | |
1306 | cpu_to_apicid[cpu] = apicid; | |
1307 | bios_cpu_apicid[cpu] = apicid; | |
1308 | } else { | |
1309 | per_cpu(x86_cpu_to_apicid, cpu) = apicid; | |
1310 | per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1311 | } | |
1312 | ||
1313 | cpu_set(cpu, cpu_possible_map); | |
1314 | cpu_set(cpu, cpu_present_map); | |
1315 | } | |
1316 | ||
0c81c746 SS |
1317 | int hard_smp_processor_id(void) |
1318 | { | |
1319 | return read_apic_id(); | |
1320 | } | |
1321 | ||
89039b37 | 1322 | /* |
0e078e2f | 1323 | * Power management |
89039b37 | 1324 | */ |
0e078e2f TG |
1325 | #ifdef CONFIG_PM |
1326 | ||
1327 | static struct { | |
1328 | /* 'active' is true if the local APIC was enabled by us and | |
1329 | not the BIOS; this signifies that we are also responsible | |
1330 | for disabling it before entering apm/acpi suspend */ | |
1331 | int active; | |
1332 | /* r/w apic fields */ | |
1333 | unsigned int apic_id; | |
1334 | unsigned int apic_taskpri; | |
1335 | unsigned int apic_ldr; | |
1336 | unsigned int apic_dfr; | |
1337 | unsigned int apic_spiv; | |
1338 | unsigned int apic_lvtt; | |
1339 | unsigned int apic_lvtpc; | |
1340 | unsigned int apic_lvt0; | |
1341 | unsigned int apic_lvt1; | |
1342 | unsigned int apic_lvterr; | |
1343 | unsigned int apic_tmict; | |
1344 | unsigned int apic_tdcr; | |
1345 | unsigned int apic_thmr; | |
1346 | } apic_pm_state; | |
1347 | ||
1348 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1349 | { | |
1350 | unsigned long flags; | |
1351 | int maxlvt; | |
89039b37 | 1352 | |
0e078e2f TG |
1353 | if (!apic_pm_state.active) |
1354 | return 0; | |
89039b37 | 1355 | |
0e078e2f | 1356 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 1357 | |
2d7a66d0 | 1358 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
1359 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
1360 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1361 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1362 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1363 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1364 | if (maxlvt >= 4) | |
1365 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1366 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1367 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1368 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1369 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1370 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
1371 | #ifdef CONFIG_X86_MCE_INTEL | |
1372 | if (maxlvt >= 5) | |
1373 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1374 | #endif | |
1375 | local_irq_save(flags); | |
1376 | disable_local_APIC(); | |
1377 | local_irq_restore(flags); | |
1378 | return 0; | |
1da177e4 LT |
1379 | } |
1380 | ||
0e078e2f | 1381 | static int lapic_resume(struct sys_device *dev) |
1da177e4 | 1382 | { |
0e078e2f TG |
1383 | unsigned int l, h; |
1384 | unsigned long flags; | |
1385 | int maxlvt; | |
1da177e4 | 1386 | |
0e078e2f TG |
1387 | if (!apic_pm_state.active) |
1388 | return 0; | |
89b831ef | 1389 | |
0e078e2f | 1390 | maxlvt = lapic_get_maxlvt(); |
1da177e4 | 1391 | |
0e078e2f | 1392 | local_irq_save(flags); |
6e1cb38a SS |
1393 | if (!x2apic) { |
1394 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1395 | l &= ~MSR_IA32_APICBASE_BASE; | |
1396 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
1397 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1398 | } else | |
1399 | enable_x2apic(); | |
1400 | ||
0e078e2f TG |
1401 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
1402 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
1403 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
1404 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
1405 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
1406 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
1407 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
1408 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
1409 | #ifdef CONFIG_X86_MCE_INTEL | |
1410 | if (maxlvt >= 5) | |
1411 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
1412 | #endif | |
1413 | if (maxlvt >= 4) | |
1414 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
1415 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
1416 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
1417 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
1418 | apic_write(APIC_ESR, 0); | |
1419 | apic_read(APIC_ESR); | |
1420 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
1421 | apic_write(APIC_ESR, 0); | |
1422 | apic_read(APIC_ESR); | |
1423 | local_irq_restore(flags); | |
1424 | return 0; | |
1425 | } | |
b8ce3359 | 1426 | |
0e078e2f TG |
1427 | static struct sysdev_class lapic_sysclass = { |
1428 | .name = "lapic", | |
1429 | .resume = lapic_resume, | |
1430 | .suspend = lapic_suspend, | |
1431 | }; | |
b8ce3359 | 1432 | |
0e078e2f | 1433 | static struct sys_device device_lapic = { |
e83a5fdc HS |
1434 | .id = 0, |
1435 | .cls = &lapic_sysclass, | |
0e078e2f | 1436 | }; |
b8ce3359 | 1437 | |
0e078e2f TG |
1438 | static void __cpuinit apic_pm_activate(void) |
1439 | { | |
1440 | apic_pm_state.active = 1; | |
1da177e4 LT |
1441 | } |
1442 | ||
0e078e2f | 1443 | static int __init init_lapic_sysfs(void) |
1da177e4 | 1444 | { |
0e078e2f | 1445 | int error; |
e83a5fdc | 1446 | |
0e078e2f TG |
1447 | if (!cpu_has_apic) |
1448 | return 0; | |
1449 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
e83a5fdc | 1450 | |
0e078e2f TG |
1451 | error = sysdev_class_register(&lapic_sysclass); |
1452 | if (!error) | |
1453 | error = sysdev_register(&device_lapic); | |
1454 | return error; | |
1da177e4 | 1455 | } |
0e078e2f TG |
1456 | device_initcall(init_lapic_sysfs); |
1457 | ||
1458 | #else /* CONFIG_PM */ | |
1459 | ||
1460 | static void apic_pm_activate(void) { } | |
1461 | ||
1462 | #endif /* CONFIG_PM */ | |
1da177e4 LT |
1463 | |
1464 | /* | |
f8bf3c65 | 1465 | * apic_is_clustered_box() -- Check if we can expect good TSC |
1da177e4 LT |
1466 | * |
1467 | * Thus far, the major user of this is IBM's Summit2 series: | |
1468 | * | |
637029c6 | 1469 | * Clustered boxes may have unsynced TSC problems if they are |
1da177e4 LT |
1470 | * multi-chassis. Use available data to take a good guess. |
1471 | * If in doubt, go HPET. | |
1472 | */ | |
f8bf3c65 | 1473 | __cpuinit int apic_is_clustered_box(void) |
1da177e4 LT |
1474 | { |
1475 | int i, clusters, zeros; | |
1476 | unsigned id; | |
322850af | 1477 | u16 *bios_cpu_apicid; |
1da177e4 LT |
1478 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); |
1479 | ||
322850af YL |
1480 | /* |
1481 | * there is not this kind of box with AMD CPU yet. | |
1482 | * Some AMD box with quadcore cpu and 8 sockets apicid | |
1483 | * will be [4, 0x23] or [8, 0x27] could be thought to | |
f8fffa45 | 1484 | * vsmp box still need checking... |
322850af | 1485 | */ |
1cb68487 | 1486 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box()) |
322850af YL |
1487 | return 0; |
1488 | ||
23ca4bba | 1489 | bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); |
376ec33f | 1490 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 LT |
1491 | |
1492 | for (i = 0; i < NR_CPUS; i++) { | |
e8c10ef9 | 1493 | /* are we being called early in kernel startup? */ |
693e3c56 MT |
1494 | if (bios_cpu_apicid) { |
1495 | id = bios_cpu_apicid[i]; | |
e8c10ef9 | 1496 | } |
1497 | else if (i < nr_cpu_ids) { | |
1498 | if (cpu_present(i)) | |
1499 | id = per_cpu(x86_bios_cpu_apicid, i); | |
1500 | else | |
1501 | continue; | |
1502 | } | |
1503 | else | |
1504 | break; | |
1505 | ||
1da177e4 LT |
1506 | if (id != BAD_APICID) |
1507 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
1508 | } | |
1509 | ||
1510 | /* Problem: Partially populated chassis may not have CPUs in some of | |
1511 | * the APIC clusters they have been allocated. Only present CPUs have | |
602a54a8 | 1512 | * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. |
1513 | * Since clusters are allocated sequentially, count zeros only if | |
1514 | * they are bounded by ones. | |
1da177e4 LT |
1515 | */ |
1516 | clusters = 0; | |
1517 | zeros = 0; | |
1518 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
1519 | if (test_bit(i, clustermap)) { | |
1520 | clusters += 1 + zeros; | |
1521 | zeros = 0; | |
1522 | } else | |
1523 | ++zeros; | |
1524 | } | |
1525 | ||
1cb68487 RT |
1526 | /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are |
1527 | * not guaranteed to be synced between boards | |
1528 | */ | |
1529 | if (is_vsmp_box() && clusters > 1) | |
1530 | return 1; | |
1531 | ||
1da177e4 | 1532 | /* |
f8bf3c65 | 1533 | * If clusters > 2, then should be multi-chassis. |
1da177e4 LT |
1534 | * May have to revisit this when multi-core + hyperthreaded CPUs come |
1535 | * out, but AFAIK this will work even for them. | |
1536 | */ | |
1537 | return (clusters > 2); | |
1538 | } | |
1539 | ||
6e1cb38a SS |
1540 | static __init int setup_nox2apic(char *str) |
1541 | { | |
1542 | disable_x2apic = 1; | |
1543 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_X2APIC); | |
1544 | return 0; | |
1545 | } | |
1546 | early_param("nox2apic", setup_nox2apic); | |
1547 | ||
1548 | ||
1da177e4 | 1549 | /* |
0e078e2f | 1550 | * APIC command line parameters |
1da177e4 | 1551 | */ |
0e078e2f | 1552 | static int __init apic_set_verbosity(char *str) |
1da177e4 | 1553 | { |
0e078e2f TG |
1554 | if (str == NULL) { |
1555 | skip_ioapic_setup = 0; | |
1556 | ioapic_force = 1; | |
1557 | return 0; | |
1da177e4 | 1558 | } |
0e078e2f TG |
1559 | if (strcmp("debug", str) == 0) |
1560 | apic_verbosity = APIC_DEBUG; | |
1561 | else if (strcmp("verbose", str) == 0) | |
1562 | apic_verbosity = APIC_VERBOSE; | |
1563 | else { | |
1564 | printk(KERN_WARNING "APIC Verbosity level %s not recognised" | |
1565 | " use apic=verbose or apic=debug\n", str); | |
1566 | return -EINVAL; | |
1da177e4 LT |
1567 | } |
1568 | ||
1da177e4 LT |
1569 | return 0; |
1570 | } | |
0e078e2f | 1571 | early_param("apic", apic_set_verbosity); |
1da177e4 | 1572 | |
6935d1f9 TG |
1573 | static __init int setup_disableapic(char *str) |
1574 | { | |
1da177e4 | 1575 | disable_apic = 1; |
9175fc06 | 1576 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
2c8c0e6b AK |
1577 | return 0; |
1578 | } | |
1579 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 1580 | |
2c8c0e6b | 1581 | /* same as disableapic, for compatibility */ |
6935d1f9 TG |
1582 | static __init int setup_nolapic(char *str) |
1583 | { | |
2c8c0e6b | 1584 | return setup_disableapic(str); |
6935d1f9 | 1585 | } |
2c8c0e6b | 1586 | early_param("nolapic", setup_nolapic); |
1da177e4 | 1587 | |
2e7c2838 LT |
1588 | static int __init parse_lapic_timer_c2_ok(char *arg) |
1589 | { | |
1590 | local_apic_timer_c2_ok = 1; | |
1591 | return 0; | |
1592 | } | |
1593 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
1594 | ||
36fef094 | 1595 | static int __init parse_disable_apic_timer(char *arg) |
6935d1f9 | 1596 | { |
1da177e4 | 1597 | disable_apic_timer = 1; |
36fef094 CG |
1598 | return 0; |
1599 | } | |
1600 | early_param("noapictimer", parse_disable_apic_timer); | |
1601 | ||
1602 | static int __init parse_nolapic_timer(char *arg) | |
1603 | { | |
1604 | disable_apic_timer = 1; | |
1605 | return 0; | |
6935d1f9 | 1606 | } |
36fef094 | 1607 | early_param("nolapic_timer", parse_nolapic_timer); |
73dea47f | 1608 | |
0c3749c4 AK |
1609 | static __init int setup_apicpmtimer(char *s) |
1610 | { | |
1611 | apic_calibrate_pmtmr = 1; | |
7fd67843 | 1612 | notsc_setup(NULL); |
b8ce3359 | 1613 | return 0; |
0c3749c4 AK |
1614 | } |
1615 | __setup("apicpmtimer", setup_apicpmtimer); | |
1616 | ||
1e934dda YL |
1617 | static int __init lapic_insert_resource(void) |
1618 | { | |
1619 | if (!apic_phys) | |
1620 | return -1; | |
1621 | ||
1622 | /* Put local APIC into the resource map. */ | |
1623 | lapic_resource.start = apic_phys; | |
1624 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
1625 | insert_resource(&iomem_resource, &lapic_resource); | |
1626 | ||
1627 | return 0; | |
1628 | } | |
1629 | ||
1630 | /* | |
1631 | * need call insert after e820_reserve_resources() | |
1632 | * that is using request_resource | |
1633 | */ | |
1634 | late_initcall(lapic_insert_resource); |