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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
d25bf7e5 | 26 | #include <linux/module.h> |
39928722 | 27 | #include <linux/ioport.h> |
ba7eda4c | 28 | #include <linux/clockchips.h> |
70a20025 | 29 | #include <linux/acpi_pmtmr.h> |
1da177e4 LT |
30 | |
31 | #include <asm/atomic.h> | |
32 | #include <asm/smp.h> | |
33 | #include <asm/mtrr.h> | |
34 | #include <asm/mpspec.h> | |
35 | #include <asm/pgalloc.h> | |
36 | #include <asm/mach_apic.h> | |
75152114 | 37 | #include <asm/nmi.h> |
95833c83 | 38 | #include <asm/idle.h> |
73dea47f AK |
39 | #include <asm/proto.h> |
40 | #include <asm/timex.h> | |
2d0c87c3 | 41 | #include <asm/hpet.h> |
2c8c0e6b | 42 | #include <asm/apic.h> |
1da177e4 LT |
43 | |
44 | int apic_verbosity; | |
fb79d22e | 45 | int disable_apic_timer __cpuinitdata; |
bc1d99c1 | 46 | static int apic_calibrate_pmtmr __initdata; |
1da177e4 | 47 | |
2e7c2838 LT |
48 | /* Local APIC timer works in C2? */ |
49 | int local_apic_timer_c2_ok; | |
50 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
51 | ||
39928722 AD |
52 | static struct resource lapic_resource = { |
53 | .name = "Local APIC", | |
54 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
55 | }; | |
56 | ||
d03030e9 TG |
57 | static unsigned int calibration_result; |
58 | ||
ba7eda4c TG |
59 | static int lapic_next_event(unsigned long delta, |
60 | struct clock_event_device *evt); | |
61 | static void lapic_timer_setup(enum clock_event_mode mode, | |
62 | struct clock_event_device *evt); | |
63 | ||
64 | static void lapic_timer_broadcast(cpumask_t mask); | |
65 | ||
66 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen); | |
67 | ||
68 | static struct clock_event_device lapic_clockevent = { | |
69 | .name = "lapic", | |
70 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
71 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
72 | .shift = 32, | |
73 | .set_mode = lapic_timer_setup, | |
74 | .set_next_event = lapic_next_event, | |
75 | .broadcast = lapic_timer_broadcast, | |
76 | .rating = 100, | |
77 | .irq = -1, | |
78 | }; | |
79 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
80 | ||
81 | static int lapic_next_event(unsigned long delta, | |
82 | struct clock_event_device *evt) | |
83 | { | |
84 | apic_write(APIC_TMICT, delta); | |
85 | return 0; | |
86 | } | |
87 | ||
88 | static void lapic_timer_setup(enum clock_event_mode mode, | |
89 | struct clock_event_device *evt) | |
90 | { | |
91 | unsigned long flags; | |
92 | unsigned int v; | |
93 | ||
94 | /* Lapic used as dummy for broadcast ? */ | |
95 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
96 | return; | |
97 | ||
98 | local_irq_save(flags); | |
99 | ||
100 | switch (mode) { | |
101 | case CLOCK_EVT_MODE_PERIODIC: | |
102 | case CLOCK_EVT_MODE_ONESHOT: | |
103 | __setup_APIC_LVTT(calibration_result, | |
104 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
105 | break; | |
106 | case CLOCK_EVT_MODE_UNUSED: | |
107 | case CLOCK_EVT_MODE_SHUTDOWN: | |
108 | v = apic_read(APIC_LVTT); | |
109 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
110 | apic_write(APIC_LVTT, v); | |
111 | break; | |
112 | case CLOCK_EVT_MODE_RESUME: | |
113 | /* Nothing to do here */ | |
114 | break; | |
115 | } | |
116 | ||
117 | local_irq_restore(flags); | |
118 | } | |
119 | ||
120 | /* | |
121 | * Local APIC timer broadcast function | |
122 | */ | |
123 | static void lapic_timer_broadcast(cpumask_t mask) | |
124 | { | |
125 | #ifdef CONFIG_SMP | |
126 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
127 | #endif | |
128 | } | |
129 | ||
1da177e4 LT |
130 | static void apic_pm_activate(void); |
131 | ||
8339e9fb FLV |
132 | void apic_wait_icr_idle(void) |
133 | { | |
134 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
135 | cpu_relax(); | |
136 | } | |
137 | ||
3c6bb07a | 138 | u32 safe_apic_wait_icr_idle(void) |
8339e9fb | 139 | { |
3c6bb07a | 140 | u32 send_status; |
8339e9fb FLV |
141 | int timeout; |
142 | ||
143 | timeout = 0; | |
144 | do { | |
145 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
146 | if (!send_status) | |
147 | break; | |
148 | udelay(100); | |
149 | } while (timeout++ < 1000); | |
150 | ||
151 | return send_status; | |
152 | } | |
153 | ||
1da177e4 LT |
154 | void enable_NMI_through_LVT0 (void * dummy) |
155 | { | |
11a8e778 | 156 | unsigned int v; |
6935d1f9 TG |
157 | |
158 | /* unmask and set to NMI */ | |
159 | v = APIC_DM_NMI; | |
11a8e778 | 160 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
161 | } |
162 | ||
37e650c7 | 163 | int lapic_get_maxlvt(void) |
1da177e4 | 164 | { |
11a8e778 | 165 | unsigned int v, maxlvt; |
1da177e4 LT |
166 | |
167 | v = apic_read(APIC_LVR); | |
1da177e4 LT |
168 | maxlvt = GET_APIC_MAXLVT(v); |
169 | return maxlvt; | |
170 | } | |
171 | ||
172 | void clear_local_APIC(void) | |
173 | { | |
174 | int maxlvt; | |
175 | unsigned int v; | |
176 | ||
37e650c7 | 177 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
178 | |
179 | /* | |
704fc59e | 180 | * Masking an LVT entry can trigger a local APIC error |
1da177e4 LT |
181 | * if the vector is zero. Mask LVTERR first to prevent this. |
182 | */ | |
183 | if (maxlvt >= 3) { | |
184 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
11a8e778 | 185 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); |
1da177e4 LT |
186 | } |
187 | /* | |
188 | * Careful: we have to set masks only first to deassert | |
189 | * any level-triggered sources. | |
190 | */ | |
191 | v = apic_read(APIC_LVTT); | |
11a8e778 | 192 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); |
1da177e4 | 193 | v = apic_read(APIC_LVT0); |
11a8e778 | 194 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 | 195 | v = apic_read(APIC_LVT1); |
11a8e778 | 196 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); |
1da177e4 LT |
197 | if (maxlvt >= 4) { |
198 | v = apic_read(APIC_LVTPC); | |
11a8e778 | 199 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); |
1da177e4 LT |
200 | } |
201 | ||
202 | /* | |
203 | * Clean APIC state for other OSs: | |
204 | */ | |
11a8e778 AK |
205 | apic_write(APIC_LVTT, APIC_LVT_MASKED); |
206 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
207 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
1da177e4 | 208 | if (maxlvt >= 3) |
11a8e778 | 209 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); |
1da177e4 | 210 | if (maxlvt >= 4) |
11a8e778 | 211 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); |
5a40b7c2 AK |
212 | apic_write(APIC_ESR, 0); |
213 | apic_read(APIC_ESR); | |
1da177e4 LT |
214 | } |
215 | ||
208fb931 | 216 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 217 | { |
a8fcf1a2 AK |
218 | /* Go back to Virtual Wire compatibility mode */ |
219 | unsigned long value; | |
208fb931 | 220 | |
a8fcf1a2 AK |
221 | /* For the spurious interrupt use vector F, and enable it */ |
222 | value = apic_read(APIC_SPIV); | |
223 | value &= ~APIC_VECTOR_MASK; | |
224 | value |= APIC_SPIV_APIC_ENABLED; | |
225 | value |= 0xf; | |
226 | apic_write(APIC_SPIV, value); | |
227 | ||
228 | if (!virt_wire_setup) { | |
bc1d99c1 CW |
229 | /* |
230 | * For LVT0 make it edge triggered, active high, | |
231 | * external and enabled | |
232 | */ | |
a8fcf1a2 AK |
233 | value = apic_read(APIC_LVT0); |
234 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
208fb931 | 235 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | |
a8fcf1a2 | 236 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED ); |
208fb931 | 237 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; |
a8fcf1a2 AK |
238 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); |
239 | apic_write(APIC_LVT0, value); | |
240 | } else { | |
241 | /* Disable LVT0 */ | |
242 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
208fb931 | 243 | } |
a8fcf1a2 AK |
244 | |
245 | /* For LVT1 make it edge triggered, active high, nmi and enabled */ | |
246 | value = apic_read(APIC_LVT1); | |
247 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
248 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
249 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
250 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
251 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
252 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
253 | } |
254 | ||
255 | void disable_local_APIC(void) | |
256 | { | |
257 | unsigned int value; | |
258 | ||
259 | clear_local_APIC(); | |
260 | ||
261 | /* | |
262 | * Disable APIC (implies clearing of registers | |
263 | * for 82489DX!). | |
264 | */ | |
265 | value = apic_read(APIC_SPIV); | |
266 | value &= ~APIC_SPIV_APIC_ENABLED; | |
11a8e778 | 267 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
268 | } |
269 | ||
9b7711f0 HS |
270 | void lapic_shutdown(void) |
271 | { | |
272 | unsigned long flags; | |
273 | ||
274 | if (!cpu_has_apic) | |
275 | return; | |
276 | ||
277 | local_irq_save(flags); | |
278 | ||
279 | disable_local_APIC(); | |
280 | ||
281 | local_irq_restore(flags); | |
282 | } | |
283 | ||
1da177e4 LT |
284 | /* |
285 | * This is to verify that we're looking at a real local APIC. | |
286 | * Check these against your board if the CPUs aren't getting | |
287 | * started for no apparent reason. | |
288 | */ | |
289 | int __init verify_local_APIC(void) | |
290 | { | |
291 | unsigned int reg0, reg1; | |
292 | ||
293 | /* | |
294 | * The version register is read-only in a real APIC. | |
295 | */ | |
296 | reg0 = apic_read(APIC_LVR); | |
297 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
298 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
299 | reg1 = apic_read(APIC_LVR); | |
300 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
301 | ||
302 | /* | |
303 | * The two version reads above should print the same | |
304 | * numbers. If the second one is different, then we | |
305 | * poke at a non-APIC. | |
306 | */ | |
307 | if (reg1 != reg0) | |
308 | return 0; | |
309 | ||
310 | /* | |
311 | * Check if the version looks reasonably. | |
312 | */ | |
313 | reg1 = GET_APIC_VERSION(reg0); | |
314 | if (reg1 == 0x00 || reg1 == 0xff) | |
315 | return 0; | |
37e650c7 | 316 | reg1 = lapic_get_maxlvt(); |
1da177e4 LT |
317 | if (reg1 < 0x02 || reg1 == 0xff) |
318 | return 0; | |
319 | ||
320 | /* | |
321 | * The ID register is read/write in a real APIC. | |
322 | */ | |
323 | reg0 = apic_read(APIC_ID); | |
324 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); | |
325 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); | |
326 | reg1 = apic_read(APIC_ID); | |
327 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); | |
328 | apic_write(APIC_ID, reg0); | |
329 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
330 | return 0; | |
331 | ||
332 | /* | |
333 | * The next two are just to see if we have sane values. | |
334 | * They're only really relevant if we're in Virtual Wire | |
335 | * compatibility mode, but most boxes are anymore. | |
336 | */ | |
337 | reg0 = apic_read(APIC_LVT0); | |
338 | apic_printk(APIC_DEBUG,"Getting LVT0: %x\n", reg0); | |
339 | reg1 = apic_read(APIC_LVT1); | |
340 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
341 | ||
342 | return 1; | |
343 | } | |
344 | ||
345 | void __init sync_Arb_IDs(void) | |
346 | { | |
347 | /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */ | |
348 | unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
349 | if (ver >= 0x14) /* P4 or higher */ | |
350 | return; | |
351 | ||
352 | /* | |
353 | * Wait for idle. | |
354 | */ | |
355 | apic_wait_icr_idle(); | |
356 | ||
357 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
11a8e778 | 358 | apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG |
1da177e4 LT |
359 | | APIC_DM_INIT); |
360 | } | |
361 | ||
1da177e4 LT |
362 | /* |
363 | * An initial setup of the virtual wire mode. | |
364 | */ | |
365 | void __init init_bsp_APIC(void) | |
366 | { | |
11a8e778 | 367 | unsigned int value; |
1da177e4 LT |
368 | |
369 | /* | |
370 | * Don't do the setup now if we have a SMP BIOS as the | |
371 | * through-I/O-APIC virtual wire mode might be active. | |
372 | */ | |
373 | if (smp_found_config || !cpu_has_apic) | |
374 | return; | |
375 | ||
376 | value = apic_read(APIC_LVR); | |
1da177e4 LT |
377 | |
378 | /* | |
379 | * Do not trust the local APIC being empty at bootup. | |
380 | */ | |
381 | clear_local_APIC(); | |
382 | ||
383 | /* | |
384 | * Enable APIC. | |
385 | */ | |
386 | value = apic_read(APIC_SPIV); | |
387 | value &= ~APIC_VECTOR_MASK; | |
388 | value |= APIC_SPIV_APIC_ENABLED; | |
389 | value |= APIC_SPIV_FOCUS_DISABLED; | |
390 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 391 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
392 | |
393 | /* | |
394 | * Set up the virtual wire mode. | |
395 | */ | |
11a8e778 | 396 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 397 | value = APIC_DM_NMI; |
11a8e778 | 398 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
399 | } |
400 | ||
e6982c67 | 401 | void __cpuinit setup_local_APIC (void) |
1da177e4 | 402 | { |
11a8e778 | 403 | unsigned int value, maxlvt; |
da7ed9f9 | 404 | int i, j; |
1da177e4 | 405 | |
1da177e4 | 406 | value = apic_read(APIC_LVR); |
1da177e4 | 407 | |
fe7414a2 | 408 | BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f); |
1da177e4 LT |
409 | |
410 | /* | |
411 | * Double-check whether this APIC is really registered. | |
412 | * This is meaningless in clustered apic mode, so we skip it. | |
413 | */ | |
414 | if (!apic_id_registered()) | |
415 | BUG(); | |
416 | ||
417 | /* | |
418 | * Intel recommends to set DFR, LDR and TPR before enabling | |
419 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
420 | * document number 292116). So here it goes... | |
421 | */ | |
422 | init_apic_ldr(); | |
423 | ||
424 | /* | |
425 | * Set Task Priority to 'accept all'. We never change this | |
426 | * later on. | |
427 | */ | |
428 | value = apic_read(APIC_TASKPRI); | |
429 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 430 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 431 | |
da7ed9f9 VG |
432 | /* |
433 | * After a crash, we no longer service the interrupts and a pending | |
434 | * interrupt from previous kernel might still have ISR bit set. | |
435 | * | |
436 | * Most probably by now CPU has serviced that pending interrupt and | |
437 | * it might not have done the ack_APIC_irq() because it thought, | |
438 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
439 | * does not clear the ISR bit and cpu thinks it has already serivced | |
440 | * the interrupt. Hence a vector might get locked. It was noticed | |
441 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
442 | */ | |
443 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
444 | value = apic_read(APIC_ISR + i*0x10); | |
445 | for (j = 31; j >= 0; j--) { | |
446 | if (value & (1<<j)) | |
447 | ack_APIC_irq(); | |
448 | } | |
449 | } | |
450 | ||
1da177e4 LT |
451 | /* |
452 | * Now that we are all set up, enable the APIC | |
453 | */ | |
454 | value = apic_read(APIC_SPIV); | |
455 | value &= ~APIC_VECTOR_MASK; | |
456 | /* | |
457 | * Enable APIC | |
458 | */ | |
459 | value |= APIC_SPIV_APIC_ENABLED; | |
460 | ||
3f14c746 AK |
461 | /* We always use processor focus */ |
462 | ||
1da177e4 LT |
463 | /* |
464 | * Set spurious IRQ vector | |
465 | */ | |
466 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 467 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
468 | |
469 | /* | |
470 | * Set up LVT0, LVT1: | |
471 | * | |
472 | * set up through-local-APIC on the BP's LINT0. This is not | |
473 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
474 | * we delegate interrupts to the 8259A. | |
475 | */ | |
476 | /* | |
477 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
478 | */ | |
479 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
a8fcf1a2 | 480 | if (!smp_processor_id() && !value) { |
1da177e4 | 481 | value = APIC_DM_EXTINT; |
bc1d99c1 CW |
482 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", |
483 | smp_processor_id()); | |
1da177e4 LT |
484 | } else { |
485 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
bc1d99c1 CW |
486 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
487 | smp_processor_id()); | |
1da177e4 | 488 | } |
11a8e778 | 489 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
490 | |
491 | /* | |
492 | * only the BP should see the LINT1 NMI signal, obviously. | |
493 | */ | |
494 | if (!smp_processor_id()) | |
495 | value = APIC_DM_NMI; | |
496 | else | |
497 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
11a8e778 | 498 | apic_write(APIC_LVT1, value); |
1da177e4 | 499 | |
61c11341 | 500 | { |
1da177e4 | 501 | unsigned oldvalue; |
37e650c7 | 502 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
503 | oldvalue = apic_read(APIC_ESR); |
504 | value = ERROR_APIC_VECTOR; // enables sending errors | |
11a8e778 | 505 | apic_write(APIC_LVTERR, value); |
1da177e4 LT |
506 | /* |
507 | * spec says clear errors after enabling vector. | |
508 | */ | |
509 | if (maxlvt > 3) | |
510 | apic_write(APIC_ESR, 0); | |
511 | value = apic_read(APIC_ESR); | |
512 | if (value != oldvalue) | |
513 | apic_printk(APIC_VERBOSE, | |
514 | "ESR value after enabling vector: %08x, after %08x\n", | |
515 | oldvalue, value); | |
1da177e4 LT |
516 | } |
517 | ||
518 | nmi_watchdog_default(); | |
f2802e7f | 519 | setup_apic_nmi_watchdog(NULL); |
1da177e4 LT |
520 | apic_pm_activate(); |
521 | } | |
522 | ||
523 | #ifdef CONFIG_PM | |
524 | ||
525 | static struct { | |
526 | /* 'active' is true if the local APIC was enabled by us and | |
527 | not the BIOS; this signifies that we are also responsible | |
528 | for disabling it before entering apm/acpi suspend */ | |
529 | int active; | |
530 | /* r/w apic fields */ | |
531 | unsigned int apic_id; | |
532 | unsigned int apic_taskpri; | |
533 | unsigned int apic_ldr; | |
534 | unsigned int apic_dfr; | |
535 | unsigned int apic_spiv; | |
536 | unsigned int apic_lvtt; | |
537 | unsigned int apic_lvtpc; | |
538 | unsigned int apic_lvt0; | |
539 | unsigned int apic_lvt1; | |
540 | unsigned int apic_lvterr; | |
541 | unsigned int apic_tmict; | |
542 | unsigned int apic_tdcr; | |
543 | unsigned int apic_thmr; | |
544 | } apic_pm_state; | |
545 | ||
0b9c33a7 | 546 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
547 | { |
548 | unsigned long flags; | |
f990fff4 | 549 | int maxlvt; |
1da177e4 LT |
550 | |
551 | if (!apic_pm_state.active) | |
552 | return 0; | |
553 | ||
37e650c7 | 554 | maxlvt = lapic_get_maxlvt(); |
f990fff4 | 555 | |
1da177e4 LT |
556 | apic_pm_state.apic_id = apic_read(APIC_ID); |
557 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); | |
558 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
559 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
560 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
561 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
f990fff4 KW |
562 | if (maxlvt >= 4) |
563 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1da177e4 LT |
564 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); |
565 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
566 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
567 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
568 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
f990fff4 KW |
569 | #ifdef CONFIG_X86_MCE_INTEL |
570 | if (maxlvt >= 5) | |
571 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
572 | #endif | |