[mirror_ubuntu-zesty-kernel.git] / arch / x86 / kernel / apic_64.c

/*
 *	Local APIC handling, local APIC timers
 *
 *	(c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
 *
 *	Fixes
 *	Maciej W. Rozycki	:	Bits for genuine 82489DX APICs;
 *					thanks to Eric Gilmore
 *					and Rolf G. Tews
 *					for testing these extensively.
 *	Maciej W. Rozycki	:	Various updates and fixes.
 *	Mikael Pettersson	:	Power Management for UP-APIC.
 *	Pavel Machek and
 *	Mikael Pettersson	:	PM converted to driver model.
 */

#include <linux/init.h>

#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/bootmem.h>
#include <linux/interrupt.h>
#include <linux/mc146818rtc.h>
#include <linux/kernel_stat.h>
#include <linux/sysdev.h>
#include <linux/module.h>
#include <linux/ioport.h>

#include <asm/atomic.h>
#include <asm/smp.h>
#include <asm/mtrr.h>
#include <asm/mpspec.h>
#include <asm/pgalloc.h>
#include <asm/mach_apic.h>
#include <asm/nmi.h>
#include <asm/idle.h>
#include <asm/proto.h>
#include <asm/timex.h>
#include <asm/hpet.h>
#include <asm/apic.h>

int apic_verbosity;
int apic_runs_main_timer;
int apic_calibrate_pmtmr __initdata;

int disable_apic_timer __initdata;

/* Local APIC timer works in C2? */
int local_apic_timer_c2_ok;
EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);

static struct resource *ioapic_resources;
static struct resource lapic_resource = {
	.name = "Local APIC",
	.flags = IORESOURCE_MEM | IORESOURCE_BUSY,
};

static unsigned int calibration_result;

/*
 * cpu_mask that denotes the CPUs that needs timer interrupt coming in as
 * IPIs in place of local APIC timers
 */
static cpumask_t timer_interrupt_broadcast_ipi_mask;

/* Using APIC to generate smp_local_timer_interrupt? */
int using_apic_timer __read_mostly = 0;

static void apic_pm_activate(void);

void apic_wait_icr_idle(void)
{
	while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
		cpu_relax();
}

unsigned int safe_apic_wait_icr_idle(void)
{
	unsigned int send_status;
	int timeout;

	timeout = 0;
	do {
		send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
		if (!send_status)
			break;
		udelay(100);
	} while (timeout++ < 1000);

	return send_status;
}

void enable_NMI_through_LVT0 (void * dummy)
{
	unsigned int v;

	/* unmask and set to NMI */
	v = APIC_DM_NMI;
	apic_write(APIC_LVT0, v);
}

int get_maxlvt(void)
{
	unsigned int v, maxlvt;

	v = apic_read(APIC_LVR);
	maxlvt = GET_APIC_MAXLVT(v);
	return maxlvt;
}

/*
 * 'what should we do if we get a hw irq event on an illegal vector'.
 * each architecture has to answer this themselves.
 */
void ack_bad_irq(unsigned int irq)
{
	printk("unexpected IRQ trap at vector %02x\n", irq);
	/*
	 * Currently unexpected vectors happen only on SMP and APIC.
	 * We _must_ ack these because every local APIC has only N
	 * irq slots per priority level, and a 'hanging, unacked' IRQ
	 * holds up an irq slot - in excessive cases (when multiple
	 * unexpected vectors occur) that might lock up the APIC
	 * completely.
	 * But don't ack when the APIC is disabled. -AK
	 */
	if (!disable_apic)
		ack_APIC_irq();
}

void clear_local_APIC(void)
{
	int maxlvt;
	unsigned int v;

	maxlvt = get_maxlvt();

	/*
	 * Masking an LVT entry can trigger a local APIC error
	 * if the vector is zero. Mask LVTERR first to prevent this.
	 */
	if (maxlvt >= 3) {
		v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
		apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
	}
	/*
	 * Careful: we have to set masks only first to deassert
	 * any level-triggered sources.
	 */
	v = apic_read(APIC_LVTT);
	apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
	v = apic_read(APIC_LVT0);
	apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
	v = apic_read(APIC_LVT1);
	apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
	if (maxlvt >= 4) {
		v = apic_read(APIC_LVTPC);
		apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
	}

	/*
	 * Clean APIC state for other OSs:
	 */
	apic_write(APIC_LVTT, APIC_LVT_MASKED);
	apic_write(APIC_LVT0, APIC_LVT_MASKED);
	apic_write(APIC_LVT1, APIC_LVT_MASKED);
	if (maxlvt >= 3)
		apic_write(APIC_LVTERR, APIC_LVT_MASKED);
	if (maxlvt >= 4)
		apic_write(APIC_LVTPC, APIC_LVT_MASKED);
	apic_write(APIC_ESR, 0);
	apic_read(APIC_ESR);
}

void disconnect_bsp_APIC(int virt_wire_setup)
{
	/* Go back to Virtual Wire compatibility mode */
	unsigned long value;

	/* For the spurious interrupt use vector F, and enable it */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	value |= APIC_SPIV_APIC_ENABLED;
	value |= 0xf;
	apic_write(APIC_SPIV, value);

	if (!virt_wire_setup) {
		/* For LVT0 make it edge triggered, active high, external and enabled */
		value = apic_read(APIC_LVT0);
		value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
			APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
		value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
		value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
		apic_write(APIC_LVT0, value);
	} else {
		/* Disable LVT0 */
		apic_write(APIC_LVT0, APIC_LVT_MASKED);
	}

	/* For LVT1 make it edge triggered, active high, nmi and enabled */
	value = apic_read(APIC_LVT1);
	value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
			APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
	value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
	value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
	apic_write(APIC_LVT1, value);
}

void disable_local_APIC(void)
{
	unsigned int value;

	clear_local_APIC();

	/*
	 * Disable APIC (implies clearing of registers
	 * for 82489DX!).
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_SPIV_APIC_ENABLED;
	apic_write(APIC_SPIV, value);
}

/*
 * This is to verify that we're looking at a real local APIC.
 * Check these against your board if the CPUs aren't getting
 * started for no apparent reason.
 */
int __init verify_local_APIC(void)
{
	unsigned int reg0, reg1;

	/*
	 * The version register is read-only in a real APIC.
	 */
	reg0 = apic_read(APIC_LVR);
	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
	apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
	reg1 = apic_read(APIC_LVR);
	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);

	/*
	 * The two version reads above should print the same
	 * numbers.  If the second one is different, then we
	 * poke at a non-APIC.
	 */
	if (reg1 != reg0)
		return 0;

	/*
	 * Check if the version looks reasonably.
	 */
	reg1 = GET_APIC_VERSION(reg0);
	if (reg1 == 0x00 || reg1 == 0xff)
		return 0;
	reg1 = get_maxlvt();
	if (reg1 < 0x02 || reg1 == 0xff)
		return 0;

	/*
	 * The ID register is read/write in a real APIC.
	 */
	reg0 = apic_read(APIC_ID);
	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
	apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
	reg1 = apic_read(APIC_ID);
	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
	apic_write(APIC_ID, reg0);
	if (reg1 != (reg0 ^ APIC_ID_MASK))
		return 0;

	/*
	 * The next two are just to see if we have sane values.
	 * They're only really relevant if we're in Virtual Wire
	 * compatibility mode, but most boxes are anymore.
	 */
	reg0 = apic_read(APIC_LVT0);
	apic_printk(APIC_DEBUG,"Getting LVT0: %x\n", reg0);
	reg1 = apic_read(APIC_LVT1);
	apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);

	return 1;
}

void __init sync_Arb_IDs(void)
{
	/* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
	unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
	if (ver >= 0x14)	/* P4 or higher */
		return;

	/*
	 * Wait for idle.
	 */
	apic_wait_icr_idle();

	apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
	apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
				| APIC_DM_INIT);
}

/*
 * An initial setup of the virtual wire mode.
 */
void __init init_bsp_APIC(void)
{
	unsigned int value;

	/*
	 * Don't do the setup now if we have a SMP BIOS as the
	 * through-I/O-APIC virtual wire mode might be active.
	 */
	if (smp_found_config || !cpu_has_apic)
		return;

	value = apic_read(APIC_LVR);

	/*
	 * Do not trust the local APIC being empty at bootup.
	 */
	clear_local_APIC();

	/*
	 * Enable APIC.
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	value |= APIC_SPIV_APIC_ENABLED;
	value |= APIC_SPIV_FOCUS_DISABLED;
	value |= SPURIOUS_APIC_VECTOR;
	apic_write(APIC_SPIV, value);

	/*
	 * Set up the virtual wire mode.
	 */
	apic_write(APIC_LVT0, APIC_DM_EXTINT);
	value = APIC_DM_NMI;
	apic_write(APIC_LVT1, value);
}

void __cpuinit setup_local_APIC (void)
{
	unsigned int value, maxlvt;
	int i, j;

	value = apic_read(APIC_LVR);

	BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f);

	/*
	 * Double-check whether this APIC is really registered.
	 * This is meaningless in clustered apic mode, so we skip it.
	 */
	if (!apic_id_registered())
		BUG();

	/*
	 * Intel recommends to set DFR, LDR and TPR before enabling
	 * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
	 * document number 292116).  So here it goes...
	 */
	init_apic_ldr();

	/*
	 * Set Task Priority to 'accept all'. We never change this
	 * later on.
	 */
	value = apic_read(APIC_TASKPRI);
	value &= ~APIC_TPRI_MASK;
	apic_write(APIC_TASKPRI, value);

	/*
	 * After a crash, we no longer service the interrupts and a pending
	 * interrupt from previous kernel might still have ISR bit set.
	 *
	 * Most probably by now CPU has serviced that pending interrupt and
	 * it might not have done the ack_APIC_irq() because it thought,
	 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
	 * does not clear the ISR bit and cpu thinks it has already serivced
	 * the interrupt. Hence a vector might get locked. It was noticed
	 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
	 */
	for (i = APIC_ISR_NR - 1; i >= 0; i--) {
		value = apic_read(APIC_ISR + i*0x10);
		for (j = 31; j >= 0; j--) {
			if (value & (1<<j))
				ack_APIC_irq();
		}
	}

	/*
	 * Now that we are all set up, enable the APIC
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	/*
	 * Enable APIC
	 */
	value |= APIC_SPIV_APIC_ENABLED;

	/* We always use processor focus */

	/*
	 * Set spurious IRQ vector
	 */
	value |= SPURIOUS_APIC_VECTOR;
	apic_write(APIC_SPIV, value);

	/*
	 * Set up LVT0, LVT1:
	 *
	 * set up through-local-APIC on the BP's LINT0. This is not
	 * strictly necessary in pure symmetric-IO mode, but sometimes
	 * we delegate interrupts to the 8259A.
	 */
	/*
	 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
	 */
	value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
	if (!smp_processor_id() && !value) {
		value = APIC_DM_EXTINT;
		apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", smp_processor_id());
	} else {
		value = APIC_DM_EXTINT | APIC_LVT_MASKED;
		apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id());
	}
	apic_write(APIC_LVT0, value);

	/*
	 * only the BP should see the LINT1 NMI signal, obviously.
	 */
	if (!smp_processor_id())
		value = APIC_DM_NMI;
	else
		value = APIC_DM_NMI | APIC_LVT_MASKED;
	apic_write(APIC_LVT1, value);

	{
		unsigned oldvalue;
		maxlvt = get_maxlvt();
		oldvalue = apic_read(APIC_ESR);
		value = ERROR_APIC_VECTOR;      // enables sending errors
		apic_write(APIC_LVTERR, value);
		/*
		 * spec says clear errors after enabling vector.
		 */
		if (maxlvt > 3)
			apic_write(APIC_ESR, 0);
		value = apic_read(APIC_ESR);
		if (value != oldvalue)
			apic_printk(APIC_VERBOSE,
			"ESR value after enabling vector: %08x, after %08x\n",
			oldvalue, value);
	}

	nmi_watchdog_default();
	setup_apic_nmi_watchdog(NULL);
	apic_pm_activate();
}

#ifdef CONFIG_PM

static struct {
	/* 'active' is true if the local APIC was enabled by us and
	   not the BIOS; this signifies that we are also responsible
	   for disabling it before entering apm/acpi suspend */
	int active;
	/* r/w apic fields */
	unsigned int apic_id;
	unsigned int apic_taskpri;
	unsigned int apic_ldr;
	unsigned int apic_dfr;
	unsigned int apic_spiv;
	unsigned int apic_lvtt;
	unsigned int apic_lvtpc;
	unsigned int apic_lvt0;
	unsigned int apic_lvt1;
	unsigned int apic_lvterr;
	unsigned int apic_tmict;
	unsigned int apic_tdcr;
	unsigned int apic_thmr;
} apic_pm_state;

static int lapic_suspend(struct sys_device *dev, pm_message_t state)
{
	unsigned long flags;
	int maxlvt;

	if (!apic_pm_state.active)
		return 0;

	maxlvt = get_maxlvt();

	apic_pm_state.apic_id = apic_read(APIC_ID);
	apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
	apic_pm_state.apic_ldr = apic_read(APIC_LDR);
	apic_pm_state.apic_dfr = apic_read(APIC_DFR);
	apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
	apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
	if (maxlvt >= 4)
		apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
	apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
	apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
	apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
	apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
	apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
#ifdef CONFIG_X86_MCE_INTEL
	if (maxlvt >= 5)
		apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Local APIC handling, local APIC timers
	3	*
	4	* (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
	5	*
	6	* Fixes
	7	* Maciej W. Rozycki : Bits for genuine 82489DX APICs;
	8	* thanks to Eric Gilmore
	9	* and Rolf G. Tews
	10	* for testing these extensively.
	11	* Maciej W. Rozycki : Various updates and fixes.
	12	* Mikael Pettersson : Power Management for UP-APIC.
	13	* Pavel Machek and
	14	* Mikael Pettersson : PM converted to driver model.
	15	*/
	16
1da177e4 LT	17	#include <linux/init.h>
	18
	19	#include <linux/mm.h>
1da177e4 LT	20	#include <linux/delay.h>
1da177e4 LT	21	#include <linux/bootmem.h>
1da177e4 LT	22	#include <linux/interrupt.h>
	23	#include <linux/mc146818rtc.h>
	24	#include <linux/kernel_stat.h>
	25	#include <linux/sysdev.h>
d25bf7e5	26	#include <linux/module.h>
39928722	27	#include <linux/ioport.h>
1da177e4 LT	28
	29	#include <asm/atomic.h>
	30	#include <asm/smp.h>
	31	#include <asm/mtrr.h>
	32	#include <asm/mpspec.h>
	33	#include <asm/pgalloc.h>
	34	#include <asm/mach_apic.h>
75152114	35	#include <asm/nmi.h>
95833c83	36	#include <asm/idle.h>
73dea47f AK	37	#include <asm/proto.h>
73dea47f AK	38	#include <asm/timex.h>
2d0c87c3	39	#include <asm/hpet.h>
2c8c0e6b	40	#include <asm/apic.h>
1da177e4 LT	41
1da177e4 LT	42	int apic_verbosity;
73dea47f	43	int apic_runs_main_timer;
0c3749c4	44	int apic_calibrate_pmtmr __initdata;
1da177e4 LT	45
	46	int disable_apic_timer __initdata;
	47
2e7c2838 LT	48	/* Local APIC timer works in C2? */
	49	int local_apic_timer_c2_ok;
	50	EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
	51
39928722 AD	52	static struct resource *ioapic_resources;
	53	static struct resource lapic_resource = {
	54	.name = "Local APIC",
	55	.flags = IORESOURCE_MEM \| IORESOURCE_BUSY,
	56	};
	57
d03030e9 TG	58	static unsigned int calibration_result;
d03030e9 TG	59
d25bf7e5 VP	60	/*
	61	* cpu_mask that denotes the CPUs that needs timer interrupt coming in as
	62	* IPIs in place of local APIC timers
	63	*/
	64	static cpumask_t timer_interrupt_broadcast_ipi_mask;
	65
1da177e4	66	/* Using APIC to generate smp_local_timer_interrupt? */
acae9d32	67	int using_apic_timer __read_mostly = 0;
1da177e4	68
1da177e4 LT	69	static void apic_pm_activate(void);
1da177e4 LT	70
8339e9fb FLV	71	void apic_wait_icr_idle(void)
	72	{
	73	while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
	74	cpu_relax();
	75	}
	76
	77	unsigned int safe_apic_wait_icr_idle(void)
	78	{
	79	unsigned int send_status;
	80	int timeout;
	81
	82	timeout = 0;
	83	do {
	84	send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
	85	if (!send_status)
	86	break;
	87	udelay(100);
	88	} while (timeout++ < 1000);
	89
	90	return send_status;
	91	}
	92
1da177e4 LT	93	void enable_NMI_through_LVT0 (void * dummy)
1da177e4 LT	94	{
11a8e778	95	unsigned int v;
6935d1f9 TG	96
	97	/* unmask and set to NMI */
	98	v = APIC_DM_NMI;
11a8e778	99	apic_write(APIC_LVT0, v);
1da177e4 LT	100	}
	101
	102	int get_maxlvt(void)
	103	{
11a8e778	104	unsigned int v, maxlvt;
1da177e4 LT	105
1da177e4 LT	106	v = apic_read(APIC_LVR);
1da177e4 LT	107	maxlvt = GET_APIC_MAXLVT(v);
	108	return maxlvt;
	109	}
	110
3777a959 AK	111	/*
	112	* 'what should we do if we get a hw irq event on an illegal vector'.
	113	* each architecture has to answer this themselves.
	114	*/
	115	void ack_bad_irq(unsigned int irq)
	116	{
	117	printk("unexpected IRQ trap at vector %02x\n", irq);
	118	/*
	119	* Currently unexpected vectors happen only on SMP and APIC.
	120	* We _must_ ack these because every local APIC has only N
	121	* irq slots per priority level, and a 'hanging, unacked' IRQ
	122	* holds up an irq slot - in excessive cases (when multiple
	123	* unexpected vectors occur) that might lock up the APIC
	124	* completely.
6935d1f9	125	* But don't ack when the APIC is disabled. -AK
3777a959 AK	126	*/
	127	if (!disable_apic)
	128	ack_APIC_irq();
	129	}
	130
1da177e4 LT	131	void clear_local_APIC(void)
	132	{
	133	int maxlvt;
	134	unsigned int v;
	135
	136	maxlvt = get_maxlvt();
	137
	138	/*
704fc59e	139	* Masking an LVT entry can trigger a local APIC error
1da177e4 LT	140	* if the vector is zero. Mask LVTERR first to prevent this.
	141	*/
	142	if (maxlvt >= 3) {
	143	v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
11a8e778	144	apic_write(APIC_LVTERR, v \| APIC_LVT_MASKED);
1da177e4 LT	145	}
	146	/*
	147	* Careful: we have to set masks only first to deassert
	148	* any level-triggered sources.
	149	*/
	150	v = apic_read(APIC_LVTT);
11a8e778	151	apic_write(APIC_LVTT, v \| APIC_LVT_MASKED);
1da177e4	152	v = apic_read(APIC_LVT0);
11a8e778	153	apic_write(APIC_LVT0, v \| APIC_LVT_MASKED);
1da177e4	154	v = apic_read(APIC_LVT1);
11a8e778	155	apic_write(APIC_LVT1, v \| APIC_LVT_MASKED);
1da177e4 LT	156	if (maxlvt >= 4) {
1da177e4 LT	157	v = apic_read(APIC_LVTPC);
11a8e778	158	apic_write(APIC_LVTPC, v \| APIC_LVT_MASKED);
1da177e4 LT	159	}
	160
	161	/*
	162	* Clean APIC state for other OSs:
	163	*/
11a8e778 AK	164	apic_write(APIC_LVTT, APIC_LVT_MASKED);
	165	apic_write(APIC_LVT0, APIC_LVT_MASKED);
	166	apic_write(APIC_LVT1, APIC_LVT_MASKED);
1da177e4	167	if (maxlvt >= 3)
11a8e778	168	apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1da177e4	169	if (maxlvt >= 4)
11a8e778	170	apic_write(APIC_LVTPC, APIC_LVT_MASKED);
5a40b7c2 AK	171	apic_write(APIC_ESR, 0);
5a40b7c2 AK	172	apic_read(APIC_ESR);
1da177e4 LT	173	}
1da177e4 LT	174
208fb931	175	void disconnect_bsp_APIC(int virt_wire_setup)
1da177e4	176	{
a8fcf1a2 AK	177	/* Go back to Virtual Wire compatibility mode */
a8fcf1a2 AK	178	unsigned long value;
208fb931	179
a8fcf1a2 AK	180	/* For the spurious interrupt use vector F, and enable it */
	181	value = apic_read(APIC_SPIV);
	182	value &= ~APIC_VECTOR_MASK;
	183	value \|= APIC_SPIV_APIC_ENABLED;
	184	value \|= 0xf;
	185	apic_write(APIC_SPIV, value);
	186
	187	if (!virt_wire_setup) {
	188	/* For LVT0 make it edge triggered, active high, external and enabled */
	189	value = apic_read(APIC_LVT0);
	190	value &= ~(APIC_MODE_MASK \| APIC_SEND_PENDING \|
208fb931	191	APIC_INPUT_POLARITY \| APIC_LVT_REMOTE_IRR \|
a8fcf1a2	192	APIC_LVT_LEVEL_TRIGGER \| APIC_LVT_MASKED );
208fb931	193	value \|= APIC_LVT_REMOTE_IRR \| APIC_SEND_PENDING;
a8fcf1a2 AK	194	value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
	195	apic_write(APIC_LVT0, value);
	196	} else {
	197	/* Disable LVT0 */
	198	apic_write(APIC_LVT0, APIC_LVT_MASKED);
208fb931	199	}
a8fcf1a2 AK	200
	201	/* For LVT1 make it edge triggered, active high, nmi and enabled */
	202	value = apic_read(APIC_LVT1);
	203	value &= ~(APIC_MODE_MASK \| APIC_SEND_PENDING \|
	204	APIC_INPUT_POLARITY \| APIC_LVT_REMOTE_IRR \|
	205	APIC_LVT_LEVEL_TRIGGER \| APIC_LVT_MASKED);
	206	value \|= APIC_LVT_REMOTE_IRR \| APIC_SEND_PENDING;
	207	value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
	208	apic_write(APIC_LVT1, value);
1da177e4 LT	209	}
	210
	211	void disable_local_APIC(void)
	212	{
	213	unsigned int value;
	214
	215	clear_local_APIC();
	216
	217	/*
	218	* Disable APIC (implies clearing of registers
	219	* for 82489DX!).
	220	*/
	221	value = apic_read(APIC_SPIV);
	222	value &= ~APIC_SPIV_APIC_ENABLED;
11a8e778	223	apic_write(APIC_SPIV, value);
1da177e4 LT	224	}
	225
	226	/*
	227	* This is to verify that we're looking at a real local APIC.
	228	* Check these against your board if the CPUs aren't getting
	229	* started for no apparent reason.
	230	*/
	231	int __init verify_local_APIC(void)
	232	{
	233	unsigned int reg0, reg1;
	234
	235	/*
	236	* The version register is read-only in a real APIC.
	237	*/
	238	reg0 = apic_read(APIC_LVR);
	239	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
	240	apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
	241	reg1 = apic_read(APIC_LVR);
	242	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
	243
	244	/*
	245	* The two version reads above should print the same
	246	* numbers. If the second one is different, then we
	247	* poke at a non-APIC.
	248	*/
	249	if (reg1 != reg0)
	250	return 0;
	251
	252	/*
	253	* Check if the version looks reasonably.
	254	*/
	255	reg1 = GET_APIC_VERSION(reg0);
	256	if (reg1 == 0x00 \|\| reg1 == 0xff)
	257	return 0;
	258	reg1 = get_maxlvt();
	259	if (reg1 < 0x02 \|\| reg1 == 0xff)
	260	return 0;
	261
	262	/*
	263	* The ID register is read/write in a real APIC.
	264	*/
	265	reg0 = apic_read(APIC_ID);
	266	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
	267	apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
	268	reg1 = apic_read(APIC_ID);
	269	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
	270	apic_write(APIC_ID, reg0);
	271	if (reg1 != (reg0 ^ APIC_ID_MASK))
	272	return 0;
	273
	274	/*
	275	* The next two are just to see if we have sane values.
	276	* They're only really relevant if we're in Virtual Wire
	277	* compatibility mode, but most boxes are anymore.
	278	*/
	279	reg0 = apic_read(APIC_LVT0);
	280	apic_printk(APIC_DEBUG,"Getting LVT0: %x\n", reg0);
	281	reg1 = apic_read(APIC_LVT1);
	282	apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
	283
	284	return 1;
	285	}
	286
	287	void __init sync_Arb_IDs(void)
288	{
289	/* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
290	unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
291	if (ver >= 0x14) /* P4 or higher */
292	return;
293
294	/*
295	* Wait for idle.
296	*/
297	apic_wait_icr_idle();
298
299	apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
11a8e778	300	apic_write(APIC_ICR, APIC_DEST_ALLINC \| APIC_INT_LEVELTRIG
1da177e4 LT	301	\| APIC_DM_INIT);
	302	}
	303
1da177e4 LT	304	/*
	305	* An initial setup of the virtual wire mode.
	306	*/
	307	void __init init_bsp_APIC(void)
	308	{
11a8e778	309	unsigned int value;
1da177e4 LT	310
	311	/*
	312	* Don't do the setup now if we have a SMP BIOS as the
	313	* through-I/O-APIC virtual wire mode might be active.
	314	*/
	315	if (smp_found_config \|\| !cpu_has_apic)
	316	return;
	317
	318	value = apic_read(APIC_LVR);
1da177e4 LT	319
	320	/*
	321	* Do not trust the local APIC being empty at bootup.
	322	*/
	323	clear_local_APIC();
	324
	325	/*
	326	* Enable APIC.
	327	*/
	328	value = apic_read(APIC_SPIV);
	329	value &= ~APIC_VECTOR_MASK;
	330	value \|= APIC_SPIV_APIC_ENABLED;
	331	value \|= APIC_SPIV_FOCUS_DISABLED;
	332	value \|= SPURIOUS_APIC_VECTOR;
11a8e778	333	apic_write(APIC_SPIV, value);
1da177e4 LT	334
	335	/*
	336	* Set up the virtual wire mode.
	337	*/
11a8e778	338	apic_write(APIC_LVT0, APIC_DM_EXTINT);
1da177e4	339	value = APIC_DM_NMI;
11a8e778	340	apic_write(APIC_LVT1, value);
1da177e4 LT	341	}
1da177e4 LT	342
e6982c67	343	void __cpuinit setup_local_APIC (void)
1da177e4	344	{
11a8e778	345	unsigned int value, maxlvt;
da7ed9f9	346	int i, j;
1da177e4	347
1da177e4	348	value = apic_read(APIC_LVR);
1da177e4	349
fe7414a2	350	BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f);
1da177e4 LT	351
	352	/*
	353	* Double-check whether this APIC is really registered.
	354	* This is meaningless in clustered apic mode, so we skip it.
	355	*/
	356	if (!apic_id_registered())
	357	BUG();
	358
	359	/*
	360	* Intel recommends to set DFR, LDR and TPR before enabling
	361	* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
	362	* document number 292116). So here it goes...
	363	*/
	364	init_apic_ldr();
	365
	366	/*
	367	* Set Task Priority to 'accept all'. We never change this
	368	* later on.
	369	*/
	370	value = apic_read(APIC_TASKPRI);
	371	value &= ~APIC_TPRI_MASK;
11a8e778	372	apic_write(APIC_TASKPRI, value);
1da177e4	373
da7ed9f9 VG	374	/*
	375	* After a crash, we no longer service the interrupts and a pending
	376	* interrupt from previous kernel might still have ISR bit set.
	377	*
	378	* Most probably by now CPU has serviced that pending interrupt and
	379	* it might not have done the ack_APIC_irq() because it thought,
	380	* interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
	381	* does not clear the ISR bit and cpu thinks it has already serivced
	382	* the interrupt. Hence a vector might get locked. It was noticed
	383	* for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
	384	*/
	385	for (i = APIC_ISR_NR - 1; i >= 0; i--) {
	386	value = apic_read(APIC_ISR + i*0x10);
	387	for (j = 31; j >= 0; j--) {
	388	if (value & (1<<j))
	389	ack_APIC_irq();
	390	}
	391	}
	392
1da177e4 LT	393	/*
	394	* Now that we are all set up, enable the APIC
	395	*/
	396	value = apic_read(APIC_SPIV);
	397	value &= ~APIC_VECTOR_MASK;
	398	/*
	399	* Enable APIC
	400	*/
	401	value \|= APIC_SPIV_APIC_ENABLED;
	402
3f14c746 AK	403	/* We always use processor focus */
3f14c746 AK	404
1da177e4 LT	405	/*
	406	* Set spurious IRQ vector
	407	*/
	408	value \|= SPURIOUS_APIC_VECTOR;
11a8e778	409	apic_write(APIC_SPIV, value);
1da177e4 LT	410
	411	/*
	412	* Set up LVT0, LVT1:
	413	*
	414	* set up through-local-APIC on the BP's LINT0. This is not
	415	* strictly necessary in pure symmetric-IO mode, but sometimes
	416	* we delegate interrupts to the 8259A.
	417	*/
	418	/*
	419	* TODO: set up through-local-APIC from through-I/O-APIC? --macro
	420	*/
	421	value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
a8fcf1a2	422	if (!smp_processor_id() && !value) {
1da177e4 LT	423	value = APIC_DM_EXTINT;
	424	apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", smp_processor_id());
	425	} else {
	426	value = APIC_DM_EXTINT \| APIC_LVT_MASKED;
	427	apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id());
	428	}
11a8e778	429	apic_write(APIC_LVT0, value);
1da177e4 LT	430
	431	/*
	432	* only the BP should see the LINT1 NMI signal, obviously.
	433	*/
	434	if (!smp_processor_id())
	435	value = APIC_DM_NMI;
	436	else
	437	value = APIC_DM_NMI \| APIC_LVT_MASKED;
11a8e778	438	apic_write(APIC_LVT1, value);
1da177e4	439
61c11341	440	{
1da177e4 LT	441	unsigned oldvalue;
1da177e4 LT	442	maxlvt = get_maxlvt();
1da177e4 LT	443	oldvalue = apic_read(APIC_ESR);
1da177e4 LT	444	value = ERROR_APIC_VECTOR; // enables sending errors
11a8e778	445	apic_write(APIC_LVTERR, value);
1da177e4 LT	446	/*
	447	* spec says clear errors after enabling vector.
	448	*/
	449	if (maxlvt > 3)
	450	apic_write(APIC_ESR, 0);
	451	value = apic_read(APIC_ESR);
	452	if (value != oldvalue)
	453	apic_printk(APIC_VERBOSE,
	454	"ESR value after enabling vector: %08x, after %08x\n",
	455	oldvalue, value);
1da177e4 LT	456	}
	457
	458	nmi_watchdog_default();
f2802e7f	459	setup_apic_nmi_watchdog(NULL);
1da177e4 LT	460	apic_pm_activate();
	461	}
	462
	463	#ifdef CONFIG_PM
	464
	465	static struct {
	466	/* 'active' is true if the local APIC was enabled by us and
	467	not the BIOS; this signifies that we are also responsible
	468	for disabling it before entering apm/acpi suspend */
	469	int active;
	470	/* r/w apic fields */
	471	unsigned int apic_id;
	472	unsigned int apic_taskpri;
	473	unsigned int apic_ldr;
	474	unsigned int apic_dfr;
	475	unsigned int apic_spiv;
	476	unsigned int apic_lvtt;
	477	unsigned int apic_lvtpc;
	478	unsigned int apic_lvt0;
	479	unsigned int apic_lvt1;
	480	unsigned int apic_lvterr;
	481	unsigned int apic_tmict;
	482	unsigned int apic_tdcr;
	483	unsigned int apic_thmr;
	484	} apic_pm_state;
	485
0b9c33a7	486	static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1da177e4 LT	487	{
1da177e4 LT	488	unsigned long flags;
f990fff4	489	int maxlvt;
1da177e4 LT	490
	491	if (!apic_pm_state.active)
	492	return 0;
	493
f990fff4 KW	494	maxlvt = get_maxlvt();
f990fff4 KW	495
1da177e4 LT	496	apic_pm_state.apic_id = apic_read(APIC_ID);
	497	apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
	498	apic_pm_state.apic_ldr = apic_read(APIC_LDR);
	499	apic_pm_state.apic_dfr = apic_read(APIC_DFR);
	500	apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
	501	apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
f990fff4 KW	502	if (maxlvt >= 4)
f990fff4 KW	503	apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1da177e4 LT	504	apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
	505	apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
	506	apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
	507	apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
	508	apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
f990fff4 KW	509	#ifdef CONFIG_X86_MCE_INTEL
	510	if (maxlvt >= 5)
	511	apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
	512	#endif