]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
d25bf7e5 | 26 | #include <linux/module.h> |
39928722 | 27 | #include <linux/ioport.h> |
ba7eda4c | 28 | #include <linux/clockchips.h> |
1da177e4 LT |
29 | |
30 | #include <asm/atomic.h> | |
31 | #include <asm/smp.h> | |
32 | #include <asm/mtrr.h> | |
33 | #include <asm/mpspec.h> | |
34 | #include <asm/pgalloc.h> | |
35 | #include <asm/mach_apic.h> | |
75152114 | 36 | #include <asm/nmi.h> |
95833c83 | 37 | #include <asm/idle.h> |
73dea47f AK |
38 | #include <asm/proto.h> |
39 | #include <asm/timex.h> | |
2d0c87c3 | 40 | #include <asm/hpet.h> |
2c8c0e6b | 41 | #include <asm/apic.h> |
1da177e4 LT |
42 | |
43 | int apic_verbosity; | |
73dea47f | 44 | int apic_runs_main_timer; |
0c3749c4 | 45 | int apic_calibrate_pmtmr __initdata; |
1da177e4 LT |
46 | |
47 | int disable_apic_timer __initdata; | |
48 | ||
2e7c2838 LT |
49 | /* Local APIC timer works in C2? */ |
50 | int local_apic_timer_c2_ok; | |
51 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
52 | ||
39928722 AD |
53 | static struct resource *ioapic_resources; |
54 | static struct resource lapic_resource = { | |
55 | .name = "Local APIC", | |
56 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
57 | }; | |
58 | ||
d03030e9 TG |
59 | static unsigned int calibration_result; |
60 | ||
ba7eda4c TG |
61 | static int lapic_next_event(unsigned long delta, |
62 | struct clock_event_device *evt); | |
63 | static void lapic_timer_setup(enum clock_event_mode mode, | |
64 | struct clock_event_device *evt); | |
65 | ||
66 | static void lapic_timer_broadcast(cpumask_t mask); | |
67 | ||
68 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen); | |
69 | ||
70 | static struct clock_event_device lapic_clockevent = { | |
71 | .name = "lapic", | |
72 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
73 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
74 | .shift = 32, | |
75 | .set_mode = lapic_timer_setup, | |
76 | .set_next_event = lapic_next_event, | |
77 | .broadcast = lapic_timer_broadcast, | |
78 | .rating = 100, | |
79 | .irq = -1, | |
80 | }; | |
81 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
82 | ||
83 | static int lapic_next_event(unsigned long delta, | |
84 | struct clock_event_device *evt) | |
85 | { | |
86 | apic_write(APIC_TMICT, delta); | |
87 | return 0; | |
88 | } | |
89 | ||
90 | static void lapic_timer_setup(enum clock_event_mode mode, | |
91 | struct clock_event_device *evt) | |
92 | { | |
93 | unsigned long flags; | |
94 | unsigned int v; | |
95 | ||
96 | /* Lapic used as dummy for broadcast ? */ | |
97 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
98 | return; | |
99 | ||
100 | local_irq_save(flags); | |
101 | ||
102 | switch (mode) { | |
103 | case CLOCK_EVT_MODE_PERIODIC: | |
104 | case CLOCK_EVT_MODE_ONESHOT: | |
105 | __setup_APIC_LVTT(calibration_result, | |
106 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
107 | break; | |
108 | case CLOCK_EVT_MODE_UNUSED: | |
109 | case CLOCK_EVT_MODE_SHUTDOWN: | |
110 | v = apic_read(APIC_LVTT); | |
111 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
112 | apic_write(APIC_LVTT, v); | |
113 | break; | |
114 | case CLOCK_EVT_MODE_RESUME: | |
115 | /* Nothing to do here */ | |
116 | break; | |
117 | } | |
118 | ||
119 | local_irq_restore(flags); | |
120 | } | |
121 | ||
122 | /* | |
123 | * Local APIC timer broadcast function | |
124 | */ | |
125 | static void lapic_timer_broadcast(cpumask_t mask) | |
126 | { | |
127 | #ifdef CONFIG_SMP | |
128 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
129 | #endif | |
130 | } | |
131 | ||
d25bf7e5 VP |
132 | /* |
133 | * cpu_mask that denotes the CPUs that needs timer interrupt coming in as | |
134 | * IPIs in place of local APIC timers | |
135 | */ | |
136 | static cpumask_t timer_interrupt_broadcast_ipi_mask; | |
137 | ||
1da177e4 | 138 | /* Using APIC to generate smp_local_timer_interrupt? */ |
acae9d32 | 139 | int using_apic_timer __read_mostly = 0; |
1da177e4 | 140 | |
1da177e4 LT |
141 | static void apic_pm_activate(void); |
142 | ||
8339e9fb FLV |
143 | void apic_wait_icr_idle(void) |
144 | { | |
145 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
146 | cpu_relax(); | |
147 | } | |
148 | ||
149 | unsigned int safe_apic_wait_icr_idle(void) | |
150 | { | |
151 | unsigned int send_status; | |
152 | int timeout; | |
153 | ||
154 | timeout = 0; | |
155 | do { | |
156 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
157 | if (!send_status) | |
158 | break; | |
159 | udelay(100); | |
160 | } while (timeout++ < 1000); | |
161 | ||
162 | return send_status; | |
163 | } | |
164 | ||
1da177e4 LT |
165 | void enable_NMI_through_LVT0 (void * dummy) |
166 | { | |
11a8e778 | 167 | unsigned int v; |
6935d1f9 TG |
168 | |
169 | /* unmask and set to NMI */ | |
170 | v = APIC_DM_NMI; | |
11a8e778 | 171 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
172 | } |
173 | ||
174 | int get_maxlvt(void) | |
175 | { | |
11a8e778 | 176 | unsigned int v, maxlvt; |
1da177e4 LT |
177 | |
178 | v = apic_read(APIC_LVR); | |
1da177e4 LT |
179 | maxlvt = GET_APIC_MAXLVT(v); |
180 | return maxlvt; | |
181 | } | |
182 | ||
3777a959 AK |
183 | /* |
184 | * 'what should we do if we get a hw irq event on an illegal vector'. | |
185 | * each architecture has to answer this themselves. | |
186 | */ | |
187 | void ack_bad_irq(unsigned int irq) | |
188 | { | |
189 | printk("unexpected IRQ trap at vector %02x\n", irq); | |
190 | /* | |
191 | * Currently unexpected vectors happen only on SMP and APIC. | |
192 | * We _must_ ack these because every local APIC has only N | |
193 | * irq slots per priority level, and a 'hanging, unacked' IRQ | |
194 | * holds up an irq slot - in excessive cases (when multiple | |
195 | * unexpected vectors occur) that might lock up the APIC | |
196 | * completely. | |
6935d1f9 | 197 | * But don't ack when the APIC is disabled. -AK |
3777a959 AK |
198 | */ |
199 | if (!disable_apic) | |
200 | ack_APIC_irq(); | |
201 | } | |
202 | ||
1da177e4 LT |
203 | void clear_local_APIC(void) |
204 | { | |
205 | int maxlvt; | |
206 | unsigned int v; | |
207 | ||
208 | maxlvt = get_maxlvt(); | |
209 | ||
210 | /* | |
704fc59e | 211 | * Masking an LVT entry can trigger a local APIC error |
1da177e4 LT |
212 | * if the vector is zero. Mask LVTERR first to prevent this. |
213 | */ | |
214 | if (maxlvt >= 3) { | |
215 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
11a8e778 | 216 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); |
1da177e4 LT |
217 | } |
218 | /* | |
219 | * Careful: we have to set masks only first to deassert | |
220 | * any level-triggered sources. | |
221 | */ | |
222 | v = apic_read(APIC_LVTT); | |
11a8e778 | 223 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); |
1da177e4 | 224 | v = apic_read(APIC_LVT0); |
11a8e778 | 225 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 | 226 | v = apic_read(APIC_LVT1); |
11a8e778 | 227 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); |
1da177e4 LT |
228 | if (maxlvt >= 4) { |
229 | v = apic_read(APIC_LVTPC); | |
11a8e778 | 230 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); |
1da177e4 LT |
231 | } |
232 | ||
233 | /* | |
234 | * Clean APIC state for other OSs: | |
235 | */ | |
11a8e778 AK |
236 | apic_write(APIC_LVTT, APIC_LVT_MASKED); |
237 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
238 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
1da177e4 | 239 | if (maxlvt >= 3) |
11a8e778 | 240 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); |
1da177e4 | 241 | if (maxlvt >= 4) |
11a8e778 | 242 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); |
5a40b7c2 AK |
243 | apic_write(APIC_ESR, 0); |
244 | apic_read(APIC_ESR); | |
1da177e4 LT |
245 | } |
246 | ||
208fb931 | 247 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 248 | { |
a8fcf1a2 AK |
249 | /* Go back to Virtual Wire compatibility mode */ |
250 | unsigned long value; | |
208fb931 | 251 | |
a8fcf1a2 AK |
252 | /* For the spurious interrupt use vector F, and enable it */ |
253 | value = apic_read(APIC_SPIV); | |
254 | value &= ~APIC_VECTOR_MASK; | |
255 | value |= APIC_SPIV_APIC_ENABLED; | |
256 | value |= 0xf; | |
257 | apic_write(APIC_SPIV, value); | |
258 | ||
259 | if (!virt_wire_setup) { | |
260 | /* For LVT0 make it edge triggered, active high, external and enabled */ | |
261 | value = apic_read(APIC_LVT0); | |
262 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
208fb931 | 263 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | |
a8fcf1a2 | 264 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED ); |
208fb931 | 265 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; |
a8fcf1a2 AK |
266 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); |
267 | apic_write(APIC_LVT0, value); | |
268 | } else { | |
269 | /* Disable LVT0 */ | |
270 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
208fb931 | 271 | } |
a8fcf1a2 AK |
272 | |
273 | /* For LVT1 make it edge triggered, active high, nmi and enabled */ | |
274 | value = apic_read(APIC_LVT1); | |
275 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
276 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
277 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
278 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
279 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
280 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
281 | } |
282 | ||
283 | void disable_local_APIC(void) | |
284 | { | |
285 | unsigned int value; | |
286 | ||
287 | clear_local_APIC(); | |
288 | ||
289 | /* | |
290 | * Disable APIC (implies clearing of registers | |
291 | * for 82489DX!). | |
292 | */ | |
293 | value = apic_read(APIC_SPIV); | |
294 | value &= ~APIC_SPIV_APIC_ENABLED; | |
11a8e778 | 295 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
296 | } |
297 | ||
298 | /* | |
299 | * This is to verify that we're looking at a real local APIC. | |
300 | * Check these against your board if the CPUs aren't getting | |
301 | * started for no apparent reason. | |
302 | */ | |
303 | int __init verify_local_APIC(void) | |
304 | { | |
305 | unsigned int reg0, reg1; | |
306 | ||
307 | /* | |
308 | * The version register is read-only in a real APIC. | |
309 | */ | |
310 | reg0 = apic_read(APIC_LVR); | |
311 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
312 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
313 | reg1 = apic_read(APIC_LVR); | |
314 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
315 | ||
316 | /* | |
317 | * The two version reads above should print the same | |
318 | * numbers. If the second one is different, then we | |
319 | * poke at a non-APIC. | |
320 | */ | |
321 | if (reg1 != reg0) | |
322 | return 0; | |
323 | ||
324 | /* | |
325 | * Check if the version looks reasonably. | |
326 | */ | |
327 | reg1 = GET_APIC_VERSION(reg0); | |
328 | if (reg1 == 0x00 || reg1 == 0xff) | |
329 | return 0; | |
330 | reg1 = get_maxlvt(); | |
331 | if (reg1 < 0x02 || reg1 == 0xff) | |
332 | return 0; | |
333 | ||
334 | /* | |
335 | * The ID register is read/write in a real APIC. | |
336 | */ | |
337 | reg0 = apic_read(APIC_ID); | |
338 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); | |
339 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); | |
340 | reg1 = apic_read(APIC_ID); | |
341 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); | |
342 | apic_write(APIC_ID, reg0); | |
343 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
344 | return 0; | |
345 | ||
346 | /* | |
347 | * The next two are just to see if we have sane values. | |
348 | * They're only really relevant if we're in Virtual Wire | |
349 | * compatibility mode, but most boxes are anymore. | |
350 | */ | |
351 | reg0 = apic_read(APIC_LVT0); | |
352 | apic_printk(APIC_DEBUG,"Getting LVT0: %x\n", reg0); | |
353 | reg1 = apic_read(APIC_LVT1); | |
354 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
355 | ||
356 | return 1; | |
357 | } | |
358 | ||
359 | void __init sync_Arb_IDs(void) | |
360 | { | |
361 | /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */ | |
362 | unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
363 | if (ver >= 0x14) /* P4 or higher */ | |
364 | return; | |
365 | ||
366 | /* | |
367 | * Wait for idle. | |
368 | */ | |
369 | apic_wait_icr_idle(); | |
370 | ||
371 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
11a8e778 | 372 | apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG |
1da177e4 LT |
373 | | APIC_DM_INIT); |
374 | } | |
375 | ||
1da177e4 LT |
376 | /* |
377 | * An initial setup of the virtual wire mode. | |
378 | */ | |
379 | void __init init_bsp_APIC(void) | |
380 | { | |
11a8e778 | 381 | unsigned int value; |
1da177e4 LT |
382 | |
383 | /* | |
384 | * Don't do the setup now if we have a SMP BIOS as the | |
385 | * through-I/O-APIC virtual wire mode might be active. | |
386 | */ | |
387 | if (smp_found_config || !cpu_has_apic) | |
388 | return; | |
389 | ||
390 | value = apic_read(APIC_LVR); | |
1da177e4 LT |
391 | |
392 | /* | |
393 | * Do not trust the local APIC being empty at bootup. | |
394 | */ | |
395 | clear_local_APIC(); | |
396 | ||
397 | /* | |
398 | * Enable APIC. | |
399 | */ | |
400 | value = apic_read(APIC_SPIV); | |
401 | value &= ~APIC_VECTOR_MASK; | |
402 | value |= APIC_SPIV_APIC_ENABLED; | |
403 | value |= APIC_SPIV_FOCUS_DISABLED; | |
404 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 405 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
406 | |
407 | /* | |
408 | * Set up the virtual wire mode. | |
409 | */ | |
11a8e778 | 410 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 411 | value = APIC_DM_NMI; |
11a8e778 | 412 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
413 | } |
414 | ||
e6982c67 | 415 | void __cpuinit setup_local_APIC (void) |
1da177e4 | 416 | { |
11a8e778 | 417 | unsigned int value, maxlvt; |
da7ed9f9 | 418 | int i, j; |
1da177e4 | 419 | |
1da177e4 | 420 | value = apic_read(APIC_LVR); |
1da177e4 | 421 | |
fe7414a2 | 422 | BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f); |
1da177e4 LT |
423 | |
424 | /* | |
425 | * Double-check whether this APIC is really registered. | |
426 | * This is meaningless in clustered apic mode, so we skip it. | |
427 | */ | |
428 | if (!apic_id_registered()) | |
429 | BUG(); | |
430 | ||
431 | /* | |
432 | * Intel recommends to set DFR, LDR and TPR before enabling | |
433 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
434 | * document number 292116). So here it goes... | |
435 | */ | |
436 | init_apic_ldr(); | |
437 | ||
438 | /* | |
439 | * Set Task Priority to 'accept all'. We never change this | |
440 | * later on. | |
441 | */ | |
442 | value = apic_read(APIC_TASKPRI); | |
443 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 444 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 445 | |
da7ed9f9 VG |
446 | /* |
447 | * After a crash, we no longer service the interrupts and a pending | |
448 | * interrupt from previous kernel might still have ISR bit set. | |
449 | * | |
450 | * Most probably by now CPU has serviced that pending interrupt and | |
451 | * it might not have done the ack_APIC_irq() because it thought, | |
452 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
453 | * does not clear the ISR bit and cpu thinks it has already serivced | |
454 | * the interrupt. Hence a vector might get locked. It was noticed | |
455 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
456 | */ | |
457 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
458 | value = apic_read(APIC_ISR + i*0x10); | |
459 | for (j = 31; j >= 0; j--) { | |
460 | if (value & (1<<j)) | |
461 | ack_APIC_irq(); | |
462 | } | |
463 | } | |
464 | ||
1da177e4 LT |
465 | /* |
466 | * Now that we are all set up, enable the APIC | |
467 | */ | |
468 | value = apic_read(APIC_SPIV); | |
469 | value &= ~APIC_VECTOR_MASK; | |
470 | /* | |
471 | * Enable APIC | |
472 | */ | |
473 | value |= APIC_SPIV_APIC_ENABLED; | |
474 | ||
3f14c746 AK |
475 | /* We always use processor focus */ |
476 | ||
1da177e4 LT |
477 | /* |
478 | * Set spurious IRQ vector | |
479 | */ | |
480 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 481 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
482 | |
483 | /* | |
484 | * Set up LVT0, LVT1: | |
485 | * | |
486 | * set up through-local-APIC on the BP's LINT0. This is not | |
487 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
488 | * we delegate interrupts to the 8259A. | |
489 | */ | |
490 | /* | |
491 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
492 | */ | |
493 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
a8fcf1a2 | 494 | if (!smp_processor_id() && !value) { |
1da177e4 LT |
495 | value = APIC_DM_EXTINT; |
496 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", smp_processor_id()); | |
497 | } else { | |
498 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
499 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id()); | |
500 | } | |
11a8e778 | 501 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
502 | |
503 | /* | |
504 | * only the BP should see the LINT1 NMI signal, obviously. | |
505 | */ | |
506 | if (!smp_processor_id()) | |
507 | value = APIC_DM_NMI; | |
508 | else | |
509 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
11a8e778 | 510 | apic_write(APIC_LVT1, value); |
1da177e4 | 511 | |
61c11341 | 512 | { |
1da177e4 LT |
513 | unsigned oldvalue; |
514 | maxlvt = get_maxlvt(); | |
1da177e4 LT |
515 | oldvalue = apic_read(APIC_ESR); |
516 | value = ERROR_APIC_VECTOR; // enables sending errors | |
11a8e778 | 517 | apic_write(APIC_LVTERR, value); |
1da177e4 LT |
518 | /* |
519 | * spec says clear errors after enabling vector. | |
520 | */ | |
521 | if (maxlvt > 3) | |
522 | apic_write(APIC_ESR, 0); | |
523 | value = apic_read(APIC_ESR); | |
524 | if (value != oldvalue) | |
525 | apic_printk(APIC_VERBOSE, | |
526 | "ESR value after enabling vector: %08x, after %08x\n", | |
527 | oldvalue, value); | |
1da177e4 LT |
528 | } |
529 | ||
530 | nmi_watchdog_default(); | |
f2802e7f | 531 | setup_apic_nmi_watchdog(NULL); |
1da177e4 LT |
532 | apic_pm_activate(); |
533 | } | |
534 | ||
535 | #ifdef CONFIG_PM | |
536 | ||
537 | static struct { | |
538 | /* 'active' is true if the local APIC was enabled by us and | |
539 | not the BIOS; this signifies that we are also responsible | |
540 | for disabling it before entering apm/acpi suspend */ | |
541 | int active; | |
542 | /* r/w apic fields */ | |
543 | unsigned int apic_id; | |
544 | unsigned int apic_taskpri; | |
545 | unsigned int apic_ldr; | |
546 | unsigned int apic_dfr; | |
547 | unsigned int apic_spiv; | |
548 | unsigned int apic_lvtt; | |
549 | unsigned int apic_lvtpc; | |
550 | unsigned int apic_lvt0; | |
551 | unsigned int apic_lvt1; | |
552 | unsigned int apic_lvterr; | |
553 | unsigned int apic_tmict; | |
554 | unsigned int apic_tdcr; | |
555 | unsigned int apic_thmr; | |
556 | } apic_pm_state; | |
557 | ||
0b9c33a7 | 558 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
559 | { |
560 | unsigned long flags; | |
f990fff4 | 561 | int maxlvt; |
1da177e4 LT |
562 | |
563 | if (!apic_pm_state.active) | |
564 | return 0; | |
565 | ||
f990fff4 KW |
566 | maxlvt = get_maxlvt(); |
567 | ||
1da177e4 LT |
568 | apic_pm_state.apic_id = apic_read(APIC_ID); |
569 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); | |
570 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
571 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
572 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
573 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
f990fff4 KW |
574 | if (maxlvt >= 4) |
575 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1da177e4 LT |
576 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); |
577 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
578 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
579 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
580 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
f990fff4 KW |
581 | #ifdef CONFIG_X86_MCE_INTEL |
582 | if (maxlvt >= 5) | |
583 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
584 | #endif | |