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1da177e4 LT |
1 | #include <linux/init.h> |
2 | #include <linux/bitops.h> | |
3 | #include <linux/mm.h> | |
8d71a2ea | 4 | |
8bdbd962 | 5 | #include <linux/io.h> |
1da177e4 | 6 | #include <asm/processor.h> |
d3f7eae1 | 7 | #include <asm/apic.h> |
1f442d70 | 8 | #include <asm/cpu.h> |
42937e81 | 9 | #include <asm/pci-direct.h> |
1da177e4 | 10 | |
8d71a2ea YL |
11 | #ifdef CONFIG_X86_64 |
12 | # include <asm/numa_64.h> | |
13 | # include <asm/mmconfig.h> | |
14 | # include <asm/cacheflush.h> | |
15 | #endif | |
16 | ||
1da177e4 LT |
17 | #include "cpu.h" |
18 | ||
6c62aa4a | 19 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
20 | /* |
21 | * B step AMD K6 before B 9730xxxx have hardware bugs that can cause | |
22 | * misexecution of code under Linux. Owners of such processors should | |
23 | * contact AMD for precise details and a CPU swap. | |
24 | * | |
25 | * See http://www.multimania.com/poulot/k6bug.html | |
26 | * http://www.amd.com/K6/k6docs/revgd.html | |
27 | * | |
28 | * The following test is erm.. interesting. AMD neglected to up | |
29 | * the chip setting when fixing the bug but they also tweaked some | |
30 | * performance at the same time.. | |
31 | */ | |
fb87a298 | 32 | |
1da177e4 LT |
33 | extern void vide(void); |
34 | __asm__(".align 4\nvide: ret"); | |
35 | ||
11fdd252 YL |
36 | static void __cpuinit init_amd_k5(struct cpuinfo_x86 *c) |
37 | { | |
38 | /* | |
39 | * General Systems BIOSen alias the cpu frequency registers | |
40 | * of the Elan at 0x000df000. Unfortuantly, one of the Linux | |
41 | * drivers subsequently pokes it, and changes the CPU speed. | |
42 | * Workaround : Remove the unneeded alias. | |
43 | */ | |
44 | #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ | |
45 | #define CBAR_ENB (0x80000000) | |
46 | #define CBAR_KEY (0X000000CB) | |
47 | if (c->x86_model == 9 || c->x86_model == 10) { | |
8bdbd962 AC |
48 | if (inl(CBAR) & CBAR_ENB) |
49 | outl(0 | CBAR_KEY, CBAR); | |
11fdd252 YL |
50 | } |
51 | } | |
52 | ||
53 | ||
54 | static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c) | |
55 | { | |
56 | u32 l, h; | |
57 | int mbytes = num_physpages >> (20-PAGE_SHIFT); | |
58 | ||
59 | if (c->x86_model < 6) { | |
60 | /* Based on AMD doc 20734R - June 2000 */ | |
61 | if (c->x86_model == 0) { | |
62 | clear_cpu_cap(c, X86_FEATURE_APIC); | |
63 | set_cpu_cap(c, X86_FEATURE_PGE); | |
64 | } | |
65 | return; | |
66 | } | |
67 | ||
68 | if (c->x86_model == 6 && c->x86_mask == 1) { | |
69 | const int K6_BUG_LOOP = 1000000; | |
70 | int n; | |
71 | void (*f_vide)(void); | |
72 | unsigned long d, d2; | |
73 | ||
74 | printk(KERN_INFO "AMD K6 stepping B detected - "); | |
75 | ||
76 | /* | |
77 | * It looks like AMD fixed the 2.6.2 bug and improved indirect | |
78 | * calls at the same time. | |
79 | */ | |
80 | ||
81 | n = K6_BUG_LOOP; | |
82 | f_vide = vide; | |
83 | rdtscl(d); | |
84 | while (n--) | |
85 | f_vide(); | |
86 | rdtscl(d2); | |
87 | d = d2-d; | |
88 | ||
89 | if (d > 20*K6_BUG_LOOP) | |
8bdbd962 AC |
90 | printk(KERN_CONT |
91 | "system stability may be impaired when more than 32 MB are used.\n"); | |
11fdd252 | 92 | else |
8bdbd962 | 93 | printk(KERN_CONT "probably OK (after B9730xxxx).\n"); |
11fdd252 YL |
94 | printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n"); |
95 | } | |
96 | ||
97 | /* K6 with old style WHCR */ | |
98 | if (c->x86_model < 8 || | |
99 | (c->x86_model == 8 && c->x86_mask < 8)) { | |
100 | /* We can only write allocate on the low 508Mb */ | |
101 | if (mbytes > 508) | |
102 | mbytes = 508; | |
103 | ||
104 | rdmsr(MSR_K6_WHCR, l, h); | |
105 | if ((l&0x0000FFFF) == 0) { | |
106 | unsigned long flags; | |
107 | l = (1<<0)|((mbytes/4)<<1); | |
108 | local_irq_save(flags); | |
109 | wbinvd(); | |
110 | wrmsr(MSR_K6_WHCR, l, h); | |
111 | local_irq_restore(flags); | |
112 | printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n", | |
113 | mbytes); | |
114 | } | |
115 | return; | |
116 | } | |
117 | ||
118 | if ((c->x86_model == 8 && c->x86_mask > 7) || | |
119 | c->x86_model == 9 || c->x86_model == 13) { | |
120 | /* The more serious chips .. */ | |
121 | ||
122 | if (mbytes > 4092) | |
123 | mbytes = 4092; | |
124 | ||
125 | rdmsr(MSR_K6_WHCR, l, h); | |
126 | if ((l&0xFFFF0000) == 0) { | |
127 | unsigned long flags; | |
128 | l = ((mbytes>>2)<<22)|(1<<16); | |
129 | local_irq_save(flags); | |
130 | wbinvd(); | |
131 | wrmsr(MSR_K6_WHCR, l, h); | |
132 | local_irq_restore(flags); | |
133 | printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n", | |
134 | mbytes); | |
135 | } | |
136 | ||
137 | return; | |
138 | } | |
139 | ||
140 | if (c->x86_model == 10) { | |
141 | /* AMD Geode LX is model 10 */ | |
142 | /* placeholder for any needed mods */ | |
143 | return; | |
144 | } | |
145 | } | |
146 | ||
1f442d70 YL |
147 | static void __cpuinit amd_k7_smp_check(struct cpuinfo_x86 *c) |
148 | { | |
149 | #ifdef CONFIG_SMP | |
150 | /* calling is from identify_secondary_cpu() ? */ | |
151 | if (c->cpu_index == boot_cpu_id) | |
152 | return; | |
153 | ||
154 | /* | |
155 | * Certain Athlons might work (for various values of 'work') in SMP | |
156 | * but they are not certified as MP capable. | |
157 | */ | |
158 | /* Athlon 660/661 is valid. */ | |
159 | if ((c->x86_model == 6) && ((c->x86_mask == 0) || | |
160 | (c->x86_mask == 1))) | |
161 | goto valid_k7; | |
162 | ||
163 | /* Duron 670 is valid */ | |
164 | if ((c->x86_model == 7) && (c->x86_mask == 0)) | |
165 | goto valid_k7; | |
166 | ||
167 | /* | |
168 | * Athlon 662, Duron 671, and Athlon >model 7 have capability | |
169 | * bit. It's worth noting that the A5 stepping (662) of some | |
170 | * Athlon XP's have the MP bit set. | |
171 | * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for | |
172 | * more. | |
173 | */ | |
174 | if (((c->x86_model == 6) && (c->x86_mask >= 2)) || | |
175 | ((c->x86_model == 7) && (c->x86_mask >= 1)) || | |
176 | (c->x86_model > 7)) | |
177 | if (cpu_has_mp) | |
178 | goto valid_k7; | |
179 | ||
180 | /* If we get here, not a certified SMP capable AMD system. */ | |
181 | ||
182 | /* | |
183 | * Don't taint if we are running SMP kernel on a single non-MP | |
184 | * approved Athlon | |
185 | */ | |
186 | WARN_ONCE(1, "WARNING: This combination of AMD" | |
7da8b6dd | 187 | " processors is not suitable for SMP.\n"); |
1f442d70 YL |
188 | if (!test_taint(TAINT_UNSAFE_SMP)) |
189 | add_taint(TAINT_UNSAFE_SMP); | |
190 | ||
191 | valid_k7: | |
192 | ; | |
193 | #endif | |
194 | } | |
195 | ||
11fdd252 YL |
196 | static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c) |
197 | { | |
198 | u32 l, h; | |
199 | ||
200 | /* | |
201 | * Bit 15 of Athlon specific MSR 15, needs to be 0 | |
202 | * to enable SSE on Palomino/Morgan/Barton CPU's. | |
203 | * If the BIOS didn't enable it already, enable it here. | |
204 | */ | |
205 | if (c->x86_model >= 6 && c->x86_model <= 10) { | |
206 | if (!cpu_has(c, X86_FEATURE_XMM)) { | |
207 | printk(KERN_INFO "Enabling disabled K7/SSE Support.\n"); | |
208 | rdmsr(MSR_K7_HWCR, l, h); | |
209 | l &= ~0x00008000; | |
210 | wrmsr(MSR_K7_HWCR, l, h); | |
211 | set_cpu_cap(c, X86_FEATURE_XMM); | |
212 | } | |
213 | } | |
214 | ||
215 | /* | |
216 | * It's been determined by AMD that Athlons since model 8 stepping 1 | |
217 | * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx | |
218 | * As per AMD technical note 27212 0.2 | |
219 | */ | |
220 | if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) { | |
221 | rdmsr(MSR_K7_CLK_CTL, l, h); | |
222 | if ((l & 0xfff00000) != 0x20000000) { | |
8bdbd962 AC |
223 | printk(KERN_INFO |
224 | "CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", | |
225 | l, ((l & 0x000fffff)|0x20000000)); | |
11fdd252 YL |
226 | wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); |
227 | } | |
228 | } | |
229 | ||
230 | set_cpu_cap(c, X86_FEATURE_K7); | |
1f442d70 YL |
231 | |
232 | amd_k7_smp_check(c); | |
11fdd252 | 233 | } |
6c62aa4a YL |
234 | #endif |
235 | ||
236 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) | |
237 | static int __cpuinit nearby_node(int apicid) | |
238 | { | |
239 | int i, node; | |
240 | ||
241 | for (i = apicid - 1; i >= 0; i--) { | |
242 | node = apicid_to_node[i]; | |
243 | if (node != NUMA_NO_NODE && node_online(node)) | |
244 | return node; | |
245 | } | |
246 | for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { | |
247 | node = apicid_to_node[i]; | |
248 | if (node != NUMA_NO_NODE && node_online(node)) | |
249 | return node; | |
250 | } | |
251 | return first_node(node_online_map); /* Shouldn't happen */ | |
252 | } | |
253 | #endif | |
11fdd252 | 254 | |
4a376ec3 | 255 | /* |
23588c38 AH |
256 | * Fixup core topology information for |
257 | * (1) AMD multi-node processors | |
258 | * Assumption: Number of cores in each internal node is the same. | |
4a376ec3 AH |
259 | */ |
260 | #ifdef CONFIG_X86_HT | |
23588c38 | 261 | static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c) |
4a376ec3 | 262 | { |
9d260ebc | 263 | u32 nodes, cores_per_node; |
23588c38 AH |
264 | u8 node_id; |
265 | unsigned long long value; | |
4a376ec3 AH |
266 | int cpu = smp_processor_id(); |
267 | ||
23588c38 AH |
268 | /* get information required for multi-node processors */ |
269 | if (cpu_has(c, X86_FEATURE_TOPOEXT)) { | |
270 | value = cpuid_ecx(0x8000001e); | |
271 | nodes = ((value >> 8) & 7) + 1; | |
272 | node_id = value & 7; | |
273 | } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { | |
274 | rdmsrl(MSR_FAM10H_NODE_ID, value); | |
275 | nodes = ((value >> 3) & 7) + 1; | |
276 | node_id = value & 7; | |
277 | } else | |
4a376ec3 AH |
278 | return; |
279 | ||
23588c38 AH |
280 | /* fixup multi-node processor information */ |
281 | if (nodes > 1) { | |
282 | set_cpu_cap(c, X86_FEATURE_AMD_DCM); | |
283 | cores_per_node = c->x86_max_cores / nodes; | |
9d260ebc | 284 | |
23588c38 AH |
285 | /* store NodeID, use llc_shared_map to store sibling info */ |
286 | per_cpu(cpu_llc_id, cpu) = node_id; | |
4a376ec3 | 287 | |
23588c38 AH |
288 | /* core id to be in range from 0 to (cores_per_node - 1) */ |
289 | c->cpu_core_id = c->cpu_core_id % cores_per_node; | |
290 | } | |
4a376ec3 AH |
291 | } |
292 | #endif | |
293 | ||
11fdd252 YL |
294 | /* |
295 | * On a AMD dual core setup the lower bits of the APIC id distingush the cores. | |
296 | * Assumes number of cores is a power of two. | |
297 | */ | |
298 | static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c) | |
299 | { | |
300 | #ifdef CONFIG_X86_HT | |
301 | unsigned bits; | |
99bd0c0f | 302 | int cpu = smp_processor_id(); |
11fdd252 YL |
303 | |
304 | bits = c->x86_coreid_bits; | |
11fdd252 YL |
305 | /* Low order bits define the core id (index of core in socket) */ |
306 | c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); | |
307 | /* Convert the initial APIC ID into the socket ID */ | |
308 | c->phys_proc_id = c->initial_apicid >> bits; | |
99bd0c0f AH |
309 | /* use socket ID also for last level cache */ |
310 | per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; | |
23588c38 | 311 | amd_get_topology(c); |
11fdd252 YL |
312 | #endif |
313 | } | |
314 | ||
6a812691 AH |
315 | int amd_get_nb_id(int cpu) |
316 | { | |
317 | int id = 0; | |
318 | #ifdef CONFIG_SMP | |
319 | id = per_cpu(cpu_llc_id, cpu); | |
320 | #endif | |
321 | return id; | |
322 | } | |
323 | EXPORT_SYMBOL_GPL(amd_get_nb_id); | |
324 | ||
6c62aa4a YL |
325 | static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c) |
326 | { | |
327 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) | |
328 | int cpu = smp_processor_id(); | |
329 | int node; | |
0d96b9ff | 330 | unsigned apicid = c->apicid; |
6c62aa4a | 331 | |
4a376ec3 | 332 | node = per_cpu(cpu_llc_id, cpu); |
6c62aa4a | 333 | |
6c62aa4a YL |
334 | if (apicid_to_node[apicid] != NUMA_NO_NODE) |
335 | node = apicid_to_node[apicid]; | |
336 | if (!node_online(node)) { | |
337 | /* Two possibilities here: | |
338 | - The CPU is missing memory and no node was created. | |
339 | In that case try picking one from a nearby CPU | |
340 | - The APIC IDs differ from the HyperTransport node IDs | |
341 | which the K8 northbridge parsing fills in. | |
342 | Assume they are all increased by a constant offset, | |
343 | but in the same order as the HT nodeids. | |
344 | If that doesn't result in a usable node fall back to the | |
345 | path for the previous case. */ | |
346 | ||
347 | int ht_nodeid = c->initial_apicid; | |
348 | ||
349 | if (ht_nodeid >= 0 && | |
350 | apicid_to_node[ht_nodeid] != NUMA_NO_NODE) | |
351 | node = apicid_to_node[ht_nodeid]; | |
352 | /* Pick a nearby node */ | |
353 | if (!node_online(node)) | |
354 | node = nearby_node(apicid); | |
355 | } | |
356 | numa_set_node(cpu, node); | |
6c62aa4a YL |
357 | #endif |
358 | } | |
359 | ||
11fdd252 YL |
360 | static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c) |
361 | { | |
362 | #ifdef CONFIG_X86_HT | |
363 | unsigned bits, ecx; | |
364 | ||
365 | /* Multi core CPU? */ | |
366 | if (c->extended_cpuid_level < 0x80000008) | |
367 | return; | |
368 | ||
369 | ecx = cpuid_ecx(0x80000008); | |
370 | ||
371 | c->x86_max_cores = (ecx & 0xff) + 1; | |
372 | ||
373 | /* CPU telling us the core id bits shift? */ | |
374 | bits = (ecx >> 12) & 0xF; | |
375 | ||
376 | /* Otherwise recompute */ | |
377 | if (bits == 0) { | |
378 | while ((1 << bits) < c->x86_max_cores) | |
379 | bits++; | |
380 | } | |
381 | ||
382 | c->x86_coreid_bits = bits; | |
383 | #endif | |
384 | } | |
385 | ||
03ae5768 | 386 | static void __cpuinit early_init_amd(struct cpuinfo_x86 *c) |
2b16a235 | 387 | { |
11fdd252 YL |
388 | early_init_amd_mc(c); |
389 | ||
40fb1715 VP |
390 | /* |
391 | * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate | |
392 | * with P/T states and does not stop in deep C-states | |
393 | */ | |
394 | if (c->x86_power & (1 << 8)) { | |
e3224234 | 395 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); |
40fb1715 VP |
396 | set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); |
397 | } | |
5fef55fd | 398 | |
6c62aa4a YL |
399 | #ifdef CONFIG_X86_64 |
400 | set_cpu_cap(c, X86_FEATURE_SYSCALL32); | |
401 | #else | |
5fef55fd | 402 | /* Set MTRR capability flag if appropriate */ |
6c62aa4a YL |
403 | if (c->x86 == 5) |
404 | if (c->x86_model == 13 || c->x86_model == 9 || | |
405 | (c->x86_model == 8 && c->x86_mask >= 8)) | |
406 | set_cpu_cap(c, X86_FEATURE_K6_MTRR); | |
407 | #endif | |
42937e81 AH |
408 | #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) |
409 | /* check CPU config space for extended APIC ID */ | |
2cb07860 | 410 | if (cpu_has_apic && c->x86 >= 0xf) { |
42937e81 AH |
411 | unsigned int val; |
412 | val = read_pci_config(0, 24, 0, 0x68); | |
413 | if ((val & ((1 << 17) | (1 << 18))) == ((1 << 17) | (1 << 18))) | |
414 | set_cpu_cap(c, X86_FEATURE_EXTD_APICID); | |
415 | } | |
416 | #endif | |
acf01734 BP |
417 | |
418 | /* We need to do the following only once */ | |
419 | if (c != &boot_cpu_data) | |
420 | return; | |
421 | ||
422 | if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { | |
423 | ||
424 | if (c->x86 > 0x10 || | |
425 | (c->x86 == 0x10 && c->x86_model >= 0x2)) { | |
426 | u64 val; | |
427 | ||
428 | rdmsrl(MSR_K7_HWCR, val); | |
429 | if (!(val & BIT(24))) | |
430 | printk(KERN_WARNING FW_BUG "TSC doesn't count " | |
431 | "with P0 frequency!\n"); | |
432 | } | |
433 | } | |
2b16a235 AK |
434 | } |
435 | ||
b4af3f7c | 436 | static void __cpuinit init_amd(struct cpuinfo_x86 *c) |
1da177e4 | 437 | { |
7d318d77 | 438 | #ifdef CONFIG_SMP |
3c92c2ba | 439 | unsigned long long value; |
7d318d77 | 440 | |
fb87a298 PC |
441 | /* |
442 | * Disable TLB flush filter by setting HWCR.FFDIS on K8 | |
7d318d77 AK |
443 | * bit 6 of msr C001_0015 |
444 | * | |
445 | * Errata 63 for SH-B3 steppings | |
446 | * Errata 122 for all steppings (F+ have it disabled by default) | |
447 | */ | |
11fdd252 | 448 | if (c->x86 == 0xf) { |
7d318d77 AK |
449 | rdmsrl(MSR_K7_HWCR, value); |
450 | value |= 1 << 6; | |
451 | wrmsrl(MSR_K7_HWCR, value); | |
452 | } | |
453 | #endif | |
454 | ||
2b16a235 AK |
455 | early_init_amd(c); |
456 | ||
fb87a298 PC |
457 | /* |
458 | * Bit 31 in normal CPUID used for nonstandard 3DNow ID; | |
16282a8e | 459 | * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway |
fb87a298 | 460 | */ |
16282a8e | 461 | clear_cpu_cap(c, 0*32+31); |
fb87a298 | 462 | |
6c62aa4a YL |
463 | #ifdef CONFIG_X86_64 |
464 | /* On C+ stepping K8 rep microcode works well for copy/memset */ | |
465 | if (c->x86 == 0xf) { | |
466 | u32 level; | |
467 | ||
468 | level = cpuid_eax(1); | |
8bdbd962 | 469 | if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) |
6c62aa4a | 470 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); |
fbd8b181 KW |
471 | |
472 | /* | |
473 | * Some BIOSes incorrectly force this feature, but only K8 | |
474 | * revision D (model = 0x14) and later actually support it. | |
6b0f43dd | 475 | * (AMD Erratum #110, docId: 25759). |
fbd8b181 | 476 | */ |
6b0f43dd BP |
477 | if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { |
478 | u64 val; | |
479 | ||
fbd8b181 | 480 | clear_cpu_cap(c, X86_FEATURE_LAHF_LM); |
6b0f43dd BP |
481 | if (!rdmsrl_amd_safe(0xc001100d, &val)) { |
482 | val &= ~(1ULL << 32); | |
483 | wrmsrl_amd_safe(0xc001100d, val); | |
484 | } | |
485 | } | |
486 | ||
6c62aa4a | 487 | } |
12d8a961 | 488 | if (c->x86 >= 0x10) |
6c62aa4a | 489 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); |
0d96b9ff YL |
490 | |
491 | /* get apicid instead of initial apic id from cpuid */ | |
492 | c->apicid = hard_smp_processor_id(); | |
6c62aa4a YL |
493 | #else |
494 | ||
495 | /* | |
496 | * FIXME: We should handle the K5 here. Set up the write | |
497 | * range and also turn on MSR 83 bits 4 and 31 (write alloc, | |
498 | * no bus pipeline) | |
499 | */ | |
500 | ||
fb87a298 PC |
501 | switch (c->x86) { |
502 | case 4: | |
11fdd252 YL |
503 | init_amd_k5(c); |
504 | break; | |
fb87a298 | 505 | case 5: |
11fdd252 | 506 | init_amd_k6(c); |
1da177e4 | 507 | break; |
11fdd252 YL |
508 | case 6: /* An Athlon/Duron */ |
509 | init_amd_k7(c); | |
1da177e4 LT |
510 | break; |
511 | } | |
11fdd252 YL |
512 | |
513 | /* K6s reports MCEs but don't actually have all the MSRs */ | |
514 | if (c->x86 < 6) | |
515 | clear_cpu_cap(c, X86_FEATURE_MCE); | |
6c62aa4a | 516 | #endif |
11fdd252 | 517 | |
6c62aa4a | 518 | /* Enable workaround for FXSAVE leak */ |
18bd057b | 519 | if (c->x86 >= 6) |
16282a8e | 520 | set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK); |
1da177e4 | 521 | |
11fdd252 YL |
522 | if (!c->x86_model_id[0]) { |
523 | switch (c->x86) { | |
524 | case 0xf: | |
525 | /* Should distinguish Models here, but this is only | |
526 | a fallback anyways. */ | |
527 | strcpy(c->x86_model_id, "Hammer"); | |
528 | break; | |
529 | } | |
530 | } | |
3dd9d514 | 531 | |
27c13ece | 532 | cpu_detect_cache_sizes(c); |
3dd9d514 | 533 | |
11fdd252 | 534 | /* Multi core CPU? */ |
6c62aa4a | 535 | if (c->extended_cpuid_level >= 0x80000008) { |
11fdd252 | 536 | amd_detect_cmp(c); |
6c62aa4a YL |
537 | srat_detect_node(c); |
538 | } | |
faee9a5d | 539 | |
6c62aa4a | 540 | #ifdef CONFIG_X86_32 |
11fdd252 | 541 | detect_ht(c); |
6c62aa4a | 542 | #endif |
39b3a791 | 543 | |
11fdd252 | 544 | if (c->extended_cpuid_level >= 0x80000006) { |
d9fadd7b | 545 | if (cpuid_edx(0x80000006) & 0xf000) |
67cddd94 AK |
546 | num_cache_leaves = 4; |
547 | else | |
548 | num_cache_leaves = 3; | |
549 | } | |
3556ddfa | 550 | |
12d8a961 | 551 | if (c->x86 >= 0xf) |
11fdd252 | 552 | set_cpu_cap(c, X86_FEATURE_K8); |
de421863 | 553 | |
11fdd252 YL |
554 | if (cpu_has_xmm2) { |
555 | /* MFENCE stops RDTSC speculation */ | |
16282a8e | 556 | set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); |
11fdd252 | 557 | } |
6c62aa4a YL |
558 | |
559 | #ifdef CONFIG_X86_64 | |
560 | if (c->x86 == 0x10) { | |
561 | /* do this for boot cpu */ | |
562 | if (c == &boot_cpu_data) | |
563 | check_enable_amd_mmconf_dmi(); | |
564 | ||
565 | fam10h_check_enable_mmcfg(); | |
566 | } | |
567 | ||
12d8a961 | 568 | if (c == &boot_cpu_data && c->x86 >= 0xf) { |
6c62aa4a YL |
569 | unsigned long long tseg; |
570 | ||
571 | /* | |
572 | * Split up direct mapping around the TSEG SMM area. | |
573 | * Don't do it for gbpages because there seems very little | |
574 | * benefit in doing so. | |
575 | */ | |
576 | if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { | |
8bdbd962 AC |
577 | printk(KERN_DEBUG "tseg: %010llx\n", tseg); |
578 | if ((tseg>>PMD_SHIFT) < | |
6c62aa4a | 579 | (max_low_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) || |
8bdbd962 | 580 | ((tseg>>PMD_SHIFT) < |
6c62aa4a | 581 | (max_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) && |
8bdbd962 AC |
582 | (tseg>>PMD_SHIFT) >= (1ULL<<(32 - PMD_SHIFT)))) |
583 | set_memory_4k((unsigned long)__va(tseg), 1); | |
6c62aa4a YL |
584 | } |
585 | } | |
586 | #endif | |
1da177e4 LT |
587 | } |
588 | ||
6c62aa4a | 589 | #ifdef CONFIG_X86_32 |
8bdbd962 AC |
590 | static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, |
591 | unsigned int size) | |
1da177e4 LT |
592 | { |
593 | /* AMD errata T13 (order #21922) */ | |
594 | if ((c->x86 == 6)) { | |
8bdbd962 AC |
595 | /* Duron Rev A0 */ |
596 | if (c->x86_model == 3 && c->x86_mask == 0) | |
1da177e4 | 597 | size = 64; |
8bdbd962 | 598 | /* Tbird rev A1/A2 */ |
1da177e4 | 599 | if (c->x86_model == 4 && |
8bdbd962 | 600 | (c->x86_mask == 0 || c->x86_mask == 1)) |
1da177e4 LT |
601 | size = 256; |
602 | } | |
603 | return size; | |
604 | } | |
6c62aa4a | 605 | #endif |
1da177e4 | 606 | |
02dde8b4 | 607 | static const struct cpu_dev __cpuinitconst amd_cpu_dev = { |
1da177e4 | 608 | .c_vendor = "AMD", |
fb87a298 | 609 | .c_ident = { "AuthenticAMD" }, |
6c62aa4a | 610 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
611 | .c_models = { |
612 | { .vendor = X86_VENDOR_AMD, .family = 4, .model_names = | |
613 | { | |
614 | [3] = "486 DX/2", | |
615 | [7] = "486 DX/2-WB", | |
fb87a298 PC |
616 | [8] = "486 DX/4", |
617 | [9] = "486 DX/4-WB", | |
1da177e4 | 618 | [14] = "Am5x86-WT", |
fb87a298 | 619 | [15] = "Am5x86-WB" |
1da177e4 LT |
620 | } |
621 | }, | |
622 | }, | |
6c62aa4a YL |
623 | .c_size_cache = amd_size_cache, |
624 | #endif | |
03ae5768 | 625 | .c_early_init = early_init_amd, |
1da177e4 | 626 | .c_init = init_amd, |
10a434fc | 627 | .c_x86_vendor = X86_VENDOR_AMD, |
1da177e4 LT |
628 | }; |
629 | ||
10a434fc | 630 | cpu_dev_register(amd_cpu_dev); |
d78d671d HR |
631 | |
632 | /* | |
633 | * AMD errata checking | |
634 | * | |
635 | * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or | |
636 | * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that | |
637 | * have an OSVW id assigned, which it takes as first argument. Both take a | |
638 | * variable number of family-specific model-stepping ranges created by | |
639 | * AMD_MODEL_RANGE(). Each erratum also has to be declared as extern const | |
640 | * int[] in arch/x86/include/asm/processor.h. | |
641 | * | |
642 | * Example: | |
643 | * | |
644 | * const int amd_erratum_319[] = | |
645 | * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), | |
646 | * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), | |
647 | * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); | |
648 | */ | |
649 | ||
9d8888c2 HR |
650 | const int amd_erratum_400[] = |
651 | AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), | |
652 | AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); | |
a5b91606 | 653 | EXPORT_SYMBOL_GPL(amd_erratum_400); |
9d8888c2 | 654 | |
1be85a6d HR |
655 | const int amd_erratum_383[] = |
656 | AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); | |
a5b91606 | 657 | EXPORT_SYMBOL_GPL(amd_erratum_383); |
9d8888c2 | 658 | |
d78d671d HR |
659 | bool cpu_has_amd_erratum(const int *erratum) |
660 | { | |
661 | struct cpuinfo_x86 *cpu = ¤t_cpu_data; | |
662 | int osvw_id = *erratum++; | |
663 | u32 range; | |
664 | u32 ms; | |
665 | ||
666 | /* | |
667 | * If called early enough that current_cpu_data hasn't been initialized | |
668 | * yet, fall back to boot_cpu_data. | |
669 | */ | |
670 | if (cpu->x86 == 0) | |
671 | cpu = &boot_cpu_data; | |
672 | ||
673 | if (cpu->x86_vendor != X86_VENDOR_AMD) | |
674 | return false; | |
675 | ||
676 | if (osvw_id >= 0 && osvw_id < 65536 && | |
677 | cpu_has(cpu, X86_FEATURE_OSVW)) { | |
678 | u64 osvw_len; | |
679 | ||
680 | rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); | |
681 | if (osvw_id < osvw_len) { | |
682 | u64 osvw_bits; | |
683 | ||
684 | rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), | |
685 | osvw_bits); | |
686 | return osvw_bits & (1ULL << (osvw_id & 0x3f)); | |
687 | } | |
688 | } | |
689 | ||
690 | /* OSVW unavailable or ID unknown, match family-model-stepping range */ | |
07a7795c | 691 | ms = (cpu->x86_model << 4) | cpu->x86_mask; |
d78d671d HR |
692 | while ((range = *erratum++)) |
693 | if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && | |
694 | (ms >= AMD_MODEL_RANGE_START(range)) && | |
695 | (ms <= AMD_MODEL_RANGE_END(range))) | |
696 | return true; | |
697 | ||
698 | return false; | |
699 | } | |
a5b91606 PA |
700 | |
701 | EXPORT_SYMBOL_GPL(cpu_has_amd_erratum); |