[mirror_ubuntu-artful-kernel.git] / arch / x86 / kernel / cpu / amd.c

#include <linux/init.h>
#include <linux/bitops.h>
#include <linux/mm.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/apic.h>

#include <mach_apic.h>
#include "cpu.h"

/*
 *	B step AMD K6 before B 9730xxxx have hardware bugs that can cause
 *	misexecution of code under Linux. Owners of such processors should
 *	contact AMD for precise details and a CPU swap.
 *
 *	See	http://www.multimania.com/poulot/k6bug.html
 *		http://www.amd.com/K6/k6docs/revgd.html
 *
 *	The following test is erm.. interesting. AMD neglected to up
 *	the chip setting when fixing the bug but they also tweaked some
 *	performance at the same time..
 */

extern void vide(void);
__asm__(".align 4\nvide: ret");

static void __cpuinit init_amd_k5(struct cpuinfo_x86 *c)
{
/*
 * General Systems BIOSen alias the cpu frequency registers
 * of the Elan at 0x000df000. Unfortuantly, one of the Linux
 * drivers subsequently pokes it, and changes the CPU speed.
 * Workaround : Remove the unneeded alias.
 */
#define CBAR		(0xfffc) /* Configuration Base Address  (32-bit) */
#define CBAR_ENB	(0x80000000)
#define CBAR_KEY	(0X000000CB)
	if (c->x86_model == 9 || c->x86_model == 10) {
		if (inl (CBAR) & CBAR_ENB)
			outl (0 | CBAR_KEY, CBAR);
	}
}


static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c)
{
	u32 l, h;
	int mbytes = num_physpages >> (20-PAGE_SHIFT);

	if (c->x86_model < 6) {
		/* Based on AMD doc 20734R - June 2000 */
		if (c->x86_model == 0) {
			clear_cpu_cap(c, X86_FEATURE_APIC);
			set_cpu_cap(c, X86_FEATURE_PGE);
		}
		return;
	}

	if (c->x86_model == 6 && c->x86_mask == 1) {
		const int K6_BUG_LOOP = 1000000;
		int n;
		void (*f_vide)(void);
		unsigned long d, d2;

		printk(KERN_INFO "AMD K6 stepping B detected - ");

		/*
		 * It looks like AMD fixed the 2.6.2 bug and improved indirect
		 * calls at the same time.
		 */

		n = K6_BUG_LOOP;
		f_vide = vide;
		rdtscl(d);
		while (n--)
			f_vide();
		rdtscl(d2);
		d = d2-d;

		if (d > 20*K6_BUG_LOOP)
			printk("system stability may be impaired when more than 32 MB are used.\n");
		else
			printk("probably OK (after B9730xxxx).\n");
		printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
	}

	/* K6 with old style WHCR */
	if (c->x86_model < 8 ||
	   (c->x86_model == 8 && c->x86_mask < 8)) {
		/* We can only write allocate on the low 508Mb */
		if (mbytes > 508)
			mbytes = 508;

		rdmsr(MSR_K6_WHCR, l, h);
		if ((l&0x0000FFFF) == 0) {
			unsigned long flags;
			l = (1<<0)|((mbytes/4)<<1);
			local_irq_save(flags);
			wbinvd();
			wrmsr(MSR_K6_WHCR, l, h);
			local_irq_restore(flags);
			printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
				mbytes);
		}
		return;
	}

	if ((c->x86_model == 8 && c->x86_mask > 7) ||
	     c->x86_model == 9 || c->x86_model == 13) {
		/* The more serious chips .. */

		if (mbytes > 4092)
			mbytes = 4092;

		rdmsr(MSR_K6_WHCR, l, h);
		if ((l&0xFFFF0000) == 0) {
			unsigned long flags;
			l = ((mbytes>>2)<<22)|(1<<16);
			local_irq_save(flags);
			wbinvd();
			wrmsr(MSR_K6_WHCR, l, h);
			local_irq_restore(flags);
			printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
				mbytes);
		}

		return;
	}

	if (c->x86_model == 10) {
		/* AMD Geode LX is model 10 */
		/* placeholder for any needed mods */
		return;
	}
}

static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c)
{
	u32 l, h;

	/*
	 * Bit 15 of Athlon specific MSR 15, needs to be 0
	 * to enable SSE on Palomino/Morgan/Barton CPU's.
	 * If the BIOS didn't enable it already, enable it here.
	 */
	if (c->x86_model >= 6 && c->x86_model <= 10) {
		if (!cpu_has(c, X86_FEATURE_XMM)) {
			printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
			rdmsr(MSR_K7_HWCR, l, h);
			l &= ~0x00008000;
			wrmsr(MSR_K7_HWCR, l, h);
			set_cpu_cap(c, X86_FEATURE_XMM);
		}
	}

	/*
	 * It's been determined by AMD that Athlons since model 8 stepping 1
	 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
	 * As per AMD technical note 27212 0.2
	 */
	if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
		rdmsr(MSR_K7_CLK_CTL, l, h);
		if ((l & 0xfff00000) != 0x20000000) {
			printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
				((l & 0x000fffff)|0x20000000));
			wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
		}
	}

	set_cpu_cap(c, X86_FEATURE_K7);
}

/*
 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
 * Assumes number of cores is a power of two.
 */
static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
{
#ifdef CONFIG_X86_HT
	unsigned bits;

	bits = c->x86_coreid_bits;

	/* Low order bits define the core id (index of core in socket) */
	c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
	/* Convert the initial APIC ID into the socket ID */
	c->phys_proc_id = c->initial_apicid >> bits;
#endif
}

static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
{
#ifdef CONFIG_X86_HT
	unsigned bits, ecx;

	/* Multi core CPU? */
	if (c->extended_cpuid_level < 0x80000008)
		return;

	ecx = cpuid_ecx(0x80000008);

	c->x86_max_cores = (ecx & 0xff) + 1;

	/* CPU telling us the core id bits shift? */
	bits = (ecx >> 12) & 0xF;

	/* Otherwise recompute */
	if (bits == 0) {
		while ((1 << bits) < c->x86_max_cores)
			bits++;
	}

	c->x86_coreid_bits = bits;
#endif
}

static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
{
	early_init_amd_mc(c);

	if (c->x86_power & (1<<8))
		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);

	/*  Set MTRR capability flag if appropriate */
	if (c->x86_model == 13 || c->x86_model == 9 ||
	   (c->x86_model == 8 && c->x86_mask >= 8))
		set_cpu_cap(c, X86_FEATURE_K6_MTRR);
}

static void __cpuinit init_amd(struct cpuinfo_x86 *c)
{
#ifdef CONFIG_SMP
	unsigned long long value;

	/*
	 * Disable TLB flush filter by setting HWCR.FFDIS on K8
	 * bit 6 of msr C001_0015
	 *
	 * Errata 63 for SH-B3 steppings
	 * Errata 122 for all steppings (F+ have it disabled by default)
	 */
	if (c->x86 == 0xf) {
		rdmsrl(MSR_K7_HWCR, value);
		value |= 1 << 6;
		wrmsrl(MSR_K7_HWCR, value);
	}
#endif

	early_init_amd(c);

	/*
	 *	FIXME: We should handle the K5 here. Set up the write
	 *	range and also turn on MSR 83 bits 4 and 31 (write alloc,
	 *	no bus pipeline)
	 */

	/*
	 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
	 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
	 */
	clear_cpu_cap(c, 0*32+31);

	switch (c->x86) {
	case 4:
		init_amd_k5(c);
		break;
	case 5:
		init_amd_k6(c);
		break;
	case 6: /* An Athlon/Duron */
		init_amd_k7(c);
		break;
	}

	/* K6s reports MCEs but don't actually have all the MSRs */
	if (c->x86 < 6)
		clear_cpu_cap(c, X86_FEATURE_MCE);

	if (c->x86 >= 6)
		set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);

	if (!c->x86_model_id[0]) {
		switch (c->x86) {
		case 0xf:
			/* Should distinguish Models here, but this is only
			   a fallback anyways. */
			strcpy(c->x86_model_id, "Hammer");
			break;
		}
	}

	display_cacheinfo(c);

	/* Multi core CPU? */
	if (c->extended_cpuid_level >= 0x80000008)
		amd_detect_cmp(c);

	detect_ht(c);

	if (c->extended_cpuid_level >= 0x80000006) {
		if ((c->x86 >= 0x0f) && (cpuid_edx(0x80000006) & 0xf000))
			num_cache_leaves = 4;
		else
			num_cache_leaves = 3;
	}

	if (c->x86 >= 0xf && c->x86 <= 0x11)
		set_cpu_cap(c, X86_FEATURE_K8);

	if (cpu_has_xmm2) {
		/* MFENCE stops RDTSC speculation */
		set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
	}
}

static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
{
	/* AMD errata T13 (order #21922) */
	if ((c->x86 == 6)) {
		if (c->x86_model == 3 && c->x86_mask == 0)	/* Duron Rev A0 */
			size = 64;
		if (c->x86_model == 4 &&
		    (c->x86_mask == 0 || c->x86_mask == 1))	/* Tbird rev A1/A2 */
			size = 256;
	}
	return size;
}

static struct cpu_dev amd_cpu_dev __cpuinitdata = {
	.c_vendor	= "AMD",
	.c_ident	= { "AuthenticAMD" },
	.c_models = {
		{ .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
		  {
			  [3] = "486 DX/2",
			  [7] = "486 DX/2-WB",
			  [8] = "486 DX/4",
			  [9] = "486 DX/4-WB",
			  [14] = "Am5x86-WT",
			  [15] = "Am5x86-WB"
		  }
		},
	},
	.c_early_init   = early_init_amd,
	.c_init		= init_amd,
	.c_size_cache	= amd_size_cache,
	.c_x86_vendor	= X86_VENDOR_AMD,
};

cpu_dev_register(amd_cpu_dev);
Commit	Line	Data
1da177e4 LT	1	#include <linux/init.h>
	2	#include <linux/bitops.h>
	3	#include <linux/mm.h>
	4	#include <asm/io.h>
	5	#include <asm/processor.h>
d3f7eae1	6	#include <asm/apic.h>
1da177e4	7
dd46e3ca	8	#include <mach_apic.h>
1da177e4 LT	9	#include "cpu.h"
	10
	11	/*
	12	* B step AMD K6 before B 9730xxxx have hardware bugs that can cause
	13	* misexecution of code under Linux. Owners of such processors should
	14	* contact AMD for precise details and a CPU swap.
	15	*
	16	* See http://www.multimania.com/poulot/k6bug.html
	17	* http://www.amd.com/K6/k6docs/revgd.html
	18	*
	19	* The following test is erm.. interesting. AMD neglected to up
	20	* the chip setting when fixing the bug but they also tweaked some
	21	* performance at the same time..
	22	*/
fb87a298	23
1da177e4 LT	24	extern void vide(void);
	25	__asm__(".align 4\nvide: ret");
	26
11fdd252 YL	27	static void __cpuinit init_amd_k5(struct cpuinfo_x86 *c)
	28	{
	29	/*
	30	* General Systems BIOSen alias the cpu frequency registers
	31	* of the Elan at 0x000df000. Unfortuantly, one of the Linux
	32	* drivers subsequently pokes it, and changes the CPU speed.
	33	* Workaround : Remove the unneeded alias.
	34	*/
	35	#define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
	36	#define CBAR_ENB (0x80000000)
	37	#define CBAR_KEY (0X000000CB)
	38	if (c->x86_model == 9 \|\| c->x86_model == 10) {
	39	if (inl (CBAR) & CBAR_ENB)
	40	outl (0 \| CBAR_KEY, CBAR);
	41	}
	42	}
	43
	44
	45	static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c)
	46	{
	47	u32 l, h;
	48	int mbytes = num_physpages >> (20-PAGE_SHIFT);
	49
	50	if (c->x86_model < 6) {
	51	/* Based on AMD doc 20734R - June 2000 */
	52	if (c->x86_model == 0) {
	53	clear_cpu_cap(c, X86_FEATURE_APIC);
	54	set_cpu_cap(c, X86_FEATURE_PGE);
	55	}
	56	return;
	57	}
	58
	59	if (c->x86_model == 6 && c->x86_mask == 1) {
	60	const int K6_BUG_LOOP = 1000000;
	61	int n;
	62	void (*f_vide)(void);
	63	unsigned long d, d2;
	64
	65	printk(KERN_INFO "AMD K6 stepping B detected - ");
	66
	67	/*
	68	* It looks like AMD fixed the 2.6.2 bug and improved indirect
	69	* calls at the same time.
	70	*/
	71
	72	n = K6_BUG_LOOP;
	73	f_vide = vide;
	74	rdtscl(d);
	75	while (n--)
	76	f_vide();
	77	rdtscl(d2);
	78	d = d2-d;
	79
	80	if (d > 20*K6_BUG_LOOP)
	81	printk("system stability may be impaired when more than 32 MB are used.\n");
	82	else
	83	printk("probably OK (after B9730xxxx).\n");
	84	printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
	85	}
	86
	87	/* K6 with old style WHCR */
	88	if (c->x86_model < 8 \|\|
	89	(c->x86_model == 8 && c->x86_mask < 8)) {
	90	/* We can only write allocate on the low 508Mb */
91	if (mbytes > 508)
92	mbytes = 508;
93
94	rdmsr(MSR_K6_WHCR, l, h);
95	if ((l&0x0000FFFF) == 0) {
96	unsigned long flags;
97	l = (1<<0)\|((mbytes/4)<<1);
98	local_irq_save(flags);
99	wbinvd();
100	wrmsr(MSR_K6_WHCR, l, h);
101	local_irq_restore(flags);
102	printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
103	mbytes);
104	}
105	return;
106	}
107
108	if ((c->x86_model == 8 && c->x86_mask > 7) \|\|
109	c->x86_model == 9 \|\| c->x86_model == 13) {
110	/* The more serious chips .. */
111
112	if (mbytes > 4092)
113	mbytes = 4092;
114
115	rdmsr(MSR_K6_WHCR, l, h);
116	if ((l&0xFFFF0000) == 0) {
117	unsigned long flags;
118	l = ((mbytes>>2)<<22)\|(1<<16);
119	local_irq_save(flags);
120	wbinvd();
121	wrmsr(MSR_K6_WHCR, l, h);
122	local_irq_restore(flags);
123	printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
124	mbytes);
125	}
126
127	return;
128	}
129
130	if (c->x86_model == 10) {
131	/* AMD Geode LX is model 10 */
132	/* placeholder for any needed mods */
133	return;
134	}
135	}
136
137	static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c)
138	{
139	u32 l, h;
140
141	/*
142	* Bit 15 of Athlon specific MSR 15, needs to be 0
143	* to enable SSE on Palomino/Morgan/Barton CPU's.
144	* If the BIOS didn't enable it already, enable it here.
145	*/
146	if (c->x86_model >= 6 && c->x86_model <= 10) {
147	if (!cpu_has(c, X86_FEATURE_XMM)) {
148	printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
149	rdmsr(MSR_K7_HWCR, l, h);
150	l &= ~0x00008000;
151	wrmsr(MSR_K7_HWCR, l, h);
152	set_cpu_cap(c, X86_FEATURE_XMM);
153	}
154	}
155
156	/*
157	* It's been determined by AMD that Athlons since model 8 stepping 1
158	* are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
159	* As per AMD technical note 27212 0.2
160	*/
161	if ((c->x86_model == 8 && c->x86_mask >= 1) \|\| (c->x86_model > 8)) {
162	rdmsr(MSR_K7_CLK_CTL, l, h);
163	if ((l & 0xfff00000) != 0x20000000) {
164	printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
165	((l & 0x000fffff)\|0x20000000));
166	wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)\|0x20000000, h);
167	}
168	}
169
170	set_cpu_cap(c, X86_FEATURE_K7);
171	}
172
173	/*
174	* On a AMD dual core setup the lower bits of the APIC id distingush the cores.
175	* Assumes number of cores is a power of two.
176	*/
177	static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
178	{
179	#ifdef CONFIG_X86_HT
180	unsigned bits;
181
182	bits = c->x86_coreid_bits;
183
184	/* Low order bits define the core id (index of core in socket) */
185	c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
186	/* Convert the initial APIC ID into the socket ID */
187	c->phys_proc_id = c->initial_apicid >> bits;
188	#endif
189	}
190
191	static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
192	{
193	#ifdef CONFIG_X86_HT
194	unsigned bits, ecx;
195
196	/* Multi core CPU? */
197	if (c->extended_cpuid_level < 0x80000008)
198	return;
199
200	ecx = cpuid_ecx(0x80000008);
201
202	c->x86_max_cores = (ecx & 0xff) + 1;
203
204	/* CPU telling us the core id bits shift? */
205	bits = (ecx >> 12) & 0xF;
206
207	/* Otherwise recompute */
208	if (bits == 0) {
209	while ((1 << bits) < c->x86_max_cores)
210	bits++;
211	}
212
213	c->x86_coreid_bits = bits;
214	#endif
215	}
216
03ae5768	217	static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
2b16a235	218	{
11fdd252 YL	219	early_init_amd_mc(c);
11fdd252 YL	220
e3224234 YL	221	if (c->x86_power & (1<<8))
e3224234 YL	222	set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
5fef55fd YL	223
	224	/* Set MTRR capability flag if appropriate */
	225	if (c->x86_model == 13 \|\| c->x86_model == 9 \|\|
	226	(c->x86_model == 8 && c->x86_mask >= 8))
	227	set_cpu_cap(c, X86_FEATURE_K6_MTRR);
2b16a235 AK	228	}
2b16a235 AK	229
b4af3f7c	230	static void __cpuinit init_amd(struct cpuinfo_x86 *c)
1da177e4	231	{
7d318d77	232	#ifdef CONFIG_SMP
3c92c2ba	233	unsigned long long value;
7d318d77	234
fb87a298 PC	235	/*
fb87a298 PC	236	* Disable TLB flush filter by setting HWCR.FFDIS on K8
7d318d77 AK	237	* bit 6 of msr C001_0015
	238	*
	239	* Errata 63 for SH-B3 steppings
	240	* Errata 122 for all steppings (F+ have it disabled by default)
	241	*/
11fdd252	242	if (c->x86 == 0xf) {
7d318d77 AK	243	rdmsrl(MSR_K7_HWCR, value);
	244	value \|= 1 << 6;
	245	wrmsrl(MSR_K7_HWCR, value);
	246	}
	247	#endif
	248
2b16a235 AK	249	early_init_amd(c);
2b16a235 AK	250
1da177e4 LT	251	/*
	252	* FIXME: We should handle the K5 here. Set up the write
	253	* range and also turn on MSR 83 bits 4 and 31 (write alloc,
	254	* no bus pipeline)
	255	*/
	256
fb87a298 PC	257	/*
fb87a298 PC	258	* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
16282a8e	259	* 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
fb87a298	260	*/
16282a8e	261	clear_cpu_cap(c, 0*32+31);
fb87a298	262
fb87a298 PC	263	switch (c->x86) {
fb87a298 PC	264	case 4:
11fdd252 YL	265	init_amd_k5(c);
11fdd252 YL	266	break;
fb87a298	267	case 5:
11fdd252	268	init_amd_k6(c);
1da177e4	269	break;
11fdd252 YL	270	case 6: /* An Athlon/Duron */
11fdd252 YL	271	init_amd_k7(c);
1da177e4 LT	272	break;
1da177e4 LT	273	}
11fdd252 YL	274
	275	/* K6s reports MCEs but don't actually have all the MSRs */
	276	if (c->x86 < 6)
	277	clear_cpu_cap(c, X86_FEATURE_MCE);
	278
18bd057b	279	if (c->x86 >= 6)
16282a8e	280	set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
1da177e4	281
11fdd252 YL	282	if (!c->x86_model_id[0]) {
	283	switch (c->x86) {
	284	case 0xf:
	285	/* Should distinguish Models here, but this is only
	286	a fallback anyways. */
	287	strcpy(c->x86_model_id, "Hammer");
	288	break;
	289	}
	290	}
3dd9d514	291
11fdd252	292	display_cacheinfo(c);
3dd9d514	293
11fdd252 YL	294	/* Multi core CPU? */
	295	if (c->extended_cpuid_level >= 0x80000008)
	296	amd_detect_cmp(c);
faee9a5d	297
11fdd252	298	detect_ht(c);
39b3a791	299
11fdd252 YL	300	if (c->extended_cpuid_level >= 0x80000006) {
11fdd252 YL	301	if ((c->x86 >= 0x0f) && (cpuid_edx(0x80000006) & 0xf000))
67cddd94 AK	302	num_cache_leaves = 4;
	303	else
	304	num_cache_leaves = 3;
	305	}
3556ddfa	306
11fdd252 YL	307	if (c->x86 >= 0xf && c->x86 <= 0x11)
11fdd252 YL	308	set_cpu_cap(c, X86_FEATURE_K8);
de421863	309
11fdd252 YL	310	if (cpu_has_xmm2) {
11fdd252 YL	311	/* MFENCE stops RDTSC speculation */
16282a8e	312	set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
11fdd252	313	}
1da177e4 LT	314	}
1da177e4 LT	315
fb87a298	316	static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
1da177e4 LT	317	{
	318	/* AMD errata T13 (order #21922) */
	319	if ((c->x86 == 6)) {
	320	if (c->x86_model == 3 && c->x86_mask == 0) /* Duron Rev A0 */
	321	size = 64;
	322	if (c->x86_model == 4 &&
fb87a298	323	(c->x86_mask == 0 \|\| c->x86_mask == 1)) /* Tbird rev A1/A2 */
1da177e4 LT	324	size = 256;
	325	}
	326	return size;
	327	}
	328
95414930	329	static struct cpu_dev amd_cpu_dev __cpuinitdata = {
1da177e4	330	.c_vendor = "AMD",
fb87a298	331	.c_ident = { "AuthenticAMD" },
1da177e4 LT	332	.c_models = {
	333	{ .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
	334	{
	335	[3] = "486 DX/2",
	336	[7] = "486 DX/2-WB",
fb87a298 PC	337	[8] = "486 DX/4",
fb87a298 PC	338	[9] = "486 DX/4-WB",
1da177e4	339	[14] = "Am5x86-WT",
fb87a298	340	[15] = "Am5x86-WB"
1da177e4 LT	341	}
	342	},
	343	},
03ae5768	344	.c_early_init = early_init_amd,
1da177e4	345	.c_init = init_amd,
1da177e4	346	.c_size_cache = amd_size_cache,
10a434fc	347	.c_x86_vendor = X86_VENDOR_AMD,
1da177e4 LT	348	};
1da177e4 LT	349
10a434fc	350	cpu_dev_register(amd_cpu_dev);