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69c60c88 | 1 | #include <linux/export.h> |
1da177e4 | 2 | #include <linux/bitops.h> |
5cdd174f | 3 | #include <linux/elf.h> |
1da177e4 | 4 | #include <linux/mm.h> |
8d71a2ea | 5 | |
8bdbd962 | 6 | #include <linux/io.h> |
c98fdeaa | 7 | #include <linux/sched.h> |
e6017571 | 8 | #include <linux/sched/clock.h> |
4e26d11f | 9 | #include <linux/random.h> |
1da177e4 | 10 | #include <asm/processor.h> |
d3f7eae1 | 11 | #include <asm/apic.h> |
1f442d70 | 12 | #include <asm/cpu.h> |
26bfa5f8 | 13 | #include <asm/smp.h> |
42937e81 | 14 | #include <asm/pci-direct.h> |
b466bdb6 | 15 | #include <asm/delay.h> |
1da177e4 | 16 | |
8d71a2ea | 17 | #ifdef CONFIG_X86_64 |
8d71a2ea | 18 | # include <asm/mmconfig.h> |
d1163651 | 19 | # include <asm/set_memory.h> |
8d71a2ea YL |
20 | #endif |
21 | ||
1da177e4 LT |
22 | #include "cpu.h" |
23 | ||
3344ed30 TG |
24 | static const int amd_erratum_383[]; |
25 | static const int amd_erratum_400[]; | |
26 | static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum); | |
27 | ||
cc2749e4 AG |
28 | /* |
29 | * nodes_per_socket: Stores the number of nodes per socket. | |
30 | * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX | |
31 | * Node Identifiers[10:8] | |
32 | */ | |
33 | static u32 nodes_per_socket = 1; | |
34 | ||
2c929ce6 BP |
35 | static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) |
36 | { | |
2c929ce6 BP |
37 | u32 gprs[8] = { 0 }; |
38 | int err; | |
39 | ||
682469a5 BP |
40 | WARN_ONCE((boot_cpu_data.x86 != 0xf), |
41 | "%s should only be used on K8!\n", __func__); | |
2c929ce6 BP |
42 | |
43 | gprs[1] = msr; | |
44 | gprs[7] = 0x9c5a203a; | |
45 | ||
46 | err = rdmsr_safe_regs(gprs); | |
47 | ||
48 | *p = gprs[0] | ((u64)gprs[2] << 32); | |
49 | ||
50 | return err; | |
51 | } | |
52 | ||
53 | static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) | |
54 | { | |
2c929ce6 BP |
55 | u32 gprs[8] = { 0 }; |
56 | ||
682469a5 BP |
57 | WARN_ONCE((boot_cpu_data.x86 != 0xf), |
58 | "%s should only be used on K8!\n", __func__); | |
2c929ce6 BP |
59 | |
60 | gprs[0] = (u32)val; | |
61 | gprs[1] = msr; | |
62 | gprs[2] = val >> 32; | |
63 | gprs[7] = 0x9c5a203a; | |
64 | ||
65 | return wrmsr_safe_regs(gprs); | |
66 | } | |
67 | ||
1da177e4 LT |
68 | /* |
69 | * B step AMD K6 before B 9730xxxx have hardware bugs that can cause | |
70 | * misexecution of code under Linux. Owners of such processors should | |
71 | * contact AMD for precise details and a CPU swap. | |
72 | * | |
73 | * See http://www.multimania.com/poulot/k6bug.html | |
d7de8649 AH |
74 | * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" |
75 | * (Publication # 21266 Issue Date: August 1998) | |
1da177e4 LT |
76 | * |
77 | * The following test is erm.. interesting. AMD neglected to up | |
78 | * the chip setting when fixing the bug but they also tweaked some | |
79 | * performance at the same time.. | |
80 | */ | |
fb87a298 | 81 | |
277d5b40 | 82 | extern __visible void vide(void); |
de642faf JP |
83 | __asm__(".globl vide\n" |
84 | ".type vide, @function\n" | |
85 | ".align 4\n" | |
86 | "vide: ret\n"); | |
1da177e4 | 87 | |
148f9bb8 | 88 | static void init_amd_k5(struct cpuinfo_x86 *c) |
11fdd252 | 89 | { |
26bfa5f8 | 90 | #ifdef CONFIG_X86_32 |
11fdd252 YL |
91 | /* |
92 | * General Systems BIOSen alias the cpu frequency registers | |
6a6256f9 | 93 | * of the Elan at 0x000df000. Unfortunately, one of the Linux |
11fdd252 YL |
94 | * drivers subsequently pokes it, and changes the CPU speed. |
95 | * Workaround : Remove the unneeded alias. | |
96 | */ | |
97 | #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ | |
98 | #define CBAR_ENB (0x80000000) | |
99 | #define CBAR_KEY (0X000000CB) | |
100 | if (c->x86_model == 9 || c->x86_model == 10) { | |
8bdbd962 AC |
101 | if (inl(CBAR) & CBAR_ENB) |
102 | outl(0 | CBAR_KEY, CBAR); | |
11fdd252 | 103 | } |
26bfa5f8 | 104 | #endif |
11fdd252 YL |
105 | } |
106 | ||
148f9bb8 | 107 | static void init_amd_k6(struct cpuinfo_x86 *c) |
11fdd252 | 108 | { |
26bfa5f8 | 109 | #ifdef CONFIG_X86_32 |
11fdd252 | 110 | u32 l, h; |
46a84132 | 111 | int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); |
11fdd252 YL |
112 | |
113 | if (c->x86_model < 6) { | |
114 | /* Based on AMD doc 20734R - June 2000 */ | |
115 | if (c->x86_model == 0) { | |
116 | clear_cpu_cap(c, X86_FEATURE_APIC); | |
117 | set_cpu_cap(c, X86_FEATURE_PGE); | |
118 | } | |
119 | return; | |
120 | } | |
121 | ||
122 | if (c->x86_model == 6 && c->x86_mask == 1) { | |
123 | const int K6_BUG_LOOP = 1000000; | |
124 | int n; | |
125 | void (*f_vide)(void); | |
37963666 | 126 | u64 d, d2; |
11fdd252 | 127 | |
1b74dde7 | 128 | pr_info("AMD K6 stepping B detected - "); |
11fdd252 YL |
129 | |
130 | /* | |
131 | * It looks like AMD fixed the 2.6.2 bug and improved indirect | |
132 | * calls at the same time. | |
133 | */ | |
134 | ||
135 | n = K6_BUG_LOOP; | |
136 | f_vide = vide; | |
4ea1636b | 137 | d = rdtsc(); |
11fdd252 YL |
138 | while (n--) |
139 | f_vide(); | |
4ea1636b | 140 | d2 = rdtsc(); |
11fdd252 YL |
141 | d = d2-d; |
142 | ||
143 | if (d > 20*K6_BUG_LOOP) | |
1b74dde7 | 144 | pr_cont("system stability may be impaired when more than 32 MB are used.\n"); |
11fdd252 | 145 | else |
1b74dde7 | 146 | pr_cont("probably OK (after B9730xxxx).\n"); |
11fdd252 YL |
147 | } |
148 | ||
149 | /* K6 with old style WHCR */ | |
150 | if (c->x86_model < 8 || | |
151 | (c->x86_model == 8 && c->x86_mask < 8)) { | |
152 | /* We can only write allocate on the low 508Mb */ | |
153 | if (mbytes > 508) | |
154 | mbytes = 508; | |
155 | ||
156 | rdmsr(MSR_K6_WHCR, l, h); | |
157 | if ((l&0x0000FFFF) == 0) { | |
158 | unsigned long flags; | |
159 | l = (1<<0)|((mbytes/4)<<1); | |
160 | local_irq_save(flags); | |
161 | wbinvd(); | |
162 | wrmsr(MSR_K6_WHCR, l, h); | |
163 | local_irq_restore(flags); | |
1b74dde7 | 164 | pr_info("Enabling old style K6 write allocation for %d Mb\n", |
11fdd252 YL |
165 | mbytes); |
166 | } | |
167 | return; | |
168 | } | |
169 | ||
170 | if ((c->x86_model == 8 && c->x86_mask > 7) || | |
171 | c->x86_model == 9 || c->x86_model == 13) { | |
172 | /* The more serious chips .. */ | |
173 | ||
174 | if (mbytes > 4092) | |
175 | mbytes = 4092; | |
176 | ||
177 | rdmsr(MSR_K6_WHCR, l, h); | |
178 | if ((l&0xFFFF0000) == 0) { | |
179 | unsigned long flags; | |
180 | l = ((mbytes>>2)<<22)|(1<<16); | |
181 | local_irq_save(flags); | |
182 | wbinvd(); | |
183 | wrmsr(MSR_K6_WHCR, l, h); | |
184 | local_irq_restore(flags); | |
1b74dde7 | 185 | pr_info("Enabling new style K6 write allocation for %d Mb\n", |
11fdd252 YL |
186 | mbytes); |
187 | } | |
188 | ||
189 | return; | |
190 | } | |
191 | ||
192 | if (c->x86_model == 10) { | |
193 | /* AMD Geode LX is model 10 */ | |
194 | /* placeholder for any needed mods */ | |
195 | return; | |
196 | } | |
26bfa5f8 | 197 | #endif |
11fdd252 YL |
198 | } |
199 | ||
26bfa5f8 | 200 | static void init_amd_k7(struct cpuinfo_x86 *c) |
1f442d70 | 201 | { |
26bfa5f8 BP |
202 | #ifdef CONFIG_X86_32 |
203 | u32 l, h; | |
204 | ||
205 | /* | |
206 | * Bit 15 of Athlon specific MSR 15, needs to be 0 | |
207 | * to enable SSE on Palomino/Morgan/Barton CPU's. | |
208 | * If the BIOS didn't enable it already, enable it here. | |
209 | */ | |
210 | if (c->x86_model >= 6 && c->x86_model <= 10) { | |
211 | if (!cpu_has(c, X86_FEATURE_XMM)) { | |
1b74dde7 | 212 | pr_info("Enabling disabled K7/SSE Support.\n"); |
26bfa5f8 BP |
213 | msr_clear_bit(MSR_K7_HWCR, 15); |
214 | set_cpu_cap(c, X86_FEATURE_XMM); | |
215 | } | |
216 | } | |
217 | ||
218 | /* | |
219 | * It's been determined by AMD that Athlons since model 8 stepping 1 | |
220 | * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx | |
221 | * As per AMD technical note 27212 0.2 | |
222 | */ | |
223 | if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) { | |
224 | rdmsr(MSR_K7_CLK_CTL, l, h); | |
225 | if ((l & 0xfff00000) != 0x20000000) { | |
1b74dde7 CY |
226 | pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", |
227 | l, ((l & 0x000fffff)|0x20000000)); | |
26bfa5f8 BP |
228 | wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); |
229 | } | |
230 | } | |
231 | ||
232 | set_cpu_cap(c, X86_FEATURE_K7); | |
233 | ||
1f442d70 | 234 | /* calling is from identify_secondary_cpu() ? */ |
f6e9456c | 235 | if (!c->cpu_index) |
1f442d70 YL |
236 | return; |
237 | ||
238 | /* | |
239 | * Certain Athlons might work (for various values of 'work') in SMP | |
240 | * but they are not certified as MP capable. | |
241 | */ | |
242 | /* Athlon 660/661 is valid. */ | |
243 | if ((c->x86_model == 6) && ((c->x86_mask == 0) || | |
244 | (c->x86_mask == 1))) | |
1077c932 | 245 | return; |
1f442d70 YL |
246 | |
247 | /* Duron 670 is valid */ | |
248 | if ((c->x86_model == 7) && (c->x86_mask == 0)) | |
1077c932 | 249 | return; |
1f442d70 YL |
250 | |
251 | /* | |
252 | * Athlon 662, Duron 671, and Athlon >model 7 have capability | |
253 | * bit. It's worth noting that the A5 stepping (662) of some | |
254 | * Athlon XP's have the MP bit set. | |
255 | * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for | |
256 | * more. | |
257 | */ | |
258 | if (((c->x86_model == 6) && (c->x86_mask >= 2)) || | |
259 | ((c->x86_model == 7) && (c->x86_mask >= 1)) || | |
260 | (c->x86_model > 7)) | |
26bfa5f8 | 261 | if (cpu_has(c, X86_FEATURE_MP)) |
1077c932 | 262 | return; |
1f442d70 YL |
263 | |
264 | /* If we get here, not a certified SMP capable AMD system. */ | |
265 | ||
266 | /* | |
267 | * Don't taint if we are running SMP kernel on a single non-MP | |
268 | * approved Athlon | |
269 | */ | |
270 | WARN_ONCE(1, "WARNING: This combination of AMD" | |
7da8b6dd | 271 | " processors is not suitable for SMP.\n"); |
8c90487c | 272 | add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); |
6c62aa4a | 273 | #endif |
26bfa5f8 | 274 | } |
6c62aa4a | 275 | |
645a7919 | 276 | #ifdef CONFIG_NUMA |
bbc9e2f4 TH |
277 | /* |
278 | * To workaround broken NUMA config. Read the comment in | |
279 | * srat_detect_node(). | |
280 | */ | |
148f9bb8 | 281 | static int nearby_node(int apicid) |
6c62aa4a YL |
282 | { |
283 | int i, node; | |
284 | ||
285 | for (i = apicid - 1; i >= 0; i--) { | |
bbc9e2f4 | 286 | node = __apicid_to_node[i]; |
6c62aa4a YL |
287 | if (node != NUMA_NO_NODE && node_online(node)) |
288 | return node; | |
289 | } | |
290 | for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { | |
bbc9e2f4 | 291 | node = __apicid_to_node[i]; |
6c62aa4a YL |
292 | if (node != NUMA_NO_NODE && node_online(node)) |
293 | return node; | |
294 | } | |
295 | return first_node(node_online_map); /* Shouldn't happen */ | |
296 | } | |
297 | #endif | |
11fdd252 | 298 | |
4a376ec3 | 299 | /* |
23588c38 AH |
300 | * Fixup core topology information for |
301 | * (1) AMD multi-node processors | |
302 | * Assumption: Number of cores in each internal node is the same. | |
6057b4d3 | 303 | * (2) AMD processors supporting compute units |
4a376ec3 | 304 | */ |
c8e56d20 | 305 | #ifdef CONFIG_SMP |
148f9bb8 | 306 | static void amd_get_topology(struct cpuinfo_x86 *c) |
4a376ec3 | 307 | { |
23588c38 | 308 | u8 node_id; |
4a376ec3 AH |
309 | int cpu = smp_processor_id(); |
310 | ||
23588c38 | 311 | /* get information required for multi-node processors */ |
362f924b | 312 | if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { |
79a8b9aa | 313 | u32 eax, ebx, ecx, edx; |
6057b4d3 | 314 | |
79a8b9aa BP |
315 | cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); |
316 | ||
317 | node_id = ecx & 0xff; | |
318 | smp_num_siblings = ((ebx >> 8) & 0xff) + 1; | |
319 | ||
320 | if (c->x86 == 0x15) | |
321 | c->cu_id = ebx & 0xff; | |
b6a50cdd | 322 | |
08b25963 YG |
323 | if (c->x86 >= 0x17) { |
324 | c->cpu_core_id = ebx & 0xff; | |
325 | ||
326 | if (smp_num_siblings > 1) | |
327 | c->x86_max_cores /= smp_num_siblings; | |
328 | } | |
329 | ||
b6a50cdd YG |
330 | /* |
331 | * We may have multiple LLCs if L3 caches exist, so check if we | |
332 | * have an L3 cache by looking at the L3 cache CPUID leaf. | |
333 | */ | |
334 | if (cpuid_edx(0x80000006)) { | |
335 | if (c->x86 == 0x17) { | |
336 | /* | |
337 | * LLC is at the core complex level. | |
338 | * Core complex id is ApicId[3]. | |
339 | */ | |
340 | per_cpu(cpu_llc_id, cpu) = c->apicid >> 3; | |
341 | } else { | |
342 | /* LLC is at the node level. */ | |
343 | per_cpu(cpu_llc_id, cpu) = node_id; | |
344 | } | |
345 | } | |
23588c38 | 346 | } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { |
6057b4d3 AH |
347 | u64 value; |
348 | ||
23588c38 | 349 | rdmsrl(MSR_FAM10H_NODE_ID, value); |
23588c38 | 350 | node_id = value & 7; |
b6a50cdd YG |
351 | |
352 | per_cpu(cpu_llc_id, cpu) = node_id; | |
23588c38 | 353 | } else |
4a376ec3 AH |
354 | return; |
355 | ||
23588c38 | 356 | /* fixup multi-node processor information */ |
cc2749e4 | 357 | if (nodes_per_socket > 1) { |
d518573d | 358 | u32 cus_per_node; |
6057b4d3 | 359 | |
23588c38 | 360 | set_cpu_cap(c, X86_FEATURE_AMD_DCM); |
ee6825c8 | 361 | cus_per_node = c->x86_max_cores / nodes_per_socket; |
9d260ebc | 362 | |
9e81509e | 363 | /* core id has to be in the [0 .. cores_per_node - 1] range */ |
8196dab4 | 364 | c->cpu_core_id %= cus_per_node; |
23588c38 | 365 | } |
4a376ec3 AH |
366 | } |
367 | #endif | |
368 | ||
11fdd252 | 369 | /* |
aa5e5dc2 | 370 | * On a AMD dual core setup the lower bits of the APIC id distinguish the cores. |
11fdd252 YL |
371 | * Assumes number of cores is a power of two. |
372 | */ | |
148f9bb8 | 373 | static void amd_detect_cmp(struct cpuinfo_x86 *c) |
11fdd252 | 374 | { |
c8e56d20 | 375 | #ifdef CONFIG_SMP |
11fdd252 | 376 | unsigned bits; |
99bd0c0f | 377 | int cpu = smp_processor_id(); |
11fdd252 YL |
378 | |
379 | bits = c->x86_coreid_bits; | |
11fdd252 YL |
380 | /* Low order bits define the core id (index of core in socket) */ |
381 | c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); | |
382 | /* Convert the initial APIC ID into the socket ID */ | |
383 | c->phys_proc_id = c->initial_apicid >> bits; | |
99bd0c0f AH |
384 | /* use socket ID also for last level cache */ |
385 | per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; | |
23588c38 | 386 | amd_get_topology(c); |
11fdd252 YL |
387 | #endif |
388 | } | |
389 | ||
8b84c8df | 390 | u16 amd_get_nb_id(int cpu) |
6a812691 | 391 | { |
8b84c8df | 392 | u16 id = 0; |
6a812691 AH |
393 | #ifdef CONFIG_SMP |
394 | id = per_cpu(cpu_llc_id, cpu); | |
395 | #endif | |
396 | return id; | |
397 | } | |
398 | EXPORT_SYMBOL_GPL(amd_get_nb_id); | |
399 | ||
cc2749e4 AG |
400 | u32 amd_get_nodes_per_socket(void) |
401 | { | |
402 | return nodes_per_socket; | |
403 | } | |
404 | EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket); | |
405 | ||
148f9bb8 | 406 | static void srat_detect_node(struct cpuinfo_x86 *c) |
6c62aa4a | 407 | { |
645a7919 | 408 | #ifdef CONFIG_NUMA |
6c62aa4a YL |
409 | int cpu = smp_processor_id(); |
410 | int node; | |
0d96b9ff | 411 | unsigned apicid = c->apicid; |
6c62aa4a | 412 | |
bbc9e2f4 TH |
413 | node = numa_cpu_node(cpu); |
414 | if (node == NUMA_NO_NODE) | |
415 | node = per_cpu(cpu_llc_id, cpu); | |
6c62aa4a | 416 | |
64be4c1c | 417 | /* |
68894632 AH |
418 | * On multi-fabric platform (e.g. Numascale NumaChip) a |
419 | * platform-specific handler needs to be called to fixup some | |
420 | * IDs of the CPU. | |
64be4c1c | 421 | */ |
68894632 | 422 | if (x86_cpuinit.fixup_cpu_id) |
64be4c1c DB |
423 | x86_cpuinit.fixup_cpu_id(c, node); |
424 | ||
6c62aa4a | 425 | if (!node_online(node)) { |
bbc9e2f4 TH |
426 | /* |
427 | * Two possibilities here: | |
428 | * | |
429 | * - The CPU is missing memory and no node was created. In | |
430 | * that case try picking one from a nearby CPU. | |
431 | * | |
432 | * - The APIC IDs differ from the HyperTransport node IDs | |
433 | * which the K8 northbridge parsing fills in. Assume | |
434 | * they are all increased by a constant offset, but in | |
435 | * the same order as the HT nodeids. If that doesn't | |
436 | * result in a usable node fall back to the path for the | |
437 | * previous case. | |
438 | * | |
439 | * This workaround operates directly on the mapping between | |
440 | * APIC ID and NUMA node, assuming certain relationship | |
441 | * between APIC ID, HT node ID and NUMA topology. As going | |
442 | * through CPU mapping may alter the outcome, directly | |
443 | * access __apicid_to_node[]. | |
444 | */ | |
6c62aa4a YL |
445 | int ht_nodeid = c->initial_apicid; |
446 | ||
7030a7e9 | 447 | if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE) |
bbc9e2f4 | 448 | node = __apicid_to_node[ht_nodeid]; |
6c62aa4a YL |
449 | /* Pick a nearby node */ |
450 | if (!node_online(node)) | |
451 | node = nearby_node(apicid); | |
452 | } | |
453 | numa_set_node(cpu, node); | |
6c62aa4a YL |
454 | #endif |
455 | } | |
456 | ||
148f9bb8 | 457 | static void early_init_amd_mc(struct cpuinfo_x86 *c) |
11fdd252 | 458 | { |
c8e56d20 | 459 | #ifdef CONFIG_SMP |
11fdd252 YL |
460 | unsigned bits, ecx; |
461 | ||
462 | /* Multi core CPU? */ | |
463 | if (c->extended_cpuid_level < 0x80000008) | |
464 | return; | |
465 | ||
466 | ecx = cpuid_ecx(0x80000008); | |
467 | ||
468 | c->x86_max_cores = (ecx & 0xff) + 1; | |
469 | ||
470 | /* CPU telling us the core id bits shift? */ | |
471 | bits = (ecx >> 12) & 0xF; | |
472 | ||
473 | /* Otherwise recompute */ | |
474 | if (bits == 0) { | |
475 | while ((1 << bits) < c->x86_max_cores) | |
476 | bits++; | |
477 | } | |
478 | ||
479 | c->x86_coreid_bits = bits; | |
480 | #endif | |
481 | } | |
482 | ||
148f9bb8 | 483 | static void bsp_init_amd(struct cpuinfo_x86 *c) |
8fa8b035 | 484 | { |
26bfa5f8 BP |
485 | |
486 | #ifdef CONFIG_X86_64 | |
487 | if (c->x86 >= 0xf) { | |
488 | unsigned long long tseg; | |
489 | ||
490 | /* | |
491 | * Split up direct mapping around the TSEG SMM area. | |
492 | * Don't do it for gbpages because there seems very little | |
493 | * benefit in doing so. | |
494 | */ | |
495 | if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { | |
496 | unsigned long pfn = tseg >> PAGE_SHIFT; | |
497 | ||
1b74dde7 | 498 | pr_debug("tseg: %010llx\n", tseg); |
26bfa5f8 BP |
499 | if (pfn_range_is_mapped(pfn, pfn + 1)) |
500 | set_memory_4k((unsigned long)__va(tseg), 1); | |
501 | } | |
502 | } | |
503 | #endif | |
504 | ||
8fa8b035 BP |
505 | if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { |
506 | ||
507 | if (c->x86 > 0x10 || | |
508 | (c->x86 == 0x10 && c->x86_model >= 0x2)) { | |
509 | u64 val; | |
510 | ||
511 | rdmsrl(MSR_K7_HWCR, val); | |
512 | if (!(val & BIT(24))) | |
1b74dde7 | 513 | pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); |
8fa8b035 BP |
514 | } |
515 | } | |
516 | ||
517 | if (c->x86 == 0x15) { | |
518 | unsigned long upperbit; | |
519 | u32 cpuid, assoc; | |
520 | ||
521 | cpuid = cpuid_edx(0x80000005); | |
522 | assoc = cpuid >> 16 & 0xff; | |
523 | upperbit = ((cpuid >> 24) << 10) / assoc; | |
524 | ||
525 | va_align.mask = (upperbit - 1) & PAGE_MASK; | |
526 | va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; | |
4e26d11f HMG |
527 | |
528 | /* A random value per boot for bit slice [12:upper_bit) */ | |
529 | va_align.bits = get_random_int() & va_align.mask; | |
8fa8b035 | 530 | } |
b466bdb6 HR |
531 | |
532 | if (cpu_has(c, X86_FEATURE_MWAITX)) | |
533 | use_mwaitx_delay(); | |
8dfeae0d HR |
534 | |
535 | if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { | |
536 | u32 ecx; | |
537 | ||
538 | ecx = cpuid_ecx(0x8000001e); | |
539 | nodes_per_socket = ((ecx >> 8) & 7) + 1; | |
540 | } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) { | |
541 | u64 value; | |
542 | ||
543 | rdmsrl(MSR_FAM10H_NODE_ID, value); | |
544 | nodes_per_socket = ((value >> 3) & 7) + 1; | |
545 | } | |
8fa8b035 BP |
546 | } |
547 | ||
148f9bb8 | 548 | static void early_init_amd(struct cpuinfo_x86 *c) |
2b16a235 | 549 | { |
11fdd252 YL |
550 | early_init_amd_mc(c); |
551 | ||
40fb1715 VP |
552 | /* |
553 | * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate | |
554 | * with P/T states and does not stop in deep C-states | |
555 | */ | |
556 | if (c->x86_power & (1 << 8)) { | |
e3224234 | 557 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); |
40fb1715 VP |
558 | set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); |
559 | } | |
5fef55fd | 560 | |
01fe03ff HR |
561 | /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ |
562 | if (c->x86_power & BIT(12)) | |
563 | set_cpu_cap(c, X86_FEATURE_ACC_POWER); | |
564 | ||
6c62aa4a YL |
565 | #ifdef CONFIG_X86_64 |
566 | set_cpu_cap(c, X86_FEATURE_SYSCALL32); | |
567 | #else | |
5fef55fd | 568 | /* Set MTRR capability flag if appropriate */ |
6c62aa4a YL |
569 | if (c->x86 == 5) |
570 | if (c->x86_model == 13 || c->x86_model == 9 || | |
571 | (c->x86_model == 8 && c->x86_mask >= 8)) | |
572 | set_cpu_cap(c, X86_FEATURE_K6_MTRR); | |
573 | #endif | |
42937e81 | 574 | #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) |
b9d16a2a AG |
575 | /* |
576 | * ApicID can always be treated as an 8-bit value for AMD APIC versions | |
577 | * >= 0x10, but even old K8s came out of reset with version 0x10. So, we | |
578 | * can safely set X86_FEATURE_EXTD_APICID unconditionally for families | |
579 | * after 16h. | |
580 | */ | |
425d8c2f BP |
581 | if (boot_cpu_has(X86_FEATURE_APIC)) { |
582 | if (c->x86 > 0x16) | |
42937e81 | 583 | set_cpu_cap(c, X86_FEATURE_EXTD_APICID); |
425d8c2f BP |
584 | else if (c->x86 >= 0xf) { |
585 | /* check CPU config space for extended APIC ID */ | |
586 | unsigned int val; | |
587 | ||
588 | val = read_pci_config(0, 24, 0, 0x68); | |
589 | if ((val >> 17 & 0x3) == 0x3) | |
590 | set_cpu_cap(c, X86_FEATURE_EXTD_APICID); | |
591 | } | |
42937e81 AH |
592 | } |
593 | #endif | |
3b564968 | 594 | |
c1118b36 PB |
595 | /* |
596 | * This is only needed to tell the kernel whether to use VMCALL | |
597 | * and VMMCALL. VMMCALL is never executed except under virt, so | |
598 | * we can set it unconditionally. | |
599 | */ | |
600 | set_cpu_cap(c, X86_FEATURE_VMMCALL); | |
601 | ||
3b564968 | 602 | /* F16h erratum 793, CVE-2013-6885 */ |
8f86a737 BP |
603 | if (c->x86 == 0x16 && c->x86_model <= 0xf) |
604 | msr_set_bit(MSR_AMD64_LS_CFG, 15); | |
2b16a235 | 605 | |
3344ed30 TG |
606 | /* |
607 | * Check whether the machine is affected by erratum 400. This is | |
608 | * used to select the proper idle routine and to enable the check | |
609 | * whether the machine is affected in arch_post_acpi_init(), which | |
610 | * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check. | |
611 | */ | |
612 | if (cpu_has_amd_erratum(c, amd_erratum_400)) | |
613 | set_cpu_bug(c, X86_BUG_AMD_E400); | |
614 | } | |
e6ee94d5 | 615 | |
26bfa5f8 BP |
616 | static void init_amd_k8(struct cpuinfo_x86 *c) |
617 | { | |
618 | u32 level; | |
619 | u64 value; | |
620 | ||
621 | /* On C+ stepping K8 rep microcode works well for copy/memset */ | |
622 | level = cpuid_eax(1); | |
623 | if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) | |
624 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); | |
625 | ||
626 | /* | |
627 | * Some BIOSes incorrectly force this feature, but only K8 revision D | |
628 | * (model = 0x14) and later actually support it. | |
629 | * (AMD Erratum #110, docId: 25759). | |
630 | */ | |
631 | if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { | |
632 | clear_cpu_cap(c, X86_FEATURE_LAHF_LM); | |
633 | if (!rdmsrl_amd_safe(0xc001100d, &value)) { | |
634 | value &= ~BIT_64(32); | |
635 | wrmsrl_amd_safe(0xc001100d, value); | |
636 | } | |
637 | } | |
638 | ||
639 | if (!c->x86_model_id[0]) | |
640 | strcpy(c->x86_model_id, "Hammer"); | |
6f9b63a0 BP |
641 | |
642 | #ifdef CONFIG_SMP | |
643 | /* | |
644 | * Disable TLB flush filter by setting HWCR.FFDIS on K8 | |
645 | * bit 6 of msr C001_0015 | |
646 | * | |
647 | * Errata 63 for SH-B3 steppings | |
648 | * Errata 122 for all steppings (F+ have it disabled by default) | |
649 | */ | |
650 | msr_set_bit(MSR_K7_HWCR, 6); | |
651 | #endif | |
96e5d28a | 652 | set_cpu_bug(c, X86_BUG_SWAPGS_FENCE); |
26bfa5f8 BP |
653 | } |
654 | ||
655 | static void init_amd_gh(struct cpuinfo_x86 *c) | |
656 | { | |
657 | #ifdef CONFIG_X86_64 | |
658 | /* do this for boot cpu */ | |
659 | if (c == &boot_cpu_data) | |
660 | check_enable_amd_mmconf_dmi(); | |
661 | ||
662 | fam10h_check_enable_mmcfg(); | |
663 | #endif | |
664 | ||
665 | /* | |
666 | * Disable GART TLB Walk Errors on Fam10h. We do this here because this | |
667 | * is always needed when GART is enabled, even in a kernel which has no | |
668 | * MCE support built in. BIOS should disable GartTlbWlk Errors already. | |
669 | * If it doesn't, we do it here as suggested by the BKDG. | |
670 | * | |
671 | * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 | |
672 | */ | |
673 | msr_set_bit(MSR_AMD64_MCx_MASK(4), 10); | |
674 | ||
675 | /* | |
676 | * On family 10h BIOS may not have properly enabled WC+ support, causing | |
677 | * it to be converted to CD memtype. This may result in performance | |
678 | * degradation for certain nested-paging guests. Prevent this conversion | |
679 | * by clearing bit 24 in MSR_AMD64_BU_CFG2. | |
680 | * | |
681 | * NOTE: we want to use the _safe accessors so as not to #GP kvm | |
682 | * guests on older kvm hosts. | |
683 | */ | |
684 | msr_clear_bit(MSR_AMD64_BU_CFG2, 24); | |
685 | ||
686 | if (cpu_has_amd_erratum(c, amd_erratum_383)) | |
687 | set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH); | |
688 | } | |
689 | ||
d1992996 EC |
690 | #define MSR_AMD64_DE_CFG 0xC0011029 |
691 | ||
692 | static void init_amd_ln(struct cpuinfo_x86 *c) | |
693 | { | |
694 | /* | |
695 | * Apply erratum 665 fix unconditionally so machines without a BIOS | |
696 | * fix work. | |
697 | */ | |
698 | msr_set_bit(MSR_AMD64_DE_CFG, 31); | |
699 | } | |
700 | ||
26bfa5f8 BP |
701 | static void init_amd_bd(struct cpuinfo_x86 *c) |
702 | { | |
703 | u64 value; | |
704 | ||
705 | /* re-enable TopologyExtensions if switched off by BIOS */ | |
96685a55 | 706 | if ((c->x86_model >= 0x10) && (c->x86_model <= 0x6f) && |
26bfa5f8 BP |
707 | !cpu_has(c, X86_FEATURE_TOPOEXT)) { |
708 | ||
709 | if (msr_set_bit(0xc0011005, 54) > 0) { | |
710 | rdmsrl(0xc0011005, value); | |
711 | if (value & BIT_64(54)) { | |
712 | set_cpu_cap(c, X86_FEATURE_TOPOEXT); | |
96685a55 | 713 | pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n"); |
26bfa5f8 BP |
714 | } |
715 | } | |
716 | } | |
717 | ||
718 | /* | |
719 | * The way access filter has a performance penalty on some workloads. | |
720 | * Disable it on the affected CPUs. | |
721 | */ | |
722 | if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) { | |
ae8b7875 | 723 | if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) { |
26bfa5f8 | 724 | value |= 0x1E; |
ae8b7875 | 725 | wrmsrl_safe(MSR_F15H_IC_CFG, value); |
26bfa5f8 BP |
726 | } |
727 | } | |
728 | } | |
729 | ||
148f9bb8 | 730 | static void init_amd(struct cpuinfo_x86 *c) |
1da177e4 | 731 | { |
8e8da023 | 732 | u32 dummy; |
7d318d77 | 733 | |
2b16a235 AK |
734 | early_init_amd(c); |
735 | ||
fb87a298 PC |
736 | /* |
737 | * Bit 31 in normal CPUID used for nonstandard 3DNow ID; | |
16282a8e | 738 | * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway |
fb87a298 | 739 | */ |
16282a8e | 740 | clear_cpu_cap(c, 0*32+31); |
fb87a298 | 741 | |
12d8a961 | 742 | if (c->x86 >= 0x10) |
6c62aa4a | 743 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); |
0d96b9ff YL |
744 | |
745 | /* get apicid instead of initial apic id from cpuid */ | |
746 | c->apicid = hard_smp_processor_id(); | |
11fdd252 YL |
747 | |
748 | /* K6s reports MCEs but don't actually have all the MSRs */ | |
749 | if (c->x86 < 6) | |
750 | clear_cpu_cap(c, X86_FEATURE_MCE); | |
26bfa5f8 BP |
751 | |
752 | switch (c->x86) { | |
753 | case 4: init_amd_k5(c); break; | |
754 | case 5: init_amd_k6(c); break; | |
755 | case 6: init_amd_k7(c); break; | |
756 | case 0xf: init_amd_k8(c); break; | |
757 | case 0x10: init_amd_gh(c); break; | |
d1992996 | 758 | case 0x12: init_amd_ln(c); break; |
26bfa5f8 BP |
759 | case 0x15: init_amd_bd(c); break; |
760 | } | |
11fdd252 | 761 | |
6c62aa4a | 762 | /* Enable workaround for FXSAVE leak */ |
18bd057b | 763 | if (c->x86 >= 6) |
9b13a93d | 764 | set_cpu_bug(c, X86_BUG_FXSAVE_LEAK); |
1da177e4 | 765 | |
27c13ece | 766 | cpu_detect_cache_sizes(c); |
3dd9d514 | 767 | |
11fdd252 | 768 | /* Multi core CPU? */ |
6c62aa4a | 769 | if (c->extended_cpuid_level >= 0x80000008) { |
11fdd252 | 770 | amd_detect_cmp(c); |
6c62aa4a YL |
771 | srat_detect_node(c); |
772 | } | |
faee9a5d | 773 | |
6c62aa4a | 774 | #ifdef CONFIG_X86_32 |
11fdd252 | 775 | detect_ht(c); |
6c62aa4a | 776 | #endif |
39b3a791 | 777 | |
04a15418 | 778 | init_amd_cacheinfo(c); |
3556ddfa | 779 | |
12d8a961 | 780 | if (c->x86 >= 0xf) |
11fdd252 | 781 | set_cpu_cap(c, X86_FEATURE_K8); |
de421863 | 782 | |
054efb64 | 783 | if (cpu_has(c, X86_FEATURE_XMM2)) { |
11fdd252 | 784 | /* MFENCE stops RDTSC speculation */ |
16282a8e | 785 | set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); |
11fdd252 | 786 | } |
6c62aa4a | 787 | |
e9cdd343 BO |
788 | /* |
789 | * Family 0x12 and above processors have APIC timer | |
790 | * running in deep C states. | |
791 | */ | |
792 | if (c->x86 > 0x11) | |
b87cf80a | 793 | set_cpu_cap(c, X86_FEATURE_ARAT); |
5bbc097d | 794 | |
8e8da023 | 795 | rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); |
a930dc45 BP |
796 | |
797 | /* 3DNow or LM implies PREFETCHW */ | |
798 | if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH)) | |
799 | if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM)) | |
800 | set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH); | |
61f01dd9 | 801 | |
def9331a JG |
802 | /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */ |
803 | if (!cpu_has(c, X86_FEATURE_XENPV)) | |
804 | set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); | |
1da177e4 LT |
805 | } |
806 | ||
6c62aa4a | 807 | #ifdef CONFIG_X86_32 |
148f9bb8 | 808 | static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) |
1da177e4 LT |
809 | { |
810 | /* AMD errata T13 (order #21922) */ | |
811 | if ((c->x86 == 6)) { | |
8bdbd962 AC |
812 | /* Duron Rev A0 */ |
813 | if (c->x86_model == 3 && c->x86_mask == 0) | |
1da177e4 | 814 | size = 64; |
8bdbd962 | 815 | /* Tbird rev A1/A2 */ |
1da177e4 | 816 | if (c->x86_model == 4 && |
8bdbd962 | 817 | (c->x86_mask == 0 || c->x86_mask == 1)) |
1da177e4 LT |
818 | size = 256; |
819 | } | |
820 | return size; | |
821 | } | |
6c62aa4a | 822 | #endif |
1da177e4 | 823 | |
148f9bb8 | 824 | static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) |
b46882e4 BP |
825 | { |
826 | u32 ebx, eax, ecx, edx; | |
827 | u16 mask = 0xfff; | |
828 | ||
829 | if (c->x86 < 0xf) | |
830 | return; | |
831 | ||
832 | if (c->extended_cpuid_level < 0x80000006) | |
833 | return; | |
834 | ||
835 | cpuid(0x80000006, &eax, &ebx, &ecx, &edx); | |
836 | ||
837 | tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask; | |
838 | tlb_lli_4k[ENTRIES] = ebx & mask; | |
839 | ||
840 | /* | |
841 | * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB | |
842 | * characteristics from the CPUID function 0x80000005 instead. | |
843 | */ | |
844 | if (c->x86 == 0xf) { | |
845 | cpuid(0x80000005, &eax, &ebx, &ecx, &edx); | |
846 | mask = 0xff; | |
847 | } | |
848 | ||
849 | /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ | |
d1393367 BP |
850 | if (!((eax >> 16) & mask)) |
851 | tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff; | |
852 | else | |
b46882e4 | 853 | tlb_lld_2m[ENTRIES] = (eax >> 16) & mask; |
b46882e4 BP |
854 | |
855 | /* a 4M entry uses two 2M entries */ | |
856 | tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1; | |
857 | ||
858 | /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ | |
859 | if (!(eax & mask)) { | |
860 | /* Erratum 658 */ | |
861 | if (c->x86 == 0x15 && c->x86_model <= 0x1f) { | |
862 | tlb_lli_2m[ENTRIES] = 1024; | |
863 | } else { | |
864 | cpuid(0x80000005, &eax, &ebx, &ecx, &edx); | |
865 | tlb_lli_2m[ENTRIES] = eax & 0xff; | |
866 | } | |
867 | } else | |
868 | tlb_lli_2m[ENTRIES] = eax & mask; | |
869 | ||
870 | tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; | |
871 | } | |
872 | ||
148f9bb8 | 873 | static const struct cpu_dev amd_cpu_dev = { |
1da177e4 | 874 | .c_vendor = "AMD", |
fb87a298 | 875 | .c_ident = { "AuthenticAMD" }, |
6c62aa4a | 876 | #ifdef CONFIG_X86_32 |
09dc68d9 JB |
877 | .legacy_models = { |
878 | { .family = 4, .model_names = | |
1da177e4 LT |
879 | { |
880 | [3] = "486 DX/2", | |
881 | [7] = "486 DX/2-WB", | |
fb87a298 PC |
882 | [8] = "486 DX/4", |
883 | [9] = "486 DX/4-WB", | |
1da177e4 | 884 | [14] = "Am5x86-WT", |
fb87a298 | 885 | [15] = "Am5x86-WB" |
1da177e4 LT |
886 | } |
887 | }, | |
888 | }, | |
09dc68d9 | 889 | .legacy_cache_size = amd_size_cache, |
6c62aa4a | 890 | #endif |
03ae5768 | 891 | .c_early_init = early_init_amd, |
b46882e4 | 892 | .c_detect_tlb = cpu_detect_tlb_amd, |
8fa8b035 | 893 | .c_bsp_init = bsp_init_amd, |
1da177e4 | 894 | .c_init = init_amd, |
10a434fc | 895 | .c_x86_vendor = X86_VENDOR_AMD, |
1da177e4 LT |
896 | }; |
897 | ||
10a434fc | 898 | cpu_dev_register(amd_cpu_dev); |
d78d671d HR |
899 | |
900 | /* | |
901 | * AMD errata checking | |
902 | * | |
903 | * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or | |
904 | * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that | |
905 | * have an OSVW id assigned, which it takes as first argument. Both take a | |
906 | * variable number of family-specific model-stepping ranges created by | |
7d7dc116 | 907 | * AMD_MODEL_RANGE(). |
d78d671d HR |
908 | * |
909 | * Example: | |
910 | * | |
911 | * const int amd_erratum_319[] = | |
912 | * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), | |
913 | * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), | |
914 | * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); | |
915 | */ | |
916 | ||
7d7dc116 BP |
917 | #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } |
918 | #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } | |
919 | #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ | |
920 | ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) | |
921 | #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) | |
922 | #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) | |
923 | #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) | |
924 | ||
925 | static const int amd_erratum_400[] = | |
328935e6 | 926 | AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), |
9d8888c2 HR |
927 | AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); |
928 | ||
e6ee94d5 | 929 | static const int amd_erratum_383[] = |
1be85a6d | 930 | AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); |
9d8888c2 | 931 | |
8c6b79bb TK |
932 | |
933 | static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) | |
d78d671d | 934 | { |
d78d671d HR |
935 | int osvw_id = *erratum++; |
936 | u32 range; | |
937 | u32 ms; | |
938 | ||
d78d671d HR |
939 | if (osvw_id >= 0 && osvw_id < 65536 && |
940 | cpu_has(cpu, X86_FEATURE_OSVW)) { | |
941 | u64 osvw_len; | |
942 | ||
943 | rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); | |
944 | if (osvw_id < osvw_len) { | |
945 | u64 osvw_bits; | |
946 | ||
947 | rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), | |
948 | osvw_bits); | |
949 | return osvw_bits & (1ULL << (osvw_id & 0x3f)); | |
950 | } | |
951 | } | |
952 | ||
953 | /* OSVW unavailable or ID unknown, match family-model-stepping range */ | |
07a7795c | 954 | ms = (cpu->x86_model << 4) | cpu->x86_mask; |
d78d671d HR |
955 | while ((range = *erratum++)) |
956 | if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && | |
957 | (ms >= AMD_MODEL_RANGE_START(range)) && | |
958 | (ms <= AMD_MODEL_RANGE_END(range))) | |
959 | return true; | |
960 | ||
961 | return false; | |
962 | } | |
d6d55f0b JS |
963 | |
964 | void set_dr_addr_mask(unsigned long mask, int dr) | |
965 | { | |
362f924b | 966 | if (!boot_cpu_has(X86_FEATURE_BPEXT)) |
d6d55f0b JS |
967 | return; |
968 | ||
969 | switch (dr) { | |
970 | case 0: | |
971 | wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0); | |
972 | break; | |
973 | case 1: | |
974 | case 2: | |
975 | case 3: | |
976 | wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0); | |
977 | break; | |
978 | default: | |
979 | break; | |
980 | } | |
981 | } |