]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | #include <linux/init.h> |
2 | #include <linux/bitops.h> | |
5cdd174f | 3 | #include <linux/elf.h> |
1da177e4 | 4 | #include <linux/mm.h> |
8d71a2ea | 5 | |
8bdbd962 | 6 | #include <linux/io.h> |
1da177e4 | 7 | #include <asm/processor.h> |
d3f7eae1 | 8 | #include <asm/apic.h> |
1f442d70 | 9 | #include <asm/cpu.h> |
42937e81 | 10 | #include <asm/pci-direct.h> |
1da177e4 | 11 | |
8d71a2ea YL |
12 | #ifdef CONFIG_X86_64 |
13 | # include <asm/numa_64.h> | |
14 | # include <asm/mmconfig.h> | |
15 | # include <asm/cacheflush.h> | |
16 | #endif | |
17 | ||
1da177e4 LT |
18 | #include "cpu.h" |
19 | ||
6c62aa4a | 20 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
21 | /* |
22 | * B step AMD K6 before B 9730xxxx have hardware bugs that can cause | |
23 | * misexecution of code under Linux. Owners of such processors should | |
24 | * contact AMD for precise details and a CPU swap. | |
25 | * | |
26 | * See http://www.multimania.com/poulot/k6bug.html | |
27 | * http://www.amd.com/K6/k6docs/revgd.html | |
28 | * | |
29 | * The following test is erm.. interesting. AMD neglected to up | |
30 | * the chip setting when fixing the bug but they also tweaked some | |
31 | * performance at the same time.. | |
32 | */ | |
fb87a298 | 33 | |
1da177e4 LT |
34 | extern void vide(void); |
35 | __asm__(".align 4\nvide: ret"); | |
36 | ||
11fdd252 YL |
37 | static void __cpuinit init_amd_k5(struct cpuinfo_x86 *c) |
38 | { | |
39 | /* | |
40 | * General Systems BIOSen alias the cpu frequency registers | |
41 | * of the Elan at 0x000df000. Unfortuantly, one of the Linux | |
42 | * drivers subsequently pokes it, and changes the CPU speed. | |
43 | * Workaround : Remove the unneeded alias. | |
44 | */ | |
45 | #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ | |
46 | #define CBAR_ENB (0x80000000) | |
47 | #define CBAR_KEY (0X000000CB) | |
48 | if (c->x86_model == 9 || c->x86_model == 10) { | |
8bdbd962 AC |
49 | if (inl(CBAR) & CBAR_ENB) |
50 | outl(0 | CBAR_KEY, CBAR); | |
11fdd252 YL |
51 | } |
52 | } | |
53 | ||
54 | ||
55 | static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c) | |
56 | { | |
57 | u32 l, h; | |
58 | int mbytes = num_physpages >> (20-PAGE_SHIFT); | |
59 | ||
60 | if (c->x86_model < 6) { | |
61 | /* Based on AMD doc 20734R - June 2000 */ | |
62 | if (c->x86_model == 0) { | |
63 | clear_cpu_cap(c, X86_FEATURE_APIC); | |
64 | set_cpu_cap(c, X86_FEATURE_PGE); | |
65 | } | |
66 | return; | |
67 | } | |
68 | ||
69 | if (c->x86_model == 6 && c->x86_mask == 1) { | |
70 | const int K6_BUG_LOOP = 1000000; | |
71 | int n; | |
72 | void (*f_vide)(void); | |
73 | unsigned long d, d2; | |
74 | ||
75 | printk(KERN_INFO "AMD K6 stepping B detected - "); | |
76 | ||
77 | /* | |
78 | * It looks like AMD fixed the 2.6.2 bug and improved indirect | |
79 | * calls at the same time. | |
80 | */ | |
81 | ||
82 | n = K6_BUG_LOOP; | |
83 | f_vide = vide; | |
84 | rdtscl(d); | |
85 | while (n--) | |
86 | f_vide(); | |
87 | rdtscl(d2); | |
88 | d = d2-d; | |
89 | ||
90 | if (d > 20*K6_BUG_LOOP) | |
8bdbd962 AC |
91 | printk(KERN_CONT |
92 | "system stability may be impaired when more than 32 MB are used.\n"); | |
11fdd252 | 93 | else |
8bdbd962 | 94 | printk(KERN_CONT "probably OK (after B9730xxxx).\n"); |
11fdd252 YL |
95 | printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n"); |
96 | } | |
97 | ||
98 | /* K6 with old style WHCR */ | |
99 | if (c->x86_model < 8 || | |
100 | (c->x86_model == 8 && c->x86_mask < 8)) { | |
101 | /* We can only write allocate on the low 508Mb */ | |
102 | if (mbytes > 508) | |
103 | mbytes = 508; | |
104 | ||
105 | rdmsr(MSR_K6_WHCR, l, h); | |
106 | if ((l&0x0000FFFF) == 0) { | |
107 | unsigned long flags; | |
108 | l = (1<<0)|((mbytes/4)<<1); | |
109 | local_irq_save(flags); | |
110 | wbinvd(); | |
111 | wrmsr(MSR_K6_WHCR, l, h); | |
112 | local_irq_restore(flags); | |
113 | printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n", | |
114 | mbytes); | |
115 | } | |
116 | return; | |
117 | } | |
118 | ||
119 | if ((c->x86_model == 8 && c->x86_mask > 7) || | |
120 | c->x86_model == 9 || c->x86_model == 13) { | |
121 | /* The more serious chips .. */ | |
122 | ||
123 | if (mbytes > 4092) | |
124 | mbytes = 4092; | |
125 | ||
126 | rdmsr(MSR_K6_WHCR, l, h); | |
127 | if ((l&0xFFFF0000) == 0) { | |
128 | unsigned long flags; | |
129 | l = ((mbytes>>2)<<22)|(1<<16); | |
130 | local_irq_save(flags); | |
131 | wbinvd(); | |
132 | wrmsr(MSR_K6_WHCR, l, h); | |
133 | local_irq_restore(flags); | |
134 | printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n", | |
135 | mbytes); | |
136 | } | |
137 | ||
138 | return; | |
139 | } | |
140 | ||
141 | if (c->x86_model == 10) { | |
142 | /* AMD Geode LX is model 10 */ | |
143 | /* placeholder for any needed mods */ | |
144 | return; | |
145 | } | |
146 | } | |
147 | ||
1f442d70 YL |
148 | static void __cpuinit amd_k7_smp_check(struct cpuinfo_x86 *c) |
149 | { | |
150 | #ifdef CONFIG_SMP | |
151 | /* calling is from identify_secondary_cpu() ? */ | |
f6e9456c | 152 | if (!c->cpu_index) |
1f442d70 YL |
153 | return; |
154 | ||
155 | /* | |
156 | * Certain Athlons might work (for various values of 'work') in SMP | |
157 | * but they are not certified as MP capable. | |
158 | */ | |
159 | /* Athlon 660/661 is valid. */ | |
160 | if ((c->x86_model == 6) && ((c->x86_mask == 0) || | |
161 | (c->x86_mask == 1))) | |
162 | goto valid_k7; | |
163 | ||
164 | /* Duron 670 is valid */ | |
165 | if ((c->x86_model == 7) && (c->x86_mask == 0)) | |
166 | goto valid_k7; | |
167 | ||
168 | /* | |
169 | * Athlon 662, Duron 671, and Athlon >model 7 have capability | |
170 | * bit. It's worth noting that the A5 stepping (662) of some | |
171 | * Athlon XP's have the MP bit set. | |
172 | * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for | |
173 | * more. | |
174 | */ | |
175 | if (((c->x86_model == 6) && (c->x86_mask >= 2)) || | |
176 | ((c->x86_model == 7) && (c->x86_mask >= 1)) || | |
177 | (c->x86_model > 7)) | |
178 | if (cpu_has_mp) | |
179 | goto valid_k7; | |
180 | ||
181 | /* If we get here, not a certified SMP capable AMD system. */ | |
182 | ||
183 | /* | |
184 | * Don't taint if we are running SMP kernel on a single non-MP | |
185 | * approved Athlon | |
186 | */ | |
187 | WARN_ONCE(1, "WARNING: This combination of AMD" | |
7da8b6dd | 188 | " processors is not suitable for SMP.\n"); |
1f442d70 YL |
189 | if (!test_taint(TAINT_UNSAFE_SMP)) |
190 | add_taint(TAINT_UNSAFE_SMP); | |
191 | ||
192 | valid_k7: | |
193 | ; | |
194 | #endif | |
195 | } | |
196 | ||
11fdd252 YL |
197 | static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c) |
198 | { | |
199 | u32 l, h; | |
200 | ||
201 | /* | |
202 | * Bit 15 of Athlon specific MSR 15, needs to be 0 | |
203 | * to enable SSE on Palomino/Morgan/Barton CPU's. | |
204 | * If the BIOS didn't enable it already, enable it here. | |
205 | */ | |
206 | if (c->x86_model >= 6 && c->x86_model <= 10) { | |
207 | if (!cpu_has(c, X86_FEATURE_XMM)) { | |
208 | printk(KERN_INFO "Enabling disabled K7/SSE Support.\n"); | |
209 | rdmsr(MSR_K7_HWCR, l, h); | |
210 | l &= ~0x00008000; | |
211 | wrmsr(MSR_K7_HWCR, l, h); | |
212 | set_cpu_cap(c, X86_FEATURE_XMM); | |
213 | } | |
214 | } | |
215 | ||
216 | /* | |
217 | * It's been determined by AMD that Athlons since model 8 stepping 1 | |
218 | * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx | |
219 | * As per AMD technical note 27212 0.2 | |
220 | */ | |
221 | if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) { | |
222 | rdmsr(MSR_K7_CLK_CTL, l, h); | |
223 | if ((l & 0xfff00000) != 0x20000000) { | |
8bdbd962 AC |
224 | printk(KERN_INFO |
225 | "CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", | |
226 | l, ((l & 0x000fffff)|0x20000000)); | |
11fdd252 YL |
227 | wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); |
228 | } | |
229 | } | |
230 | ||
231 | set_cpu_cap(c, X86_FEATURE_K7); | |
1f442d70 YL |
232 | |
233 | amd_k7_smp_check(c); | |
11fdd252 | 234 | } |
6c62aa4a YL |
235 | #endif |
236 | ||
645a7919 | 237 | #ifdef CONFIG_NUMA |
bbc9e2f4 TH |
238 | /* |
239 | * To workaround broken NUMA config. Read the comment in | |
240 | * srat_detect_node(). | |
241 | */ | |
6c62aa4a YL |
242 | static int __cpuinit nearby_node(int apicid) |
243 | { | |
244 | int i, node; | |
245 | ||
246 | for (i = apicid - 1; i >= 0; i--) { | |
bbc9e2f4 | 247 | node = __apicid_to_node[i]; |
6c62aa4a YL |
248 | if (node != NUMA_NO_NODE && node_online(node)) |
249 | return node; | |
250 | } | |
251 | for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { | |
bbc9e2f4 | 252 | node = __apicid_to_node[i]; |
6c62aa4a YL |
253 | if (node != NUMA_NO_NODE && node_online(node)) |
254 | return node; | |
255 | } | |
256 | return first_node(node_online_map); /* Shouldn't happen */ | |
257 | } | |
258 | #endif | |
11fdd252 | 259 | |
4a376ec3 | 260 | /* |
23588c38 AH |
261 | * Fixup core topology information for |
262 | * (1) AMD multi-node processors | |
263 | * Assumption: Number of cores in each internal node is the same. | |
6057b4d3 | 264 | * (2) AMD processors supporting compute units |
4a376ec3 AH |
265 | */ |
266 | #ifdef CONFIG_X86_HT | |
23588c38 | 267 | static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c) |
4a376ec3 | 268 | { |
9e81509e | 269 | u32 nodes, cores_per_cu = 1; |
23588c38 | 270 | u8 node_id; |
4a376ec3 AH |
271 | int cpu = smp_processor_id(); |
272 | ||
23588c38 AH |
273 | /* get information required for multi-node processors */ |
274 | if (cpu_has(c, X86_FEATURE_TOPOEXT)) { | |
6057b4d3 AH |
275 | u32 eax, ebx, ecx, edx; |
276 | ||
277 | cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); | |
278 | nodes = ((ecx >> 8) & 7) + 1; | |
279 | node_id = ecx & 7; | |
280 | ||
281 | /* get compute unit information */ | |
282 | smp_num_siblings = ((ebx >> 8) & 3) + 1; | |
283 | c->compute_unit_id = ebx & 0xff; | |
9e81509e | 284 | cores_per_cu += ((ebx >> 8) & 3); |
23588c38 | 285 | } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { |
6057b4d3 AH |
286 | u64 value; |
287 | ||
23588c38 AH |
288 | rdmsrl(MSR_FAM10H_NODE_ID, value); |
289 | nodes = ((value >> 3) & 7) + 1; | |
290 | node_id = value & 7; | |
291 | } else | |
4a376ec3 AH |
292 | return; |
293 | ||
23588c38 AH |
294 | /* fixup multi-node processor information */ |
295 | if (nodes > 1) { | |
6057b4d3 | 296 | u32 cores_per_node; |
d518573d | 297 | u32 cus_per_node; |
6057b4d3 | 298 | |
23588c38 AH |
299 | set_cpu_cap(c, X86_FEATURE_AMD_DCM); |
300 | cores_per_node = c->x86_max_cores / nodes; | |
d518573d | 301 | cus_per_node = cores_per_node / cores_per_cu; |
9d260ebc | 302 | |
23588c38 AH |
303 | /* store NodeID, use llc_shared_map to store sibling info */ |
304 | per_cpu(cpu_llc_id, cpu) = node_id; | |
4a376ec3 | 305 | |
9e81509e | 306 | /* core id has to be in the [0 .. cores_per_node - 1] range */ |
d518573d AH |
307 | c->cpu_core_id %= cores_per_node; |
308 | c->compute_unit_id %= cus_per_node; | |
23588c38 | 309 | } |
4a376ec3 AH |
310 | } |
311 | #endif | |
312 | ||
11fdd252 YL |
313 | /* |
314 | * On a AMD dual core setup the lower bits of the APIC id distingush the cores. | |
315 | * Assumes number of cores is a power of two. | |
316 | */ | |
317 | static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c) | |
318 | { | |
319 | #ifdef CONFIG_X86_HT | |
320 | unsigned bits; | |
99bd0c0f | 321 | int cpu = smp_processor_id(); |
11fdd252 YL |
322 | |
323 | bits = c->x86_coreid_bits; | |
11fdd252 YL |
324 | /* Low order bits define the core id (index of core in socket) */ |
325 | c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); | |
326 | /* Convert the initial APIC ID into the socket ID */ | |
327 | c->phys_proc_id = c->initial_apicid >> bits; | |
99bd0c0f AH |
328 | /* use socket ID also for last level cache */ |
329 | per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; | |
23588c38 | 330 | amd_get_topology(c); |
11fdd252 YL |
331 | #endif |
332 | } | |
333 | ||
6a812691 AH |
334 | int amd_get_nb_id(int cpu) |
335 | { | |
336 | int id = 0; | |
337 | #ifdef CONFIG_SMP | |
338 | id = per_cpu(cpu_llc_id, cpu); | |
339 | #endif | |
340 | return id; | |
341 | } | |
342 | EXPORT_SYMBOL_GPL(amd_get_nb_id); | |
343 | ||
6c62aa4a YL |
344 | static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c) |
345 | { | |
645a7919 | 346 | #ifdef CONFIG_NUMA |
6c62aa4a YL |
347 | int cpu = smp_processor_id(); |
348 | int node; | |
0d96b9ff | 349 | unsigned apicid = c->apicid; |
6c62aa4a | 350 | |
bbc9e2f4 TH |
351 | node = numa_cpu_node(cpu); |
352 | if (node == NUMA_NO_NODE) | |
353 | node = per_cpu(cpu_llc_id, cpu); | |
6c62aa4a | 354 | |
6c62aa4a | 355 | if (!node_online(node)) { |
bbc9e2f4 TH |
356 | /* |
357 | * Two possibilities here: | |
358 | * | |
359 | * - The CPU is missing memory and no node was created. In | |
360 | * that case try picking one from a nearby CPU. | |
361 | * | |
362 | * - The APIC IDs differ from the HyperTransport node IDs | |
363 | * which the K8 northbridge parsing fills in. Assume | |
364 | * they are all increased by a constant offset, but in | |
365 | * the same order as the HT nodeids. If that doesn't | |
366 | * result in a usable node fall back to the path for the | |
367 | * previous case. | |
368 | * | |
369 | * This workaround operates directly on the mapping between | |
370 | * APIC ID and NUMA node, assuming certain relationship | |
371 | * between APIC ID, HT node ID and NUMA topology. As going | |
372 | * through CPU mapping may alter the outcome, directly | |
373 | * access __apicid_to_node[]. | |
374 | */ | |
6c62aa4a YL |
375 | int ht_nodeid = c->initial_apicid; |
376 | ||
377 | if (ht_nodeid >= 0 && | |
bbc9e2f4 TH |
378 | __apicid_to_node[ht_nodeid] != NUMA_NO_NODE) |
379 | node = __apicid_to_node[ht_nodeid]; | |
6c62aa4a YL |
380 | /* Pick a nearby node */ |
381 | if (!node_online(node)) | |
382 | node = nearby_node(apicid); | |
383 | } | |
384 | numa_set_node(cpu, node); | |
6c62aa4a YL |
385 | #endif |
386 | } | |
387 | ||
11fdd252 YL |
388 | static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c) |
389 | { | |
390 | #ifdef CONFIG_X86_HT | |
391 | unsigned bits, ecx; | |
392 | ||
393 | /* Multi core CPU? */ | |
394 | if (c->extended_cpuid_level < 0x80000008) | |
395 | return; | |
396 | ||
397 | ecx = cpuid_ecx(0x80000008); | |
398 | ||
399 | c->x86_max_cores = (ecx & 0xff) + 1; | |
400 | ||
401 | /* CPU telling us the core id bits shift? */ | |
402 | bits = (ecx >> 12) & 0xF; | |
403 | ||
404 | /* Otherwise recompute */ | |
405 | if (bits == 0) { | |
406 | while ((1 << bits) < c->x86_max_cores) | |
407 | bits++; | |
408 | } | |
409 | ||
410 | c->x86_coreid_bits = bits; | |
411 | #endif | |
412 | } | |
413 | ||
8fa8b035 BP |
414 | static void __cpuinit bsp_init_amd(struct cpuinfo_x86 *c) |
415 | { | |
416 | if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { | |
417 | ||
418 | if (c->x86 > 0x10 || | |
419 | (c->x86 == 0x10 && c->x86_model >= 0x2)) { | |
420 | u64 val; | |
421 | ||
422 | rdmsrl(MSR_K7_HWCR, val); | |
423 | if (!(val & BIT(24))) | |
424 | printk(KERN_WARNING FW_BUG "TSC doesn't count " | |
425 | "with P0 frequency!\n"); | |
426 | } | |
427 | } | |
428 | ||
429 | if (c->x86 == 0x15) { | |
430 | unsigned long upperbit; | |
431 | u32 cpuid, assoc; | |
432 | ||
433 | cpuid = cpuid_edx(0x80000005); | |
434 | assoc = cpuid >> 16 & 0xff; | |
435 | upperbit = ((cpuid >> 24) << 10) / assoc; | |
436 | ||
437 | va_align.mask = (upperbit - 1) & PAGE_MASK; | |
438 | va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; | |
439 | } | |
440 | } | |
441 | ||
03ae5768 | 442 | static void __cpuinit early_init_amd(struct cpuinfo_x86 *c) |
2b16a235 | 443 | { |
11fdd252 YL |
444 | early_init_amd_mc(c); |
445 | ||
40fb1715 VP |
446 | /* |
447 | * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate | |
448 | * with P/T states and does not stop in deep C-states | |
449 | */ | |
450 | if (c->x86_power & (1 << 8)) { | |
e3224234 | 451 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); |
40fb1715 VP |
452 | set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); |
453 | } | |
5fef55fd | 454 | |
6c62aa4a YL |
455 | #ifdef CONFIG_X86_64 |
456 | set_cpu_cap(c, X86_FEATURE_SYSCALL32); | |
457 | #else | |
5fef55fd | 458 | /* Set MTRR capability flag if appropriate */ |
6c62aa4a YL |
459 | if (c->x86 == 5) |
460 | if (c->x86_model == 13 || c->x86_model == 9 || | |
461 | (c->x86_model == 8 && c->x86_mask >= 8)) | |
462 | set_cpu_cap(c, X86_FEATURE_K6_MTRR); | |
463 | #endif | |
42937e81 AH |
464 | #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) |
465 | /* check CPU config space for extended APIC ID */ | |
2cb07860 | 466 | if (cpu_has_apic && c->x86 >= 0xf) { |
42937e81 AH |
467 | unsigned int val; |
468 | val = read_pci_config(0, 24, 0, 0x68); | |
469 | if ((val & ((1 << 17) | (1 << 18))) == ((1 << 17) | (1 << 18))) | |
470 | set_cpu_cap(c, X86_FEATURE_EXTD_APICID); | |
471 | } | |
472 | #endif | |
2b16a235 AK |
473 | } |
474 | ||
b4af3f7c | 475 | static void __cpuinit init_amd(struct cpuinfo_x86 *c) |
1da177e4 | 476 | { |
7d318d77 | 477 | #ifdef CONFIG_SMP |
3c92c2ba | 478 | unsigned long long value; |
7d318d77 | 479 | |
fb87a298 PC |
480 | /* |
481 | * Disable TLB flush filter by setting HWCR.FFDIS on K8 | |
7d318d77 AK |
482 | * bit 6 of msr C001_0015 |
483 | * | |
484 | * Errata 63 for SH-B3 steppings | |
485 | * Errata 122 for all steppings (F+ have it disabled by default) | |
486 | */ | |
11fdd252 | 487 | if (c->x86 == 0xf) { |
7d318d77 AK |
488 | rdmsrl(MSR_K7_HWCR, value); |
489 | value |= 1 << 6; | |
490 | wrmsrl(MSR_K7_HWCR, value); | |
491 | } | |
492 | #endif | |
493 | ||
2b16a235 AK |
494 | early_init_amd(c); |
495 | ||
fb87a298 PC |
496 | /* |
497 | * Bit 31 in normal CPUID used for nonstandard 3DNow ID; | |
16282a8e | 498 | * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway |
fb87a298 | 499 | */ |
16282a8e | 500 | clear_cpu_cap(c, 0*32+31); |
fb87a298 | 501 | |
6c62aa4a YL |
502 | #ifdef CONFIG_X86_64 |
503 | /* On C+ stepping K8 rep microcode works well for copy/memset */ | |
504 | if (c->x86 == 0xf) { | |
505 | u32 level; | |
506 | ||
507 | level = cpuid_eax(1); | |
8bdbd962 | 508 | if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) |
6c62aa4a | 509 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); |
fbd8b181 KW |
510 | |
511 | /* | |
512 | * Some BIOSes incorrectly force this feature, but only K8 | |
513 | * revision D (model = 0x14) and later actually support it. | |
6b0f43dd | 514 | * (AMD Erratum #110, docId: 25759). |
fbd8b181 | 515 | */ |
6b0f43dd BP |
516 | if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { |
517 | u64 val; | |
518 | ||
fbd8b181 | 519 | clear_cpu_cap(c, X86_FEATURE_LAHF_LM); |
6b0f43dd BP |
520 | if (!rdmsrl_amd_safe(0xc001100d, &val)) { |
521 | val &= ~(1ULL << 32); | |
522 | wrmsrl_amd_safe(0xc001100d, val); | |
523 | } | |
524 | } | |
525 | ||
6c62aa4a | 526 | } |
12d8a961 | 527 | if (c->x86 >= 0x10) |
6c62aa4a | 528 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); |
0d96b9ff YL |
529 | |
530 | /* get apicid instead of initial apic id from cpuid */ | |
531 | c->apicid = hard_smp_processor_id(); | |
6c62aa4a YL |
532 | #else |
533 | ||
534 | /* | |
535 | * FIXME: We should handle the K5 here. Set up the write | |
536 | * range and also turn on MSR 83 bits 4 and 31 (write alloc, | |
537 | * no bus pipeline) | |
538 | */ | |
539 | ||
fb87a298 PC |
540 | switch (c->x86) { |
541 | case 4: | |
11fdd252 YL |
542 | init_amd_k5(c); |
543 | break; | |
fb87a298 | 544 | case 5: |
11fdd252 | 545 | init_amd_k6(c); |
1da177e4 | 546 | break; |
11fdd252 YL |
547 | case 6: /* An Athlon/Duron */ |
548 | init_amd_k7(c); | |
1da177e4 LT |
549 | break; |
550 | } | |
11fdd252 YL |
551 | |
552 | /* K6s reports MCEs but don't actually have all the MSRs */ | |
553 | if (c->x86 < 6) | |
554 | clear_cpu_cap(c, X86_FEATURE_MCE); | |
6c62aa4a | 555 | #endif |
11fdd252 | 556 | |
6c62aa4a | 557 | /* Enable workaround for FXSAVE leak */ |
18bd057b | 558 | if (c->x86 >= 6) |
16282a8e | 559 | set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK); |
1da177e4 | 560 | |
11fdd252 YL |
561 | if (!c->x86_model_id[0]) { |
562 | switch (c->x86) { | |
563 | case 0xf: | |
564 | /* Should distinguish Models here, but this is only | |
565 | a fallback anyways. */ | |
566 | strcpy(c->x86_model_id, "Hammer"); | |
567 | break; | |
568 | } | |
569 | } | |
3dd9d514 | 570 | |
27c13ece | 571 | cpu_detect_cache_sizes(c); |
3dd9d514 | 572 | |
11fdd252 | 573 | /* Multi core CPU? */ |
6c62aa4a | 574 | if (c->extended_cpuid_level >= 0x80000008) { |
11fdd252 | 575 | amd_detect_cmp(c); |
6c62aa4a YL |
576 | srat_detect_node(c); |
577 | } | |
faee9a5d | 578 | |
6c62aa4a | 579 | #ifdef CONFIG_X86_32 |
11fdd252 | 580 | detect_ht(c); |
6c62aa4a | 581 | #endif |
39b3a791 | 582 | |
11fdd252 | 583 | if (c->extended_cpuid_level >= 0x80000006) { |
d9fadd7b | 584 | if (cpuid_edx(0x80000006) & 0xf000) |
67cddd94 AK |
585 | num_cache_leaves = 4; |
586 | else | |
587 | num_cache_leaves = 3; | |
588 | } | |
3556ddfa | 589 | |
12d8a961 | 590 | if (c->x86 >= 0xf) |
11fdd252 | 591 | set_cpu_cap(c, X86_FEATURE_K8); |
de421863 | 592 | |
11fdd252 YL |
593 | if (cpu_has_xmm2) { |
594 | /* MFENCE stops RDTSC speculation */ | |
16282a8e | 595 | set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); |
11fdd252 | 596 | } |
6c62aa4a YL |
597 | |
598 | #ifdef CONFIG_X86_64 | |
599 | if (c->x86 == 0x10) { | |
600 | /* do this for boot cpu */ | |
601 | if (c == &boot_cpu_data) | |
602 | check_enable_amd_mmconf_dmi(); | |
603 | ||
604 | fam10h_check_enable_mmcfg(); | |
605 | } | |
606 | ||
12d8a961 | 607 | if (c == &boot_cpu_data && c->x86 >= 0xf) { |
6c62aa4a YL |
608 | unsigned long long tseg; |
609 | ||
610 | /* | |
611 | * Split up direct mapping around the TSEG SMM area. | |
612 | * Don't do it for gbpages because there seems very little | |
613 | * benefit in doing so. | |
614 | */ | |
615 | if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { | |
8bdbd962 AC |
616 | printk(KERN_DEBUG "tseg: %010llx\n", tseg); |
617 | if ((tseg>>PMD_SHIFT) < | |
6c62aa4a | 618 | (max_low_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) || |
8bdbd962 | 619 | ((tseg>>PMD_SHIFT) < |
6c62aa4a | 620 | (max_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) && |
8bdbd962 AC |
621 | (tseg>>PMD_SHIFT) >= (1ULL<<(32 - PMD_SHIFT)))) |
622 | set_memory_4k((unsigned long)__va(tseg), 1); | |
6c62aa4a YL |
623 | } |
624 | } | |
625 | #endif | |
b87cf80a | 626 | |
e9cdd343 BO |
627 | /* |
628 | * Family 0x12 and above processors have APIC timer | |
629 | * running in deep C states. | |
630 | */ | |
631 | if (c->x86 > 0x11) | |
b87cf80a | 632 | set_cpu_cap(c, X86_FEATURE_ARAT); |
5bbc097d JR |
633 | |
634 | /* | |
635 | * Disable GART TLB Walk Errors on Fam10h. We do this here | |
636 | * because this is always needed when GART is enabled, even in a | |
637 | * kernel which has no MCE support built in. | |
638 | */ | |
639 | if (c->x86 == 0x10) { | |
640 | /* | |
641 | * BIOS should disable GartTlbWlk Errors themself. If | |
642 | * it doesn't do it here as suggested by the BKDG. | |
643 | * | |
644 | * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 | |
645 | */ | |
646 | u64 mask; | |
d47cc0db | 647 | int err; |
5bbc097d | 648 | |
d47cc0db RJ |
649 | err = rdmsrl_safe(MSR_AMD64_MCx_MASK(4), &mask); |
650 | if (err == 0) { | |
651 | mask |= (1 << 10); | |
652 | checking_wrmsrl(MSR_AMD64_MCx_MASK(4), mask); | |
653 | } | |
5bbc097d | 654 | } |
1da177e4 LT |
655 | } |
656 | ||
6c62aa4a | 657 | #ifdef CONFIG_X86_32 |
8bdbd962 AC |
658 | static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, |
659 | unsigned int size) | |
1da177e4 LT |
660 | { |
661 | /* AMD errata T13 (order #21922) */ | |
662 | if ((c->x86 == 6)) { | |
8bdbd962 AC |
663 | /* Duron Rev A0 */ |
664 | if (c->x86_model == 3 && c->x86_mask == 0) | |
1da177e4 | 665 | size = 64; |
8bdbd962 | 666 | /* Tbird rev A1/A2 */ |
1da177e4 | 667 | if (c->x86_model == 4 && |
8bdbd962 | 668 | (c->x86_mask == 0 || c->x86_mask == 1)) |
1da177e4 LT |
669 | size = 256; |
670 | } | |
671 | return size; | |
672 | } | |
6c62aa4a | 673 | #endif |
1da177e4 | 674 | |
02dde8b4 | 675 | static const struct cpu_dev __cpuinitconst amd_cpu_dev = { |
1da177e4 | 676 | .c_vendor = "AMD", |
fb87a298 | 677 | .c_ident = { "AuthenticAMD" }, |
6c62aa4a | 678 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
679 | .c_models = { |
680 | { .vendor = X86_VENDOR_AMD, .family = 4, .model_names = | |
681 | { | |
682 | [3] = "486 DX/2", | |
683 | [7] = "486 DX/2-WB", | |
fb87a298 PC |
684 | [8] = "486 DX/4", |
685 | [9] = "486 DX/4-WB", | |
1da177e4 | 686 | [14] = "Am5x86-WT", |
fb87a298 | 687 | [15] = "Am5x86-WB" |
1da177e4 LT |
688 | } |
689 | }, | |
690 | }, | |
6c62aa4a YL |
691 | .c_size_cache = amd_size_cache, |
692 | #endif | |
03ae5768 | 693 | .c_early_init = early_init_amd, |
8fa8b035 | 694 | .c_bsp_init = bsp_init_amd, |
1da177e4 | 695 | .c_init = init_amd, |
10a434fc | 696 | .c_x86_vendor = X86_VENDOR_AMD, |
1da177e4 LT |
697 | }; |
698 | ||
10a434fc | 699 | cpu_dev_register(amd_cpu_dev); |
d78d671d HR |
700 | |
701 | /* | |
702 | * AMD errata checking | |
703 | * | |
704 | * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or | |
705 | * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that | |
706 | * have an OSVW id assigned, which it takes as first argument. Both take a | |
707 | * variable number of family-specific model-stepping ranges created by | |
708 | * AMD_MODEL_RANGE(). Each erratum also has to be declared as extern const | |
709 | * int[] in arch/x86/include/asm/processor.h. | |
710 | * | |
711 | * Example: | |
712 | * | |
713 | * const int amd_erratum_319[] = | |
714 | * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), | |
715 | * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), | |
716 | * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); | |
717 | */ | |
718 | ||
9d8888c2 | 719 | const int amd_erratum_400[] = |
328935e6 | 720 | AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), |
9d8888c2 | 721 | AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); |
a5b91606 | 722 | EXPORT_SYMBOL_GPL(amd_erratum_400); |
9d8888c2 | 723 | |
1be85a6d HR |
724 | const int amd_erratum_383[] = |
725 | AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); | |
a5b91606 | 726 | EXPORT_SYMBOL_GPL(amd_erratum_383); |
9d8888c2 | 727 | |
d78d671d HR |
728 | bool cpu_has_amd_erratum(const int *erratum) |
729 | { | |
7b543a53 | 730 | struct cpuinfo_x86 *cpu = __this_cpu_ptr(&cpu_info); |
d78d671d HR |
731 | int osvw_id = *erratum++; |
732 | u32 range; | |
733 | u32 ms; | |
734 | ||
735 | /* | |
736 | * If called early enough that current_cpu_data hasn't been initialized | |
737 | * yet, fall back to boot_cpu_data. | |
738 | */ | |
739 | if (cpu->x86 == 0) | |
740 | cpu = &boot_cpu_data; | |
741 | ||
742 | if (cpu->x86_vendor != X86_VENDOR_AMD) | |
743 | return false; | |
744 | ||
745 | if (osvw_id >= 0 && osvw_id < 65536 && | |
746 | cpu_has(cpu, X86_FEATURE_OSVW)) { | |
747 | u64 osvw_len; | |
748 | ||
749 | rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); | |
750 | if (osvw_id < osvw_len) { | |
751 | u64 osvw_bits; | |
752 | ||
753 | rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), | |
754 | osvw_bits); | |
755 | return osvw_bits & (1ULL << (osvw_id & 0x3f)); | |
756 | } | |
757 | } | |
758 | ||
759 | /* OSVW unavailable or ID unknown, match family-model-stepping range */ | |
07a7795c | 760 | ms = (cpu->x86_model << 4) | cpu->x86_mask; |
d78d671d HR |
761 | while ((range = *erratum++)) |
762 | if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && | |
763 | (ms >= AMD_MODEL_RANGE_START(range)) && | |
764 | (ms <= AMD_MODEL_RANGE_END(range))) | |
765 | return true; | |
766 | ||
767 | return false; | |
768 | } | |
a5b91606 PA |
769 | |
770 | EXPORT_SYMBOL_GPL(cpu_has_amd_erratum); |