[mirror_ubuntu-artful-kernel.git] / arch / x86 / kernel / cpu / amd.c

#include <linux/init.h>
#include <linux/bitops.h>
#include <linux/mm.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/apic.h>
#include <asm/mach_apic.h>

#include "cpu.h"

/*
 *	B step AMD K6 before B 9730xxxx have hardware bugs that can cause
 *	misexecution of code under Linux. Owners of such processors should
 *	contact AMD for precise details and a CPU swap.
 *
 *	See	http://www.multimania.com/poulot/k6bug.html
 *		http://www.amd.com/K6/k6docs/revgd.html
 *
 *	The following test is erm.. interesting. AMD neglected to up
 *	the chip setting when fixing the bug but they also tweaked some
 *	performance at the same time..
 */

extern void vide(void);
__asm__(".align 4\nvide: ret");

#ifdef CONFIG_X86_LOCAL_APIC
#define ENABLE_C1E_MASK         0x18000000
#define CPUID_PROCESSOR_SIGNATURE       1
#define CPUID_XFAM              0x0ff00000
#define CPUID_XFAM_K8           0x00000000
#define CPUID_XFAM_10H          0x00100000
#define CPUID_XFAM_11H          0x00200000
#define CPUID_XMOD              0x000f0000
#define CPUID_XMOD_REV_F        0x00040000

/* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
static __cpuinit int amd_apic_timer_broken(void)
{
	u32 lo, hi;
	u32 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
	switch (eax & CPUID_XFAM) {
	case CPUID_XFAM_K8:
		if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
			break;
	case CPUID_XFAM_10H:
	case CPUID_XFAM_11H:
		rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
		if (lo & ENABLE_C1E_MASK) {
			if (smp_processor_id() != boot_cpu_physical_apicid)
				printk(KERN_INFO "AMD C1E detected late. "
				       "	Force timer broadcast.\n");
			return 1;
		}
		break;
	default:
		/* err on the side of caution */
		return 1;
	}
	return 0;
}
#endif

int force_mwait __cpuinitdata;

static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
{
	if (cpuid_eax(0x80000000) >= 0x80000007) {
		c->x86_power = cpuid_edx(0x80000007);
		if (c->x86_power & (1<<8))
			set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
	}
}

static void __cpuinit init_amd(struct cpuinfo_x86 *c)
{
	u32 l, h;
	int mbytes = num_physpages >> (20-PAGE_SHIFT);
	int r;

#ifdef CONFIG_SMP
	unsigned long long value;

	/*
	 * Disable TLB flush filter by setting HWCR.FFDIS on K8
	 * bit 6 of msr C001_0015
	 *
	 * Errata 63 for SH-B3 steppings
	 * Errata 122 for all steppings (F+ have it disabled by default)
	 */
	if (c->x86 == 15) {
		rdmsrl(MSR_K7_HWCR, value);
		value |= 1 << 6;
		wrmsrl(MSR_K7_HWCR, value);
	}
#endif

	early_init_amd(c);

	/*
	 *	FIXME: We should handle the K5 here. Set up the write
	 *	range and also turn on MSR 83 bits 4 and 31 (write alloc,
	 *	no bus pipeline)
	 */

	/*
	 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
	 * DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
	 */
	clear_bit(0*32+31, c->x86_capability);

	r = get_model_name(c);

	switch (c->x86) {
	case 4:
		/*
		 * General Systems BIOSen alias the cpu frequency registers
		 * of the Elan at 0x000df000. Unfortuantly, one of the Linux
		 * drivers subsequently pokes it, and changes the CPU speed.
		 * Workaround : Remove the unneeded alias.
		 */
#define CBAR		(0xfffc) /* Configuration Base Address  (32-bit) */
#define CBAR_ENB	(0x80000000)
#define CBAR_KEY	(0X000000CB)
			if (c->x86_model == 9 || c->x86_model == 10) {
				if (inl (CBAR) & CBAR_ENB)
					outl (0 | CBAR_KEY, CBAR);
			}
			break;
	case 5:
			if (c->x86_model < 6) {
				/* Based on AMD doc 20734R - June 2000 */
				if (c->x86_model == 0) {
					clear_bit(X86_FEATURE_APIC, c->x86_capability);
					set_bit(X86_FEATURE_PGE, c->x86_capability);
				}
				break;
			}

			if (c->x86_model == 6 && c->x86_mask == 1) {
				const int K6_BUG_LOOP = 1000000;
				int n;
				void (*f_vide)(void);
				unsigned long d, d2;

				printk(KERN_INFO "AMD K6 stepping B detected - ");

				/*
				 * It looks like AMD fixed the 2.6.2 bug and improved indirect
				 * calls at the same time.
				 */

				n = K6_BUG_LOOP;
				f_vide = vide;
				rdtscl(d);
				while (n--)
					f_vide();
				rdtscl(d2);
				d = d2-d;

				if (d > 20*K6_BUG_LOOP)
					printk("system stability may be impaired when more than 32 MB are used.\n");
				else
					printk("probably OK (after B9730xxxx).\n");
				printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
			}

			/* K6 with old style WHCR */
			if (c->x86_model < 8 ||
			   (c->x86_model == 8 && c->x86_mask < 8)) {
				/* We can only write allocate on the low 508Mb */
				if (mbytes > 508)
					mbytes = 508;

				rdmsr(MSR_K6_WHCR, l, h);
				if ((l&0x0000FFFF) == 0) {
					unsigned long flags;
					l = (1<<0)|((mbytes/4)<<1);
					local_irq_save(flags);
					wbinvd();
					wrmsr(MSR_K6_WHCR, l, h);
					local_irq_restore(flags);
					printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
						mbytes);
				}
				break;
			}

			if ((c->x86_model == 8 && c->x86_mask > 7) ||
			     c->x86_model == 9 || c->x86_model == 13) {
				/* The more serious chips .. */

				if (mbytes > 4092)
					mbytes = 4092;

				rdmsr(MSR_K6_WHCR, l, h);
				if ((l&0xFFFF0000) == 0) {
					unsigned long flags;
					l = ((mbytes>>2)<<22)|(1<<16);
					local_irq_save(flags);
					wbinvd();
					wrmsr(MSR_K6_WHCR, l, h);
					local_irq_restore(flags);
					printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
						mbytes);
				}

				/*  Set MTRR capability flag if appropriate */
				if (c->x86_model == 13 || c->x86_model == 9 ||
				   (c->x86_model == 8 && c->x86_mask >= 8))
					set_bit(X86_FEATURE_K6_MTRR, c->x86_capability);
				break;
			}

			if (c->x86_model == 10) {
				/* AMD Geode LX is model 10 */
				/* placeholder for any needed mods */
				break;
			}
			break;
	case 6: /* An Athlon/Duron */

			/*
			 * Bit 15 of Athlon specific MSR 15, needs to be 0
			 * to enable SSE on Palomino/Morgan/Barton CPU's.
			 * If the BIOS didn't enable it already, enable it here.
			 */
			if (c->x86_model >= 6 && c->x86_model <= 10) {
				if (!cpu_has(c, X86_FEATURE_XMM)) {
					printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
					rdmsr(MSR_K7_HWCR, l, h);
					l &= ~0x00008000;
					wrmsr(MSR_K7_HWCR, l, h);
					set_bit(X86_FEATURE_XMM, c->x86_capability);
				}
			}

			/*
			 * It's been determined by AMD that Athlons since model 8 stepping 1
			 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
			 * As per AMD technical note 27212 0.2
			 */
			if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
				rdmsr(MSR_K7_CLK_CTL, l, h);
				if ((l & 0xfff00000) != 0x20000000) {
					printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
						((l & 0x000fffff)|0x20000000));
					wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
				}
			}
			break;
	}

	switch (c->x86) {
	case 15:
	/* Use K8 tuning for Fam10h and Fam11h */
	case 0x10:
	case 0x11:
		set_bit(X86_FEATURE_K8, c->x86_capability);
		break;
	case 6:
		set_bit(X86_FEATURE_K7, c->x86_capability);
		break;
	}
	if (c->x86 >= 6)
		set_bit(X86_FEATURE_FXSAVE_LEAK, c->x86_capability);

	display_cacheinfo(c);

	if (cpuid_eax(0x80000000) >= 0x80000008)
		c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;

#ifdef CONFIG_X86_HT
	/*
	 * On a AMD multi core setup the lower bits of the APIC id
	 * distinguish the cores.
	 */
	if (c->x86_max_cores > 1) {
		int cpu = smp_processor_id();
		unsigned bits = (cpuid_ecx(0x80000008) >> 12) & 0xf;

		if (bits == 0) {
			while ((1 << bits) < c->x86_max_cores)
				bits++;
		}
		c->cpu_core_id = c->phys_proc_id & ((1<<bits)-1);
		c->phys_proc_id >>= bits;
		printk(KERN_INFO "CPU %d(%d) -> Core %d\n",
		       cpu, c->x86_max_cores, c->cpu_core_id);
	}
#endif

	if (cpuid_eax(0x80000000) >= 0x80000006) {
		if ((c->x86 == 0x10) && (cpuid_edx(0x80000006) & 0xf000))
			num_cache_leaves = 4;
		else
			num_cache_leaves = 3;
	}

#ifdef CONFIG_X86_LOCAL_APIC
	if (amd_apic_timer_broken())
		local_apic_timer_disabled = 1;
#endif

	/* K6s reports MCEs but don't actually have all the MSRs */
	if (c->x86 < 6)
		clear_bit(X86_FEATURE_MCE, c->x86_capability);

	if (cpu_has_xmm2)
		set_bit(X86_FEATURE_MFENCE_RDTSC, c->x86_capability);
}

static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
{
	/* AMD errata T13 (order #21922) */
	if ((c->x86 == 6)) {
		if (c->x86_model == 3 && c->x86_mask == 0)	/* Duron Rev A0 */
			size = 64;
		if (c->x86_model == 4 &&
		    (c->x86_mask == 0 || c->x86_mask == 1))	/* Tbird rev A1/A2 */
			size = 256;
	}
	return size;
}

static struct cpu_dev amd_cpu_dev __cpuinitdata = {
	.c_vendor	= "AMD",
	.c_ident	= { "AuthenticAMD" },
	.c_models = {
		{ .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
		  {
			  [3] = "486 DX/2",
			  [7] = "486 DX/2-WB",
			  [8] = "486 DX/4",
			  [9] = "486 DX/4-WB",
			  [14] = "Am5x86-WT",
			  [15] = "Am5x86-WB"
		  }
		},
	},
	.c_early_init   = early_init_amd,
	.c_init		= init_amd,
	.c_size_cache	= amd_size_cache,
};

int __init amd_init_cpu(void)
{
	cpu_devs[X86_VENDOR_AMD] = &amd_cpu_dev;
	return 0;
}

cpu_vendor_dev_register(X86_VENDOR_AMD, &amd_cpu_dev);
Commit	Line	Data
1da177e4 LT	1	#include <linux/init.h>
	2	#include <linux/bitops.h>
	3	#include <linux/mm.h>
	4	#include <asm/io.h>
	5	#include <asm/processor.h>
d3f7eae1	6	#include <asm/apic.h>
c1e3619e	7	#include <asm/mach_apic.h>
1da177e4 LT	8
	9	#include "cpu.h"
	10
	11	/*
	12	* B step AMD K6 before B 9730xxxx have hardware bugs that can cause
	13	* misexecution of code under Linux. Owners of such processors should
	14	* contact AMD for precise details and a CPU swap.
	15	*
	16	* See http://www.multimania.com/poulot/k6bug.html
	17	* http://www.amd.com/K6/k6docs/revgd.html
	18	*
	19	* The following test is erm.. interesting. AMD neglected to up
	20	* the chip setting when fixing the bug but they also tweaked some
	21	* performance at the same time..
	22	*/
fb87a298	23
1da177e4 LT	24	extern void vide(void);
	25	__asm__(".align 4\nvide: ret");
	26
d3f7eae1	27	#ifdef CONFIG_X86_LOCAL_APIC
3556ddfa AK	28	#define ENABLE_C1E_MASK 0x18000000
	29	#define CPUID_PROCESSOR_SIGNATURE 1
	30	#define CPUID_XFAM 0x0ff00000
	31	#define CPUID_XFAM_K8 0x00000000
	32	#define CPUID_XFAM_10H 0x00100000
	33	#define CPUID_XFAM_11H 0x00200000
	34	#define CPUID_XMOD 0x000f0000
	35	#define CPUID_XMOD_REV_F 0x00040000
	36
	37	/* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
	38	static __cpuinit int amd_apic_timer_broken(void)
	39	{
	40	u32 lo, hi;
	41	u32 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
	42	switch (eax & CPUID_XFAM) {
	43	case CPUID_XFAM_K8:
	44	if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
	45	break;
	46	case CPUID_XFAM_10H:
	47	case CPUID_XFAM_11H:
	48	rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
c1e3619e TG	49	if (lo & ENABLE_C1E_MASK) {
	50	if (smp_processor_id() != boot_cpu_physical_apicid)
	51	printk(KERN_INFO "AMD C1E detected late. "
	52	" Force timer broadcast.\n");
3556ddfa	53	return 1;
c1e3619e TG	54	}
	55	break;
	56	default:
	57	/* err on the side of caution */
3556ddfa	58	return 1;
c1e3619e	59	}
3556ddfa AK	60	return 0;
3556ddfa AK	61	}
d3f7eae1	62	#endif
3556ddfa	63
f039b754 AK	64	int force_mwait __cpuinitdata;
f039b754 AK	65
03ae5768	66	static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
2b16a235 AK	67	{
	68	if (cpuid_eax(0x80000000) >= 0x80000007) {
	69	c->x86_power = cpuid_edx(0x80000007);
	70	if (c->x86_power & (1<<8))
	71	set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
	72	}
	73	}
	74
b4af3f7c	75	static void __cpuinit init_amd(struct cpuinfo_x86 *c)
1da177e4 LT	76	{
	77	u32 l, h;
	78	int mbytes = num_physpages >> (20-PAGE_SHIFT);
	79	int r;
	80
7d318d77	81	#ifdef CONFIG_SMP
3c92c2ba	82	unsigned long long value;
7d318d77	83
fb87a298 PC	84	/*
fb87a298 PC	85	* Disable TLB flush filter by setting HWCR.FFDIS on K8
7d318d77 AK	86	* bit 6 of msr C001_0015
	87	*
	88	* Errata 63 for SH-B3 steppings
	89	* Errata 122 for all steppings (F+ have it disabled by default)
	90	*/
	91	if (c->x86 == 15) {
	92	rdmsrl(MSR_K7_HWCR, value);
	93	value \|= 1 << 6;
	94	wrmsrl(MSR_K7_HWCR, value);
	95	}
	96	#endif
	97
2b16a235 AK	98	early_init_amd(c);
2b16a235 AK	99
1da177e4 LT	100	/*
	101	* FIXME: We should handle the K5 here. Set up the write
	102	* range and also turn on MSR 83 bits 4 and 31 (write alloc,
	103	* no bus pipeline)
	104	*/
	105
fb87a298 PC	106	/*
	107	* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
	108	* DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
	109	*/
1da177e4	110	clear_bit(0*32+31, c->x86_capability);
fb87a298	111
1da177e4 LT	112	r = get_model_name(c);
1da177e4 LT	113
fb87a298 PC	114	switch (c->x86) {
fb87a298 PC	115	case 4:
1da177e4 LT	116	/*
	117	* General Systems BIOSen alias the cpu frequency registers
	118	* of the Elan at 0x000df000. Unfortuantly, one of the Linux
	119	* drivers subsequently pokes it, and changes the CPU speed.
	120	* Workaround : Remove the unneeded alias.
	121	*/
	122	#define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
	123	#define CBAR_ENB (0x80000000)
	124	#define CBAR_KEY (0X000000CB)
fb87a298	125	if (c->x86_model == 9 \|\| c->x86_model == 10) {
1da177e4 LT	126	if (inl (CBAR) & CBAR_ENB)
	127	outl (0 \| CBAR_KEY, CBAR);
	128	}
	129	break;
fb87a298 PC	130	case 5:
fb87a298 PC	131	if (c->x86_model < 6) {
1da177e4	132	/* Based on AMD doc 20734R - June 2000 */
fb87a298	133	if (c->x86_model == 0) {
1da177e4 LT	134	clear_bit(X86_FEATURE_APIC, c->x86_capability);
	135	set_bit(X86_FEATURE_PGE, c->x86_capability);
	136	}
	137	break;
	138	}
fb87a298 PC	139
fb87a298 PC	140	if (c->x86_model == 6 && c->x86_mask == 1) {
1da177e4 LT	141	const int K6_BUG_LOOP = 1000000;
	142	int n;
	143	void (*f_vide)(void);
	144	unsigned long d, d2;
fb87a298	145
1da177e4	146	printk(KERN_INFO "AMD K6 stepping B detected - ");
fb87a298	147
1da177e4	148	/*
fb87a298	149	* It looks like AMD fixed the 2.6.2 bug and improved indirect
1da177e4 LT	150	* calls at the same time.
	151	*/
	152
	153	n = K6_BUG_LOOP;
	154	f_vide = vide;
	155	rdtscl(d);
fb87a298	156	while (n--)
1da177e4 LT	157	f_vide();
	158	rdtscl(d2);
	159	d = d2-d;
6df0532e	160
fb87a298	161	if (d > 20*K6_BUG_LOOP)
1da177e4	162	printk("system stability may be impaired when more than 32 MB are used.\n");
fb87a298	163	else
1da177e4 LT	164	printk("probably OK (after B9730xxxx).\n");
	165	printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
	166	}
	167
	168	/* K6 with old style WHCR */
	169	if (c->x86_model < 8 \|\|
fb87a298	170	(c->x86_model == 8 && c->x86_mask < 8)) {
1da177e4	171	/* We can only write allocate on the low 508Mb */
fb87a298 PC	172	if (mbytes > 508)
fb87a298 PC	173	mbytes = 508;
1da177e4 LT	174
1da177e4 LT	175	rdmsr(MSR_K6_WHCR, l, h);
fb87a298	176	if ((l&0x0000FFFF) == 0) {
1da177e4	177	unsigned long flags;
fb87a298	178	l = (1<<0)\|((mbytes/4)<<1);
1da177e4 LT	179	local_irq_save(flags);
	180	wbinvd();
	181	wrmsr(MSR_K6_WHCR, l, h);
	182	local_irq_restore(flags);
	183	printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
	184	mbytes);
	185	}
	186	break;
	187	}
	188
fb87a298	189	if ((c->x86_model == 8 && c->x86_mask > 7) \|\|
1da177e4 LT	190	c->x86_model == 9 \|\| c->x86_model == 13) {
	191	/* The more serious chips .. */
	192
fb87a298 PC	193	if (mbytes > 4092)
fb87a298 PC	194	mbytes = 4092;
1da177e4 LT	195
1da177e4 LT	196	rdmsr(MSR_K6_WHCR, l, h);
fb87a298	197	if ((l&0xFFFF0000) == 0) {
1da177e4	198	unsigned long flags;
fb87a298	199	l = ((mbytes>>2)<<22)\|(1<<16);
1da177e4 LT	200	local_irq_save(flags);
	201	wbinvd();
	202	wrmsr(MSR_K6_WHCR, l, h);
	203	local_irq_restore(flags);
	204	printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
	205	mbytes);
	206	}
	207
	208	/* Set MTRR capability flag if appropriate */
	209	if (c->x86_model == 13 \|\| c->x86_model == 9 \|\|
	210	(c->x86_model == 8 && c->x86_mask >= 8))
	211	set_bit(X86_FEATURE_K6_MTRR, c->x86_capability);
	212	break;
	213	}
1da177e4	214
f90b8116 JC	215	if (c->x86_model == 10) {
	216	/* AMD Geode LX is model 10 */
	217	/* placeholder for any needed mods */
	218	break;
	219	}
	220	break;
fb87a298 PC	221	case 6: /* An Athlon/Duron */
	222
	223	/*
	224	* Bit 15 of Athlon specific MSR 15, needs to be 0
	225	* to enable SSE on Palomino/Morgan/Barton CPU's.
1da177e4 LT	226	* If the BIOS didn't enable it already, enable it here.
	227	*/
	228	if (c->x86_model >= 6 && c->x86_model <= 10) {
	229	if (!cpu_has(c, X86_FEATURE_XMM)) {
	230	printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
	231	rdmsr(MSR_K7_HWCR, l, h);
	232	l &= ~0x00008000;
	233	wrmsr(MSR_K7_HWCR, l, h);
	234	set_bit(X86_FEATURE_XMM, c->x86_capability);
	235	}
	236	}
	237
fb87a298 PC	238	/*
fb87a298 PC	239	* It's been determined by AMD that Athlons since model 8 stepping 1
1da177e4 LT	240	* are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
	241	* As per AMD technical note 27212 0.2
	242	*/
fb87a298	243	if ((c->x86_model == 8 && c->x86_mask >= 1) \|\| (c->x86_model > 8)) {
1da177e4 LT	244	rdmsr(MSR_K7_CLK_CTL, l, h);
	245	if ((l & 0xfff00000) != 0x20000000) {
	246	printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
	247	((l & 0x000fffff)\|0x20000000));
	248	wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)\|0x20000000, h);
	249	}
	250	}
	251	break;
	252	}
	253
	254	switch (c->x86) {
	255	case 15:
398cf2ab AK	256	/* Use K8 tuning for Fam10h and Fam11h */
	257	case 0x10:
	258	case 0x11:
1da177e4 LT	259	set_bit(X86_FEATURE_K8, c->x86_capability);
	260	break;
	261	case 6:
fb87a298	262	set_bit(X86_FEATURE_K7, c->x86_capability);
1da177e4 LT	263	break;
1da177e4 LT	264	}
18bd057b AK	265	if (c->x86 >= 6)
18bd057b AK	266	set_bit(X86_FEATURE_FXSAVE_LEAK, c->x86_capability);
1da177e4 LT	267
1da177e4 LT	268	display_cacheinfo(c);
3dd9d514	269
fb87a298	270	if (cpuid_eax(0x80000000) >= 0x80000008)
94605eff	271	c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
3dd9d514	272
b41e2939	273	#ifdef CONFIG_X86_HT
63518644	274	/*
faee9a5d	275	* On a AMD multi core setup the lower bits of the APIC id
27b46d76	276	* distinguish the cores.
63518644	277	*/
94605eff	278	if (c->x86_max_cores > 1) {
a158608b	279	int cpu = smp_processor_id();
faee9a5d AK	280	unsigned bits = (cpuid_ecx(0x80000008) >> 12) & 0xf;
	281
	282	if (bits == 0) {
	283	while ((1 << bits) < c->x86_max_cores)
	284	bits++;
	285	}
4b89aff9 RS	286	c->cpu_core_id = c->phys_proc_id & ((1<<bits)-1);
4b89aff9 RS	287	c->phys_proc_id >>= bits;
63518644	288	printk(KERN_INFO "CPU %d(%d) -> Core %d\n",
4b89aff9	289	cpu, c->x86_max_cores, c->cpu_core_id);
63518644	290	}
1da177e4	291	#endif
39b3a791	292
67cddd94 AK	293	if (cpuid_eax(0x80000000) >= 0x80000006) {
	294	if ((c->x86 == 0x10) && (cpuid_edx(0x80000006) & 0xf000))
	295	num_cache_leaves = 4;
	296	else
	297	num_cache_leaves = 3;
	298	}
3556ddfa	299
d3f7eae1	300	#ifdef CONFIG_X86_LOCAL_APIC
3556ddfa	301	if (amd_apic_timer_broken())
d3f7eae1 AK	302	local_apic_timer_disabled = 1;
d3f7eae1 AK	303	#endif
f039b754	304
c12ceb76 AK	305	/* K6s reports MCEs but don't actually have all the MSRs */
	306	if (c->x86 < 6)
	307	clear_bit(X86_FEATURE_MCE, c->x86_capability);
de421863	308
aa629992	309	if (cpu_has_xmm2)
de421863	310	set_bit(X86_FEATURE_MFENCE_RDTSC, c->x86_capability);
1da177e4 LT	311	}
1da177e4 LT	312
fb87a298	313	static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
1da177e4 LT	314	{
	315	/* AMD errata T13 (order #21922) */
	316	if ((c->x86 == 6)) {
	317	if (c->x86_model == 3 && c->x86_mask == 0) /* Duron Rev A0 */
	318	size = 64;
	319	if (c->x86_model == 4 &&
fb87a298	320	(c->x86_mask == 0 \|\| c->x86_mask == 1)) /* Tbird rev A1/A2 */
1da177e4 LT	321	size = 256;
	322	}
	323	return size;
	324	}
	325
95414930	326	static struct cpu_dev amd_cpu_dev __cpuinitdata = {
1da177e4	327	.c_vendor = "AMD",
fb87a298	328	.c_ident = { "AuthenticAMD" },
1da177e4 LT	329	.c_models = {
	330	{ .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
	331	{
	332	[3] = "486 DX/2",
	333	[7] = "486 DX/2-WB",
fb87a298 PC	334	[8] = "486 DX/4",
fb87a298 PC	335	[9] = "486 DX/4-WB",
1da177e4	336	[14] = "Am5x86-WT",
fb87a298	337	[15] = "Am5x86-WB"
1da177e4 LT	338	}
	339	},
	340	},
03ae5768	341	.c_early_init = early_init_amd,
1da177e4	342	.c_init = init_amd,
1da177e4 LT	343	.c_size_cache = amd_size_cache,
	344	};
	345
	346	int __init amd_init_cpu(void)
	347	{
	348	cpu_devs[X86_VENDOR_AMD] = &amd_cpu_dev;
	349	return 0;
	350	}
03ae5768 TP	351
03ae5768 TP	352	cpu_vendor_dev_register(X86_VENDOR_AMD, &amd_cpu_dev);