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x86, cpu: AMD errata checking framework
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CommitLineData
1da177e4
LT
1#include <linux/init.h>
2#include <linux/bitops.h>
3#include <linux/mm.h>
8d71a2ea 4
8bdbd962 5#include <linux/io.h>
1da177e4 6#include <asm/processor.h>
d3f7eae1 7#include <asm/apic.h>
1f442d70 8#include <asm/cpu.h>
42937e81 9#include <asm/pci-direct.h>
1da177e4 10
8d71a2ea
YL
11#ifdef CONFIG_X86_64
12# include <asm/numa_64.h>
13# include <asm/mmconfig.h>
14# include <asm/cacheflush.h>
15#endif
16
1da177e4
LT
17#include "cpu.h"
18
6c62aa4a 19#ifdef CONFIG_X86_32
1da177e4
LT
20/*
21 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
22 * misexecution of code under Linux. Owners of such processors should
23 * contact AMD for precise details and a CPU swap.
24 *
25 * See http://www.multimania.com/poulot/k6bug.html
26 * http://www.amd.com/K6/k6docs/revgd.html
27 *
28 * The following test is erm.. interesting. AMD neglected to up
29 * the chip setting when fixing the bug but they also tweaked some
30 * performance at the same time..
31 */
fb87a298 32
1da177e4
LT
33extern void vide(void);
34__asm__(".align 4\nvide: ret");
35
11fdd252
YL
36static void __cpuinit init_amd_k5(struct cpuinfo_x86 *c)
37{
38/*
39 * General Systems BIOSen alias the cpu frequency registers
40 * of the Elan at 0x000df000. Unfortuantly, one of the Linux
41 * drivers subsequently pokes it, and changes the CPU speed.
42 * Workaround : Remove the unneeded alias.
43 */
44#define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
45#define CBAR_ENB (0x80000000)
46#define CBAR_KEY (0X000000CB)
47 if (c->x86_model == 9 || c->x86_model == 10) {
8bdbd962
AC
48 if (inl(CBAR) & CBAR_ENB)
49 outl(0 | CBAR_KEY, CBAR);
11fdd252
YL
50 }
51}
52
53
54static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c)
55{
56 u32 l, h;
57 int mbytes = num_physpages >> (20-PAGE_SHIFT);
58
59 if (c->x86_model < 6) {
60 /* Based on AMD doc 20734R - June 2000 */
61 if (c->x86_model == 0) {
62 clear_cpu_cap(c, X86_FEATURE_APIC);
63 set_cpu_cap(c, X86_FEATURE_PGE);
64 }
65 return;
66 }
67
68 if (c->x86_model == 6 && c->x86_mask == 1) {
69 const int K6_BUG_LOOP = 1000000;
70 int n;
71 void (*f_vide)(void);
72 unsigned long d, d2;
73
74 printk(KERN_INFO "AMD K6 stepping B detected - ");
75
76 /*
77 * It looks like AMD fixed the 2.6.2 bug and improved indirect
78 * calls at the same time.
79 */
80
81 n = K6_BUG_LOOP;
82 f_vide = vide;
83 rdtscl(d);
84 while (n--)
85 f_vide();
86 rdtscl(d2);
87 d = d2-d;
88
89 if (d > 20*K6_BUG_LOOP)
8bdbd962
AC
90 printk(KERN_CONT
91 "system stability may be impaired when more than 32 MB are used.\n");
11fdd252 92 else
8bdbd962 93 printk(KERN_CONT "probably OK (after B9730xxxx).\n");
11fdd252
YL
94 printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
95 }
96
97 /* K6 with old style WHCR */
98 if (c->x86_model < 8 ||
99 (c->x86_model == 8 && c->x86_mask < 8)) {
100 /* We can only write allocate on the low 508Mb */
101 if (mbytes > 508)
102 mbytes = 508;
103
104 rdmsr(MSR_K6_WHCR, l, h);
105 if ((l&0x0000FFFF) == 0) {
106 unsigned long flags;
107 l = (1<<0)|((mbytes/4)<<1);
108 local_irq_save(flags);
109 wbinvd();
110 wrmsr(MSR_K6_WHCR, l, h);
111 local_irq_restore(flags);
112 printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
113 mbytes);
114 }
115 return;
116 }
117
118 if ((c->x86_model == 8 && c->x86_mask > 7) ||
119 c->x86_model == 9 || c->x86_model == 13) {
120 /* The more serious chips .. */
121
122 if (mbytes > 4092)
123 mbytes = 4092;
124
125 rdmsr(MSR_K6_WHCR, l, h);
126 if ((l&0xFFFF0000) == 0) {
127 unsigned long flags;
128 l = ((mbytes>>2)<<22)|(1<<16);
129 local_irq_save(flags);
130 wbinvd();
131 wrmsr(MSR_K6_WHCR, l, h);
132 local_irq_restore(flags);
133 printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
134 mbytes);
135 }
136
137 return;
138 }
139
140 if (c->x86_model == 10) {
141 /* AMD Geode LX is model 10 */
142 /* placeholder for any needed mods */
143 return;
144 }
145}
146
1f442d70
YL
147static void __cpuinit amd_k7_smp_check(struct cpuinfo_x86 *c)
148{
149#ifdef CONFIG_SMP
150 /* calling is from identify_secondary_cpu() ? */
151 if (c->cpu_index == boot_cpu_id)
152 return;
153
154 /*
155 * Certain Athlons might work (for various values of 'work') in SMP
156 * but they are not certified as MP capable.
157 */
158 /* Athlon 660/661 is valid. */
159 if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
160 (c->x86_mask == 1)))
161 goto valid_k7;
162
163 /* Duron 670 is valid */
164 if ((c->x86_model == 7) && (c->x86_mask == 0))
165 goto valid_k7;
166
167 /*
168 * Athlon 662, Duron 671, and Athlon >model 7 have capability
169 * bit. It's worth noting that the A5 stepping (662) of some
170 * Athlon XP's have the MP bit set.
171 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
172 * more.
173 */
174 if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
175 ((c->x86_model == 7) && (c->x86_mask >= 1)) ||
176 (c->x86_model > 7))
177 if (cpu_has_mp)
178 goto valid_k7;
179
180 /* If we get here, not a certified SMP capable AMD system. */
181
182 /*
183 * Don't taint if we are running SMP kernel on a single non-MP
184 * approved Athlon
185 */
186 WARN_ONCE(1, "WARNING: This combination of AMD"
7da8b6dd 187 " processors is not suitable for SMP.\n");
1f442d70
YL
188 if (!test_taint(TAINT_UNSAFE_SMP))
189 add_taint(TAINT_UNSAFE_SMP);
190
191valid_k7:
192 ;
193#endif
194}
195
11fdd252
YL
196static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c)
197{
198 u32 l, h;
199
200 /*
201 * Bit 15 of Athlon specific MSR 15, needs to be 0
202 * to enable SSE on Palomino/Morgan/Barton CPU's.
203 * If the BIOS didn't enable it already, enable it here.
204 */
205 if (c->x86_model >= 6 && c->x86_model <= 10) {
206 if (!cpu_has(c, X86_FEATURE_XMM)) {
207 printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
208 rdmsr(MSR_K7_HWCR, l, h);
209 l &= ~0x00008000;
210 wrmsr(MSR_K7_HWCR, l, h);
211 set_cpu_cap(c, X86_FEATURE_XMM);
212 }
213 }
214
215 /*
216 * It's been determined by AMD that Athlons since model 8 stepping 1
217 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
218 * As per AMD technical note 27212 0.2
219 */
220 if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
221 rdmsr(MSR_K7_CLK_CTL, l, h);
222 if ((l & 0xfff00000) != 0x20000000) {
8bdbd962
AC
223 printk(KERN_INFO
224 "CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
225 l, ((l & 0x000fffff)|0x20000000));
11fdd252
YL
226 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
227 }
228 }
229
230 set_cpu_cap(c, X86_FEATURE_K7);
1f442d70
YL
231
232 amd_k7_smp_check(c);
11fdd252 233}
6c62aa4a
YL
234#endif
235
236#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
237static int __cpuinit nearby_node(int apicid)
238{
239 int i, node;
240
241 for (i = apicid - 1; i >= 0; i--) {
242 node = apicid_to_node[i];
243 if (node != NUMA_NO_NODE && node_online(node))
244 return node;
245 }
246 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
247 node = apicid_to_node[i];
248 if (node != NUMA_NO_NODE && node_online(node))
249 return node;
250 }
251 return first_node(node_online_map); /* Shouldn't happen */
252}
253#endif
11fdd252 254
4a376ec3
AH
255/*
256 * Fixup core topology information for AMD multi-node processors.
9d260ebc 257 * Assumption: Number of cores in each internal node is the same.
4a376ec3
AH
258 */
259#ifdef CONFIG_X86_HT
260static void __cpuinit amd_fixup_dcm(struct cpuinfo_x86 *c)
261{
9d260ebc
AH
262 unsigned long long value;
263 u32 nodes, cores_per_node;
4a376ec3
AH
264 int cpu = smp_processor_id();
265
9d260ebc
AH
266 if (!cpu_has(c, X86_FEATURE_NODEID_MSR))
267 return;
268
4a376ec3
AH
269 /* fixup topology information only once for a core */
270 if (cpu_has(c, X86_FEATURE_AMD_DCM))
271 return;
272
9d260ebc
AH
273 rdmsrl(MSR_FAM10H_NODE_ID, value);
274
275 nodes = ((value >> 3) & 7) + 1;
276 if (nodes == 1)
4a376ec3
AH
277 return;
278
279 set_cpu_cap(c, X86_FEATURE_AMD_DCM);
9d260ebc 280 cores_per_node = c->x86_max_cores / nodes;
4a376ec3 281
9d260ebc
AH
282 /* store NodeID, use llc_shared_map to store sibling info */
283 per_cpu(cpu_llc_id, cpu) = value & 7;
4a376ec3 284
9d260ebc
AH
285 /* fixup core id to be in range from 0 to (cores_per_node - 1) */
286 c->cpu_core_id = c->cpu_core_id % cores_per_node;
4a376ec3
AH
287}
288#endif
289
11fdd252
YL
290/*
291 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
292 * Assumes number of cores is a power of two.
293 */
294static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
295{
296#ifdef CONFIG_X86_HT
297 unsigned bits;
99bd0c0f 298 int cpu = smp_processor_id();
11fdd252
YL
299
300 bits = c->x86_coreid_bits;
11fdd252
YL
301 /* Low order bits define the core id (index of core in socket) */
302 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
303 /* Convert the initial APIC ID into the socket ID */
304 c->phys_proc_id = c->initial_apicid >> bits;
99bd0c0f
AH
305 /* use socket ID also for last level cache */
306 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
4a376ec3
AH
307 /* fixup topology information on multi-node processors */
308 if ((c->x86 == 0x10) && (c->x86_model == 9))
309 amd_fixup_dcm(c);
11fdd252
YL
310#endif
311}
312
6a812691
AH
313int amd_get_nb_id(int cpu)
314{
315 int id = 0;
316#ifdef CONFIG_SMP
317 id = per_cpu(cpu_llc_id, cpu);
318#endif
319 return id;
320}
321EXPORT_SYMBOL_GPL(amd_get_nb_id);
322
6c62aa4a
YL
323static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
324{
325#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
326 int cpu = smp_processor_id();
327 int node;
0d96b9ff 328 unsigned apicid = c->apicid;
6c62aa4a 329
4a376ec3 330 node = per_cpu(cpu_llc_id, cpu);
6c62aa4a 331
6c62aa4a
YL
332 if (apicid_to_node[apicid] != NUMA_NO_NODE)
333 node = apicid_to_node[apicid];
334 if (!node_online(node)) {
335 /* Two possibilities here:
336 - The CPU is missing memory and no node was created.
337 In that case try picking one from a nearby CPU
338 - The APIC IDs differ from the HyperTransport node IDs
339 which the K8 northbridge parsing fills in.
340 Assume they are all increased by a constant offset,
341 but in the same order as the HT nodeids.
342 If that doesn't result in a usable node fall back to the
343 path for the previous case. */
344
345 int ht_nodeid = c->initial_apicid;
346
347 if (ht_nodeid >= 0 &&
348 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
349 node = apicid_to_node[ht_nodeid];
350 /* Pick a nearby node */
351 if (!node_online(node))
352 node = nearby_node(apicid);
353 }
354 numa_set_node(cpu, node);
6c62aa4a
YL
355#endif
356}
357
11fdd252
YL
358static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
359{
360#ifdef CONFIG_X86_HT
361 unsigned bits, ecx;
362
363 /* Multi core CPU? */
364 if (c->extended_cpuid_level < 0x80000008)
365 return;
366
367 ecx = cpuid_ecx(0x80000008);
368
369 c->x86_max_cores = (ecx & 0xff) + 1;
370
371 /* CPU telling us the core id bits shift? */
372 bits = (ecx >> 12) & 0xF;
373
374 /* Otherwise recompute */
375 if (bits == 0) {
376 while ((1 << bits) < c->x86_max_cores)
377 bits++;
378 }
379
380 c->x86_coreid_bits = bits;
381#endif
382}
383
03ae5768 384static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
2b16a235 385{
11fdd252
YL
386 early_init_amd_mc(c);
387
40fb1715
VP
388 /*
389 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
390 * with P/T states and does not stop in deep C-states
391 */
392 if (c->x86_power & (1 << 8)) {
e3224234 393 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
40fb1715
VP
394 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
395 }
5fef55fd 396
6c62aa4a
YL
397#ifdef CONFIG_X86_64
398 set_cpu_cap(c, X86_FEATURE_SYSCALL32);
399#else
5fef55fd 400 /* Set MTRR capability flag if appropriate */
6c62aa4a
YL
401 if (c->x86 == 5)
402 if (c->x86_model == 13 || c->x86_model == 9 ||
403 (c->x86_model == 8 && c->x86_mask >= 8))
404 set_cpu_cap(c, X86_FEATURE_K6_MTRR);
405#endif
42937e81
AH
406#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
407 /* check CPU config space for extended APIC ID */
2cb07860 408 if (cpu_has_apic && c->x86 >= 0xf) {
42937e81
AH
409 unsigned int val;
410 val = read_pci_config(0, 24, 0, 0x68);
411 if ((val & ((1 << 17) | (1 << 18))) == ((1 << 17) | (1 << 18)))
412 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
413 }
414#endif
2b16a235
AK
415}
416
b4af3f7c 417static void __cpuinit init_amd(struct cpuinfo_x86 *c)
1da177e4 418{
7d318d77 419#ifdef CONFIG_SMP
3c92c2ba 420 unsigned long long value;
7d318d77 421
fb87a298
PC
422 /*
423 * Disable TLB flush filter by setting HWCR.FFDIS on K8
7d318d77
AK
424 * bit 6 of msr C001_0015
425 *
426 * Errata 63 for SH-B3 steppings
427 * Errata 122 for all steppings (F+ have it disabled by default)
428 */
11fdd252 429 if (c->x86 == 0xf) {
7d318d77
AK
430 rdmsrl(MSR_K7_HWCR, value);
431 value |= 1 << 6;
432 wrmsrl(MSR_K7_HWCR, value);
433 }
434#endif
435
2b16a235
AK
436 early_init_amd(c);
437
fb87a298
PC
438 /*
439 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
16282a8e 440 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
fb87a298 441 */
16282a8e 442 clear_cpu_cap(c, 0*32+31);
fb87a298 443
6c62aa4a
YL
444#ifdef CONFIG_X86_64
445 /* On C+ stepping K8 rep microcode works well for copy/memset */
446 if (c->x86 == 0xf) {
447 u32 level;
448
449 level = cpuid_eax(1);
8bdbd962 450 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
6c62aa4a 451 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
fbd8b181
KW
452
453 /*
454 * Some BIOSes incorrectly force this feature, but only K8
455 * revision D (model = 0x14) and later actually support it.
6b0f43dd 456 * (AMD Erratum #110, docId: 25759).
fbd8b181 457 */
6b0f43dd
BP
458 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
459 u64 val;
460
fbd8b181 461 clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
6b0f43dd
BP
462 if (!rdmsrl_amd_safe(0xc001100d, &val)) {
463 val &= ~(1ULL << 32);
464 wrmsrl_amd_safe(0xc001100d, val);
465 }
466 }
467
6c62aa4a 468 }
12d8a961 469 if (c->x86 >= 0x10)
6c62aa4a 470 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
0d96b9ff
YL
471
472 /* get apicid instead of initial apic id from cpuid */
473 c->apicid = hard_smp_processor_id();
6c62aa4a
YL
474#else
475
476 /*
477 * FIXME: We should handle the K5 here. Set up the write
478 * range and also turn on MSR 83 bits 4 and 31 (write alloc,
479 * no bus pipeline)
480 */
481
fb87a298
PC
482 switch (c->x86) {
483 case 4:
11fdd252
YL
484 init_amd_k5(c);
485 break;
fb87a298 486 case 5:
11fdd252 487 init_amd_k6(c);
1da177e4 488 break;
11fdd252
YL
489 case 6: /* An Athlon/Duron */
490 init_amd_k7(c);
1da177e4
LT
491 break;
492 }
11fdd252
YL
493
494 /* K6s reports MCEs but don't actually have all the MSRs */
495 if (c->x86 < 6)
496 clear_cpu_cap(c, X86_FEATURE_MCE);
6c62aa4a 497#endif
11fdd252 498
6c62aa4a 499 /* Enable workaround for FXSAVE leak */
18bd057b 500 if (c->x86 >= 6)
16282a8e 501 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
1da177e4 502
11fdd252
YL
503 if (!c->x86_model_id[0]) {
504 switch (c->x86) {
505 case 0xf:
506 /* Should distinguish Models here, but this is only
507 a fallback anyways. */
508 strcpy(c->x86_model_id, "Hammer");
509 break;
510 }
511 }
3dd9d514 512
27c13ece 513 cpu_detect_cache_sizes(c);
3dd9d514 514
11fdd252 515 /* Multi core CPU? */
6c62aa4a 516 if (c->extended_cpuid_level >= 0x80000008) {
11fdd252 517 amd_detect_cmp(c);
6c62aa4a
YL
518 srat_detect_node(c);
519 }
faee9a5d 520
6c62aa4a 521#ifdef CONFIG_X86_32
11fdd252 522 detect_ht(c);
6c62aa4a 523#endif
39b3a791 524
11fdd252
YL
525 if (c->extended_cpuid_level >= 0x80000006) {
526 if ((c->x86 >= 0x0f) && (cpuid_edx(0x80000006) & 0xf000))
67cddd94
AK
527 num_cache_leaves = 4;
528 else
529 num_cache_leaves = 3;
530 }
3556ddfa 531
12d8a961 532 if (c->x86 >= 0xf)
11fdd252 533 set_cpu_cap(c, X86_FEATURE_K8);
de421863 534
11fdd252
YL
535 if (cpu_has_xmm2) {
536 /* MFENCE stops RDTSC speculation */
16282a8e 537 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
11fdd252 538 }
6c62aa4a
YL
539
540#ifdef CONFIG_X86_64
541 if (c->x86 == 0x10) {
542 /* do this for boot cpu */
543 if (c == &boot_cpu_data)
544 check_enable_amd_mmconf_dmi();
545
546 fam10h_check_enable_mmcfg();
547 }
548
12d8a961 549 if (c == &boot_cpu_data && c->x86 >= 0xf) {
6c62aa4a
YL
550 unsigned long long tseg;
551
552 /*
553 * Split up direct mapping around the TSEG SMM area.
554 * Don't do it for gbpages because there seems very little
555 * benefit in doing so.
556 */
557 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
8bdbd962
AC
558 printk(KERN_DEBUG "tseg: %010llx\n", tseg);
559 if ((tseg>>PMD_SHIFT) <
6c62aa4a 560 (max_low_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) ||
8bdbd962 561 ((tseg>>PMD_SHIFT) <
6c62aa4a 562 (max_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) &&
8bdbd962
AC
563 (tseg>>PMD_SHIFT) >= (1ULL<<(32 - PMD_SHIFT))))
564 set_memory_4k((unsigned long)__va(tseg), 1);
6c62aa4a
YL
565 }
566 }
567#endif
1da177e4
LT
568}
569
6c62aa4a 570#ifdef CONFIG_X86_32
8bdbd962
AC
571static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c,
572 unsigned int size)
1da177e4
LT
573{
574 /* AMD errata T13 (order #21922) */
575 if ((c->x86 == 6)) {
8bdbd962
AC
576 /* Duron Rev A0 */
577 if (c->x86_model == 3 && c->x86_mask == 0)
1da177e4 578 size = 64;
8bdbd962 579 /* Tbird rev A1/A2 */
1da177e4 580 if (c->x86_model == 4 &&
8bdbd962 581 (c->x86_mask == 0 || c->x86_mask == 1))
1da177e4
LT
582 size = 256;
583 }
584 return size;
585}
6c62aa4a 586#endif
1da177e4 587
02dde8b4 588static const struct cpu_dev __cpuinitconst amd_cpu_dev = {
1da177e4 589 .c_vendor = "AMD",
fb87a298 590 .c_ident = { "AuthenticAMD" },
6c62aa4a 591#ifdef CONFIG_X86_32
1da177e4
LT
592 .c_models = {
593 { .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
594 {
595 [3] = "486 DX/2",
596 [7] = "486 DX/2-WB",
fb87a298
PC
597 [8] = "486 DX/4",
598 [9] = "486 DX/4-WB",
1da177e4 599 [14] = "Am5x86-WT",
fb87a298 600 [15] = "Am5x86-WB"
1da177e4
LT
601 }
602 },
603 },
6c62aa4a
YL
604 .c_size_cache = amd_size_cache,
605#endif
03ae5768 606 .c_early_init = early_init_amd,
1da177e4 607 .c_init = init_amd,
10a434fc 608 .c_x86_vendor = X86_VENDOR_AMD,
1da177e4
LT
609};
610
10a434fc 611cpu_dev_register(amd_cpu_dev);
d78d671d
HR
612
613/*
614 * AMD errata checking
615 *
616 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
617 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
618 * have an OSVW id assigned, which it takes as first argument. Both take a
619 * variable number of family-specific model-stepping ranges created by
620 * AMD_MODEL_RANGE(). Each erratum also has to be declared as extern const
621 * int[] in arch/x86/include/asm/processor.h.
622 *
623 * Example:
624 *
625 * const int amd_erratum_319[] =
626 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
627 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
628 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
629 */
630
631bool cpu_has_amd_erratum(const int *erratum)
632{
633 struct cpuinfo_x86 *cpu = &current_cpu_data;
634 int osvw_id = *erratum++;
635 u32 range;
636 u32 ms;
637
638 /*
639 * If called early enough that current_cpu_data hasn't been initialized
640 * yet, fall back to boot_cpu_data.
641 */
642 if (cpu->x86 == 0)
643 cpu = &boot_cpu_data;
644
645 if (cpu->x86_vendor != X86_VENDOR_AMD)
646 return false;
647
648 if (osvw_id >= 0 && osvw_id < 65536 &&
649 cpu_has(cpu, X86_FEATURE_OSVW)) {
650 u64 osvw_len;
651
652 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
653 if (osvw_id < osvw_len) {
654 u64 osvw_bits;
655
656 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
657 osvw_bits);
658 return osvw_bits & (1ULL << (osvw_id & 0x3f));
659 }
660 }
661
662 /* OSVW unavailable or ID unknown, match family-model-stepping range */
663 ms = (cpu->x86_model << 8) | cpu->x86_mask;
664 while ((range = *erratum++))
665 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
666 (ms >= AMD_MODEL_RANGE_START(range)) &&
667 (ms <= AMD_MODEL_RANGE_END(range)))
668 return true;
669
670 return false;
671}