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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1353ebb4 | 2 | /* |
1353ebb4 JF |
3 | * Copyright (C) 1994 Linus Torvalds |
4 | * | |
5 | * Cyrix stuff, June 1998 by: | |
6 | * - Rafael R. Reilova (moved everything from head.S), | |
7 | * <rreilova@ececs.uc.edu> | |
8 | * - Channing Corn (tests & fixes), | |
9 | * - Andrew D. Balsa (code cleanup). | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/utsname.h> | |
61dc0f55 | 13 | #include <linux/cpu.h> |
caf7501a | 14 | #include <linux/module.h> |
a73ec77e TG |
15 | #include <linux/nospec.h> |
16 | #include <linux/prctl.h> | |
a74cfffb | 17 | #include <linux/sched/smt.h> |
da285121 | 18 | |
28a27752 | 19 | #include <asm/spec-ctrl.h> |
da285121 | 20 | #include <asm/cmdline.h> |
91eb1b79 | 21 | #include <asm/bugs.h> |
1353ebb4 | 22 | #include <asm/processor.h> |
7ebad705 | 23 | #include <asm/processor-flags.h> |
952f07ec | 24 | #include <asm/fpu/internal.h> |
1353ebb4 | 25 | #include <asm/msr.h> |
72c6d2db | 26 | #include <asm/vmx.h> |
1353ebb4 JF |
27 | #include <asm/paravirt.h> |
28 | #include <asm/alternative.h> | |
62a67e12 | 29 | #include <asm/pgtable.h> |
d1163651 | 30 | #include <asm/set_memory.h> |
c995efd5 | 31 | #include <asm/intel-family.h> |
17dbca11 | 32 | #include <asm/e820/api.h> |
6cb2b08f | 33 | #include <asm/hypervisor.h> |
1353ebb4 | 34 | |
ad3bc25a BP |
35 | #include "cpu.h" |
36 | ||
da285121 | 37 | static void __init spectre_v2_select_mitigation(void); |
24f7fc83 | 38 | static void __init ssb_select_mitigation(void); |
17dbca11 | 39 | static void __init l1tf_select_mitigation(void); |
da285121 | 40 | |
53c613fe JK |
41 | /* The base value of the SPEC_CTRL MSR that always has to be preserved. */ |
42 | u64 x86_spec_ctrl_base; | |
fa8ac498 | 43 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); |
53c613fe | 44 | static DEFINE_MUTEX(spec_ctrl_mutex); |
1b86883c | 45 | |
1115a859 KRW |
46 | /* |
47 | * The vendor and possibly platform specific bits which can be modified in | |
48 | * x86_spec_ctrl_base. | |
49 | */ | |
be6fcb54 | 50 | static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS; |
1115a859 | 51 | |
764f3c21 KRW |
52 | /* |
53 | * AMD specific MSR info for Speculative Store Bypass control. | |
9f65fb29 | 54 | * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). |
764f3c21 KRW |
55 | */ |
56 | u64 __ro_after_init x86_amd_ls_cfg_base; | |
9f65fb29 | 57 | u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; |
764f3c21 | 58 | |
aa77bfb3 | 59 | /* Control conditional STIBP in switch_to() */ |
fa1202ef | 60 | DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp); |
4c71a2b6 TG |
61 | /* Control conditional IBPB in switch_mm() */ |
62 | DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb); | |
63 | /* Control unconditional IBPB in switch_mm() */ | |
64 | DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb); | |
fa1202ef | 65 | |
04dcbdb8 TG |
66 | /* Control MDS CPU buffer clear before returning to user space */ |
67 | DEFINE_STATIC_KEY_FALSE(mds_user_clear); | |
650b68a0 | 68 | EXPORT_SYMBOL_GPL(mds_user_clear); |
07f07f55 TG |
69 | /* Control MDS CPU buffer clear before idling (halt, mwait) */ |
70 | DEFINE_STATIC_KEY_FALSE(mds_idle_clear); | |
71 | EXPORT_SYMBOL_GPL(mds_idle_clear); | |
04dcbdb8 | 72 | |
1353ebb4 JF |
73 | void __init check_bugs(void) |
74 | { | |
75 | identify_boot_cpu(); | |
55a36b65 | 76 | |
fee0aede TG |
77 | /* |
78 | * identify_boot_cpu() initialized SMT support information, let the | |
79 | * core code know. | |
80 | */ | |
b284909a | 81 | cpu_smt_check_topology(); |
fee0aede | 82 | |
62a67e12 BP |
83 | if (!IS_ENABLED(CONFIG_SMP)) { |
84 | pr_info("CPU: "); | |
85 | print_cpu_info(&boot_cpu_data); | |
86 | } | |
87 | ||
1b86883c KRW |
88 | /* |
89 | * Read the SPEC_CTRL MSR to account for reserved bits which may | |
764f3c21 KRW |
90 | * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD |
91 | * init code as it is not enumerated and depends on the family. | |
1b86883c | 92 | */ |
7eb8956a | 93 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
1b86883c KRW |
94 | rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
95 | ||
be6fcb54 TG |
96 | /* Allow STIBP in MSR_SPEC_CTRL if supported */ |
97 | if (boot_cpu_has(X86_FEATURE_STIBP)) | |
98 | x86_spec_ctrl_mask |= SPEC_CTRL_STIBP; | |
99 | ||
da285121 DW |
100 | /* Select the proper spectre mitigation before patching alternatives */ |
101 | spectre_v2_select_mitigation(); | |
102 | ||
24f7fc83 KRW |
103 | /* |
104 | * Select proper mitigation for any exposure to the Speculative Store | |
105 | * Bypass vulnerability. | |
106 | */ | |
107 | ssb_select_mitigation(); | |
108 | ||
17dbca11 AK |
109 | l1tf_select_mitigation(); |
110 | ||
62a67e12 | 111 | #ifdef CONFIG_X86_32 |
55a36b65 BP |
112 | /* |
113 | * Check whether we are able to run this kernel safely on SMP. | |
114 | * | |
115 | * - i386 is no longer supported. | |
116 | * - In order to run on anything without a TSC, we need to be | |
117 | * compiled for a i486. | |
118 | */ | |
119 | if (boot_cpu_data.x86 < 4) | |
120 | panic("Kernel requires i486+ for 'invlpg' and other features"); | |
121 | ||
bfe4bb15 MV |
122 | init_utsname()->machine[1] = |
123 | '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); | |
1353ebb4 | 124 | alternative_instructions(); |
304bceda | 125 | |
4d164092 | 126 | fpu__init_check_bugs(); |
62a67e12 BP |
127 | #else /* CONFIG_X86_64 */ |
128 | alternative_instructions(); | |
129 | ||
130 | /* | |
131 | * Make sure the first 2MB area is not mapped by huge pages | |
132 | * There are typically fixed size MTRRs in there and overlapping | |
133 | * MTRRs into large pages causes slow downs. | |
134 | * | |
135 | * Right now we don't do that with gbpages because there seems | |
136 | * very little benefit for that case. | |
137 | */ | |
138 | if (!direct_gbpages) | |
139 | set_memory_4k((unsigned long)__va(0), 1); | |
140 | #endif | |
1353ebb4 | 141 | } |
61dc0f55 | 142 | |
cc69b349 BP |
143 | void |
144 | x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) | |
5cf68754 | 145 | { |
be6fcb54 | 146 | u64 msrval, guestval, hostval = x86_spec_ctrl_base; |
cc69b349 | 147 | struct thread_info *ti = current_thread_info(); |
885f82bf | 148 | |
7eb8956a | 149 | /* Is MSR_SPEC_CTRL implemented ? */ |
cc69b349 | 150 | if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { |
be6fcb54 TG |
151 | /* |
152 | * Restrict guest_spec_ctrl to supported values. Clear the | |
153 | * modifiable bits in the host base value and or the | |
154 | * modifiable bits from the guest value. | |
155 | */ | |
156 | guestval = hostval & ~x86_spec_ctrl_mask; | |
157 | guestval |= guest_spec_ctrl & x86_spec_ctrl_mask; | |
158 | ||
cc69b349 | 159 | /* SSBD controlled in MSR_SPEC_CTRL */ |
612bc3b3 TL |
160 | if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || |
161 | static_cpu_has(X86_FEATURE_AMD_SSBD)) | |
be6fcb54 | 162 | hostval |= ssbd_tif_to_spec_ctrl(ti->flags); |
cc69b349 | 163 | |
5bfbe3ad TC |
164 | /* Conditional STIBP enabled? */ |
165 | if (static_branch_unlikely(&switch_to_cond_stibp)) | |
166 | hostval |= stibp_tif_to_spec_ctrl(ti->flags); | |
167 | ||
be6fcb54 TG |
168 | if (hostval != guestval) { |
169 | msrval = setguest ? guestval : hostval; | |
170 | wrmsrl(MSR_IA32_SPEC_CTRL, msrval); | |
cc69b349 BP |
171 | } |
172 | } | |
47c61b39 TG |
173 | |
174 | /* | |
175 | * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update | |
176 | * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported. | |
177 | */ | |
178 | if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) && | |
179 | !static_cpu_has(X86_FEATURE_VIRT_SSBD)) | |
180 | return; | |
181 | ||
182 | /* | |
183 | * If the host has SSBD mitigation enabled, force it in the host's | |
184 | * virtual MSR value. If its not permanently enabled, evaluate | |
185 | * current's TIF_SSBD thread flag. | |
186 | */ | |
187 | if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE)) | |
188 | hostval = SPEC_CTRL_SSBD; | |
189 | else | |
190 | hostval = ssbd_tif_to_spec_ctrl(ti->flags); | |
191 | ||
192 | /* Sanitize the guest value */ | |
193 | guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD; | |
194 | ||
195 | if (hostval != guestval) { | |
196 | unsigned long tif; | |
197 | ||
198 | tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) : | |
199 | ssbd_spec_ctrl_to_tif(hostval); | |
200 | ||
26c4d75b | 201 | speculation_ctrl_update(tif); |
47c61b39 | 202 | } |
5cf68754 | 203 | } |
cc69b349 | 204 | EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); |
5cf68754 | 205 | |
9f65fb29 | 206 | static void x86_amd_ssb_disable(void) |
764f3c21 | 207 | { |
9f65fb29 | 208 | u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; |
764f3c21 | 209 | |
11fb0683 TL |
210 | if (boot_cpu_has(X86_FEATURE_VIRT_SSBD)) |
211 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); | |
212 | else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) | |
764f3c21 KRW |
213 | wrmsrl(MSR_AMD64_LS_CFG, msrval); |
214 | } | |
215 | ||
15d6b7aa TG |
216 | #undef pr_fmt |
217 | #define pr_fmt(fmt) "Spectre V2 : " fmt | |
218 | ||
219 | static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = | |
220 | SPECTRE_V2_NONE; | |
221 | ||
fa1202ef TG |
222 | static enum spectre_v2_user_mitigation spectre_v2_user __ro_after_init = |
223 | SPECTRE_V2_USER_NONE; | |
224 | ||
e4f35891 | 225 | #ifdef CONFIG_RETPOLINE |
e383095c TG |
226 | static bool spectre_v2_bad_module; |
227 | ||
caf7501a AK |
228 | bool retpoline_module_ok(bool has_retpoline) |
229 | { | |
230 | if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) | |
231 | return true; | |
232 | ||
e698dcdf | 233 | pr_err("System may be vulnerable to spectre v2\n"); |
caf7501a AK |
234 | spectre_v2_bad_module = true; |
235 | return false; | |
236 | } | |
e383095c TG |
237 | |
238 | static inline const char *spectre_v2_module_string(void) | |
239 | { | |
240 | return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; | |
241 | } | |
242 | #else | |
243 | static inline const char *spectre_v2_module_string(void) { return ""; } | |
caf7501a | 244 | #endif |
da285121 | 245 | |
da285121 DW |
246 | static inline bool match_option(const char *arg, int arglen, const char *opt) |
247 | { | |
248 | int len = strlen(opt); | |
249 | ||
250 | return len == arglen && !strncmp(arg, opt, len); | |
251 | } | |
252 | ||
15d6b7aa TG |
253 | /* The kernel command line selection for spectre v2 */ |
254 | enum spectre_v2_mitigation_cmd { | |
255 | SPECTRE_V2_CMD_NONE, | |
256 | SPECTRE_V2_CMD_AUTO, | |
257 | SPECTRE_V2_CMD_FORCE, | |
258 | SPECTRE_V2_CMD_RETPOLINE, | |
259 | SPECTRE_V2_CMD_RETPOLINE_GENERIC, | |
260 | SPECTRE_V2_CMD_RETPOLINE_AMD, | |
261 | }; | |
262 | ||
fa1202ef TG |
263 | enum spectre_v2_user_cmd { |
264 | SPECTRE_V2_USER_CMD_NONE, | |
265 | SPECTRE_V2_USER_CMD_AUTO, | |
266 | SPECTRE_V2_USER_CMD_FORCE, | |
7cc765a6 | 267 | SPECTRE_V2_USER_CMD_PRCTL, |
55a97402 | 268 | SPECTRE_V2_USER_CMD_PRCTL_IBPB, |
6b3e64c2 | 269 | SPECTRE_V2_USER_CMD_SECCOMP, |
55a97402 | 270 | SPECTRE_V2_USER_CMD_SECCOMP_IBPB, |
fa1202ef TG |
271 | }; |
272 | ||
273 | static const char * const spectre_v2_user_strings[] = { | |
20c3a2c3 TL |
274 | [SPECTRE_V2_USER_NONE] = "User space: Vulnerable", |
275 | [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection", | |
276 | [SPECTRE_V2_USER_STRICT_PREFERRED] = "User space: Mitigation: STIBP always-on protection", | |
277 | [SPECTRE_V2_USER_PRCTL] = "User space: Mitigation: STIBP via prctl", | |
278 | [SPECTRE_V2_USER_SECCOMP] = "User space: Mitigation: STIBP via seccomp and prctl", | |
fa1202ef TG |
279 | }; |
280 | ||
281 | static const struct { | |
282 | const char *option; | |
283 | enum spectre_v2_user_cmd cmd; | |
284 | bool secure; | |
285 | } v2_user_options[] __initdata = { | |
55a97402 TG |
286 | { "auto", SPECTRE_V2_USER_CMD_AUTO, false }, |
287 | { "off", SPECTRE_V2_USER_CMD_NONE, false }, | |
288 | { "on", SPECTRE_V2_USER_CMD_FORCE, true }, | |
289 | { "prctl", SPECTRE_V2_USER_CMD_PRCTL, false }, | |
290 | { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB, false }, | |
291 | { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP, false }, | |
292 | { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB, false }, | |
fa1202ef TG |
293 | }; |
294 | ||
295 | static void __init spec_v2_user_print_cond(const char *reason, bool secure) | |
296 | { | |
297 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) | |
298 | pr_info("spectre_v2_user=%s forced on command line.\n", reason); | |
299 | } | |
300 | ||
301 | static enum spectre_v2_user_cmd __init | |
302 | spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd) | |
303 | { | |
304 | char arg[20]; | |
305 | int ret, i; | |
306 | ||
307 | switch (v2_cmd) { | |
308 | case SPECTRE_V2_CMD_NONE: | |
309 | return SPECTRE_V2_USER_CMD_NONE; | |
310 | case SPECTRE_V2_CMD_FORCE: | |
311 | return SPECTRE_V2_USER_CMD_FORCE; | |
312 | default: | |
313 | break; | |
314 | } | |
315 | ||
316 | ret = cmdline_find_option(boot_command_line, "spectre_v2_user", | |
317 | arg, sizeof(arg)); | |
318 | if (ret < 0) | |
319 | return SPECTRE_V2_USER_CMD_AUTO; | |
320 | ||
321 | for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) { | |
322 | if (match_option(arg, ret, v2_user_options[i].option)) { | |
323 | spec_v2_user_print_cond(v2_user_options[i].option, | |
324 | v2_user_options[i].secure); | |
325 | return v2_user_options[i].cmd; | |
326 | } | |
327 | } | |
328 | ||
329 | pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg); | |
330 | return SPECTRE_V2_USER_CMD_AUTO; | |
331 | } | |
332 | ||
333 | static void __init | |
334 | spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd) | |
335 | { | |
336 | enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE; | |
337 | bool smt_possible = IS_ENABLED(CONFIG_SMP); | |
55a97402 | 338 | enum spectre_v2_user_cmd cmd; |
fa1202ef TG |
339 | |
340 | if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP)) | |
341 | return; | |
342 | ||
343 | if (cpu_smt_control == CPU_SMT_FORCE_DISABLED || | |
344 | cpu_smt_control == CPU_SMT_NOT_SUPPORTED) | |
345 | smt_possible = false; | |
346 | ||
55a97402 TG |
347 | cmd = spectre_v2_parse_user_cmdline(v2_cmd); |
348 | switch (cmd) { | |
fa1202ef TG |
349 | case SPECTRE_V2_USER_CMD_NONE: |
350 | goto set_mode; | |
351 | case SPECTRE_V2_USER_CMD_FORCE: | |
352 | mode = SPECTRE_V2_USER_STRICT; | |
353 | break; | |
7cc765a6 | 354 | case SPECTRE_V2_USER_CMD_PRCTL: |
55a97402 | 355 | case SPECTRE_V2_USER_CMD_PRCTL_IBPB: |
7cc765a6 TG |
356 | mode = SPECTRE_V2_USER_PRCTL; |
357 | break; | |
6b3e64c2 TG |
358 | case SPECTRE_V2_USER_CMD_AUTO: |
359 | case SPECTRE_V2_USER_CMD_SECCOMP: | |
55a97402 | 360 | case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: |
6b3e64c2 TG |
361 | if (IS_ENABLED(CONFIG_SECCOMP)) |
362 | mode = SPECTRE_V2_USER_SECCOMP; | |
363 | else | |
364 | mode = SPECTRE_V2_USER_PRCTL; | |
365 | break; | |
fa1202ef TG |
366 | } |
367 | ||
20c3a2c3 TL |
368 | /* |
369 | * At this point, an STIBP mode other than "off" has been set. | |
370 | * If STIBP support is not being forced, check if STIBP always-on | |
371 | * is preferred. | |
372 | */ | |
373 | if (mode != SPECTRE_V2_USER_STRICT && | |
374 | boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON)) | |
375 | mode = SPECTRE_V2_USER_STRICT_PREFERRED; | |
376 | ||
fa1202ef TG |
377 | /* Initialize Indirect Branch Prediction Barrier */ |
378 | if (boot_cpu_has(X86_FEATURE_IBPB)) { | |
379 | setup_force_cpu_cap(X86_FEATURE_USE_IBPB); | |
4c71a2b6 | 380 | |
55a97402 TG |
381 | switch (cmd) { |
382 | case SPECTRE_V2_USER_CMD_FORCE: | |
383 | case SPECTRE_V2_USER_CMD_PRCTL_IBPB: | |
384 | case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: | |
4c71a2b6 TG |
385 | static_branch_enable(&switch_mm_always_ibpb); |
386 | break; | |
55a97402 TG |
387 | case SPECTRE_V2_USER_CMD_PRCTL: |
388 | case SPECTRE_V2_USER_CMD_AUTO: | |
389 | case SPECTRE_V2_USER_CMD_SECCOMP: | |
7cc765a6 TG |
390 | static_branch_enable(&switch_mm_cond_ibpb); |
391 | break; | |
4c71a2b6 TG |
392 | default: |
393 | break; | |
394 | } | |
395 | ||
396 | pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n", | |
55a97402 TG |
397 | static_key_enabled(&switch_mm_always_ibpb) ? |
398 | "always-on" : "conditional"); | |
fa1202ef TG |
399 | } |
400 | ||
aa77bfb3 | 401 | /* If enhanced IBRS is enabled no STIBP required */ |
fa1202ef TG |
402 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) |
403 | return; | |
404 | ||
7cc765a6 | 405 | /* |
aa77bfb3 | 406 | * If SMT is not possible or STIBP is not available clear the STIBP |
7cc765a6 TG |
407 | * mode. |
408 | */ | |
409 | if (!smt_possible || !boot_cpu_has(X86_FEATURE_STIBP)) | |
410 | mode = SPECTRE_V2_USER_NONE; | |
fa1202ef TG |
411 | set_mode: |
412 | spectre_v2_user = mode; | |
413 | /* Only print the STIBP mode when SMT possible */ | |
414 | if (smt_possible) | |
415 | pr_info("%s\n", spectre_v2_user_strings[mode]); | |
416 | } | |
417 | ||
8770709f | 418 | static const char * const spectre_v2_strings[] = { |
15d6b7aa TG |
419 | [SPECTRE_V2_NONE] = "Vulnerable", |
420 | [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", | |
421 | [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", | |
422 | [SPECTRE_V2_IBRS_ENHANCED] = "Mitigation: Enhanced IBRS", | |
423 | }; | |
424 | ||
9005c683 KA |
425 | static const struct { |
426 | const char *option; | |
427 | enum spectre_v2_mitigation_cmd cmd; | |
428 | bool secure; | |
30ba72a9 | 429 | } mitigation_options[] __initdata = { |
15d6b7aa TG |
430 | { "off", SPECTRE_V2_CMD_NONE, false }, |
431 | { "on", SPECTRE_V2_CMD_FORCE, true }, | |
432 | { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, | |
433 | { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false }, | |
434 | { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, | |
435 | { "auto", SPECTRE_V2_CMD_AUTO, false }, | |
9005c683 KA |
436 | }; |
437 | ||
495d470e | 438 | static void __init spec_v2_print_cond(const char *reason, bool secure) |
15d6b7aa | 439 | { |
495d470e | 440 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) |
15d6b7aa TG |
441 | pr_info("%s selected on command line.\n", reason); |
442 | } | |
443 | ||
da285121 DW |
444 | static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) |
445 | { | |
15d6b7aa | 446 | enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; |
da285121 | 447 | char arg[20]; |
9005c683 | 448 | int ret, i; |
9005c683 KA |
449 | |
450 | if (cmdline_find_option_bool(boot_command_line, "nospectre_v2")) | |
451 | return SPECTRE_V2_CMD_NONE; | |
9005c683 | 452 | |
24848509 TC |
453 | ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); |
454 | if (ret < 0) | |
455 | return SPECTRE_V2_CMD_AUTO; | |
456 | ||
457 | for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { | |
458 | if (!match_option(arg, ret, mitigation_options[i].option)) | |
459 | continue; | |
460 | cmd = mitigation_options[i].cmd; | |
461 | break; | |
462 | } | |
463 | ||
464 | if (i >= ARRAY_SIZE(mitigation_options)) { | |
465 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
466 | return SPECTRE_V2_CMD_AUTO; | |
da285121 DW |
467 | } |
468 | ||
9005c683 KA |
469 | if ((cmd == SPECTRE_V2_CMD_RETPOLINE || |
470 | cmd == SPECTRE_V2_CMD_RETPOLINE_AMD || | |
471 | cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) && | |
472 | !IS_ENABLED(CONFIG_RETPOLINE)) { | |
21e433bd | 473 | pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option); |
da285121 | 474 | return SPECTRE_V2_CMD_AUTO; |
9005c683 KA |
475 | } |
476 | ||
477 | if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD && | |
1a576b23 | 478 | boot_cpu_data.x86_vendor != X86_VENDOR_HYGON && |
9005c683 KA |
479 | boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { |
480 | pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n"); | |
481 | return SPECTRE_V2_CMD_AUTO; | |
482 | } | |
483 | ||
495d470e TG |
484 | spec_v2_print_cond(mitigation_options[i].option, |
485 | mitigation_options[i].secure); | |
9005c683 | 486 | return cmd; |
da285121 DW |
487 | } |
488 | ||
489 | static void __init spectre_v2_select_mitigation(void) | |
490 | { | |
491 | enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); | |
492 | enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; | |
493 | ||
494 | /* | |
495 | * If the CPU is not affected and the command line mode is NONE or AUTO | |
496 | * then nothing to do. | |
497 | */ | |
498 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && | |
499 | (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) | |
500 | return; | |
501 | ||
502 | switch (cmd) { | |
503 | case SPECTRE_V2_CMD_NONE: | |
504 | return; | |
505 | ||
506 | case SPECTRE_V2_CMD_FORCE: | |
da285121 | 507 | case SPECTRE_V2_CMD_AUTO: |
706d5168 SP |
508 | if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { |
509 | mode = SPECTRE_V2_IBRS_ENHANCED; | |
510 | /* Force it so VMEXIT will restore correctly */ | |
511 | x86_spec_ctrl_base |= SPEC_CTRL_IBRS; | |
512 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); | |
513 | goto specv2_set_mode; | |
514 | } | |
9471eee9 DL |
515 | if (IS_ENABLED(CONFIG_RETPOLINE)) |
516 | goto retpoline_auto; | |
517 | break; | |
da285121 DW |
518 | case SPECTRE_V2_CMD_RETPOLINE_AMD: |
519 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
520 | goto retpoline_amd; | |
521 | break; | |
522 | case SPECTRE_V2_CMD_RETPOLINE_GENERIC: | |
523 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
524 | goto retpoline_generic; | |
525 | break; | |
526 | case SPECTRE_V2_CMD_RETPOLINE: | |
527 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
528 | goto retpoline_auto; | |
529 | break; | |
530 | } | |
21e433bd | 531 | pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!"); |
da285121 DW |
532 | return; |
533 | ||
534 | retpoline_auto: | |
1a576b23 PW |
535 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || |
536 | boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) { | |
da285121 DW |
537 | retpoline_amd: |
538 | if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { | |
21e433bd | 539 | pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n"); |
da285121 DW |
540 | goto retpoline_generic; |
541 | } | |
ef014aae | 542 | mode = SPECTRE_V2_RETPOLINE_AMD; |
da285121 DW |
543 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD); |
544 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
545 | } else { | |
546 | retpoline_generic: | |
ef014aae | 547 | mode = SPECTRE_V2_RETPOLINE_GENERIC; |
da285121 DW |
548 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); |
549 | } | |
550 | ||
706d5168 | 551 | specv2_set_mode: |
da285121 DW |
552 | spectre_v2_enabled = mode; |
553 | pr_info("%s\n", spectre_v2_strings[mode]); | |
c995efd5 DW |
554 | |
555 | /* | |
fdf82a78 JK |
556 | * If spectre v2 protection has been enabled, unconditionally fill |
557 | * RSB during a context switch; this protects against two independent | |
558 | * issues: | |
c995efd5 | 559 | * |
fdf82a78 JK |
560 | * - RSB underflow (and switch to BTB) on Skylake+ |
561 | * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs | |
c995efd5 | 562 | */ |
fdf82a78 JK |
563 | setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); |
564 | pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n"); | |
20ffa1ca | 565 | |
dd84441a DW |
566 | /* |
567 | * Retpoline means the kernel is safe because it has no indirect | |
706d5168 SP |
568 | * branches. Enhanced IBRS protects firmware too, so, enable restricted |
569 | * speculation around firmware calls only when Enhanced IBRS isn't | |
570 | * supported. | |
571 | * | |
572 | * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because | |
573 | * the user might select retpoline on the kernel command line and if | |
574 | * the CPU supports Enhanced IBRS, kernel might un-intentionally not | |
575 | * enable IBRS around firmware calls. | |
dd84441a | 576 | */ |
706d5168 | 577 | if (boot_cpu_has(X86_FEATURE_IBRS) && mode != SPECTRE_V2_IBRS_ENHANCED) { |
dd84441a DW |
578 | setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); |
579 | pr_info("Enabling Restricted Speculation for firmware calls\n"); | |
580 | } | |
53c613fe | 581 | |
fa1202ef TG |
582 | /* Set up IBPB and STIBP depending on the general spectre V2 command */ |
583 | spectre_v2_user_select_mitigation(cmd); | |
584 | ||
53c613fe JK |
585 | /* Enable STIBP if appropriate */ |
586 | arch_smt_update(); | |
da285121 DW |
587 | } |
588 | ||
6893a959 | 589 | static void update_stibp_msr(void * __unused) |
15d6b7aa | 590 | { |
6893a959 | 591 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
15d6b7aa TG |
592 | } |
593 | ||
6893a959 TG |
594 | /* Update x86_spec_ctrl_base in case SMT state changed. */ |
595 | static void update_stibp_strict(void) | |
15d6b7aa | 596 | { |
6893a959 TG |
597 | u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP; |
598 | ||
599 | if (sched_smt_active()) | |
600 | mask |= SPEC_CTRL_STIBP; | |
601 | ||
602 | if (mask == x86_spec_ctrl_base) | |
603 | return; | |
604 | ||
605 | pr_info("Update user space SMT mitigation: STIBP %s\n", | |
606 | mask & SPEC_CTRL_STIBP ? "always-on" : "off"); | |
607 | x86_spec_ctrl_base = mask; | |
608 | on_each_cpu(update_stibp_msr, NULL, 1); | |
15d6b7aa TG |
609 | } |
610 | ||
7cc765a6 TG |
611 | /* Update the static key controlling the evaluation of TIF_SPEC_IB */ |
612 | static void update_indir_branch_cond(void) | |
613 | { | |
614 | if (sched_smt_active()) | |
615 | static_branch_enable(&switch_to_cond_stibp); | |
616 | else | |
617 | static_branch_disable(&switch_to_cond_stibp); | |
618 | } | |
619 | ||
15d6b7aa TG |
620 | void arch_smt_update(void) |
621 | { | |
6893a959 TG |
622 | /* Enhanced IBRS implies STIBP. No update required. */ |
623 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) | |
15d6b7aa TG |
624 | return; |
625 | ||
626 | mutex_lock(&spec_ctrl_mutex); | |
627 | ||
6893a959 TG |
628 | switch (spectre_v2_user) { |
629 | case SPECTRE_V2_USER_NONE: | |
630 | break; | |
631 | case SPECTRE_V2_USER_STRICT: | |
20c3a2c3 | 632 | case SPECTRE_V2_USER_STRICT_PREFERRED: |
6893a959 TG |
633 | update_stibp_strict(); |
634 | break; | |
9137bb27 | 635 | case SPECTRE_V2_USER_PRCTL: |
6b3e64c2 | 636 | case SPECTRE_V2_USER_SECCOMP: |
7cc765a6 | 637 | update_indir_branch_cond(); |
9137bb27 | 638 | break; |
15d6b7aa | 639 | } |
6893a959 | 640 | |
15d6b7aa TG |
641 | mutex_unlock(&spec_ctrl_mutex); |
642 | } | |
643 | ||
24f7fc83 KRW |
644 | #undef pr_fmt |
645 | #define pr_fmt(fmt) "Speculative Store Bypass: " fmt | |
646 | ||
f9544b2b | 647 | static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE; |
24f7fc83 KRW |
648 | |
649 | /* The kernel command line selection */ | |
650 | enum ssb_mitigation_cmd { | |
651 | SPEC_STORE_BYPASS_CMD_NONE, | |
652 | SPEC_STORE_BYPASS_CMD_AUTO, | |
653 | SPEC_STORE_BYPASS_CMD_ON, | |
a73ec77e | 654 | SPEC_STORE_BYPASS_CMD_PRCTL, |
f21b53b2 | 655 | SPEC_STORE_BYPASS_CMD_SECCOMP, |
24f7fc83 KRW |
656 | }; |
657 | ||
8770709f | 658 | static const char * const ssb_strings[] = { |
24f7fc83 | 659 | [SPEC_STORE_BYPASS_NONE] = "Vulnerable", |
a73ec77e | 660 | [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", |
f21b53b2 KC |
661 | [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", |
662 | [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp", | |
24f7fc83 KRW |
663 | }; |
664 | ||
665 | static const struct { | |
666 | const char *option; | |
667 | enum ssb_mitigation_cmd cmd; | |
30ba72a9 | 668 | } ssb_mitigation_options[] __initdata = { |
f21b53b2 KC |
669 | { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ |
670 | { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ | |
671 | { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ | |
672 | { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */ | |
673 | { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */ | |
24f7fc83 KRW |
674 | }; |
675 | ||
676 | static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) | |
677 | { | |
678 | enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO; | |
679 | char arg[20]; | |
680 | int ret, i; | |
681 | ||
682 | if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) { | |
683 | return SPEC_STORE_BYPASS_CMD_NONE; | |
684 | } else { | |
685 | ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", | |
686 | arg, sizeof(arg)); | |
687 | if (ret < 0) | |
688 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
689 | ||
690 | for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { | |
691 | if (!match_option(arg, ret, ssb_mitigation_options[i].option)) | |
692 | continue; | |
693 | ||
694 | cmd = ssb_mitigation_options[i].cmd; | |
695 | break; | |
696 | } | |
697 | ||
698 | if (i >= ARRAY_SIZE(ssb_mitigation_options)) { | |
699 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
700 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
701 | } | |
702 | } | |
703 | ||
704 | return cmd; | |
705 | } | |
706 | ||
d66d8ff3 | 707 | static enum ssb_mitigation __init __ssb_select_mitigation(void) |
24f7fc83 KRW |
708 | { |
709 | enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; | |
710 | enum ssb_mitigation_cmd cmd; | |
711 | ||
9f65fb29 | 712 | if (!boot_cpu_has(X86_FEATURE_SSBD)) |
24f7fc83 KRW |
713 | return mode; |
714 | ||
715 | cmd = ssb_parse_cmdline(); | |
716 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && | |
717 | (cmd == SPEC_STORE_BYPASS_CMD_NONE || | |
718 | cmd == SPEC_STORE_BYPASS_CMD_AUTO)) | |
719 | return mode; | |
720 | ||
721 | switch (cmd) { | |
722 | case SPEC_STORE_BYPASS_CMD_AUTO: | |
f21b53b2 KC |
723 | case SPEC_STORE_BYPASS_CMD_SECCOMP: |
724 | /* | |
725 | * Choose prctl+seccomp as the default mode if seccomp is | |
726 | * enabled. | |
727 | */ | |
728 | if (IS_ENABLED(CONFIG_SECCOMP)) | |
729 | mode = SPEC_STORE_BYPASS_SECCOMP; | |
730 | else | |
731 | mode = SPEC_STORE_BYPASS_PRCTL; | |
a73ec77e | 732 | break; |
24f7fc83 KRW |
733 | case SPEC_STORE_BYPASS_CMD_ON: |
734 | mode = SPEC_STORE_BYPASS_DISABLE; | |
735 | break; | |
a73ec77e TG |
736 | case SPEC_STORE_BYPASS_CMD_PRCTL: |
737 | mode = SPEC_STORE_BYPASS_PRCTL; | |
738 | break; | |
24f7fc83 KRW |
739 | case SPEC_STORE_BYPASS_CMD_NONE: |
740 | break; | |
741 | } | |
742 | ||
77243971 KRW |
743 | /* |
744 | * We have three CPU feature flags that are in play here: | |
745 | * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. | |
9f65fb29 | 746 | * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass |
77243971 KRW |
747 | * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation |
748 | */ | |
a73ec77e | 749 | if (mode == SPEC_STORE_BYPASS_DISABLE) { |
24f7fc83 | 750 | setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); |
77243971 | 751 | /* |
6ac2f49e KRW |
752 | * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may |
753 | * use a completely different MSR and bit dependent on family. | |
77243971 | 754 | */ |
612bc3b3 TL |
755 | if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) && |
756 | !static_cpu_has(X86_FEATURE_AMD_SSBD)) { | |
108fab4b | 757 | x86_amd_ssb_disable(); |
612bc3b3 | 758 | } else { |
9f65fb29 | 759 | x86_spec_ctrl_base |= SPEC_CTRL_SSBD; |
be6fcb54 | 760 | x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; |
4b59bdb5 | 761 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
77243971 KRW |
762 | } |
763 | } | |
764 | ||
24f7fc83 KRW |
765 | return mode; |
766 | } | |
767 | ||
ffed645e | 768 | static void ssb_select_mitigation(void) |
24f7fc83 KRW |
769 | { |
770 | ssb_mode = __ssb_select_mitigation(); | |
771 | ||
772 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
773 | pr_info("%s\n", ssb_strings[ssb_mode]); | |
774 | } | |
775 | ||
da285121 | 776 | #undef pr_fmt |
f21b53b2 | 777 | #define pr_fmt(fmt) "Speculation prctl: " fmt |
da285121 | 778 | |
6d991ba5 | 779 | static void task_update_spec_tif(struct task_struct *tsk) |
a73ec77e | 780 | { |
6d991ba5 TG |
781 | /* Force the update of the real TIF bits */ |
782 | set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE); | |
e6da8bb6 TG |
783 | |
784 | /* | |
785 | * Immediately update the speculation control MSRs for the current | |
786 | * task, but for a non-current task delay setting the CPU | |
787 | * mitigation until it is scheduled next. | |
788 | * | |
789 | * This can only happen for SECCOMP mitigation. For PRCTL it's | |
790 | * always the current task. | |
791 | */ | |
6d991ba5 | 792 | if (tsk == current) |
e6da8bb6 TG |
793 | speculation_ctrl_update_current(); |
794 | } | |
795 | ||
796 | static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) | |
797 | { | |
f21b53b2 KC |
798 | if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && |
799 | ssb_mode != SPEC_STORE_BYPASS_SECCOMP) | |
a73ec77e TG |
800 | return -ENXIO; |
801 | ||
356e4bff TG |
802 | switch (ctrl) { |
803 | case PR_SPEC_ENABLE: | |
804 | /* If speculation is force disabled, enable is not allowed */ | |
805 | if (task_spec_ssb_force_disable(task)) | |
806 | return -EPERM; | |
807 | task_clear_spec_ssb_disable(task); | |
6d991ba5 | 808 | task_update_spec_tif(task); |
356e4bff TG |
809 | break; |
810 | case PR_SPEC_DISABLE: | |
811 | task_set_spec_ssb_disable(task); | |
6d991ba5 | 812 | task_update_spec_tif(task); |
356e4bff TG |
813 | break; |
814 | case PR_SPEC_FORCE_DISABLE: | |
815 | task_set_spec_ssb_disable(task); | |
816 | task_set_spec_ssb_force_disable(task); | |
6d991ba5 | 817 | task_update_spec_tif(task); |
356e4bff TG |
818 | break; |
819 | default: | |
820 | return -ERANGE; | |
821 | } | |
a73ec77e TG |
822 | return 0; |
823 | } | |
824 | ||
9137bb27 TG |
825 | static int ib_prctl_set(struct task_struct *task, unsigned long ctrl) |
826 | { | |
827 | switch (ctrl) { | |
828 | case PR_SPEC_ENABLE: | |
829 | if (spectre_v2_user == SPECTRE_V2_USER_NONE) | |
830 | return 0; | |
831 | /* | |
832 | * Indirect branch speculation is always disabled in strict | |
833 | * mode. | |
834 | */ | |
20c3a2c3 TL |
835 | if (spectre_v2_user == SPECTRE_V2_USER_STRICT || |
836 | spectre_v2_user == SPECTRE_V2_USER_STRICT_PREFERRED) | |
9137bb27 TG |
837 | return -EPERM; |
838 | task_clear_spec_ib_disable(task); | |
839 | task_update_spec_tif(task); | |
840 | break; | |
841 | case PR_SPEC_DISABLE: | |
842 | case PR_SPEC_FORCE_DISABLE: | |
843 | /* | |
844 | * Indirect branch speculation is always allowed when | |
845 | * mitigation is force disabled. | |
846 | */ | |
847 | if (spectre_v2_user == SPECTRE_V2_USER_NONE) | |
848 | return -EPERM; | |
20c3a2c3 TL |
849 | if (spectre_v2_user == SPECTRE_V2_USER_STRICT || |
850 | spectre_v2_user == SPECTRE_V2_USER_STRICT_PREFERRED) | |
9137bb27 TG |
851 | return 0; |
852 | task_set_spec_ib_disable(task); | |
853 | if (ctrl == PR_SPEC_FORCE_DISABLE) | |
854 | task_set_spec_ib_force_disable(task); | |
855 | task_update_spec_tif(task); | |
856 | break; | |
857 | default: | |
858 | return -ERANGE; | |
859 | } | |
860 | return 0; | |
861 | } | |
862 | ||
8bf37d8c TG |
863 | int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, |
864 | unsigned long ctrl) | |
865 | { | |
866 | switch (which) { | |
867 | case PR_SPEC_STORE_BYPASS: | |
868 | return ssb_prctl_set(task, ctrl); | |
9137bb27 TG |
869 | case PR_SPEC_INDIRECT_BRANCH: |
870 | return ib_prctl_set(task, ctrl); | |
8bf37d8c TG |
871 | default: |
872 | return -ENODEV; | |
873 | } | |
874 | } | |
875 | ||
876 | #ifdef CONFIG_SECCOMP | |
877 | void arch_seccomp_spec_mitigate(struct task_struct *task) | |
878 | { | |
f21b53b2 KC |
879 | if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) |
880 | ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
6b3e64c2 TG |
881 | if (spectre_v2_user == SPECTRE_V2_USER_SECCOMP) |
882 | ib_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
8bf37d8c TG |
883 | } |
884 | #endif | |
885 | ||
7bbf1373 | 886 | static int ssb_prctl_get(struct task_struct *task) |
a73ec77e TG |
887 | { |
888 | switch (ssb_mode) { | |
889 | case SPEC_STORE_BYPASS_DISABLE: | |
890 | return PR_SPEC_DISABLE; | |
f21b53b2 | 891 | case SPEC_STORE_BYPASS_SECCOMP: |
a73ec77e | 892 | case SPEC_STORE_BYPASS_PRCTL: |
356e4bff TG |
893 | if (task_spec_ssb_force_disable(task)) |
894 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
895 | if (task_spec_ssb_disable(task)) | |
a73ec77e TG |
896 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; |
897 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
898 | default: | |
899 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
900 | return PR_SPEC_ENABLE; | |
901 | return PR_SPEC_NOT_AFFECTED; | |
902 | } | |
903 | } | |
904 | ||
9137bb27 TG |
905 | static int ib_prctl_get(struct task_struct *task) |
906 | { | |
907 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
908 | return PR_SPEC_NOT_AFFECTED; | |
909 | ||
910 | switch (spectre_v2_user) { | |
911 | case SPECTRE_V2_USER_NONE: | |
912 | return PR_SPEC_ENABLE; | |
913 | case SPECTRE_V2_USER_PRCTL: | |
6b3e64c2 | 914 | case SPECTRE_V2_USER_SECCOMP: |
9137bb27 TG |
915 | if (task_spec_ib_force_disable(task)) |
916 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
917 | if (task_spec_ib_disable(task)) | |
918 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; | |
919 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
920 | case SPECTRE_V2_USER_STRICT: | |
20c3a2c3 | 921 | case SPECTRE_V2_USER_STRICT_PREFERRED: |
9137bb27 TG |
922 | return PR_SPEC_DISABLE; |
923 | default: | |
924 | return PR_SPEC_NOT_AFFECTED; | |
925 | } | |
926 | } | |
927 | ||
7bbf1373 | 928 | int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) |
a73ec77e TG |
929 | { |
930 | switch (which) { | |
931 | case PR_SPEC_STORE_BYPASS: | |
7bbf1373 | 932 | return ssb_prctl_get(task); |
9137bb27 TG |
933 | case PR_SPEC_INDIRECT_BRANCH: |
934 | return ib_prctl_get(task); | |
a73ec77e TG |
935 | default: |
936 | return -ENODEV; | |
937 | } | |
938 | } | |
939 | ||
77243971 KRW |
940 | void x86_spec_ctrl_setup_ap(void) |
941 | { | |
7eb8956a | 942 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
4b59bdb5 | 943 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
764f3c21 KRW |
944 | |
945 | if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) | |
9f65fb29 | 946 | x86_amd_ssb_disable(); |
77243971 KRW |
947 | } |
948 | ||
56563f53 KRW |
949 | #undef pr_fmt |
950 | #define pr_fmt(fmt) "L1TF: " fmt | |
72c6d2db | 951 | |
d90a7a0e JK |
952 | /* Default mitigation for L1TF-affected CPUs */ |
953 | enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH; | |
72c6d2db | 954 | #if IS_ENABLED(CONFIG_KVM_INTEL) |
d90a7a0e | 955 | EXPORT_SYMBOL_GPL(l1tf_mitigation); |
1eb46908 | 956 | #endif |
895ae47f | 957 | enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; |
72c6d2db | 958 | EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation); |
72c6d2db | 959 | |
cc51e542 AK |
960 | /* |
961 | * These CPUs all support 44bits physical address space internally in the | |
962 | * cache but CPUID can report a smaller number of physical address bits. | |
963 | * | |
964 | * The L1TF mitigation uses the top most address bit for the inversion of | |
965 | * non present PTEs. When the installed memory reaches into the top most | |
966 | * address bit due to memory holes, which has been observed on machines | |
967 | * which report 36bits physical address bits and have 32G RAM installed, | |
968 | * then the mitigation range check in l1tf_select_mitigation() triggers. | |
969 | * This is a false positive because the mitigation is still possible due to | |
970 | * the fact that the cache uses 44bit internally. Use the cache bits | |
971 | * instead of the reported physical bits and adjust them on the affected | |
972 | * machines to 44bit if the reported bits are less than 44. | |
973 | */ | |
974 | static void override_cache_bits(struct cpuinfo_x86 *c) | |
975 | { | |
976 | if (c->x86 != 6) | |
977 | return; | |
978 | ||
979 | switch (c->x86_model) { | |
980 | case INTEL_FAM6_NEHALEM: | |
981 | case INTEL_FAM6_WESTMERE: | |
982 | case INTEL_FAM6_SANDYBRIDGE: | |
983 | case INTEL_FAM6_IVYBRIDGE: | |
984 | case INTEL_FAM6_HASWELL_CORE: | |
985 | case INTEL_FAM6_HASWELL_ULT: | |
986 | case INTEL_FAM6_HASWELL_GT3E: | |
987 | case INTEL_FAM6_BROADWELL_CORE: | |
988 | case INTEL_FAM6_BROADWELL_GT3E: | |
989 | case INTEL_FAM6_SKYLAKE_MOBILE: | |
990 | case INTEL_FAM6_SKYLAKE_DESKTOP: | |
991 | case INTEL_FAM6_KABYLAKE_MOBILE: | |
992 | case INTEL_FAM6_KABYLAKE_DESKTOP: | |
993 | if (c->x86_cache_bits < 44) | |
994 | c->x86_cache_bits = 44; | |
995 | break; | |
996 | } | |
997 | } | |
998 | ||
56563f53 KRW |
999 | static void __init l1tf_select_mitigation(void) |
1000 | { | |
1001 | u64 half_pa; | |
1002 | ||
1003 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
1004 | return; | |
1005 | ||
cc51e542 AK |
1006 | override_cache_bits(&boot_cpu_data); |
1007 | ||
d90a7a0e JK |
1008 | switch (l1tf_mitigation) { |
1009 | case L1TF_MITIGATION_OFF: | |
1010 | case L1TF_MITIGATION_FLUSH_NOWARN: | |
1011 | case L1TF_MITIGATION_FLUSH: | |
1012 | break; | |
1013 | case L1TF_MITIGATION_FLUSH_NOSMT: | |
1014 | case L1TF_MITIGATION_FULL: | |
1015 | cpu_smt_disable(false); | |
1016 | break; | |
1017 | case L1TF_MITIGATION_FULL_FORCE: | |
1018 | cpu_smt_disable(true); | |
1019 | break; | |
1020 | } | |
1021 | ||
56563f53 KRW |
1022 | #if CONFIG_PGTABLE_LEVELS == 2 |
1023 | pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n"); | |
1024 | return; | |
1025 | #endif | |
1026 | ||
56563f53 | 1027 | half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT; |
5b5e4d62 MH |
1028 | if (l1tf_mitigation != L1TF_MITIGATION_OFF && |
1029 | e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) { | |
56563f53 | 1030 | pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n"); |
6a012288 VB |
1031 | pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n", |
1032 | half_pa); | |
1033 | pr_info("However, doing so will make a part of your RAM unusable.\n"); | |
1034 | pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html might help you decide.\n"); | |
56563f53 KRW |
1035 | return; |
1036 | } | |
1037 | ||
1038 | setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV); | |
1039 | } | |
d90a7a0e JK |
1040 | |
1041 | static int __init l1tf_cmdline(char *str) | |
1042 | { | |
1043 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
1044 | return 0; | |
1045 | ||
1046 | if (!str) | |
1047 | return -EINVAL; | |
1048 | ||
1049 | if (!strcmp(str, "off")) | |
1050 | l1tf_mitigation = L1TF_MITIGATION_OFF; | |
1051 | else if (!strcmp(str, "flush,nowarn")) | |
1052 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN; | |
1053 | else if (!strcmp(str, "flush")) | |
1054 | l1tf_mitigation = L1TF_MITIGATION_FLUSH; | |
1055 | else if (!strcmp(str, "flush,nosmt")) | |
1056 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; | |
1057 | else if (!strcmp(str, "full")) | |
1058 | l1tf_mitigation = L1TF_MITIGATION_FULL; | |
1059 | else if (!strcmp(str, "full,force")) | |
1060 | l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE; | |
1061 | ||
1062 | return 0; | |
1063 | } | |
1064 | early_param("l1tf", l1tf_cmdline); | |
1065 | ||
56563f53 KRW |
1066 | #undef pr_fmt |
1067 | ||
61dc0f55 | 1068 | #ifdef CONFIG_SYSFS |
d1059518 | 1069 | |
72c6d2db TG |
1070 | #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion" |
1071 | ||
1072 | #if IS_ENABLED(CONFIG_KVM_INTEL) | |
8770709f | 1073 | static const char * const l1tf_vmx_states[] = { |
a7b9020b TG |
1074 | [VMENTER_L1D_FLUSH_AUTO] = "auto", |
1075 | [VMENTER_L1D_FLUSH_NEVER] = "vulnerable", | |
1076 | [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes", | |
1077 | [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes", | |
1078 | [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled", | |
8e0b2b91 | 1079 | [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary" |
72c6d2db TG |
1080 | }; |
1081 | ||
1082 | static ssize_t l1tf_show_state(char *buf) | |
1083 | { | |
1084 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) | |
1085 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
1086 | ||
ea156d19 PB |
1087 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED || |
1088 | (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER && | |
130d6f94 | 1089 | sched_smt_active())) { |
ea156d19 PB |
1090 | return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG, |
1091 | l1tf_vmx_states[l1tf_vmx_mitigation]); | |
130d6f94 | 1092 | } |
ea156d19 PB |
1093 | |
1094 | return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG, | |
1095 | l1tf_vmx_states[l1tf_vmx_mitigation], | |
130d6f94 | 1096 | sched_smt_active() ? "vulnerable" : "disabled"); |
72c6d2db TG |
1097 | } |
1098 | #else | |
1099 | static ssize_t l1tf_show_state(char *buf) | |
1100 | { | |
1101 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
1102 | } | |
1103 | #endif | |
1104 | ||
a8f76ae4 TC |
1105 | static char *stibp_state(void) |
1106 | { | |
34bce7c9 TC |
1107 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) |
1108 | return ""; | |
1109 | ||
fa1202ef TG |
1110 | switch (spectre_v2_user) { |
1111 | case SPECTRE_V2_USER_NONE: | |
1112 | return ", STIBP: disabled"; | |
1113 | case SPECTRE_V2_USER_STRICT: | |
1114 | return ", STIBP: forced"; | |
20c3a2c3 TL |
1115 | case SPECTRE_V2_USER_STRICT_PREFERRED: |
1116 | return ", STIBP: always-on"; | |
9137bb27 | 1117 | case SPECTRE_V2_USER_PRCTL: |
6b3e64c2 | 1118 | case SPECTRE_V2_USER_SECCOMP: |
7cc765a6 TG |
1119 | if (static_key_enabled(&switch_to_cond_stibp)) |
1120 | return ", STIBP: conditional"; | |
fa1202ef TG |
1121 | } |
1122 | return ""; | |
a8f76ae4 TC |
1123 | } |
1124 | ||
1125 | static char *ibpb_state(void) | |
1126 | { | |
4c71a2b6 | 1127 | if (boot_cpu_has(X86_FEATURE_IBPB)) { |
7cc765a6 | 1128 | if (static_key_enabled(&switch_mm_always_ibpb)) |
4c71a2b6 | 1129 | return ", IBPB: always-on"; |
7cc765a6 TG |
1130 | if (static_key_enabled(&switch_mm_cond_ibpb)) |
1131 | return ", IBPB: conditional"; | |
1132 | return ", IBPB: disabled"; | |
4c71a2b6 TG |
1133 | } |
1134 | return ""; | |
a8f76ae4 TC |
1135 | } |
1136 | ||
7bb4d366 | 1137 | static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, |
ffed645e | 1138 | char *buf, unsigned int bug) |
61dc0f55 | 1139 | { |
d1059518 | 1140 | if (!boot_cpu_has_bug(bug)) |
61dc0f55 | 1141 | return sprintf(buf, "Not affected\n"); |
d1059518 KRW |
1142 | |
1143 | switch (bug) { | |
1144 | case X86_BUG_CPU_MELTDOWN: | |
1145 | if (boot_cpu_has(X86_FEATURE_PTI)) | |
1146 | return sprintf(buf, "Mitigation: PTI\n"); | |
1147 | ||
6cb2b08f JK |
1148 | if (hypervisor_is_type(X86_HYPER_XEN_PV)) |
1149 | return sprintf(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n"); | |
1150 | ||
d1059518 KRW |
1151 | break; |
1152 | ||
1153 | case X86_BUG_SPECTRE_V1: | |
1154 | return sprintf(buf, "Mitigation: __user pointer sanitization\n"); | |
1155 | ||
1156 | case X86_BUG_SPECTRE_V2: | |
b86bda04 | 1157 | return sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], |
a8f76ae4 | 1158 | ibpb_state(), |
d1059518 | 1159 | boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", |
a8f76ae4 | 1160 | stibp_state(), |
bb4b3b77 | 1161 | boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "", |
d1059518 KRW |
1162 | spectre_v2_module_string()); |
1163 | ||
24f7fc83 KRW |
1164 | case X86_BUG_SPEC_STORE_BYPASS: |
1165 | return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); | |
1166 | ||
17dbca11 AK |
1167 | case X86_BUG_L1TF: |
1168 | if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV)) | |
72c6d2db | 1169 | return l1tf_show_state(buf); |
17dbca11 | 1170 | break; |
d1059518 KRW |
1171 | default: |
1172 | break; | |
1173 | } | |
1174 | ||
61dc0f55 TG |
1175 | return sprintf(buf, "Vulnerable\n"); |
1176 | } | |
1177 | ||
d1059518 KRW |
1178 | ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) |
1179 | { | |
1180 | return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); | |
1181 | } | |
1182 | ||
21e433bd | 1183 | ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 1184 | { |
d1059518 | 1185 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); |
61dc0f55 TG |
1186 | } |
1187 | ||
21e433bd | 1188 | ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 1189 | { |
d1059518 | 1190 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); |
61dc0f55 | 1191 | } |
c456442c KRW |
1192 | |
1193 | ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) | |
1194 | { | |
1195 | return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); | |
1196 | } | |
17dbca11 AK |
1197 | |
1198 | ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf) | |
1199 | { | |
1200 | return cpu_show_common(dev, attr, buf, X86_BUG_L1TF); | |
1201 | } | |
61dc0f55 | 1202 | #endif |