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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1353ebb4 | 2 | /* |
1353ebb4 JF |
3 | * Copyright (C) 1994 Linus Torvalds |
4 | * | |
5 | * Cyrix stuff, June 1998 by: | |
6 | * - Rafael R. Reilova (moved everything from head.S), | |
7 | * <rreilova@ececs.uc.edu> | |
8 | * - Channing Corn (tests & fixes), | |
9 | * - Andrew D. Balsa (code cleanup). | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/utsname.h> | |
61dc0f55 | 13 | #include <linux/cpu.h> |
caf7501a | 14 | #include <linux/module.h> |
a73ec77e TG |
15 | #include <linux/nospec.h> |
16 | #include <linux/prctl.h> | |
a74cfffb | 17 | #include <linux/sched/smt.h> |
da285121 | 18 | |
28a27752 | 19 | #include <asm/spec-ctrl.h> |
da285121 | 20 | #include <asm/cmdline.h> |
91eb1b79 | 21 | #include <asm/bugs.h> |
1353ebb4 | 22 | #include <asm/processor.h> |
7ebad705 | 23 | #include <asm/processor-flags.h> |
952f07ec | 24 | #include <asm/fpu/internal.h> |
1353ebb4 | 25 | #include <asm/msr.h> |
72c6d2db | 26 | #include <asm/vmx.h> |
1353ebb4 JF |
27 | #include <asm/paravirt.h> |
28 | #include <asm/alternative.h> | |
62a67e12 | 29 | #include <asm/pgtable.h> |
d1163651 | 30 | #include <asm/set_memory.h> |
c995efd5 | 31 | #include <asm/intel-family.h> |
17dbca11 | 32 | #include <asm/e820/api.h> |
6cb2b08f | 33 | #include <asm/hypervisor.h> |
1353ebb4 | 34 | |
da285121 | 35 | static void __init spectre_v2_select_mitigation(void); |
24f7fc83 | 36 | static void __init ssb_select_mitigation(void); |
17dbca11 | 37 | static void __init l1tf_select_mitigation(void); |
da285121 | 38 | |
53c613fe JK |
39 | /* The base value of the SPEC_CTRL MSR that always has to be preserved. */ |
40 | u64 x86_spec_ctrl_base; | |
fa8ac498 | 41 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); |
53c613fe | 42 | static DEFINE_MUTEX(spec_ctrl_mutex); |
1b86883c | 43 | |
1115a859 KRW |
44 | /* |
45 | * The vendor and possibly platform specific bits which can be modified in | |
46 | * x86_spec_ctrl_base. | |
47 | */ | |
be6fcb54 | 48 | static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS; |
1115a859 | 49 | |
764f3c21 KRW |
50 | /* |
51 | * AMD specific MSR info for Speculative Store Bypass control. | |
9f65fb29 | 52 | * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). |
764f3c21 KRW |
53 | */ |
54 | u64 __ro_after_init x86_amd_ls_cfg_base; | |
9f65fb29 | 55 | u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; |
764f3c21 | 56 | |
fa1202ef TG |
57 | /* Control conditional STIPB in switch_to() */ |
58 | DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp); | |
59 | ||
1353ebb4 JF |
60 | void __init check_bugs(void) |
61 | { | |
62 | identify_boot_cpu(); | |
55a36b65 | 63 | |
fee0aede TG |
64 | /* |
65 | * identify_boot_cpu() initialized SMT support information, let the | |
66 | * core code know. | |
67 | */ | |
bc2d8d26 | 68 | cpu_smt_check_topology_early(); |
fee0aede | 69 | |
62a67e12 BP |
70 | if (!IS_ENABLED(CONFIG_SMP)) { |
71 | pr_info("CPU: "); | |
72 | print_cpu_info(&boot_cpu_data); | |
73 | } | |
74 | ||
1b86883c KRW |
75 | /* |
76 | * Read the SPEC_CTRL MSR to account for reserved bits which may | |
764f3c21 KRW |
77 | * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD |
78 | * init code as it is not enumerated and depends on the family. | |
1b86883c | 79 | */ |
7eb8956a | 80 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
1b86883c KRW |
81 | rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
82 | ||
be6fcb54 TG |
83 | /* Allow STIBP in MSR_SPEC_CTRL if supported */ |
84 | if (boot_cpu_has(X86_FEATURE_STIBP)) | |
85 | x86_spec_ctrl_mask |= SPEC_CTRL_STIBP; | |
86 | ||
da285121 DW |
87 | /* Select the proper spectre mitigation before patching alternatives */ |
88 | spectre_v2_select_mitigation(); | |
89 | ||
24f7fc83 KRW |
90 | /* |
91 | * Select proper mitigation for any exposure to the Speculative Store | |
92 | * Bypass vulnerability. | |
93 | */ | |
94 | ssb_select_mitigation(); | |
95 | ||
17dbca11 AK |
96 | l1tf_select_mitigation(); |
97 | ||
62a67e12 | 98 | #ifdef CONFIG_X86_32 |
55a36b65 BP |
99 | /* |
100 | * Check whether we are able to run this kernel safely on SMP. | |
101 | * | |
102 | * - i386 is no longer supported. | |
103 | * - In order to run on anything without a TSC, we need to be | |
104 | * compiled for a i486. | |
105 | */ | |
106 | if (boot_cpu_data.x86 < 4) | |
107 | panic("Kernel requires i486+ for 'invlpg' and other features"); | |
108 | ||
bfe4bb15 MV |
109 | init_utsname()->machine[1] = |
110 | '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); | |
1353ebb4 | 111 | alternative_instructions(); |
304bceda | 112 | |
4d164092 | 113 | fpu__init_check_bugs(); |
62a67e12 BP |
114 | #else /* CONFIG_X86_64 */ |
115 | alternative_instructions(); | |
116 | ||
117 | /* | |
118 | * Make sure the first 2MB area is not mapped by huge pages | |
119 | * There are typically fixed size MTRRs in there and overlapping | |
120 | * MTRRs into large pages causes slow downs. | |
121 | * | |
122 | * Right now we don't do that with gbpages because there seems | |
123 | * very little benefit for that case. | |
124 | */ | |
125 | if (!direct_gbpages) | |
126 | set_memory_4k((unsigned long)__va(0), 1); | |
127 | #endif | |
1353ebb4 | 128 | } |
61dc0f55 | 129 | |
cc69b349 BP |
130 | void |
131 | x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) | |
5cf68754 | 132 | { |
be6fcb54 | 133 | u64 msrval, guestval, hostval = x86_spec_ctrl_base; |
cc69b349 | 134 | struct thread_info *ti = current_thread_info(); |
885f82bf | 135 | |
7eb8956a | 136 | /* Is MSR_SPEC_CTRL implemented ? */ |
cc69b349 | 137 | if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { |
be6fcb54 TG |
138 | /* |
139 | * Restrict guest_spec_ctrl to supported values. Clear the | |
140 | * modifiable bits in the host base value and or the | |
141 | * modifiable bits from the guest value. | |
142 | */ | |
143 | guestval = hostval & ~x86_spec_ctrl_mask; | |
144 | guestval |= guest_spec_ctrl & x86_spec_ctrl_mask; | |
145 | ||
cc69b349 | 146 | /* SSBD controlled in MSR_SPEC_CTRL */ |
612bc3b3 TL |
147 | if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || |
148 | static_cpu_has(X86_FEATURE_AMD_SSBD)) | |
be6fcb54 | 149 | hostval |= ssbd_tif_to_spec_ctrl(ti->flags); |
cc69b349 | 150 | |
5bfbe3ad TC |
151 | /* Conditional STIBP enabled? */ |
152 | if (static_branch_unlikely(&switch_to_cond_stibp)) | |
153 | hostval |= stibp_tif_to_spec_ctrl(ti->flags); | |
154 | ||
be6fcb54 TG |
155 | if (hostval != guestval) { |
156 | msrval = setguest ? guestval : hostval; | |
157 | wrmsrl(MSR_IA32_SPEC_CTRL, msrval); | |
cc69b349 BP |
158 | } |
159 | } | |
47c61b39 TG |
160 | |
161 | /* | |
162 | * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update | |
163 | * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported. | |
164 | */ | |
165 | if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) && | |
166 | !static_cpu_has(X86_FEATURE_VIRT_SSBD)) | |
167 | return; | |
168 | ||
169 | /* | |
170 | * If the host has SSBD mitigation enabled, force it in the host's | |
171 | * virtual MSR value. If its not permanently enabled, evaluate | |
172 | * current's TIF_SSBD thread flag. | |
173 | */ | |
174 | if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE)) | |
175 | hostval = SPEC_CTRL_SSBD; | |
176 | else | |
177 | hostval = ssbd_tif_to_spec_ctrl(ti->flags); | |
178 | ||
179 | /* Sanitize the guest value */ | |
180 | guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD; | |
181 | ||
182 | if (hostval != guestval) { | |
183 | unsigned long tif; | |
184 | ||
185 | tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) : | |
186 | ssbd_spec_ctrl_to_tif(hostval); | |
187 | ||
26c4d75b | 188 | speculation_ctrl_update(tif); |
47c61b39 | 189 | } |
5cf68754 | 190 | } |
cc69b349 | 191 | EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); |
5cf68754 | 192 | |
9f65fb29 | 193 | static void x86_amd_ssb_disable(void) |
764f3c21 | 194 | { |
9f65fb29 | 195 | u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; |
764f3c21 | 196 | |
11fb0683 TL |
197 | if (boot_cpu_has(X86_FEATURE_VIRT_SSBD)) |
198 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); | |
199 | else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) | |
764f3c21 KRW |
200 | wrmsrl(MSR_AMD64_LS_CFG, msrval); |
201 | } | |
202 | ||
15d6b7aa TG |
203 | #undef pr_fmt |
204 | #define pr_fmt(fmt) "Spectre V2 : " fmt | |
205 | ||
206 | static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = | |
207 | SPECTRE_V2_NONE; | |
208 | ||
fa1202ef TG |
209 | static enum spectre_v2_user_mitigation spectre_v2_user __ro_after_init = |
210 | SPECTRE_V2_USER_NONE; | |
211 | ||
caf7501a | 212 | #ifdef RETPOLINE |
e383095c TG |
213 | static bool spectre_v2_bad_module; |
214 | ||
caf7501a AK |
215 | bool retpoline_module_ok(bool has_retpoline) |
216 | { | |
217 | if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) | |
218 | return true; | |
219 | ||
e698dcdf | 220 | pr_err("System may be vulnerable to spectre v2\n"); |
caf7501a AK |
221 | spectre_v2_bad_module = true; |
222 | return false; | |
223 | } | |
e383095c TG |
224 | |
225 | static inline const char *spectre_v2_module_string(void) | |
226 | { | |
227 | return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; | |
228 | } | |
229 | #else | |
230 | static inline const char *spectre_v2_module_string(void) { return ""; } | |
caf7501a | 231 | #endif |
da285121 | 232 | |
da285121 DW |
233 | static inline bool match_option(const char *arg, int arglen, const char *opt) |
234 | { | |
235 | int len = strlen(opt); | |
236 | ||
237 | return len == arglen && !strncmp(arg, opt, len); | |
238 | } | |
239 | ||
15d6b7aa TG |
240 | /* The kernel command line selection for spectre v2 */ |
241 | enum spectre_v2_mitigation_cmd { | |
242 | SPECTRE_V2_CMD_NONE, | |
243 | SPECTRE_V2_CMD_AUTO, | |
244 | SPECTRE_V2_CMD_FORCE, | |
245 | SPECTRE_V2_CMD_RETPOLINE, | |
246 | SPECTRE_V2_CMD_RETPOLINE_GENERIC, | |
247 | SPECTRE_V2_CMD_RETPOLINE_AMD, | |
248 | }; | |
249 | ||
fa1202ef TG |
250 | enum spectre_v2_user_cmd { |
251 | SPECTRE_V2_USER_CMD_NONE, | |
252 | SPECTRE_V2_USER_CMD_AUTO, | |
253 | SPECTRE_V2_USER_CMD_FORCE, | |
254 | }; | |
255 | ||
256 | static const char * const spectre_v2_user_strings[] = { | |
257 | [SPECTRE_V2_USER_NONE] = "User space: Vulnerable", | |
258 | [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection", | |
259 | }; | |
260 | ||
261 | static const struct { | |
262 | const char *option; | |
263 | enum spectre_v2_user_cmd cmd; | |
264 | bool secure; | |
265 | } v2_user_options[] __initdata = { | |
266 | { "auto", SPECTRE_V2_USER_CMD_AUTO, false }, | |
267 | { "off", SPECTRE_V2_USER_CMD_NONE, false }, | |
268 | { "on", SPECTRE_V2_USER_CMD_FORCE, true }, | |
269 | }; | |
270 | ||
271 | static void __init spec_v2_user_print_cond(const char *reason, bool secure) | |
272 | { | |
273 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) | |
274 | pr_info("spectre_v2_user=%s forced on command line.\n", reason); | |
275 | } | |
276 | ||
277 | static enum spectre_v2_user_cmd __init | |
278 | spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd) | |
279 | { | |
280 | char arg[20]; | |
281 | int ret, i; | |
282 | ||
283 | switch (v2_cmd) { | |
284 | case SPECTRE_V2_CMD_NONE: | |
285 | return SPECTRE_V2_USER_CMD_NONE; | |
286 | case SPECTRE_V2_CMD_FORCE: | |
287 | return SPECTRE_V2_USER_CMD_FORCE; | |
288 | default: | |
289 | break; | |
290 | } | |
291 | ||
292 | ret = cmdline_find_option(boot_command_line, "spectre_v2_user", | |
293 | arg, sizeof(arg)); | |
294 | if (ret < 0) | |
295 | return SPECTRE_V2_USER_CMD_AUTO; | |
296 | ||
297 | for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) { | |
298 | if (match_option(arg, ret, v2_user_options[i].option)) { | |
299 | spec_v2_user_print_cond(v2_user_options[i].option, | |
300 | v2_user_options[i].secure); | |
301 | return v2_user_options[i].cmd; | |
302 | } | |
303 | } | |
304 | ||
305 | pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg); | |
306 | return SPECTRE_V2_USER_CMD_AUTO; | |
307 | } | |
308 | ||
309 | static void __init | |
310 | spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd) | |
311 | { | |
312 | enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE; | |
313 | bool smt_possible = IS_ENABLED(CONFIG_SMP); | |
314 | ||
315 | if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP)) | |
316 | return; | |
317 | ||
318 | if (cpu_smt_control == CPU_SMT_FORCE_DISABLED || | |
319 | cpu_smt_control == CPU_SMT_NOT_SUPPORTED) | |
320 | smt_possible = false; | |
321 | ||
322 | switch (spectre_v2_parse_user_cmdline(v2_cmd)) { | |
323 | case SPECTRE_V2_USER_CMD_AUTO: | |
324 | case SPECTRE_V2_USER_CMD_NONE: | |
325 | goto set_mode; | |
326 | case SPECTRE_V2_USER_CMD_FORCE: | |
327 | mode = SPECTRE_V2_USER_STRICT; | |
328 | break; | |
329 | } | |
330 | ||
331 | /* Initialize Indirect Branch Prediction Barrier */ | |
332 | if (boot_cpu_has(X86_FEATURE_IBPB)) { | |
333 | setup_force_cpu_cap(X86_FEATURE_USE_IBPB); | |
334 | pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n"); | |
335 | } | |
336 | ||
337 | /* If enhanced IBRS is enabled no STIPB required */ | |
338 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) | |
339 | return; | |
340 | ||
341 | set_mode: | |
342 | spectre_v2_user = mode; | |
343 | /* Only print the STIBP mode when SMT possible */ | |
344 | if (smt_possible) | |
345 | pr_info("%s\n", spectre_v2_user_strings[mode]); | |
346 | } | |
347 | ||
8770709f | 348 | static const char * const spectre_v2_strings[] = { |
15d6b7aa TG |
349 | [SPECTRE_V2_NONE] = "Vulnerable", |
350 | [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", | |
351 | [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", | |
352 | [SPECTRE_V2_IBRS_ENHANCED] = "Mitigation: Enhanced IBRS", | |
353 | }; | |
354 | ||
9005c683 KA |
355 | static const struct { |
356 | const char *option; | |
357 | enum spectre_v2_mitigation_cmd cmd; | |
358 | bool secure; | |
30ba72a9 | 359 | } mitigation_options[] __initdata = { |
15d6b7aa TG |
360 | { "off", SPECTRE_V2_CMD_NONE, false }, |
361 | { "on", SPECTRE_V2_CMD_FORCE, true }, | |
362 | { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, | |
363 | { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false }, | |
364 | { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, | |
365 | { "auto", SPECTRE_V2_CMD_AUTO, false }, | |
9005c683 KA |
366 | }; |
367 | ||
495d470e | 368 | static void __init spec_v2_print_cond(const char *reason, bool secure) |
15d6b7aa | 369 | { |
495d470e | 370 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) |
15d6b7aa TG |
371 | pr_info("%s selected on command line.\n", reason); |
372 | } | |
373 | ||
da285121 DW |
374 | static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) |
375 | { | |
15d6b7aa | 376 | enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; |
da285121 | 377 | char arg[20]; |
9005c683 | 378 | int ret, i; |
9005c683 KA |
379 | |
380 | if (cmdline_find_option_bool(boot_command_line, "nospectre_v2")) | |
381 | return SPECTRE_V2_CMD_NONE; | |
9005c683 | 382 | |
24848509 TC |
383 | ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); |
384 | if (ret < 0) | |
385 | return SPECTRE_V2_CMD_AUTO; | |
386 | ||
387 | for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { | |
388 | if (!match_option(arg, ret, mitigation_options[i].option)) | |
389 | continue; | |
390 | cmd = mitigation_options[i].cmd; | |
391 | break; | |
392 | } | |
393 | ||
394 | if (i >= ARRAY_SIZE(mitigation_options)) { | |
395 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
396 | return SPECTRE_V2_CMD_AUTO; | |
da285121 DW |
397 | } |
398 | ||
9005c683 KA |
399 | if ((cmd == SPECTRE_V2_CMD_RETPOLINE || |
400 | cmd == SPECTRE_V2_CMD_RETPOLINE_AMD || | |
401 | cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) && | |
402 | !IS_ENABLED(CONFIG_RETPOLINE)) { | |
21e433bd | 403 | pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option); |
da285121 | 404 | return SPECTRE_V2_CMD_AUTO; |
9005c683 KA |
405 | } |
406 | ||
407 | if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD && | |
1a576b23 | 408 | boot_cpu_data.x86_vendor != X86_VENDOR_HYGON && |
9005c683 KA |
409 | boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { |
410 | pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n"); | |
411 | return SPECTRE_V2_CMD_AUTO; | |
412 | } | |
413 | ||
495d470e TG |
414 | spec_v2_print_cond(mitigation_options[i].option, |
415 | mitigation_options[i].secure); | |
9005c683 | 416 | return cmd; |
da285121 DW |
417 | } |
418 | ||
419 | static void __init spectre_v2_select_mitigation(void) | |
420 | { | |
421 | enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); | |
422 | enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; | |
423 | ||
424 | /* | |
425 | * If the CPU is not affected and the command line mode is NONE or AUTO | |
426 | * then nothing to do. | |
427 | */ | |
428 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && | |
429 | (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) | |
430 | return; | |
431 | ||
432 | switch (cmd) { | |
433 | case SPECTRE_V2_CMD_NONE: | |
434 | return; | |
435 | ||
436 | case SPECTRE_V2_CMD_FORCE: | |
da285121 | 437 | case SPECTRE_V2_CMD_AUTO: |
706d5168 SP |
438 | if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { |
439 | mode = SPECTRE_V2_IBRS_ENHANCED; | |
440 | /* Force it so VMEXIT will restore correctly */ | |
441 | x86_spec_ctrl_base |= SPEC_CTRL_IBRS; | |
442 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); | |
443 | goto specv2_set_mode; | |
444 | } | |
9471eee9 DL |
445 | if (IS_ENABLED(CONFIG_RETPOLINE)) |
446 | goto retpoline_auto; | |
447 | break; | |
da285121 DW |
448 | case SPECTRE_V2_CMD_RETPOLINE_AMD: |
449 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
450 | goto retpoline_amd; | |
451 | break; | |
452 | case SPECTRE_V2_CMD_RETPOLINE_GENERIC: | |
453 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
454 | goto retpoline_generic; | |
455 | break; | |
456 | case SPECTRE_V2_CMD_RETPOLINE: | |
457 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
458 | goto retpoline_auto; | |
459 | break; | |
460 | } | |
21e433bd | 461 | pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!"); |
da285121 DW |
462 | return; |
463 | ||
464 | retpoline_auto: | |
1a576b23 PW |
465 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || |
466 | boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) { | |
da285121 DW |
467 | retpoline_amd: |
468 | if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { | |
21e433bd | 469 | pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n"); |
da285121 DW |
470 | goto retpoline_generic; |
471 | } | |
ef014aae | 472 | mode = SPECTRE_V2_RETPOLINE_AMD; |
da285121 DW |
473 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD); |
474 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
475 | } else { | |
476 | retpoline_generic: | |
ef014aae | 477 | mode = SPECTRE_V2_RETPOLINE_GENERIC; |
da285121 DW |
478 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); |
479 | } | |
480 | ||
706d5168 | 481 | specv2_set_mode: |
da285121 DW |
482 | spectre_v2_enabled = mode; |
483 | pr_info("%s\n", spectre_v2_strings[mode]); | |
c995efd5 DW |
484 | |
485 | /* | |
fdf82a78 JK |
486 | * If spectre v2 protection has been enabled, unconditionally fill |
487 | * RSB during a context switch; this protects against two independent | |
488 | * issues: | |
c995efd5 | 489 | * |
fdf82a78 JK |
490 | * - RSB underflow (and switch to BTB) on Skylake+ |
491 | * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs | |
c995efd5 | 492 | */ |
fdf82a78 JK |
493 | setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); |
494 | pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n"); | |
20ffa1ca | 495 | |
dd84441a DW |
496 | /* |
497 | * Retpoline means the kernel is safe because it has no indirect | |
706d5168 SP |
498 | * branches. Enhanced IBRS protects firmware too, so, enable restricted |
499 | * speculation around firmware calls only when Enhanced IBRS isn't | |
500 | * supported. | |
501 | * | |
502 | * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because | |
503 | * the user might select retpoline on the kernel command line and if | |
504 | * the CPU supports Enhanced IBRS, kernel might un-intentionally not | |
505 | * enable IBRS around firmware calls. | |
dd84441a | 506 | */ |
706d5168 | 507 | if (boot_cpu_has(X86_FEATURE_IBRS) && mode != SPECTRE_V2_IBRS_ENHANCED) { |
dd84441a DW |
508 | setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); |
509 | pr_info("Enabling Restricted Speculation for firmware calls\n"); | |
510 | } | |
53c613fe | 511 | |
fa1202ef TG |
512 | /* Set up IBPB and STIBP depending on the general spectre V2 command */ |
513 | spectre_v2_user_select_mitigation(cmd); | |
514 | ||
53c613fe JK |
515 | /* Enable STIBP if appropriate */ |
516 | arch_smt_update(); | |
da285121 DW |
517 | } |
518 | ||
15d6b7aa TG |
519 | static bool stibp_needed(void) |
520 | { | |
15d6b7aa TG |
521 | /* Enhanced IBRS makes using STIBP unnecessary. */ |
522 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) | |
523 | return false; | |
524 | ||
fa1202ef TG |
525 | /* Check for strict user mitigation mode */ |
526 | return spectre_v2_user == SPECTRE_V2_USER_STRICT; | |
15d6b7aa TG |
527 | } |
528 | ||
529 | static void update_stibp_msr(void *info) | |
530 | { | |
531 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); | |
532 | } | |
533 | ||
534 | void arch_smt_update(void) | |
535 | { | |
536 | u64 mask; | |
537 | ||
538 | if (!stibp_needed()) | |
539 | return; | |
540 | ||
541 | mutex_lock(&spec_ctrl_mutex); | |
542 | ||
543 | mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP; | |
544 | if (sched_smt_active()) | |
545 | mask |= SPEC_CTRL_STIBP; | |
546 | ||
547 | if (mask != x86_spec_ctrl_base) { | |
548 | pr_info("Spectre v2 cross-process SMT mitigation: %s STIBP\n", | |
549 | mask & SPEC_CTRL_STIBP ? "Enabling" : "Disabling"); | |
550 | x86_spec_ctrl_base = mask; | |
551 | on_each_cpu(update_stibp_msr, NULL, 1); | |
552 | } | |
553 | mutex_unlock(&spec_ctrl_mutex); | |
554 | } | |
555 | ||
24f7fc83 KRW |
556 | #undef pr_fmt |
557 | #define pr_fmt(fmt) "Speculative Store Bypass: " fmt | |
558 | ||
f9544b2b | 559 | static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE; |
24f7fc83 KRW |
560 | |
561 | /* The kernel command line selection */ | |
562 | enum ssb_mitigation_cmd { | |
563 | SPEC_STORE_BYPASS_CMD_NONE, | |
564 | SPEC_STORE_BYPASS_CMD_AUTO, | |
565 | SPEC_STORE_BYPASS_CMD_ON, | |
a73ec77e | 566 | SPEC_STORE_BYPASS_CMD_PRCTL, |
f21b53b2 | 567 | SPEC_STORE_BYPASS_CMD_SECCOMP, |
24f7fc83 KRW |
568 | }; |
569 | ||
8770709f | 570 | static const char * const ssb_strings[] = { |
24f7fc83 | 571 | [SPEC_STORE_BYPASS_NONE] = "Vulnerable", |
a73ec77e | 572 | [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", |
f21b53b2 KC |
573 | [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", |
574 | [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp", | |
24f7fc83 KRW |
575 | }; |
576 | ||
577 | static const struct { | |
578 | const char *option; | |
579 | enum ssb_mitigation_cmd cmd; | |
30ba72a9 | 580 | } ssb_mitigation_options[] __initdata = { |
f21b53b2 KC |
581 | { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ |
582 | { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ | |
583 | { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ | |
584 | { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */ | |
585 | { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */ | |
24f7fc83 KRW |
586 | }; |
587 | ||
588 | static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) | |
589 | { | |
590 | enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO; | |
591 | char arg[20]; | |
592 | int ret, i; | |
593 | ||
594 | if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) { | |
595 | return SPEC_STORE_BYPASS_CMD_NONE; | |
596 | } else { | |
597 | ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", | |
598 | arg, sizeof(arg)); | |
599 | if (ret < 0) | |
600 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
601 | ||
602 | for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { | |
603 | if (!match_option(arg, ret, ssb_mitigation_options[i].option)) | |
604 | continue; | |
605 | ||
606 | cmd = ssb_mitigation_options[i].cmd; | |
607 | break; | |
608 | } | |
609 | ||
610 | if (i >= ARRAY_SIZE(ssb_mitigation_options)) { | |
611 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
612 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
613 | } | |
614 | } | |
615 | ||
616 | return cmd; | |
617 | } | |
618 | ||
d66d8ff3 | 619 | static enum ssb_mitigation __init __ssb_select_mitigation(void) |
24f7fc83 KRW |
620 | { |
621 | enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; | |
622 | enum ssb_mitigation_cmd cmd; | |
623 | ||
9f65fb29 | 624 | if (!boot_cpu_has(X86_FEATURE_SSBD)) |
24f7fc83 KRW |
625 | return mode; |
626 | ||
627 | cmd = ssb_parse_cmdline(); | |
628 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && | |
629 | (cmd == SPEC_STORE_BYPASS_CMD_NONE || | |
630 | cmd == SPEC_STORE_BYPASS_CMD_AUTO)) | |
631 | return mode; | |
632 | ||
633 | switch (cmd) { | |
634 | case SPEC_STORE_BYPASS_CMD_AUTO: | |
f21b53b2 KC |
635 | case SPEC_STORE_BYPASS_CMD_SECCOMP: |
636 | /* | |
637 | * Choose prctl+seccomp as the default mode if seccomp is | |
638 | * enabled. | |
639 | */ | |
640 | if (IS_ENABLED(CONFIG_SECCOMP)) | |
641 | mode = SPEC_STORE_BYPASS_SECCOMP; | |
642 | else | |
643 | mode = SPEC_STORE_BYPASS_PRCTL; | |
a73ec77e | 644 | break; |
24f7fc83 KRW |
645 | case SPEC_STORE_BYPASS_CMD_ON: |
646 | mode = SPEC_STORE_BYPASS_DISABLE; | |
647 | break; | |
a73ec77e TG |
648 | case SPEC_STORE_BYPASS_CMD_PRCTL: |
649 | mode = SPEC_STORE_BYPASS_PRCTL; | |
650 | break; | |
24f7fc83 KRW |
651 | case SPEC_STORE_BYPASS_CMD_NONE: |
652 | break; | |
653 | } | |
654 | ||
77243971 KRW |
655 | /* |
656 | * We have three CPU feature flags that are in play here: | |
657 | * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. | |
9f65fb29 | 658 | * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass |
77243971 KRW |
659 | * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation |
660 | */ | |
a73ec77e | 661 | if (mode == SPEC_STORE_BYPASS_DISABLE) { |
24f7fc83 | 662 | setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); |
77243971 | 663 | /* |
6ac2f49e KRW |
664 | * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may |
665 | * use a completely different MSR and bit dependent on family. | |
77243971 | 666 | */ |
612bc3b3 TL |
667 | if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) && |
668 | !static_cpu_has(X86_FEATURE_AMD_SSBD)) { | |
108fab4b | 669 | x86_amd_ssb_disable(); |
612bc3b3 | 670 | } else { |
9f65fb29 | 671 | x86_spec_ctrl_base |= SPEC_CTRL_SSBD; |
be6fcb54 | 672 | x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; |
4b59bdb5 | 673 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
77243971 KRW |
674 | } |
675 | } | |
676 | ||
24f7fc83 KRW |
677 | return mode; |
678 | } | |
679 | ||
ffed645e | 680 | static void ssb_select_mitigation(void) |
24f7fc83 KRW |
681 | { |
682 | ssb_mode = __ssb_select_mitigation(); | |
683 | ||
684 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
685 | pr_info("%s\n", ssb_strings[ssb_mode]); | |
686 | } | |
687 | ||
da285121 | 688 | #undef pr_fmt |
f21b53b2 | 689 | #define pr_fmt(fmt) "Speculation prctl: " fmt |
da285121 | 690 | |
7bbf1373 | 691 | static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) |
a73ec77e | 692 | { |
356e4bff | 693 | bool update; |
a73ec77e | 694 | |
f21b53b2 KC |
695 | if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && |
696 | ssb_mode != SPEC_STORE_BYPASS_SECCOMP) | |
a73ec77e TG |
697 | return -ENXIO; |
698 | ||
356e4bff TG |
699 | switch (ctrl) { |
700 | case PR_SPEC_ENABLE: | |
701 | /* If speculation is force disabled, enable is not allowed */ | |
702 | if (task_spec_ssb_force_disable(task)) | |
703 | return -EPERM; | |
704 | task_clear_spec_ssb_disable(task); | |
9f65fb29 | 705 | update = test_and_clear_tsk_thread_flag(task, TIF_SSBD); |
356e4bff TG |
706 | break; |
707 | case PR_SPEC_DISABLE: | |
708 | task_set_spec_ssb_disable(task); | |
9f65fb29 | 709 | update = !test_and_set_tsk_thread_flag(task, TIF_SSBD); |
356e4bff TG |
710 | break; |
711 | case PR_SPEC_FORCE_DISABLE: | |
712 | task_set_spec_ssb_disable(task); | |
713 | task_set_spec_ssb_force_disable(task); | |
9f65fb29 | 714 | update = !test_and_set_tsk_thread_flag(task, TIF_SSBD); |
356e4bff TG |
715 | break; |
716 | default: | |
717 | return -ERANGE; | |
718 | } | |
a73ec77e | 719 | |
7bbf1373 KC |
720 | /* |
721 | * If being set on non-current task, delay setting the CPU | |
722 | * mitigation until it is next scheduled. | |
723 | */ | |
356e4bff | 724 | if (task == current && update) |
26c4d75b | 725 | speculation_ctrl_update_current(); |
a73ec77e TG |
726 | |
727 | return 0; | |
728 | } | |
729 | ||
8bf37d8c TG |
730 | int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, |
731 | unsigned long ctrl) | |
732 | { | |
733 | switch (which) { | |
734 | case PR_SPEC_STORE_BYPASS: | |
735 | return ssb_prctl_set(task, ctrl); | |
736 | default: | |
737 | return -ENODEV; | |
738 | } | |
739 | } | |
740 | ||
741 | #ifdef CONFIG_SECCOMP | |
742 | void arch_seccomp_spec_mitigate(struct task_struct *task) | |
743 | { | |
f21b53b2 KC |
744 | if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) |
745 | ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
8bf37d8c TG |
746 | } |
747 | #endif | |
748 | ||
7bbf1373 | 749 | static int ssb_prctl_get(struct task_struct *task) |
a73ec77e TG |
750 | { |
751 | switch (ssb_mode) { | |
752 | case SPEC_STORE_BYPASS_DISABLE: | |
753 | return PR_SPEC_DISABLE; | |
f21b53b2 | 754 | case SPEC_STORE_BYPASS_SECCOMP: |
a73ec77e | 755 | case SPEC_STORE_BYPASS_PRCTL: |
356e4bff TG |
756 | if (task_spec_ssb_force_disable(task)) |
757 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
758 | if (task_spec_ssb_disable(task)) | |
a73ec77e TG |
759 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; |
760 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
761 | default: | |
762 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
763 | return PR_SPEC_ENABLE; | |
764 | return PR_SPEC_NOT_AFFECTED; | |
765 | } | |
766 | } | |
767 | ||
7bbf1373 | 768 | int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) |
a73ec77e TG |
769 | { |
770 | switch (which) { | |
771 | case PR_SPEC_STORE_BYPASS: | |
7bbf1373 | 772 | return ssb_prctl_get(task); |
a73ec77e TG |
773 | default: |
774 | return -ENODEV; | |
775 | } | |
776 | } | |
777 | ||
77243971 KRW |
778 | void x86_spec_ctrl_setup_ap(void) |
779 | { | |
7eb8956a | 780 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
4b59bdb5 | 781 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
764f3c21 KRW |
782 | |
783 | if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) | |
9f65fb29 | 784 | x86_amd_ssb_disable(); |
77243971 KRW |
785 | } |
786 | ||
56563f53 KRW |
787 | #undef pr_fmt |
788 | #define pr_fmt(fmt) "L1TF: " fmt | |
72c6d2db | 789 | |
d90a7a0e JK |
790 | /* Default mitigation for L1TF-affected CPUs */ |
791 | enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH; | |
72c6d2db | 792 | #if IS_ENABLED(CONFIG_KVM_INTEL) |
d90a7a0e | 793 | EXPORT_SYMBOL_GPL(l1tf_mitigation); |
1eb46908 | 794 | #endif |
895ae47f | 795 | enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; |
72c6d2db | 796 | EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation); |
72c6d2db | 797 | |
cc51e542 AK |
798 | /* |
799 | * These CPUs all support 44bits physical address space internally in the | |
800 | * cache but CPUID can report a smaller number of physical address bits. | |
801 | * | |
802 | * The L1TF mitigation uses the top most address bit for the inversion of | |
803 | * non present PTEs. When the installed memory reaches into the top most | |
804 | * address bit due to memory holes, which has been observed on machines | |
805 | * which report 36bits physical address bits and have 32G RAM installed, | |
806 | * then the mitigation range check in l1tf_select_mitigation() triggers. | |
807 | * This is a false positive because the mitigation is still possible due to | |
808 | * the fact that the cache uses 44bit internally. Use the cache bits | |
809 | * instead of the reported physical bits and adjust them on the affected | |
810 | * machines to 44bit if the reported bits are less than 44. | |
811 | */ | |
812 | static void override_cache_bits(struct cpuinfo_x86 *c) | |
813 | { | |
814 | if (c->x86 != 6) | |
815 | return; | |
816 | ||
817 | switch (c->x86_model) { | |
818 | case INTEL_FAM6_NEHALEM: | |
819 | case INTEL_FAM6_WESTMERE: | |
820 | case INTEL_FAM6_SANDYBRIDGE: | |
821 | case INTEL_FAM6_IVYBRIDGE: | |
822 | case INTEL_FAM6_HASWELL_CORE: | |
823 | case INTEL_FAM6_HASWELL_ULT: | |
824 | case INTEL_FAM6_HASWELL_GT3E: | |
825 | case INTEL_FAM6_BROADWELL_CORE: | |
826 | case INTEL_FAM6_BROADWELL_GT3E: | |
827 | case INTEL_FAM6_SKYLAKE_MOBILE: | |
828 | case INTEL_FAM6_SKYLAKE_DESKTOP: | |
829 | case INTEL_FAM6_KABYLAKE_MOBILE: | |
830 | case INTEL_FAM6_KABYLAKE_DESKTOP: | |
831 | if (c->x86_cache_bits < 44) | |
832 | c->x86_cache_bits = 44; | |
833 | break; | |
834 | } | |
835 | } | |
836 | ||
56563f53 KRW |
837 | static void __init l1tf_select_mitigation(void) |
838 | { | |
839 | u64 half_pa; | |
840 | ||
841 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
842 | return; | |
843 | ||
cc51e542 AK |
844 | override_cache_bits(&boot_cpu_data); |
845 | ||
d90a7a0e JK |
846 | switch (l1tf_mitigation) { |
847 | case L1TF_MITIGATION_OFF: | |
848 | case L1TF_MITIGATION_FLUSH_NOWARN: | |
849 | case L1TF_MITIGATION_FLUSH: | |
850 | break; | |
851 | case L1TF_MITIGATION_FLUSH_NOSMT: | |
852 | case L1TF_MITIGATION_FULL: | |
853 | cpu_smt_disable(false); | |
854 | break; | |
855 | case L1TF_MITIGATION_FULL_FORCE: | |
856 | cpu_smt_disable(true); | |
857 | break; | |
858 | } | |
859 | ||
56563f53 KRW |
860 | #if CONFIG_PGTABLE_LEVELS == 2 |
861 | pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n"); | |
862 | return; | |
863 | #endif | |
864 | ||
56563f53 KRW |
865 | half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT; |
866 | if (e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) { | |
867 | pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n"); | |
6a012288 VB |
868 | pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n", |
869 | half_pa); | |
870 | pr_info("However, doing so will make a part of your RAM unusable.\n"); | |
871 | pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html might help you decide.\n"); | |
56563f53 KRW |
872 | return; |
873 | } | |
874 | ||
875 | setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV); | |
876 | } | |
d90a7a0e JK |
877 | |
878 | static int __init l1tf_cmdline(char *str) | |
879 | { | |
880 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
881 | return 0; | |
882 | ||
883 | if (!str) | |
884 | return -EINVAL; | |
885 | ||
886 | if (!strcmp(str, "off")) | |
887 | l1tf_mitigation = L1TF_MITIGATION_OFF; | |
888 | else if (!strcmp(str, "flush,nowarn")) | |
889 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN; | |
890 | else if (!strcmp(str, "flush")) | |
891 | l1tf_mitigation = L1TF_MITIGATION_FLUSH; | |
892 | else if (!strcmp(str, "flush,nosmt")) | |
893 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; | |
894 | else if (!strcmp(str, "full")) | |
895 | l1tf_mitigation = L1TF_MITIGATION_FULL; | |
896 | else if (!strcmp(str, "full,force")) | |
897 | l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE; | |
898 | ||
899 | return 0; | |
900 | } | |
901 | early_param("l1tf", l1tf_cmdline); | |
902 | ||
56563f53 KRW |
903 | #undef pr_fmt |
904 | ||
61dc0f55 | 905 | #ifdef CONFIG_SYSFS |
d1059518 | 906 | |
72c6d2db TG |
907 | #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion" |
908 | ||
909 | #if IS_ENABLED(CONFIG_KVM_INTEL) | |
8770709f | 910 | static const char * const l1tf_vmx_states[] = { |
a7b9020b TG |
911 | [VMENTER_L1D_FLUSH_AUTO] = "auto", |
912 | [VMENTER_L1D_FLUSH_NEVER] = "vulnerable", | |
913 | [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes", | |
914 | [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes", | |
915 | [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled", | |
8e0b2b91 | 916 | [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary" |
72c6d2db TG |
917 | }; |
918 | ||
919 | static ssize_t l1tf_show_state(char *buf) | |
920 | { | |
921 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) | |
922 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
923 | ||
ea156d19 PB |
924 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED || |
925 | (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER && | |
130d6f94 | 926 | sched_smt_active())) { |
ea156d19 PB |
927 | return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG, |
928 | l1tf_vmx_states[l1tf_vmx_mitigation]); | |
130d6f94 | 929 | } |
ea156d19 PB |
930 | |
931 | return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG, | |
932 | l1tf_vmx_states[l1tf_vmx_mitigation], | |
130d6f94 | 933 | sched_smt_active() ? "vulnerable" : "disabled"); |
72c6d2db TG |
934 | } |
935 | #else | |
936 | static ssize_t l1tf_show_state(char *buf) | |
937 | { | |
938 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
939 | } | |
940 | #endif | |
941 | ||
a8f76ae4 TC |
942 | static char *stibp_state(void) |
943 | { | |
34bce7c9 TC |
944 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) |
945 | return ""; | |
946 | ||
fa1202ef TG |
947 | switch (spectre_v2_user) { |
948 | case SPECTRE_V2_USER_NONE: | |
949 | return ", STIBP: disabled"; | |
950 | case SPECTRE_V2_USER_STRICT: | |
951 | return ", STIBP: forced"; | |
952 | } | |
953 | return ""; | |
a8f76ae4 TC |
954 | } |
955 | ||
956 | static char *ibpb_state(void) | |
957 | { | |
958 | if (boot_cpu_has(X86_FEATURE_USE_IBPB)) | |
959 | return ", IBPB"; | |
960 | else | |
961 | return ""; | |
962 | } | |
963 | ||
7bb4d366 | 964 | static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, |
ffed645e | 965 | char *buf, unsigned int bug) |
61dc0f55 | 966 | { |
d1059518 | 967 | if (!boot_cpu_has_bug(bug)) |
61dc0f55 | 968 | return sprintf(buf, "Not affected\n"); |
d1059518 KRW |
969 | |
970 | switch (bug) { | |
971 | case X86_BUG_CPU_MELTDOWN: | |
972 | if (boot_cpu_has(X86_FEATURE_PTI)) | |
973 | return sprintf(buf, "Mitigation: PTI\n"); | |
974 | ||
6cb2b08f JK |
975 | if (hypervisor_is_type(X86_HYPER_XEN_PV)) |
976 | return sprintf(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n"); | |
977 | ||
d1059518 KRW |
978 | break; |
979 | ||
980 | case X86_BUG_SPECTRE_V1: | |
981 | return sprintf(buf, "Mitigation: __user pointer sanitization\n"); | |
982 | ||
983 | case X86_BUG_SPECTRE_V2: | |
b86bda04 | 984 | return sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], |
a8f76ae4 | 985 | ibpb_state(), |
d1059518 | 986 | boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", |
a8f76ae4 | 987 | stibp_state(), |
bb4b3b77 | 988 | boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "", |
d1059518 KRW |
989 | spectre_v2_module_string()); |
990 | ||
24f7fc83 KRW |
991 | case X86_BUG_SPEC_STORE_BYPASS: |
992 | return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); | |
993 | ||
17dbca11 AK |
994 | case X86_BUG_L1TF: |
995 | if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV)) | |
72c6d2db | 996 | return l1tf_show_state(buf); |
17dbca11 | 997 | break; |
d1059518 KRW |
998 | default: |
999 | break; | |
1000 | } | |
1001 | ||
61dc0f55 TG |
1002 | return sprintf(buf, "Vulnerable\n"); |
1003 | } | |
1004 | ||
d1059518 KRW |
1005 | ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) |
1006 | { | |
1007 | return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); | |
1008 | } | |
1009 | ||
21e433bd | 1010 | ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 1011 | { |
d1059518 | 1012 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); |
61dc0f55 TG |
1013 | } |
1014 | ||
21e433bd | 1015 | ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 1016 | { |
d1059518 | 1017 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); |
61dc0f55 | 1018 | } |
c456442c KRW |
1019 | |
1020 | ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) | |
1021 | { | |
1022 | return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); | |
1023 | } | |
17dbca11 AK |
1024 | |
1025 | ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf) | |
1026 | { | |
1027 | return cpu_show_common(dev, attr, buf, X86_BUG_L1TF); | |
1028 | } | |
61dc0f55 | 1029 | #endif |