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b2441318 1// SPDX-License-Identifier: GPL-2.0
1353ebb4 2/*
1353ebb4
JF
3 * Copyright (C) 1994 Linus Torvalds
4 *
5 * Cyrix stuff, June 1998 by:
6 * - Rafael R. Reilova (moved everything from head.S),
7 * <rreilova@ececs.uc.edu>
8 * - Channing Corn (tests & fixes),
9 * - Andrew D. Balsa (code cleanup).
10 */
11#include <linux/init.h>
12#include <linux/utsname.h>
61dc0f55 13#include <linux/cpu.h>
caf7501a 14#include <linux/module.h>
a73ec77e
TG
15#include <linux/nospec.h>
16#include <linux/prctl.h>
a74cfffb 17#include <linux/sched/smt.h>
da285121 18
28a27752 19#include <asm/spec-ctrl.h>
da285121 20#include <asm/cmdline.h>
91eb1b79 21#include <asm/bugs.h>
1353ebb4 22#include <asm/processor.h>
7ebad705 23#include <asm/processor-flags.h>
952f07ec 24#include <asm/fpu/internal.h>
1353ebb4 25#include <asm/msr.h>
72c6d2db 26#include <asm/vmx.h>
1353ebb4
JF
27#include <asm/paravirt.h>
28#include <asm/alternative.h>
62a67e12 29#include <asm/pgtable.h>
d1163651 30#include <asm/set_memory.h>
c995efd5 31#include <asm/intel-family.h>
17dbca11 32#include <asm/e820/api.h>
6cb2b08f 33#include <asm/hypervisor.h>
1353ebb4 34
da285121 35static void __init spectre_v2_select_mitigation(void);
24f7fc83 36static void __init ssb_select_mitigation(void);
17dbca11 37static void __init l1tf_select_mitigation(void);
da285121 38
53c613fe
JK
39/* The base value of the SPEC_CTRL MSR that always has to be preserved. */
40u64 x86_spec_ctrl_base;
fa8ac498 41EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
53c613fe 42static DEFINE_MUTEX(spec_ctrl_mutex);
1b86883c 43
1115a859
KRW
44/*
45 * The vendor and possibly platform specific bits which can be modified in
46 * x86_spec_ctrl_base.
47 */
be6fcb54 48static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS;
1115a859 49
764f3c21
KRW
50/*
51 * AMD specific MSR info for Speculative Store Bypass control.
9f65fb29 52 * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
764f3c21
KRW
53 */
54u64 __ro_after_init x86_amd_ls_cfg_base;
9f65fb29 55u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
764f3c21 56
1353ebb4
JF
57void __init check_bugs(void)
58{
59 identify_boot_cpu();
55a36b65 60
fee0aede
TG
61 /*
62 * identify_boot_cpu() initialized SMT support information, let the
63 * core code know.
64 */
bc2d8d26 65 cpu_smt_check_topology_early();
fee0aede 66
62a67e12
BP
67 if (!IS_ENABLED(CONFIG_SMP)) {
68 pr_info("CPU: ");
69 print_cpu_info(&boot_cpu_data);
70 }
71
1b86883c
KRW
72 /*
73 * Read the SPEC_CTRL MSR to account for reserved bits which may
764f3c21
KRW
74 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
75 * init code as it is not enumerated and depends on the family.
1b86883c 76 */
7eb8956a 77 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
1b86883c
KRW
78 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
79
be6fcb54
TG
80 /* Allow STIBP in MSR_SPEC_CTRL if supported */
81 if (boot_cpu_has(X86_FEATURE_STIBP))
82 x86_spec_ctrl_mask |= SPEC_CTRL_STIBP;
83
da285121
DW
84 /* Select the proper spectre mitigation before patching alternatives */
85 spectre_v2_select_mitigation();
86
24f7fc83
KRW
87 /*
88 * Select proper mitigation for any exposure to the Speculative Store
89 * Bypass vulnerability.
90 */
91 ssb_select_mitigation();
92
17dbca11
AK
93 l1tf_select_mitigation();
94
62a67e12 95#ifdef CONFIG_X86_32
55a36b65
BP
96 /*
97 * Check whether we are able to run this kernel safely on SMP.
98 *
99 * - i386 is no longer supported.
100 * - In order to run on anything without a TSC, we need to be
101 * compiled for a i486.
102 */
103 if (boot_cpu_data.x86 < 4)
104 panic("Kernel requires i486+ for 'invlpg' and other features");
105
bfe4bb15
MV
106 init_utsname()->machine[1] =
107 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
1353ebb4 108 alternative_instructions();
304bceda 109
4d164092 110 fpu__init_check_bugs();
62a67e12
BP
111#else /* CONFIG_X86_64 */
112 alternative_instructions();
113
114 /*
115 * Make sure the first 2MB area is not mapped by huge pages
116 * There are typically fixed size MTRRs in there and overlapping
117 * MTRRs into large pages causes slow downs.
118 *
119 * Right now we don't do that with gbpages because there seems
120 * very little benefit for that case.
121 */
122 if (!direct_gbpages)
123 set_memory_4k((unsigned long)__va(0), 1);
124#endif
1353ebb4 125}
61dc0f55 126
da285121
DW
127/* The kernel command line selection */
128enum spectre_v2_mitigation_cmd {
129 SPECTRE_V2_CMD_NONE,
130 SPECTRE_V2_CMD_AUTO,
131 SPECTRE_V2_CMD_FORCE,
132 SPECTRE_V2_CMD_RETPOLINE,
133 SPECTRE_V2_CMD_RETPOLINE_GENERIC,
134 SPECTRE_V2_CMD_RETPOLINE_AMD,
135};
136
137static const char *spectre_v2_strings[] = {
138 [SPECTRE_V2_NONE] = "Vulnerable",
da285121
DW
139 [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline",
140 [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline",
706d5168 141 [SPECTRE_V2_IBRS_ENHANCED] = "Mitigation: Enhanced IBRS",
da285121
DW
142};
143
144#undef pr_fmt
55fa19d3 145#define pr_fmt(fmt) "Spectre V2 : " fmt
da285121 146
f9544b2b
KC
147static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
148 SPECTRE_V2_NONE;
caf7501a 149
cc69b349
BP
150void
151x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
5cf68754 152{
be6fcb54 153 u64 msrval, guestval, hostval = x86_spec_ctrl_base;
cc69b349 154 struct thread_info *ti = current_thread_info();
885f82bf 155
7eb8956a 156 /* Is MSR_SPEC_CTRL implemented ? */
cc69b349 157 if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
be6fcb54
TG
158 /*
159 * Restrict guest_spec_ctrl to supported values. Clear the
160 * modifiable bits in the host base value and or the
161 * modifiable bits from the guest value.
162 */
163 guestval = hostval & ~x86_spec_ctrl_mask;
164 guestval |= guest_spec_ctrl & x86_spec_ctrl_mask;
165
cc69b349 166 /* SSBD controlled in MSR_SPEC_CTRL */
612bc3b3
TL
167 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
168 static_cpu_has(X86_FEATURE_AMD_SSBD))
be6fcb54 169 hostval |= ssbd_tif_to_spec_ctrl(ti->flags);
cc69b349 170
be6fcb54
TG
171 if (hostval != guestval) {
172 msrval = setguest ? guestval : hostval;
173 wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
cc69b349
BP
174 }
175 }
47c61b39
TG
176
177 /*
178 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
179 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
180 */
181 if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
182 !static_cpu_has(X86_FEATURE_VIRT_SSBD))
183 return;
184
185 /*
186 * If the host has SSBD mitigation enabled, force it in the host's
187 * virtual MSR value. If its not permanently enabled, evaluate
188 * current's TIF_SSBD thread flag.
189 */
190 if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
191 hostval = SPEC_CTRL_SSBD;
192 else
193 hostval = ssbd_tif_to_spec_ctrl(ti->flags);
194
195 /* Sanitize the guest value */
196 guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
197
198 if (hostval != guestval) {
199 unsigned long tif;
200
201 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
202 ssbd_spec_ctrl_to_tif(hostval);
203
26c4d75b 204 speculation_ctrl_update(tif);
47c61b39 205 }
5cf68754 206}
cc69b349 207EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
5cf68754 208
9f65fb29 209static void x86_amd_ssb_disable(void)
764f3c21 210{
9f65fb29 211 u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
764f3c21 212
11fb0683
TL
213 if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
214 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
215 else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
764f3c21
KRW
216 wrmsrl(MSR_AMD64_LS_CFG, msrval);
217}
218
caf7501a 219#ifdef RETPOLINE
e383095c
TG
220static bool spectre_v2_bad_module;
221
caf7501a
AK
222bool retpoline_module_ok(bool has_retpoline)
223{
224 if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
225 return true;
226
e698dcdf 227 pr_err("System may be vulnerable to spectre v2\n");
caf7501a
AK
228 spectre_v2_bad_module = true;
229 return false;
230}
e383095c
TG
231
232static inline const char *spectre_v2_module_string(void)
233{
234 return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
235}
236#else
237static inline const char *spectre_v2_module_string(void) { return ""; }
caf7501a 238#endif
da285121
DW
239
240static void __init spec2_print_if_insecure(const char *reason)
241{
242 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
9005c683 243 pr_info("%s selected on command line.\n", reason);
da285121
DW
244}
245
246static void __init spec2_print_if_secure(const char *reason)
247{
248 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
9005c683 249 pr_info("%s selected on command line.\n", reason);
da285121
DW
250}
251
da285121
DW
252static inline bool match_option(const char *arg, int arglen, const char *opt)
253{
254 int len = strlen(opt);
255
256 return len == arglen && !strncmp(arg, opt, len);
257}
258
9005c683
KA
259static const struct {
260 const char *option;
261 enum spectre_v2_mitigation_cmd cmd;
262 bool secure;
263} mitigation_options[] = {
264 { "off", SPECTRE_V2_CMD_NONE, false },
265 { "on", SPECTRE_V2_CMD_FORCE, true },
266 { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false },
267 { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false },
268 { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
269 { "auto", SPECTRE_V2_CMD_AUTO, false },
270};
271
da285121
DW
272static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
273{
274 char arg[20];
9005c683
KA
275 int ret, i;
276 enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
277
278 if (cmdline_find_option_bool(boot_command_line, "nospectre_v2"))
279 return SPECTRE_V2_CMD_NONE;
9005c683 280
24848509
TC
281 ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
282 if (ret < 0)
283 return SPECTRE_V2_CMD_AUTO;
284
285 for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
286 if (!match_option(arg, ret, mitigation_options[i].option))
287 continue;
288 cmd = mitigation_options[i].cmd;
289 break;
290 }
291
292 if (i >= ARRAY_SIZE(mitigation_options)) {
293 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
294 return SPECTRE_V2_CMD_AUTO;
da285121
DW
295 }
296
9005c683
KA
297 if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
298 cmd == SPECTRE_V2_CMD_RETPOLINE_AMD ||
299 cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) &&
300 !IS_ENABLED(CONFIG_RETPOLINE)) {
21e433bd 301 pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option);
da285121 302 return SPECTRE_V2_CMD_AUTO;
9005c683
KA
303 }
304
305 if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD &&
1a576b23 306 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON &&
9005c683
KA
307 boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
308 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
309 return SPECTRE_V2_CMD_AUTO;
310 }
311
312 if (mitigation_options[i].secure)
313 spec2_print_if_secure(mitigation_options[i].option);
314 else
315 spec2_print_if_insecure(mitigation_options[i].option);
316
317 return cmd;
da285121
DW
318}
319
53c613fe
JK
320static bool stibp_needed(void)
321{
322 if (spectre_v2_enabled == SPECTRE_V2_NONE)
323 return false;
324
34bce7c9
TC
325 /* Enhanced IBRS makes using STIBP unnecessary. */
326 if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED)
327 return false;
328
53c613fe
JK
329 if (!boot_cpu_has(X86_FEATURE_STIBP))
330 return false;
331
332 return true;
333}
334
335static void update_stibp_msr(void *info)
336{
337 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
338}
339
340void arch_smt_update(void)
341{
342 u64 mask;
343
344 if (!stibp_needed())
345 return;
346
347 mutex_lock(&spec_ctrl_mutex);
a74cfffb
TG
348
349 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP;
350 if (sched_smt_active())
53c613fe 351 mask |= SPEC_CTRL_STIBP;
53c613fe
JK
352
353 if (mask != x86_spec_ctrl_base) {
354 pr_info("Spectre v2 cross-process SMT mitigation: %s STIBP\n",
a74cfffb 355 mask & SPEC_CTRL_STIBP ? "Enabling" : "Disabling");
53c613fe
JK
356 x86_spec_ctrl_base = mask;
357 on_each_cpu(update_stibp_msr, NULL, 1);
358 }
359 mutex_unlock(&spec_ctrl_mutex);
360}
361
da285121
DW
362static void __init spectre_v2_select_mitigation(void)
363{
364 enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
365 enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
366
367 /*
368 * If the CPU is not affected and the command line mode is NONE or AUTO
369 * then nothing to do.
370 */
371 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
372 (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
373 return;
374
375 switch (cmd) {
376 case SPECTRE_V2_CMD_NONE:
377 return;
378
379 case SPECTRE_V2_CMD_FORCE:
da285121 380 case SPECTRE_V2_CMD_AUTO:
706d5168
SP
381 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
382 mode = SPECTRE_V2_IBRS_ENHANCED;
383 /* Force it so VMEXIT will restore correctly */
384 x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
385 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
386 goto specv2_set_mode;
387 }
9471eee9
DL
388 if (IS_ENABLED(CONFIG_RETPOLINE))
389 goto retpoline_auto;
390 break;
da285121
DW
391 case SPECTRE_V2_CMD_RETPOLINE_AMD:
392 if (IS_ENABLED(CONFIG_RETPOLINE))
393 goto retpoline_amd;
394 break;
395 case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
396 if (IS_ENABLED(CONFIG_RETPOLINE))
397 goto retpoline_generic;
398 break;
399 case SPECTRE_V2_CMD_RETPOLINE:
400 if (IS_ENABLED(CONFIG_RETPOLINE))
401 goto retpoline_auto;
402 break;
403 }
21e433bd 404 pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
da285121
DW
405 return;
406
407retpoline_auto:
1a576b23
PW
408 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
409 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
da285121
DW
410 retpoline_amd:
411 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
21e433bd 412 pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
da285121
DW
413 goto retpoline_generic;
414 }
ef014aae 415 mode = SPECTRE_V2_RETPOLINE_AMD;
da285121
DW
416 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);
417 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
418 } else {
419 retpoline_generic:
ef014aae 420 mode = SPECTRE_V2_RETPOLINE_GENERIC;
da285121
DW
421 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
422 }
423
706d5168 424specv2_set_mode:
da285121
DW
425 spectre_v2_enabled = mode;
426 pr_info("%s\n", spectre_v2_strings[mode]);
c995efd5
DW
427
428 /*
fdf82a78
JK
429 * If spectre v2 protection has been enabled, unconditionally fill
430 * RSB during a context switch; this protects against two independent
431 * issues:
c995efd5 432 *
fdf82a78
JK
433 * - RSB underflow (and switch to BTB) on Skylake+
434 * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs
c995efd5 435 */
fdf82a78
JK
436 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
437 pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
20ffa1ca
DW
438
439 /* Initialize Indirect Branch Prediction Barrier if supported */
2961298e
DW
440 if (boot_cpu_has(X86_FEATURE_IBPB)) {
441 setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
21e433bd 442 pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n");
20ffa1ca 443 }
dd84441a
DW
444
445 /*
446 * Retpoline means the kernel is safe because it has no indirect
706d5168
SP
447 * branches. Enhanced IBRS protects firmware too, so, enable restricted
448 * speculation around firmware calls only when Enhanced IBRS isn't
449 * supported.
450 *
451 * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
452 * the user might select retpoline on the kernel command line and if
453 * the CPU supports Enhanced IBRS, kernel might un-intentionally not
454 * enable IBRS around firmware calls.
dd84441a 455 */
706d5168 456 if (boot_cpu_has(X86_FEATURE_IBRS) && mode != SPECTRE_V2_IBRS_ENHANCED) {
dd84441a
DW
457 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
458 pr_info("Enabling Restricted Speculation for firmware calls\n");
459 }
53c613fe
JK
460
461 /* Enable STIBP if appropriate */
462 arch_smt_update();
da285121
DW
463}
464
24f7fc83
KRW
465#undef pr_fmt
466#define pr_fmt(fmt) "Speculative Store Bypass: " fmt
467
f9544b2b 468static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
24f7fc83
KRW
469
470/* The kernel command line selection */
471enum ssb_mitigation_cmd {
472 SPEC_STORE_BYPASS_CMD_NONE,
473 SPEC_STORE_BYPASS_CMD_AUTO,
474 SPEC_STORE_BYPASS_CMD_ON,
a73ec77e 475 SPEC_STORE_BYPASS_CMD_PRCTL,
f21b53b2 476 SPEC_STORE_BYPASS_CMD_SECCOMP,
24f7fc83
KRW
477};
478
479static const char *ssb_strings[] = {
480 [SPEC_STORE_BYPASS_NONE] = "Vulnerable",
a73ec77e 481 [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled",
f21b53b2
KC
482 [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl",
483 [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
24f7fc83
KRW
484};
485
486static const struct {
487 const char *option;
488 enum ssb_mitigation_cmd cmd;
489} ssb_mitigation_options[] = {
f21b53b2
KC
490 { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */
491 { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */
492 { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */
493 { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */
494 { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
24f7fc83
KRW
495};
496
497static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
498{
499 enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
500 char arg[20];
501 int ret, i;
502
503 if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) {
504 return SPEC_STORE_BYPASS_CMD_NONE;
505 } else {
506 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
507 arg, sizeof(arg));
508 if (ret < 0)
509 return SPEC_STORE_BYPASS_CMD_AUTO;
510
511 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
512 if (!match_option(arg, ret, ssb_mitigation_options[i].option))
513 continue;
514
515 cmd = ssb_mitigation_options[i].cmd;
516 break;
517 }
518
519 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
520 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
521 return SPEC_STORE_BYPASS_CMD_AUTO;
522 }
523 }
524
525 return cmd;
526}
527
d66d8ff3 528static enum ssb_mitigation __init __ssb_select_mitigation(void)
24f7fc83
KRW
529{
530 enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
531 enum ssb_mitigation_cmd cmd;
532
9f65fb29 533 if (!boot_cpu_has(X86_FEATURE_SSBD))
24f7fc83
KRW
534 return mode;
535
536 cmd = ssb_parse_cmdline();
537 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
538 (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
539 cmd == SPEC_STORE_BYPASS_CMD_AUTO))
540 return mode;
541
542 switch (cmd) {
543 case SPEC_STORE_BYPASS_CMD_AUTO:
f21b53b2
KC
544 case SPEC_STORE_BYPASS_CMD_SECCOMP:
545 /*
546 * Choose prctl+seccomp as the default mode if seccomp is
547 * enabled.
548 */
549 if (IS_ENABLED(CONFIG_SECCOMP))
550 mode = SPEC_STORE_BYPASS_SECCOMP;
551 else
552 mode = SPEC_STORE_BYPASS_PRCTL;
a73ec77e 553 break;
24f7fc83
KRW
554 case SPEC_STORE_BYPASS_CMD_ON:
555 mode = SPEC_STORE_BYPASS_DISABLE;
556 break;
a73ec77e
TG
557 case SPEC_STORE_BYPASS_CMD_PRCTL:
558 mode = SPEC_STORE_BYPASS_PRCTL;
559 break;
24f7fc83
KRW
560 case SPEC_STORE_BYPASS_CMD_NONE:
561 break;
562 }
563
77243971
KRW
564 /*
565 * We have three CPU feature flags that are in play here:
566 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
9f65fb29 567 * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
77243971
KRW
568 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
569 */
a73ec77e 570 if (mode == SPEC_STORE_BYPASS_DISABLE) {
24f7fc83 571 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
77243971 572 /*
6ac2f49e
KRW
573 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
574 * use a completely different MSR and bit dependent on family.
77243971 575 */
612bc3b3
TL
576 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
577 !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
108fab4b 578 x86_amd_ssb_disable();
612bc3b3 579 } else {
9f65fb29 580 x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
be6fcb54 581 x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
4b59bdb5 582 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
77243971
KRW
583 }
584 }
585
24f7fc83
KRW
586 return mode;
587}
588
ffed645e 589static void ssb_select_mitigation(void)
24f7fc83
KRW
590{
591 ssb_mode = __ssb_select_mitigation();
592
593 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
594 pr_info("%s\n", ssb_strings[ssb_mode]);
595}
596
da285121 597#undef pr_fmt
f21b53b2 598#define pr_fmt(fmt) "Speculation prctl: " fmt
da285121 599
7bbf1373 600static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
a73ec77e 601{
356e4bff 602 bool update;
a73ec77e 603
f21b53b2
KC
604 if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
605 ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
a73ec77e
TG
606 return -ENXIO;
607
356e4bff
TG
608 switch (ctrl) {
609 case PR_SPEC_ENABLE:
610 /* If speculation is force disabled, enable is not allowed */
611 if (task_spec_ssb_force_disable(task))
612 return -EPERM;
613 task_clear_spec_ssb_disable(task);
9f65fb29 614 update = test_and_clear_tsk_thread_flag(task, TIF_SSBD);
356e4bff
TG
615 break;
616 case PR_SPEC_DISABLE:
617 task_set_spec_ssb_disable(task);
9f65fb29 618 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
356e4bff
TG
619 break;
620 case PR_SPEC_FORCE_DISABLE:
621 task_set_spec_ssb_disable(task);
622 task_set_spec_ssb_force_disable(task);
9f65fb29 623 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
356e4bff
TG
624 break;
625 default:
626 return -ERANGE;
627 }
a73ec77e 628
7bbf1373
KC
629 /*
630 * If being set on non-current task, delay setting the CPU
631 * mitigation until it is next scheduled.
632 */
356e4bff 633 if (task == current && update)
26c4d75b 634 speculation_ctrl_update_current();
a73ec77e
TG
635
636 return 0;
637}
638
8bf37d8c
TG
639int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
640 unsigned long ctrl)
641{
642 switch (which) {
643 case PR_SPEC_STORE_BYPASS:
644 return ssb_prctl_set(task, ctrl);
645 default:
646 return -ENODEV;
647 }
648}
649
650#ifdef CONFIG_SECCOMP
651void arch_seccomp_spec_mitigate(struct task_struct *task)
652{
f21b53b2
KC
653 if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
654 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
8bf37d8c
TG
655}
656#endif
657
7bbf1373 658static int ssb_prctl_get(struct task_struct *task)
a73ec77e
TG
659{
660 switch (ssb_mode) {
661 case SPEC_STORE_BYPASS_DISABLE:
662 return PR_SPEC_DISABLE;
f21b53b2 663 case SPEC_STORE_BYPASS_SECCOMP:
a73ec77e 664 case SPEC_STORE_BYPASS_PRCTL:
356e4bff
TG
665 if (task_spec_ssb_force_disable(task))
666 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
667 if (task_spec_ssb_disable(task))
a73ec77e
TG
668 return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
669 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
670 default:
671 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
672 return PR_SPEC_ENABLE;
673 return PR_SPEC_NOT_AFFECTED;
674 }
675}
676
7bbf1373 677int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
a73ec77e
TG
678{
679 switch (which) {
680 case PR_SPEC_STORE_BYPASS:
7bbf1373 681 return ssb_prctl_get(task);
a73ec77e
TG
682 default:
683 return -ENODEV;
684 }
685}
686
77243971
KRW
687void x86_spec_ctrl_setup_ap(void)
688{
7eb8956a 689 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
4b59bdb5 690 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
764f3c21
KRW
691
692 if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
9f65fb29 693 x86_amd_ssb_disable();
77243971
KRW
694}
695
56563f53
KRW
696#undef pr_fmt
697#define pr_fmt(fmt) "L1TF: " fmt
72c6d2db 698
d90a7a0e
JK
699/* Default mitigation for L1TF-affected CPUs */
700enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH;
72c6d2db 701#if IS_ENABLED(CONFIG_KVM_INTEL)
d90a7a0e 702EXPORT_SYMBOL_GPL(l1tf_mitigation);
1eb46908 703#endif
895ae47f 704enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
72c6d2db 705EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation);
72c6d2db 706
cc51e542
AK
707/*
708 * These CPUs all support 44bits physical address space internally in the
709 * cache but CPUID can report a smaller number of physical address bits.
710 *
711 * The L1TF mitigation uses the top most address bit for the inversion of
712 * non present PTEs. When the installed memory reaches into the top most
713 * address bit due to memory holes, which has been observed on machines
714 * which report 36bits physical address bits and have 32G RAM installed,
715 * then the mitigation range check in l1tf_select_mitigation() triggers.
716 * This is a false positive because the mitigation is still possible due to
717 * the fact that the cache uses 44bit internally. Use the cache bits
718 * instead of the reported physical bits and adjust them on the affected
719 * machines to 44bit if the reported bits are less than 44.
720 */
721static void override_cache_bits(struct cpuinfo_x86 *c)
722{
723 if (c->x86 != 6)
724 return;
725
726 switch (c->x86_model) {
727 case INTEL_FAM6_NEHALEM:
728 case INTEL_FAM6_WESTMERE:
729 case INTEL_FAM6_SANDYBRIDGE:
730 case INTEL_FAM6_IVYBRIDGE:
731 case INTEL_FAM6_HASWELL_CORE:
732 case INTEL_FAM6_HASWELL_ULT:
733 case INTEL_FAM6_HASWELL_GT3E:
734 case INTEL_FAM6_BROADWELL_CORE:
735 case INTEL_FAM6_BROADWELL_GT3E:
736 case INTEL_FAM6_SKYLAKE_MOBILE:
737 case INTEL_FAM6_SKYLAKE_DESKTOP:
738 case INTEL_FAM6_KABYLAKE_MOBILE:
739 case INTEL_FAM6_KABYLAKE_DESKTOP:
740 if (c->x86_cache_bits < 44)
741 c->x86_cache_bits = 44;
742 break;
743 }
744}
745
56563f53
KRW
746static void __init l1tf_select_mitigation(void)
747{
748 u64 half_pa;
749
750 if (!boot_cpu_has_bug(X86_BUG_L1TF))
751 return;
752
cc51e542
AK
753 override_cache_bits(&boot_cpu_data);
754
d90a7a0e
JK
755 switch (l1tf_mitigation) {
756 case L1TF_MITIGATION_OFF:
757 case L1TF_MITIGATION_FLUSH_NOWARN:
758 case L1TF_MITIGATION_FLUSH:
759 break;
760 case L1TF_MITIGATION_FLUSH_NOSMT:
761 case L1TF_MITIGATION_FULL:
762 cpu_smt_disable(false);
763 break;
764 case L1TF_MITIGATION_FULL_FORCE:
765 cpu_smt_disable(true);
766 break;
767 }
768
56563f53
KRW
769#if CONFIG_PGTABLE_LEVELS == 2
770 pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
771 return;
772#endif
773
56563f53
KRW
774 half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT;
775 if (e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) {
776 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
6a012288
VB
777 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
778 half_pa);
779 pr_info("However, doing so will make a part of your RAM unusable.\n");
780 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html might help you decide.\n");
56563f53
KRW
781 return;
782 }
783
784 setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV);
785}
d90a7a0e
JK
786
787static int __init l1tf_cmdline(char *str)
788{
789 if (!boot_cpu_has_bug(X86_BUG_L1TF))
790 return 0;
791
792 if (!str)
793 return -EINVAL;
794
795 if (!strcmp(str, "off"))
796 l1tf_mitigation = L1TF_MITIGATION_OFF;
797 else if (!strcmp(str, "flush,nowarn"))
798 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN;
799 else if (!strcmp(str, "flush"))
800 l1tf_mitigation = L1TF_MITIGATION_FLUSH;
801 else if (!strcmp(str, "flush,nosmt"))
802 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
803 else if (!strcmp(str, "full"))
804 l1tf_mitigation = L1TF_MITIGATION_FULL;
805 else if (!strcmp(str, "full,force"))
806 l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE;
807
808 return 0;
809}
810early_param("l1tf", l1tf_cmdline);
811
56563f53
KRW
812#undef pr_fmt
813
61dc0f55 814#ifdef CONFIG_SYSFS
d1059518 815
72c6d2db
TG
816#define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
817
818#if IS_ENABLED(CONFIG_KVM_INTEL)
819static const char *l1tf_vmx_states[] = {
a7b9020b
TG
820 [VMENTER_L1D_FLUSH_AUTO] = "auto",
821 [VMENTER_L1D_FLUSH_NEVER] = "vulnerable",
822 [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes",
823 [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes",
824 [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled",
8e0b2b91 825 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary"
72c6d2db
TG
826};
827
828static ssize_t l1tf_show_state(char *buf)
829{
830 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO)
831 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
832
ea156d19
PB
833 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED ||
834 (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER &&
835 cpu_smt_control == CPU_SMT_ENABLED))
836 return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG,
837 l1tf_vmx_states[l1tf_vmx_mitigation]);
838
839 return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG,
840 l1tf_vmx_states[l1tf_vmx_mitigation],
841 cpu_smt_control == CPU_SMT_ENABLED ? "vulnerable" : "disabled");
72c6d2db
TG
842}
843#else
844static ssize_t l1tf_show_state(char *buf)
845{
846 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
847}
848#endif
849
a8f76ae4
TC
850static char *stibp_state(void)
851{
34bce7c9
TC
852 if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED)
853 return "";
854
a8f76ae4
TC
855 if (x86_spec_ctrl_base & SPEC_CTRL_STIBP)
856 return ", STIBP";
857 else
858 return "";
859}
860
861static char *ibpb_state(void)
862{
863 if (boot_cpu_has(X86_FEATURE_USE_IBPB))
864 return ", IBPB";
865 else
866 return "";
867}
868
7bb4d366 869static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
ffed645e 870 char *buf, unsigned int bug)
61dc0f55 871{
d1059518 872 if (!boot_cpu_has_bug(bug))
61dc0f55 873 return sprintf(buf, "Not affected\n");
d1059518
KRW
874
875 switch (bug) {
876 case X86_BUG_CPU_MELTDOWN:
877 if (boot_cpu_has(X86_FEATURE_PTI))
878 return sprintf(buf, "Mitigation: PTI\n");
879
6cb2b08f
JK
880 if (hypervisor_is_type(X86_HYPER_XEN_PV))
881 return sprintf(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n");
882
d1059518
KRW
883 break;
884
885 case X86_BUG_SPECTRE_V1:
886 return sprintf(buf, "Mitigation: __user pointer sanitization\n");
887
888 case X86_BUG_SPECTRE_V2:
b86bda04 889 return sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled],
a8f76ae4 890 ibpb_state(),
d1059518 891 boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
a8f76ae4 892 stibp_state(),
bb4b3b77 893 boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "",
d1059518
KRW
894 spectre_v2_module_string());
895
24f7fc83
KRW
896 case X86_BUG_SPEC_STORE_BYPASS:
897 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
898
17dbca11
AK
899 case X86_BUG_L1TF:
900 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV))
72c6d2db 901 return l1tf_show_state(buf);
17dbca11 902 break;
d1059518
KRW
903 default:
904 break;
905 }
906
61dc0f55
TG
907 return sprintf(buf, "Vulnerable\n");
908}
909
d1059518
KRW
910ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
911{
912 return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
913}
914
21e433bd 915ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
61dc0f55 916{
d1059518 917 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
61dc0f55
TG
918}
919
21e433bd 920ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
61dc0f55 921{
d1059518 922 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
61dc0f55 923}
c456442c
KRW
924
925ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
926{
927 return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
928}
17dbca11
AK
929
930ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
931{
932 return cpu_show_common(dev, attr, buf, X86_BUG_L1TF);
933}
61dc0f55 934#endif