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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1353ebb4 | 2 | /* |
1353ebb4 JF |
3 | * Copyright (C) 1994 Linus Torvalds |
4 | * | |
5 | * Cyrix stuff, June 1998 by: | |
6 | * - Rafael R. Reilova (moved everything from head.S), | |
7 | * <rreilova@ececs.uc.edu> | |
8 | * - Channing Corn (tests & fixes), | |
9 | * - Andrew D. Balsa (code cleanup). | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/utsname.h> | |
61dc0f55 | 13 | #include <linux/cpu.h> |
caf7501a | 14 | #include <linux/module.h> |
da285121 DW |
15 | |
16 | #include <asm/nospec-branch.h> | |
17 | #include <asm/cmdline.h> | |
91eb1b79 | 18 | #include <asm/bugs.h> |
1353ebb4 | 19 | #include <asm/processor.h> |
7ebad705 | 20 | #include <asm/processor-flags.h> |
952f07ec | 21 | #include <asm/fpu/internal.h> |
1353ebb4 JF |
22 | #include <asm/msr.h> |
23 | #include <asm/paravirt.h> | |
24 | #include <asm/alternative.h> | |
62a67e12 | 25 | #include <asm/pgtable.h> |
d1163651 | 26 | #include <asm/set_memory.h> |
c995efd5 | 27 | #include <asm/intel-family.h> |
1353ebb4 | 28 | |
da285121 | 29 | static void __init spectre_v2_select_mitigation(void); |
24f7fc83 | 30 | static void __init ssb_select_mitigation(void); |
da285121 | 31 | |
1b86883c KRW |
32 | /* |
33 | * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any | |
34 | * writes to SPEC_CTRL contain whatever reserved bits have been set. | |
35 | */ | |
36 | static u64 __ro_after_init x86_spec_ctrl_base; | |
37 | ||
1115a859 KRW |
38 | /* |
39 | * The vendor and possibly platform specific bits which can be modified in | |
40 | * x86_spec_ctrl_base. | |
41 | */ | |
42 | static u64 __ro_after_init x86_spec_ctrl_mask = ~SPEC_CTRL_IBRS; | |
43 | ||
764f3c21 KRW |
44 | /* |
45 | * AMD specific MSR info for Speculative Store Bypass control. | |
46 | * x86_amd_ls_cfg_rds_mask is initialized in identify_boot_cpu(). | |
47 | */ | |
48 | u64 __ro_after_init x86_amd_ls_cfg_base; | |
49 | u64 __ro_after_init x86_amd_ls_cfg_rds_mask; | |
50 | ||
1353ebb4 JF |
51 | void __init check_bugs(void) |
52 | { | |
53 | identify_boot_cpu(); | |
55a36b65 | 54 | |
62a67e12 BP |
55 | if (!IS_ENABLED(CONFIG_SMP)) { |
56 | pr_info("CPU: "); | |
57 | print_cpu_info(&boot_cpu_data); | |
58 | } | |
59 | ||
1b86883c KRW |
60 | /* |
61 | * Read the SPEC_CTRL MSR to account for reserved bits which may | |
764f3c21 KRW |
62 | * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD |
63 | * init code as it is not enumerated and depends on the family. | |
1b86883c KRW |
64 | */ |
65 | if (boot_cpu_has(X86_FEATURE_IBRS)) | |
66 | rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); | |
67 | ||
da285121 DW |
68 | /* Select the proper spectre mitigation before patching alternatives */ |
69 | spectre_v2_select_mitigation(); | |
70 | ||
24f7fc83 KRW |
71 | /* |
72 | * Select proper mitigation for any exposure to the Speculative Store | |
73 | * Bypass vulnerability. | |
74 | */ | |
75 | ssb_select_mitigation(); | |
76 | ||
62a67e12 | 77 | #ifdef CONFIG_X86_32 |
55a36b65 BP |
78 | /* |
79 | * Check whether we are able to run this kernel safely on SMP. | |
80 | * | |
81 | * - i386 is no longer supported. | |
82 | * - In order to run on anything without a TSC, we need to be | |
83 | * compiled for a i486. | |
84 | */ | |
85 | if (boot_cpu_data.x86 < 4) | |
86 | panic("Kernel requires i486+ for 'invlpg' and other features"); | |
87 | ||
bfe4bb15 MV |
88 | init_utsname()->machine[1] = |
89 | '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); | |
1353ebb4 | 90 | alternative_instructions(); |
304bceda | 91 | |
4d164092 | 92 | fpu__init_check_bugs(); |
62a67e12 BP |
93 | #else /* CONFIG_X86_64 */ |
94 | alternative_instructions(); | |
95 | ||
96 | /* | |
97 | * Make sure the first 2MB area is not mapped by huge pages | |
98 | * There are typically fixed size MTRRs in there and overlapping | |
99 | * MTRRs into large pages causes slow downs. | |
100 | * | |
101 | * Right now we don't do that with gbpages because there seems | |
102 | * very little benefit for that case. | |
103 | */ | |
104 | if (!direct_gbpages) | |
105 | set_memory_4k((unsigned long)__va(0), 1); | |
106 | #endif | |
1353ebb4 | 107 | } |
61dc0f55 | 108 | |
da285121 DW |
109 | /* The kernel command line selection */ |
110 | enum spectre_v2_mitigation_cmd { | |
111 | SPECTRE_V2_CMD_NONE, | |
112 | SPECTRE_V2_CMD_AUTO, | |
113 | SPECTRE_V2_CMD_FORCE, | |
114 | SPECTRE_V2_CMD_RETPOLINE, | |
115 | SPECTRE_V2_CMD_RETPOLINE_GENERIC, | |
116 | SPECTRE_V2_CMD_RETPOLINE_AMD, | |
117 | }; | |
118 | ||
119 | static const char *spectre_v2_strings[] = { | |
120 | [SPECTRE_V2_NONE] = "Vulnerable", | |
121 | [SPECTRE_V2_RETPOLINE_MINIMAL] = "Vulnerable: Minimal generic ASM retpoline", | |
122 | [SPECTRE_V2_RETPOLINE_MINIMAL_AMD] = "Vulnerable: Minimal AMD ASM retpoline", | |
123 | [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", | |
124 | [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", | |
125 | }; | |
126 | ||
127 | #undef pr_fmt | |
55fa19d3 | 128 | #define pr_fmt(fmt) "Spectre V2 : " fmt |
da285121 DW |
129 | |
130 | static enum spectre_v2_mitigation spectre_v2_enabled = SPECTRE_V2_NONE; | |
caf7501a | 131 | |
1b86883c KRW |
132 | void x86_spec_ctrl_set(u64 val) |
133 | { | |
1115a859 | 134 | if (val & x86_spec_ctrl_mask) |
1b86883c KRW |
135 | WARN_ONCE(1, "SPEC_CTRL MSR value 0x%16llx is unknown.\n", val); |
136 | else | |
137 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base | val); | |
138 | } | |
139 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_set); | |
140 | ||
141 | u64 x86_spec_ctrl_get_default(void) | |
142 | { | |
143 | return x86_spec_ctrl_base; | |
144 | } | |
145 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_get_default); | |
146 | ||
5cf68754 KRW |
147 | void x86_spec_ctrl_set_guest(u64 guest_spec_ctrl) |
148 | { | |
149 | if (!boot_cpu_has(X86_FEATURE_IBRS)) | |
150 | return; | |
151 | if (x86_spec_ctrl_base != guest_spec_ctrl) | |
152 | wrmsrl(MSR_IA32_SPEC_CTRL, guest_spec_ctrl); | |
153 | } | |
154 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_set_guest); | |
155 | ||
156 | void x86_spec_ctrl_restore_host(u64 guest_spec_ctrl) | |
157 | { | |
158 | if (!boot_cpu_has(X86_FEATURE_IBRS)) | |
159 | return; | |
160 | if (x86_spec_ctrl_base != guest_spec_ctrl) | |
161 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); | |
162 | } | |
163 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_restore_host); | |
164 | ||
764f3c21 KRW |
165 | static void x86_amd_rds_enable(void) |
166 | { | |
167 | u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_rds_mask; | |
168 | ||
169 | if (boot_cpu_has(X86_FEATURE_AMD_RDS)) | |
170 | wrmsrl(MSR_AMD64_LS_CFG, msrval); | |
171 | } | |
172 | ||
caf7501a | 173 | #ifdef RETPOLINE |
e383095c TG |
174 | static bool spectre_v2_bad_module; |
175 | ||
caf7501a AK |
176 | bool retpoline_module_ok(bool has_retpoline) |
177 | { | |
178 | if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) | |
179 | return true; | |
180 | ||
e698dcdf | 181 | pr_err("System may be vulnerable to spectre v2\n"); |
caf7501a AK |
182 | spectre_v2_bad_module = true; |
183 | return false; | |
184 | } | |
e383095c TG |
185 | |
186 | static inline const char *spectre_v2_module_string(void) | |
187 | { | |
188 | return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; | |
189 | } | |
190 | #else | |
191 | static inline const char *spectre_v2_module_string(void) { return ""; } | |
caf7501a | 192 | #endif |
da285121 DW |
193 | |
194 | static void __init spec2_print_if_insecure(const char *reason) | |
195 | { | |
196 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
9005c683 | 197 | pr_info("%s selected on command line.\n", reason); |
da285121 DW |
198 | } |
199 | ||
200 | static void __init spec2_print_if_secure(const char *reason) | |
201 | { | |
202 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
9005c683 | 203 | pr_info("%s selected on command line.\n", reason); |
da285121 DW |
204 | } |
205 | ||
206 | static inline bool retp_compiler(void) | |
207 | { | |
208 | return __is_defined(RETPOLINE); | |
209 | } | |
210 | ||
211 | static inline bool match_option(const char *arg, int arglen, const char *opt) | |
212 | { | |
213 | int len = strlen(opt); | |
214 | ||
215 | return len == arglen && !strncmp(arg, opt, len); | |
216 | } | |
217 | ||
9005c683 KA |
218 | static const struct { |
219 | const char *option; | |
220 | enum spectre_v2_mitigation_cmd cmd; | |
221 | bool secure; | |
222 | } mitigation_options[] = { | |
223 | { "off", SPECTRE_V2_CMD_NONE, false }, | |
224 | { "on", SPECTRE_V2_CMD_FORCE, true }, | |
225 | { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, | |
226 | { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false }, | |
227 | { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, | |
228 | { "auto", SPECTRE_V2_CMD_AUTO, false }, | |
229 | }; | |
230 | ||
da285121 DW |
231 | static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) |
232 | { | |
233 | char arg[20]; | |
9005c683 KA |
234 | int ret, i; |
235 | enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; | |
236 | ||
237 | if (cmdline_find_option_bool(boot_command_line, "nospectre_v2")) | |
238 | return SPECTRE_V2_CMD_NONE; | |
239 | else { | |
21e433bd | 240 | ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); |
9005c683 KA |
241 | if (ret < 0) |
242 | return SPECTRE_V2_CMD_AUTO; | |
243 | ||
244 | for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { | |
245 | if (!match_option(arg, ret, mitigation_options[i].option)) | |
246 | continue; | |
247 | cmd = mitigation_options[i].cmd; | |
248 | break; | |
249 | } | |
250 | ||
251 | if (i >= ARRAY_SIZE(mitigation_options)) { | |
9de29eac | 252 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); |
da285121 DW |
253 | return SPECTRE_V2_CMD_AUTO; |
254 | } | |
255 | } | |
256 | ||
9005c683 KA |
257 | if ((cmd == SPECTRE_V2_CMD_RETPOLINE || |
258 | cmd == SPECTRE_V2_CMD_RETPOLINE_AMD || | |
259 | cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) && | |
260 | !IS_ENABLED(CONFIG_RETPOLINE)) { | |
21e433bd | 261 | pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option); |
da285121 | 262 | return SPECTRE_V2_CMD_AUTO; |
9005c683 KA |
263 | } |
264 | ||
265 | if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD && | |
266 | boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { | |
267 | pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n"); | |
268 | return SPECTRE_V2_CMD_AUTO; | |
269 | } | |
270 | ||
271 | if (mitigation_options[i].secure) | |
272 | spec2_print_if_secure(mitigation_options[i].option); | |
273 | else | |
274 | spec2_print_if_insecure(mitigation_options[i].option); | |
275 | ||
276 | return cmd; | |
da285121 DW |
277 | } |
278 | ||
c995efd5 DW |
279 | /* Check for Skylake-like CPUs (for RSB handling) */ |
280 | static bool __init is_skylake_era(void) | |
281 | { | |
282 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
283 | boot_cpu_data.x86 == 6) { | |
284 | switch (boot_cpu_data.x86_model) { | |
285 | case INTEL_FAM6_SKYLAKE_MOBILE: | |
286 | case INTEL_FAM6_SKYLAKE_DESKTOP: | |
287 | case INTEL_FAM6_SKYLAKE_X: | |
288 | case INTEL_FAM6_KABYLAKE_MOBILE: | |
289 | case INTEL_FAM6_KABYLAKE_DESKTOP: | |
290 | return true; | |
291 | } | |
292 | } | |
293 | return false; | |
294 | } | |
295 | ||
da285121 DW |
296 | static void __init spectre_v2_select_mitigation(void) |
297 | { | |
298 | enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); | |
299 | enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; | |
300 | ||
301 | /* | |
302 | * If the CPU is not affected and the command line mode is NONE or AUTO | |
303 | * then nothing to do. | |
304 | */ | |
305 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && | |
306 | (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) | |
307 | return; | |
308 | ||
309 | switch (cmd) { | |
310 | case SPECTRE_V2_CMD_NONE: | |
311 | return; | |
312 | ||
313 | case SPECTRE_V2_CMD_FORCE: | |
da285121 | 314 | case SPECTRE_V2_CMD_AUTO: |
9471eee9 DL |
315 | if (IS_ENABLED(CONFIG_RETPOLINE)) |
316 | goto retpoline_auto; | |
317 | break; | |
da285121 DW |
318 | case SPECTRE_V2_CMD_RETPOLINE_AMD: |
319 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
320 | goto retpoline_amd; | |
321 | break; | |
322 | case SPECTRE_V2_CMD_RETPOLINE_GENERIC: | |
323 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
324 | goto retpoline_generic; | |
325 | break; | |
326 | case SPECTRE_V2_CMD_RETPOLINE: | |
327 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
328 | goto retpoline_auto; | |
329 | break; | |
330 | } | |
21e433bd | 331 | pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!"); |
da285121 DW |
332 | return; |
333 | ||
334 | retpoline_auto: | |
335 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { | |
336 | retpoline_amd: | |
337 | if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { | |
21e433bd | 338 | pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n"); |
da285121 DW |
339 | goto retpoline_generic; |
340 | } | |
341 | mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD : | |
342 | SPECTRE_V2_RETPOLINE_MINIMAL_AMD; | |
343 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD); | |
344 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
345 | } else { | |
346 | retpoline_generic: | |
347 | mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC : | |
348 | SPECTRE_V2_RETPOLINE_MINIMAL; | |
349 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
350 | } | |
351 | ||
352 | spectre_v2_enabled = mode; | |
353 | pr_info("%s\n", spectre_v2_strings[mode]); | |
c995efd5 DW |
354 | |
355 | /* | |
21e433bd | 356 | * If neither SMEP nor PTI are available, there is a risk of |
c995efd5 DW |
357 | * hitting userspace addresses in the RSB after a context switch |
358 | * from a shallow call stack to a deeper one. To prevent this fill | |
359 | * the entire RSB, even when using IBRS. | |
360 | * | |
361 | * Skylake era CPUs have a separate issue with *underflow* of the | |
362 | * RSB, when they will predict 'ret' targets from the generic BTB. | |
363 | * The proper mitigation for this is IBRS. If IBRS is not supported | |
364 | * or deactivated in favour of retpolines the RSB fill on context | |
365 | * switch is required. | |
366 | */ | |
367 | if ((!boot_cpu_has(X86_FEATURE_PTI) && | |
368 | !boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) { | |
369 | setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); | |
21e433bd | 370 | pr_info("Spectre v2 mitigation: Filling RSB on context switch\n"); |
c995efd5 | 371 | } |
20ffa1ca DW |
372 | |
373 | /* Initialize Indirect Branch Prediction Barrier if supported */ | |
2961298e DW |
374 | if (boot_cpu_has(X86_FEATURE_IBPB)) { |
375 | setup_force_cpu_cap(X86_FEATURE_USE_IBPB); | |
21e433bd | 376 | pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n"); |
20ffa1ca | 377 | } |
dd84441a DW |
378 | |
379 | /* | |
380 | * Retpoline means the kernel is safe because it has no indirect | |
381 | * branches. But firmware isn't, so use IBRS to protect that. | |
382 | */ | |
383 | if (boot_cpu_has(X86_FEATURE_IBRS)) { | |
384 | setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); | |
385 | pr_info("Enabling Restricted Speculation for firmware calls\n"); | |
386 | } | |
da285121 DW |
387 | } |
388 | ||
24f7fc83 KRW |
389 | #undef pr_fmt |
390 | #define pr_fmt(fmt) "Speculative Store Bypass: " fmt | |
391 | ||
392 | static enum ssb_mitigation ssb_mode = SPEC_STORE_BYPASS_NONE; | |
393 | ||
394 | /* The kernel command line selection */ | |
395 | enum ssb_mitigation_cmd { | |
396 | SPEC_STORE_BYPASS_CMD_NONE, | |
397 | SPEC_STORE_BYPASS_CMD_AUTO, | |
398 | SPEC_STORE_BYPASS_CMD_ON, | |
399 | }; | |
400 | ||
401 | static const char *ssb_strings[] = { | |
402 | [SPEC_STORE_BYPASS_NONE] = "Vulnerable", | |
403 | [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled" | |
404 | }; | |
405 | ||
406 | static const struct { | |
407 | const char *option; | |
408 | enum ssb_mitigation_cmd cmd; | |
409 | } ssb_mitigation_options[] = { | |
410 | { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ | |
411 | { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ | |
412 | { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ | |
413 | }; | |
414 | ||
415 | static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) | |
416 | { | |
417 | enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO; | |
418 | char arg[20]; | |
419 | int ret, i; | |
420 | ||
421 | if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) { | |
422 | return SPEC_STORE_BYPASS_CMD_NONE; | |
423 | } else { | |
424 | ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", | |
425 | arg, sizeof(arg)); | |
426 | if (ret < 0) | |
427 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
428 | ||
429 | for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { | |
430 | if (!match_option(arg, ret, ssb_mitigation_options[i].option)) | |
431 | continue; | |
432 | ||
433 | cmd = ssb_mitigation_options[i].cmd; | |
434 | break; | |
435 | } | |
436 | ||
437 | if (i >= ARRAY_SIZE(ssb_mitigation_options)) { | |
438 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
439 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
440 | } | |
441 | } | |
442 | ||
443 | return cmd; | |
444 | } | |
445 | ||
446 | static enum ssb_mitigation_cmd __init __ssb_select_mitigation(void) | |
447 | { | |
448 | enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; | |
449 | enum ssb_mitigation_cmd cmd; | |
450 | ||
451 | if (!boot_cpu_has(X86_FEATURE_RDS)) | |
452 | return mode; | |
453 | ||
454 | cmd = ssb_parse_cmdline(); | |
455 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && | |
456 | (cmd == SPEC_STORE_BYPASS_CMD_NONE || | |
457 | cmd == SPEC_STORE_BYPASS_CMD_AUTO)) | |
458 | return mode; | |
459 | ||
460 | switch (cmd) { | |
461 | case SPEC_STORE_BYPASS_CMD_AUTO: | |
764f3c21 KRW |
462 | /* |
463 | * AMD platforms by default don't need SSB mitigation. | |
464 | */ | |
465 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
466 | break; | |
24f7fc83 KRW |
467 | case SPEC_STORE_BYPASS_CMD_ON: |
468 | mode = SPEC_STORE_BYPASS_DISABLE; | |
469 | break; | |
470 | case SPEC_STORE_BYPASS_CMD_NONE: | |
471 | break; | |
472 | } | |
473 | ||
77243971 KRW |
474 | /* |
475 | * We have three CPU feature flags that are in play here: | |
476 | * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. | |
477 | * - X86_FEATURE_RDS - CPU is able to turn off speculative store bypass | |
478 | * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation | |
479 | */ | |
480 | if (mode != SPEC_STORE_BYPASS_NONE) { | |
24f7fc83 | 481 | setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); |
77243971 KRW |
482 | /* |
483 | * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD uses | |
484 | * a completely different MSR and bit dependent on family. | |
485 | */ | |
486 | switch (boot_cpu_data.x86_vendor) { | |
487 | case X86_VENDOR_INTEL: | |
488 | x86_spec_ctrl_base |= SPEC_CTRL_RDS; | |
1115a859 | 489 | x86_spec_ctrl_mask &= ~SPEC_CTRL_RDS; |
77243971 KRW |
490 | x86_spec_ctrl_set(SPEC_CTRL_RDS); |
491 | break; | |
492 | case X86_VENDOR_AMD: | |
764f3c21 | 493 | x86_amd_rds_enable(); |
77243971 KRW |
494 | break; |
495 | } | |
496 | } | |
497 | ||
24f7fc83 KRW |
498 | return mode; |
499 | } | |
500 | ||
501 | static void ssb_select_mitigation() | |
502 | { | |
503 | ssb_mode = __ssb_select_mitigation(); | |
504 | ||
505 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
506 | pr_info("%s\n", ssb_strings[ssb_mode]); | |
507 | } | |
508 | ||
da285121 DW |
509 | #undef pr_fmt |
510 | ||
77243971 KRW |
511 | void x86_spec_ctrl_setup_ap(void) |
512 | { | |
513 | if (boot_cpu_has(X86_FEATURE_IBRS)) | |
1115a859 | 514 | x86_spec_ctrl_set(x86_spec_ctrl_base & ~x86_spec_ctrl_mask); |
764f3c21 KRW |
515 | |
516 | if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) | |
517 | x86_amd_rds_enable(); | |
77243971 KRW |
518 | } |
519 | ||
61dc0f55 | 520 | #ifdef CONFIG_SYSFS |
d1059518 KRW |
521 | |
522 | ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, | |
523 | char *buf, unsigned int bug) | |
61dc0f55 | 524 | { |
d1059518 | 525 | if (!boot_cpu_has_bug(bug)) |
61dc0f55 | 526 | return sprintf(buf, "Not affected\n"); |
d1059518 KRW |
527 | |
528 | switch (bug) { | |
529 | case X86_BUG_CPU_MELTDOWN: | |
530 | if (boot_cpu_has(X86_FEATURE_PTI)) | |
531 | return sprintf(buf, "Mitigation: PTI\n"); | |
532 | ||
533 | break; | |
534 | ||
535 | case X86_BUG_SPECTRE_V1: | |
536 | return sprintf(buf, "Mitigation: __user pointer sanitization\n"); | |
537 | ||
538 | case X86_BUG_SPECTRE_V2: | |
539 | return sprintf(buf, "%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], | |
540 | boot_cpu_has(X86_FEATURE_USE_IBPB) ? ", IBPB" : "", | |
541 | boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", | |
542 | spectre_v2_module_string()); | |
543 | ||
24f7fc83 KRW |
544 | case X86_BUG_SPEC_STORE_BYPASS: |
545 | return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); | |
546 | ||
d1059518 KRW |
547 | default: |
548 | break; | |
549 | } | |
550 | ||
61dc0f55 TG |
551 | return sprintf(buf, "Vulnerable\n"); |
552 | } | |
553 | ||
d1059518 KRW |
554 | ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) |
555 | { | |
556 | return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); | |
557 | } | |
558 | ||
21e433bd | 559 | ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 560 | { |
d1059518 | 561 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); |
61dc0f55 TG |
562 | } |
563 | ||
21e433bd | 564 | ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 565 | { |
d1059518 | 566 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); |
61dc0f55 | 567 | } |
c456442c KRW |
568 | |
569 | ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) | |
570 | { | |
571 | return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); | |
572 | } | |
61dc0f55 | 573 | #endif |