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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1353ebb4 | 2 | /* |
1353ebb4 JF |
3 | * Copyright (C) 1994 Linus Torvalds |
4 | * | |
5 | * Cyrix stuff, June 1998 by: | |
6 | * - Rafael R. Reilova (moved everything from head.S), | |
7 | * <rreilova@ececs.uc.edu> | |
8 | * - Channing Corn (tests & fixes), | |
9 | * - Andrew D. Balsa (code cleanup). | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/utsname.h> | |
61dc0f55 | 13 | #include <linux/cpu.h> |
caf7501a | 14 | #include <linux/module.h> |
a73ec77e TG |
15 | #include <linux/nospec.h> |
16 | #include <linux/prctl.h> | |
da285121 | 17 | |
28a27752 | 18 | #include <asm/spec-ctrl.h> |
da285121 | 19 | #include <asm/cmdline.h> |
91eb1b79 | 20 | #include <asm/bugs.h> |
1353ebb4 | 21 | #include <asm/processor.h> |
7ebad705 | 22 | #include <asm/processor-flags.h> |
952f07ec | 23 | #include <asm/fpu/internal.h> |
1353ebb4 JF |
24 | #include <asm/msr.h> |
25 | #include <asm/paravirt.h> | |
26 | #include <asm/alternative.h> | |
62a67e12 | 27 | #include <asm/pgtable.h> |
d1163651 | 28 | #include <asm/set_memory.h> |
c995efd5 | 29 | #include <asm/intel-family.h> |
1353ebb4 | 30 | |
da285121 | 31 | static void __init spectre_v2_select_mitigation(void); |
24f7fc83 | 32 | static void __init ssb_select_mitigation(void); |
da285121 | 33 | |
1b86883c KRW |
34 | /* |
35 | * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any | |
36 | * writes to SPEC_CTRL contain whatever reserved bits have been set. | |
37 | */ | |
885f82bf | 38 | u64 __ro_after_init x86_spec_ctrl_base; |
1b86883c | 39 | |
1115a859 KRW |
40 | /* |
41 | * The vendor and possibly platform specific bits which can be modified in | |
42 | * x86_spec_ctrl_base. | |
43 | */ | |
44 | static u64 __ro_after_init x86_spec_ctrl_mask = ~SPEC_CTRL_IBRS; | |
45 | ||
764f3c21 KRW |
46 | /* |
47 | * AMD specific MSR info for Speculative Store Bypass control. | |
9f65fb29 | 48 | * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). |
764f3c21 KRW |
49 | */ |
50 | u64 __ro_after_init x86_amd_ls_cfg_base; | |
9f65fb29 | 51 | u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; |
764f3c21 | 52 | |
1353ebb4 JF |
53 | void __init check_bugs(void) |
54 | { | |
55 | identify_boot_cpu(); | |
55a36b65 | 56 | |
62a67e12 BP |
57 | if (!IS_ENABLED(CONFIG_SMP)) { |
58 | pr_info("CPU: "); | |
59 | print_cpu_info(&boot_cpu_data); | |
60 | } | |
61 | ||
1b86883c KRW |
62 | /* |
63 | * Read the SPEC_CTRL MSR to account for reserved bits which may | |
764f3c21 KRW |
64 | * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD |
65 | * init code as it is not enumerated and depends on the family. | |
1b86883c KRW |
66 | */ |
67 | if (boot_cpu_has(X86_FEATURE_IBRS)) | |
68 | rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); | |
69 | ||
da285121 DW |
70 | /* Select the proper spectre mitigation before patching alternatives */ |
71 | spectre_v2_select_mitigation(); | |
72 | ||
24f7fc83 KRW |
73 | /* |
74 | * Select proper mitigation for any exposure to the Speculative Store | |
75 | * Bypass vulnerability. | |
76 | */ | |
77 | ssb_select_mitigation(); | |
78 | ||
62a67e12 | 79 | #ifdef CONFIG_X86_32 |
55a36b65 BP |
80 | /* |
81 | * Check whether we are able to run this kernel safely on SMP. | |
82 | * | |
83 | * - i386 is no longer supported. | |
84 | * - In order to run on anything without a TSC, we need to be | |
85 | * compiled for a i486. | |
86 | */ | |
87 | if (boot_cpu_data.x86 < 4) | |
88 | panic("Kernel requires i486+ for 'invlpg' and other features"); | |
89 | ||
bfe4bb15 MV |
90 | init_utsname()->machine[1] = |
91 | '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); | |
1353ebb4 | 92 | alternative_instructions(); |
304bceda | 93 | |
4d164092 | 94 | fpu__init_check_bugs(); |
62a67e12 BP |
95 | #else /* CONFIG_X86_64 */ |
96 | alternative_instructions(); | |
97 | ||
98 | /* | |
99 | * Make sure the first 2MB area is not mapped by huge pages | |
100 | * There are typically fixed size MTRRs in there and overlapping | |
101 | * MTRRs into large pages causes slow downs. | |
102 | * | |
103 | * Right now we don't do that with gbpages because there seems | |
104 | * very little benefit for that case. | |
105 | */ | |
106 | if (!direct_gbpages) | |
107 | set_memory_4k((unsigned long)__va(0), 1); | |
108 | #endif | |
1353ebb4 | 109 | } |
61dc0f55 | 110 | |
da285121 DW |
111 | /* The kernel command line selection */ |
112 | enum spectre_v2_mitigation_cmd { | |
113 | SPECTRE_V2_CMD_NONE, | |
114 | SPECTRE_V2_CMD_AUTO, | |
115 | SPECTRE_V2_CMD_FORCE, | |
116 | SPECTRE_V2_CMD_RETPOLINE, | |
117 | SPECTRE_V2_CMD_RETPOLINE_GENERIC, | |
118 | SPECTRE_V2_CMD_RETPOLINE_AMD, | |
119 | }; | |
120 | ||
121 | static const char *spectre_v2_strings[] = { | |
122 | [SPECTRE_V2_NONE] = "Vulnerable", | |
123 | [SPECTRE_V2_RETPOLINE_MINIMAL] = "Vulnerable: Minimal generic ASM retpoline", | |
124 | [SPECTRE_V2_RETPOLINE_MINIMAL_AMD] = "Vulnerable: Minimal AMD ASM retpoline", | |
125 | [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", | |
126 | [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", | |
127 | }; | |
128 | ||
129 | #undef pr_fmt | |
55fa19d3 | 130 | #define pr_fmt(fmt) "Spectre V2 : " fmt |
da285121 | 131 | |
f9544b2b KC |
132 | static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = |
133 | SPECTRE_V2_NONE; | |
caf7501a | 134 | |
1b86883c KRW |
135 | void x86_spec_ctrl_set(u64 val) |
136 | { | |
1115a859 | 137 | if (val & x86_spec_ctrl_mask) |
1b86883c KRW |
138 | WARN_ONCE(1, "SPEC_CTRL MSR value 0x%16llx is unknown.\n", val); |
139 | else | |
140 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base | val); | |
141 | } | |
142 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_set); | |
143 | ||
144 | u64 x86_spec_ctrl_get_default(void) | |
145 | { | |
885f82bf TG |
146 | u64 msrval = x86_spec_ctrl_base; |
147 | ||
148 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) | |
9f65fb29 | 149 | msrval |= ssbd_tif_to_spec_ctrl(current_thread_info()->flags); |
885f82bf | 150 | return msrval; |
1b86883c KRW |
151 | } |
152 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_get_default); | |
153 | ||
5cf68754 KRW |
154 | void x86_spec_ctrl_set_guest(u64 guest_spec_ctrl) |
155 | { | |
885f82bf TG |
156 | u64 host = x86_spec_ctrl_base; |
157 | ||
5cf68754 KRW |
158 | if (!boot_cpu_has(X86_FEATURE_IBRS)) |
159 | return; | |
885f82bf TG |
160 | |
161 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) | |
9f65fb29 | 162 | host |= ssbd_tif_to_spec_ctrl(current_thread_info()->flags); |
885f82bf TG |
163 | |
164 | if (host != guest_spec_ctrl) | |
5cf68754 KRW |
165 | wrmsrl(MSR_IA32_SPEC_CTRL, guest_spec_ctrl); |
166 | } | |
167 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_set_guest); | |
168 | ||
169 | void x86_spec_ctrl_restore_host(u64 guest_spec_ctrl) | |
170 | { | |
885f82bf TG |
171 | u64 host = x86_spec_ctrl_base; |
172 | ||
5cf68754 KRW |
173 | if (!boot_cpu_has(X86_FEATURE_IBRS)) |
174 | return; | |
885f82bf TG |
175 | |
176 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) | |
9f65fb29 | 177 | host |= ssbd_tif_to_spec_ctrl(current_thread_info()->flags); |
885f82bf TG |
178 | |
179 | if (host != guest_spec_ctrl) | |
180 | wrmsrl(MSR_IA32_SPEC_CTRL, host); | |
5cf68754 KRW |
181 | } |
182 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_restore_host); | |
183 | ||
9f65fb29 | 184 | static void x86_amd_ssb_disable(void) |
764f3c21 | 185 | { |
9f65fb29 | 186 | u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; |
764f3c21 | 187 | |
9f65fb29 | 188 | if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) |
764f3c21 KRW |
189 | wrmsrl(MSR_AMD64_LS_CFG, msrval); |
190 | } | |
191 | ||
caf7501a | 192 | #ifdef RETPOLINE |
e383095c TG |
193 | static bool spectre_v2_bad_module; |
194 | ||
caf7501a AK |
195 | bool retpoline_module_ok(bool has_retpoline) |
196 | { | |
197 | if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) | |
198 | return true; | |
199 | ||
e698dcdf | 200 | pr_err("System may be vulnerable to spectre v2\n"); |
caf7501a AK |
201 | spectre_v2_bad_module = true; |
202 | return false; | |
203 | } | |
e383095c TG |
204 | |
205 | static inline const char *spectre_v2_module_string(void) | |
206 | { | |
207 | return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; | |
208 | } | |
209 | #else | |
210 | static inline const char *spectre_v2_module_string(void) { return ""; } | |
caf7501a | 211 | #endif |
da285121 DW |
212 | |
213 | static void __init spec2_print_if_insecure(const char *reason) | |
214 | { | |
215 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
9005c683 | 216 | pr_info("%s selected on command line.\n", reason); |
da285121 DW |
217 | } |
218 | ||
219 | static void __init spec2_print_if_secure(const char *reason) | |
220 | { | |
221 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
9005c683 | 222 | pr_info("%s selected on command line.\n", reason); |
da285121 DW |
223 | } |
224 | ||
225 | static inline bool retp_compiler(void) | |
226 | { | |
227 | return __is_defined(RETPOLINE); | |
228 | } | |
229 | ||
230 | static inline bool match_option(const char *arg, int arglen, const char *opt) | |
231 | { | |
232 | int len = strlen(opt); | |
233 | ||
234 | return len == arglen && !strncmp(arg, opt, len); | |
235 | } | |
236 | ||
9005c683 KA |
237 | static const struct { |
238 | const char *option; | |
239 | enum spectre_v2_mitigation_cmd cmd; | |
240 | bool secure; | |
241 | } mitigation_options[] = { | |
242 | { "off", SPECTRE_V2_CMD_NONE, false }, | |
243 | { "on", SPECTRE_V2_CMD_FORCE, true }, | |
244 | { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, | |
245 | { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false }, | |
246 | { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, | |
247 | { "auto", SPECTRE_V2_CMD_AUTO, false }, | |
248 | }; | |
249 | ||
da285121 DW |
250 | static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) |
251 | { | |
252 | char arg[20]; | |
9005c683 KA |
253 | int ret, i; |
254 | enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; | |
255 | ||
256 | if (cmdline_find_option_bool(boot_command_line, "nospectre_v2")) | |
257 | return SPECTRE_V2_CMD_NONE; | |
258 | else { | |
21e433bd | 259 | ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); |
9005c683 KA |
260 | if (ret < 0) |
261 | return SPECTRE_V2_CMD_AUTO; | |
262 | ||
263 | for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { | |
264 | if (!match_option(arg, ret, mitigation_options[i].option)) | |
265 | continue; | |
266 | cmd = mitigation_options[i].cmd; | |
267 | break; | |
268 | } | |
269 | ||
270 | if (i >= ARRAY_SIZE(mitigation_options)) { | |
9de29eac | 271 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); |
da285121 DW |
272 | return SPECTRE_V2_CMD_AUTO; |
273 | } | |
274 | } | |
275 | ||
9005c683 KA |
276 | if ((cmd == SPECTRE_V2_CMD_RETPOLINE || |
277 | cmd == SPECTRE_V2_CMD_RETPOLINE_AMD || | |
278 | cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) && | |
279 | !IS_ENABLED(CONFIG_RETPOLINE)) { | |
21e433bd | 280 | pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option); |
da285121 | 281 | return SPECTRE_V2_CMD_AUTO; |
9005c683 KA |
282 | } |
283 | ||
284 | if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD && | |
285 | boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { | |
286 | pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n"); | |
287 | return SPECTRE_V2_CMD_AUTO; | |
288 | } | |
289 | ||
290 | if (mitigation_options[i].secure) | |
291 | spec2_print_if_secure(mitigation_options[i].option); | |
292 | else | |
293 | spec2_print_if_insecure(mitigation_options[i].option); | |
294 | ||
295 | return cmd; | |
da285121 DW |
296 | } |
297 | ||
c995efd5 DW |
298 | /* Check for Skylake-like CPUs (for RSB handling) */ |
299 | static bool __init is_skylake_era(void) | |
300 | { | |
301 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
302 | boot_cpu_data.x86 == 6) { | |
303 | switch (boot_cpu_data.x86_model) { | |
304 | case INTEL_FAM6_SKYLAKE_MOBILE: | |
305 | case INTEL_FAM6_SKYLAKE_DESKTOP: | |
306 | case INTEL_FAM6_SKYLAKE_X: | |
307 | case INTEL_FAM6_KABYLAKE_MOBILE: | |
308 | case INTEL_FAM6_KABYLAKE_DESKTOP: | |
309 | return true; | |
310 | } | |
311 | } | |
312 | return false; | |
313 | } | |
314 | ||
da285121 DW |
315 | static void __init spectre_v2_select_mitigation(void) |
316 | { | |
317 | enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); | |
318 | enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; | |
319 | ||
320 | /* | |
321 | * If the CPU is not affected and the command line mode is NONE or AUTO | |
322 | * then nothing to do. | |
323 | */ | |
324 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && | |
325 | (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) | |
326 | return; | |
327 | ||
328 | switch (cmd) { | |
329 | case SPECTRE_V2_CMD_NONE: | |
330 | return; | |
331 | ||
332 | case SPECTRE_V2_CMD_FORCE: | |
da285121 | 333 | case SPECTRE_V2_CMD_AUTO: |
9471eee9 DL |
334 | if (IS_ENABLED(CONFIG_RETPOLINE)) |
335 | goto retpoline_auto; | |
336 | break; | |
da285121 DW |
337 | case SPECTRE_V2_CMD_RETPOLINE_AMD: |
338 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
339 | goto retpoline_amd; | |
340 | break; | |
341 | case SPECTRE_V2_CMD_RETPOLINE_GENERIC: | |
342 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
343 | goto retpoline_generic; | |
344 | break; | |
345 | case SPECTRE_V2_CMD_RETPOLINE: | |
346 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
347 | goto retpoline_auto; | |
348 | break; | |
349 | } | |
21e433bd | 350 | pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!"); |
da285121 DW |
351 | return; |
352 | ||
353 | retpoline_auto: | |
354 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { | |
355 | retpoline_amd: | |
356 | if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { | |
21e433bd | 357 | pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n"); |
da285121 DW |
358 | goto retpoline_generic; |
359 | } | |
360 | mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD : | |
361 | SPECTRE_V2_RETPOLINE_MINIMAL_AMD; | |
362 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD); | |
363 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
364 | } else { | |
365 | retpoline_generic: | |
366 | mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC : | |
367 | SPECTRE_V2_RETPOLINE_MINIMAL; | |
368 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
369 | } | |
370 | ||
371 | spectre_v2_enabled = mode; | |
372 | pr_info("%s\n", spectre_v2_strings[mode]); | |
c995efd5 DW |
373 | |
374 | /* | |
21e433bd | 375 | * If neither SMEP nor PTI are available, there is a risk of |
c995efd5 DW |
376 | * hitting userspace addresses in the RSB after a context switch |
377 | * from a shallow call stack to a deeper one. To prevent this fill | |
378 | * the entire RSB, even when using IBRS. | |
379 | * | |
380 | * Skylake era CPUs have a separate issue with *underflow* of the | |
381 | * RSB, when they will predict 'ret' targets from the generic BTB. | |
382 | * The proper mitigation for this is IBRS. If IBRS is not supported | |
383 | * or deactivated in favour of retpolines the RSB fill on context | |
384 | * switch is required. | |
385 | */ | |
386 | if ((!boot_cpu_has(X86_FEATURE_PTI) && | |
387 | !boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) { | |
388 | setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); | |
21e433bd | 389 | pr_info("Spectre v2 mitigation: Filling RSB on context switch\n"); |
c995efd5 | 390 | } |
20ffa1ca DW |
391 | |
392 | /* Initialize Indirect Branch Prediction Barrier if supported */ | |
2961298e DW |
393 | if (boot_cpu_has(X86_FEATURE_IBPB)) { |
394 | setup_force_cpu_cap(X86_FEATURE_USE_IBPB); | |
21e433bd | 395 | pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n"); |
20ffa1ca | 396 | } |
dd84441a DW |
397 | |
398 | /* | |
399 | * Retpoline means the kernel is safe because it has no indirect | |
400 | * branches. But firmware isn't, so use IBRS to protect that. | |
401 | */ | |
402 | if (boot_cpu_has(X86_FEATURE_IBRS)) { | |
403 | setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); | |
404 | pr_info("Enabling Restricted Speculation for firmware calls\n"); | |
405 | } | |
da285121 DW |
406 | } |
407 | ||
24f7fc83 KRW |
408 | #undef pr_fmt |
409 | #define pr_fmt(fmt) "Speculative Store Bypass: " fmt | |
410 | ||
f9544b2b | 411 | static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE; |
24f7fc83 KRW |
412 | |
413 | /* The kernel command line selection */ | |
414 | enum ssb_mitigation_cmd { | |
415 | SPEC_STORE_BYPASS_CMD_NONE, | |
416 | SPEC_STORE_BYPASS_CMD_AUTO, | |
417 | SPEC_STORE_BYPASS_CMD_ON, | |
a73ec77e | 418 | SPEC_STORE_BYPASS_CMD_PRCTL, |
f21b53b2 | 419 | SPEC_STORE_BYPASS_CMD_SECCOMP, |
24f7fc83 KRW |
420 | }; |
421 | ||
422 | static const char *ssb_strings[] = { | |
423 | [SPEC_STORE_BYPASS_NONE] = "Vulnerable", | |
a73ec77e | 424 | [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", |
f21b53b2 KC |
425 | [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", |
426 | [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp", | |
24f7fc83 KRW |
427 | }; |
428 | ||
429 | static const struct { | |
430 | const char *option; | |
431 | enum ssb_mitigation_cmd cmd; | |
432 | } ssb_mitigation_options[] = { | |
f21b53b2 KC |
433 | { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ |
434 | { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ | |
435 | { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ | |
436 | { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */ | |
437 | { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */ | |
24f7fc83 KRW |
438 | }; |
439 | ||
440 | static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) | |
441 | { | |
442 | enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO; | |
443 | char arg[20]; | |
444 | int ret, i; | |
445 | ||
446 | if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) { | |
447 | return SPEC_STORE_BYPASS_CMD_NONE; | |
448 | } else { | |
449 | ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", | |
450 | arg, sizeof(arg)); | |
451 | if (ret < 0) | |
452 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
453 | ||
454 | for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { | |
455 | if (!match_option(arg, ret, ssb_mitigation_options[i].option)) | |
456 | continue; | |
457 | ||
458 | cmd = ssb_mitigation_options[i].cmd; | |
459 | break; | |
460 | } | |
461 | ||
462 | if (i >= ARRAY_SIZE(ssb_mitigation_options)) { | |
463 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
464 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
465 | } | |
466 | } | |
467 | ||
468 | return cmd; | |
469 | } | |
470 | ||
d66d8ff3 | 471 | static enum ssb_mitigation __init __ssb_select_mitigation(void) |
24f7fc83 KRW |
472 | { |
473 | enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; | |
474 | enum ssb_mitigation_cmd cmd; | |
475 | ||
9f65fb29 | 476 | if (!boot_cpu_has(X86_FEATURE_SSBD)) |
24f7fc83 KRW |
477 | return mode; |
478 | ||
479 | cmd = ssb_parse_cmdline(); | |
480 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && | |
481 | (cmd == SPEC_STORE_BYPASS_CMD_NONE || | |
482 | cmd == SPEC_STORE_BYPASS_CMD_AUTO)) | |
483 | return mode; | |
484 | ||
485 | switch (cmd) { | |
486 | case SPEC_STORE_BYPASS_CMD_AUTO: | |
f21b53b2 KC |
487 | case SPEC_STORE_BYPASS_CMD_SECCOMP: |
488 | /* | |
489 | * Choose prctl+seccomp as the default mode if seccomp is | |
490 | * enabled. | |
491 | */ | |
492 | if (IS_ENABLED(CONFIG_SECCOMP)) | |
493 | mode = SPEC_STORE_BYPASS_SECCOMP; | |
494 | else | |
495 | mode = SPEC_STORE_BYPASS_PRCTL; | |
a73ec77e | 496 | break; |
24f7fc83 KRW |
497 | case SPEC_STORE_BYPASS_CMD_ON: |
498 | mode = SPEC_STORE_BYPASS_DISABLE; | |
499 | break; | |
a73ec77e TG |
500 | case SPEC_STORE_BYPASS_CMD_PRCTL: |
501 | mode = SPEC_STORE_BYPASS_PRCTL; | |
502 | break; | |
24f7fc83 KRW |
503 | case SPEC_STORE_BYPASS_CMD_NONE: |
504 | break; | |
505 | } | |
506 | ||
77243971 KRW |
507 | /* |
508 | * We have three CPU feature flags that are in play here: | |
509 | * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. | |
9f65fb29 | 510 | * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass |
77243971 KRW |
511 | * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation |
512 | */ | |
a73ec77e | 513 | if (mode == SPEC_STORE_BYPASS_DISABLE) { |
24f7fc83 | 514 | setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); |
77243971 KRW |
515 | /* |
516 | * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD uses | |
517 | * a completely different MSR and bit dependent on family. | |
518 | */ | |
519 | switch (boot_cpu_data.x86_vendor) { | |
520 | case X86_VENDOR_INTEL: | |
9f65fb29 KRW |
521 | x86_spec_ctrl_base |= SPEC_CTRL_SSBD; |
522 | x86_spec_ctrl_mask &= ~SPEC_CTRL_SSBD; | |
523 | x86_spec_ctrl_set(SPEC_CTRL_SSBD); | |
77243971 KRW |
524 | break; |
525 | case X86_VENDOR_AMD: | |
9f65fb29 | 526 | x86_amd_ssb_disable(); |
77243971 KRW |
527 | break; |
528 | } | |
529 | } | |
530 | ||
24f7fc83 KRW |
531 | return mode; |
532 | } | |
533 | ||
ffed645e | 534 | static void ssb_select_mitigation(void) |
24f7fc83 KRW |
535 | { |
536 | ssb_mode = __ssb_select_mitigation(); | |
537 | ||
538 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
539 | pr_info("%s\n", ssb_strings[ssb_mode]); | |
540 | } | |
541 | ||
da285121 | 542 | #undef pr_fmt |
f21b53b2 | 543 | #define pr_fmt(fmt) "Speculation prctl: " fmt |
da285121 | 544 | |
7bbf1373 | 545 | static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) |
a73ec77e | 546 | { |
356e4bff | 547 | bool update; |
a73ec77e | 548 | |
f21b53b2 KC |
549 | if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && |
550 | ssb_mode != SPEC_STORE_BYPASS_SECCOMP) | |
a73ec77e TG |
551 | return -ENXIO; |
552 | ||
356e4bff TG |
553 | switch (ctrl) { |
554 | case PR_SPEC_ENABLE: | |
555 | /* If speculation is force disabled, enable is not allowed */ | |
556 | if (task_spec_ssb_force_disable(task)) | |
557 | return -EPERM; | |
558 | task_clear_spec_ssb_disable(task); | |
9f65fb29 | 559 | update = test_and_clear_tsk_thread_flag(task, TIF_SSBD); |
356e4bff TG |
560 | break; |
561 | case PR_SPEC_DISABLE: | |
562 | task_set_spec_ssb_disable(task); | |
9f65fb29 | 563 | update = !test_and_set_tsk_thread_flag(task, TIF_SSBD); |
356e4bff TG |
564 | break; |
565 | case PR_SPEC_FORCE_DISABLE: | |
566 | task_set_spec_ssb_disable(task); | |
567 | task_set_spec_ssb_force_disable(task); | |
9f65fb29 | 568 | update = !test_and_set_tsk_thread_flag(task, TIF_SSBD); |
356e4bff TG |
569 | break; |
570 | default: | |
571 | return -ERANGE; | |
572 | } | |
a73ec77e | 573 | |
7bbf1373 KC |
574 | /* |
575 | * If being set on non-current task, delay setting the CPU | |
576 | * mitigation until it is next scheduled. | |
577 | */ | |
356e4bff | 578 | if (task == current && update) |
a73ec77e TG |
579 | speculative_store_bypass_update(); |
580 | ||
581 | return 0; | |
582 | } | |
583 | ||
8bf37d8c TG |
584 | int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, |
585 | unsigned long ctrl) | |
586 | { | |
587 | switch (which) { | |
588 | case PR_SPEC_STORE_BYPASS: | |
589 | return ssb_prctl_set(task, ctrl); | |
590 | default: | |
591 | return -ENODEV; | |
592 | } | |
593 | } | |
594 | ||
595 | #ifdef CONFIG_SECCOMP | |
596 | void arch_seccomp_spec_mitigate(struct task_struct *task) | |
597 | { | |
f21b53b2 KC |
598 | if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) |
599 | ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
8bf37d8c TG |
600 | } |
601 | #endif | |
602 | ||
7bbf1373 | 603 | static int ssb_prctl_get(struct task_struct *task) |
a73ec77e TG |
604 | { |
605 | switch (ssb_mode) { | |
606 | case SPEC_STORE_BYPASS_DISABLE: | |
607 | return PR_SPEC_DISABLE; | |
f21b53b2 | 608 | case SPEC_STORE_BYPASS_SECCOMP: |
a73ec77e | 609 | case SPEC_STORE_BYPASS_PRCTL: |
356e4bff TG |
610 | if (task_spec_ssb_force_disable(task)) |
611 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
612 | if (task_spec_ssb_disable(task)) | |
a73ec77e TG |
613 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; |
614 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
615 | default: | |
616 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
617 | return PR_SPEC_ENABLE; | |
618 | return PR_SPEC_NOT_AFFECTED; | |
619 | } | |
620 | } | |
621 | ||
7bbf1373 | 622 | int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) |
a73ec77e TG |
623 | { |
624 | switch (which) { | |
625 | case PR_SPEC_STORE_BYPASS: | |
7bbf1373 | 626 | return ssb_prctl_get(task); |
a73ec77e TG |
627 | default: |
628 | return -ENODEV; | |
629 | } | |
630 | } | |
631 | ||
77243971 KRW |
632 | void x86_spec_ctrl_setup_ap(void) |
633 | { | |
634 | if (boot_cpu_has(X86_FEATURE_IBRS)) | |
1115a859 | 635 | x86_spec_ctrl_set(x86_spec_ctrl_base & ~x86_spec_ctrl_mask); |
764f3c21 KRW |
636 | |
637 | if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) | |
9f65fb29 | 638 | x86_amd_ssb_disable(); |
77243971 KRW |
639 | } |
640 | ||
61dc0f55 | 641 | #ifdef CONFIG_SYSFS |
d1059518 | 642 | |
7bb4d366 | 643 | static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, |
ffed645e | 644 | char *buf, unsigned int bug) |
61dc0f55 | 645 | { |
d1059518 | 646 | if (!boot_cpu_has_bug(bug)) |
61dc0f55 | 647 | return sprintf(buf, "Not affected\n"); |
d1059518 KRW |
648 | |
649 | switch (bug) { | |
650 | case X86_BUG_CPU_MELTDOWN: | |
651 | if (boot_cpu_has(X86_FEATURE_PTI)) | |
652 | return sprintf(buf, "Mitigation: PTI\n"); | |
653 | ||
654 | break; | |
655 | ||
656 | case X86_BUG_SPECTRE_V1: | |
657 | return sprintf(buf, "Mitigation: __user pointer sanitization\n"); | |
658 | ||
659 | case X86_BUG_SPECTRE_V2: | |
660 | return sprintf(buf, "%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], | |
661 | boot_cpu_has(X86_FEATURE_USE_IBPB) ? ", IBPB" : "", | |
662 | boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", | |
663 | spectre_v2_module_string()); | |
664 | ||
24f7fc83 KRW |
665 | case X86_BUG_SPEC_STORE_BYPASS: |
666 | return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); | |
667 | ||
d1059518 KRW |
668 | default: |
669 | break; | |
670 | } | |
671 | ||
61dc0f55 TG |
672 | return sprintf(buf, "Vulnerable\n"); |
673 | } | |
674 | ||
d1059518 KRW |
675 | ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) |
676 | { | |
677 | return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); | |
678 | } | |
679 | ||
21e433bd | 680 | ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 681 | { |
d1059518 | 682 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); |
61dc0f55 TG |
683 | } |
684 | ||
21e433bd | 685 | ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 686 | { |
d1059518 | 687 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); |
61dc0f55 | 688 | } |
c456442c KRW |
689 | |
690 | ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) | |
691 | { | |
692 | return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); | |
693 | } | |
61dc0f55 | 694 | #endif |