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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1353ebb4 | 2 | /* |
1353ebb4 JF |
3 | * Copyright (C) 1994 Linus Torvalds |
4 | * | |
5 | * Cyrix stuff, June 1998 by: | |
6 | * - Rafael R. Reilova (moved everything from head.S), | |
7 | * <rreilova@ececs.uc.edu> | |
8 | * - Channing Corn (tests & fixes), | |
9 | * - Andrew D. Balsa (code cleanup). | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/utsname.h> | |
61dc0f55 | 13 | #include <linux/cpu.h> |
caf7501a | 14 | #include <linux/module.h> |
a73ec77e TG |
15 | #include <linux/nospec.h> |
16 | #include <linux/prctl.h> | |
da285121 | 17 | |
28a27752 | 18 | #include <asm/spec-ctrl.h> |
da285121 | 19 | #include <asm/cmdline.h> |
91eb1b79 | 20 | #include <asm/bugs.h> |
1353ebb4 | 21 | #include <asm/processor.h> |
7ebad705 | 22 | #include <asm/processor-flags.h> |
952f07ec | 23 | #include <asm/fpu/internal.h> |
1353ebb4 JF |
24 | #include <asm/msr.h> |
25 | #include <asm/paravirt.h> | |
26 | #include <asm/alternative.h> | |
62a67e12 | 27 | #include <asm/pgtable.h> |
d1163651 | 28 | #include <asm/set_memory.h> |
c995efd5 | 29 | #include <asm/intel-family.h> |
6cb2b08f | 30 | #include <asm/hypervisor.h> |
1353ebb4 | 31 | |
da285121 | 32 | static void __init spectre_v2_select_mitigation(void); |
24f7fc83 | 33 | static void __init ssb_select_mitigation(void); |
da285121 | 34 | |
1b86883c KRW |
35 | /* |
36 | * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any | |
37 | * writes to SPEC_CTRL contain whatever reserved bits have been set. | |
38 | */ | |
885f82bf | 39 | u64 __ro_after_init x86_spec_ctrl_base; |
fa8ac498 | 40 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); |
1b86883c | 41 | |
1115a859 KRW |
42 | /* |
43 | * The vendor and possibly platform specific bits which can be modified in | |
44 | * x86_spec_ctrl_base. | |
45 | */ | |
be6fcb54 | 46 | static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS; |
1115a859 | 47 | |
764f3c21 KRW |
48 | /* |
49 | * AMD specific MSR info for Speculative Store Bypass control. | |
9f65fb29 | 50 | * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). |
764f3c21 KRW |
51 | */ |
52 | u64 __ro_after_init x86_amd_ls_cfg_base; | |
9f65fb29 | 53 | u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; |
764f3c21 | 54 | |
1353ebb4 JF |
55 | void __init check_bugs(void) |
56 | { | |
57 | identify_boot_cpu(); | |
55a36b65 | 58 | |
62a67e12 BP |
59 | if (!IS_ENABLED(CONFIG_SMP)) { |
60 | pr_info("CPU: "); | |
61 | print_cpu_info(&boot_cpu_data); | |
62 | } | |
63 | ||
1b86883c KRW |
64 | /* |
65 | * Read the SPEC_CTRL MSR to account for reserved bits which may | |
764f3c21 KRW |
66 | * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD |
67 | * init code as it is not enumerated and depends on the family. | |
1b86883c | 68 | */ |
7eb8956a | 69 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
1b86883c KRW |
70 | rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
71 | ||
be6fcb54 TG |
72 | /* Allow STIBP in MSR_SPEC_CTRL if supported */ |
73 | if (boot_cpu_has(X86_FEATURE_STIBP)) | |
74 | x86_spec_ctrl_mask |= SPEC_CTRL_STIBP; | |
75 | ||
da285121 DW |
76 | /* Select the proper spectre mitigation before patching alternatives */ |
77 | spectre_v2_select_mitigation(); | |
78 | ||
24f7fc83 KRW |
79 | /* |
80 | * Select proper mitigation for any exposure to the Speculative Store | |
81 | * Bypass vulnerability. | |
82 | */ | |
83 | ssb_select_mitigation(); | |
84 | ||
62a67e12 | 85 | #ifdef CONFIG_X86_32 |
55a36b65 BP |
86 | /* |
87 | * Check whether we are able to run this kernel safely on SMP. | |
88 | * | |
89 | * - i386 is no longer supported. | |
90 | * - In order to run on anything without a TSC, we need to be | |
91 | * compiled for a i486. | |
92 | */ | |
93 | if (boot_cpu_data.x86 < 4) | |
94 | panic("Kernel requires i486+ for 'invlpg' and other features"); | |
95 | ||
bfe4bb15 MV |
96 | init_utsname()->machine[1] = |
97 | '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); | |
1353ebb4 | 98 | alternative_instructions(); |
304bceda | 99 | |
4d164092 | 100 | fpu__init_check_bugs(); |
62a67e12 BP |
101 | #else /* CONFIG_X86_64 */ |
102 | alternative_instructions(); | |
103 | ||
104 | /* | |
105 | * Make sure the first 2MB area is not mapped by huge pages | |
106 | * There are typically fixed size MTRRs in there and overlapping | |
107 | * MTRRs into large pages causes slow downs. | |
108 | * | |
109 | * Right now we don't do that with gbpages because there seems | |
110 | * very little benefit for that case. | |
111 | */ | |
112 | if (!direct_gbpages) | |
113 | set_memory_4k((unsigned long)__va(0), 1); | |
114 | #endif | |
1353ebb4 | 115 | } |
61dc0f55 | 116 | |
da285121 DW |
117 | /* The kernel command line selection */ |
118 | enum spectre_v2_mitigation_cmd { | |
119 | SPECTRE_V2_CMD_NONE, | |
120 | SPECTRE_V2_CMD_AUTO, | |
121 | SPECTRE_V2_CMD_FORCE, | |
122 | SPECTRE_V2_CMD_RETPOLINE, | |
123 | SPECTRE_V2_CMD_RETPOLINE_GENERIC, | |
124 | SPECTRE_V2_CMD_RETPOLINE_AMD, | |
125 | }; | |
126 | ||
127 | static const char *spectre_v2_strings[] = { | |
128 | [SPECTRE_V2_NONE] = "Vulnerable", | |
129 | [SPECTRE_V2_RETPOLINE_MINIMAL] = "Vulnerable: Minimal generic ASM retpoline", | |
130 | [SPECTRE_V2_RETPOLINE_MINIMAL_AMD] = "Vulnerable: Minimal AMD ASM retpoline", | |
131 | [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", | |
132 | [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", | |
133 | }; | |
134 | ||
135 | #undef pr_fmt | |
55fa19d3 | 136 | #define pr_fmt(fmt) "Spectre V2 : " fmt |
da285121 | 137 | |
f9544b2b KC |
138 | static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = |
139 | SPECTRE_V2_NONE; | |
caf7501a | 140 | |
cc69b349 BP |
141 | void |
142 | x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) | |
5cf68754 | 143 | { |
be6fcb54 | 144 | u64 msrval, guestval, hostval = x86_spec_ctrl_base; |
cc69b349 | 145 | struct thread_info *ti = current_thread_info(); |
885f82bf | 146 | |
7eb8956a | 147 | /* Is MSR_SPEC_CTRL implemented ? */ |
cc69b349 | 148 | if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { |
be6fcb54 TG |
149 | /* |
150 | * Restrict guest_spec_ctrl to supported values. Clear the | |
151 | * modifiable bits in the host base value and or the | |
152 | * modifiable bits from the guest value. | |
153 | */ | |
154 | guestval = hostval & ~x86_spec_ctrl_mask; | |
155 | guestval |= guest_spec_ctrl & x86_spec_ctrl_mask; | |
156 | ||
cc69b349 | 157 | /* SSBD controlled in MSR_SPEC_CTRL */ |
612bc3b3 TL |
158 | if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || |
159 | static_cpu_has(X86_FEATURE_AMD_SSBD)) | |
be6fcb54 | 160 | hostval |= ssbd_tif_to_spec_ctrl(ti->flags); |
cc69b349 | 161 | |
be6fcb54 TG |
162 | if (hostval != guestval) { |
163 | msrval = setguest ? guestval : hostval; | |
164 | wrmsrl(MSR_IA32_SPEC_CTRL, msrval); | |
cc69b349 BP |
165 | } |
166 | } | |
47c61b39 TG |
167 | |
168 | /* | |
169 | * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update | |
170 | * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported. | |
171 | */ | |
172 | if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) && | |
173 | !static_cpu_has(X86_FEATURE_VIRT_SSBD)) | |
174 | return; | |
175 | ||
176 | /* | |
177 | * If the host has SSBD mitigation enabled, force it in the host's | |
178 | * virtual MSR value. If its not permanently enabled, evaluate | |
179 | * current's TIF_SSBD thread flag. | |
180 | */ | |
181 | if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE)) | |
182 | hostval = SPEC_CTRL_SSBD; | |
183 | else | |
184 | hostval = ssbd_tif_to_spec_ctrl(ti->flags); | |
185 | ||
186 | /* Sanitize the guest value */ | |
187 | guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD; | |
188 | ||
189 | if (hostval != guestval) { | |
190 | unsigned long tif; | |
191 | ||
192 | tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) : | |
193 | ssbd_spec_ctrl_to_tif(hostval); | |
194 | ||
195 | speculative_store_bypass_update(tif); | |
196 | } | |
5cf68754 | 197 | } |
cc69b349 | 198 | EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); |
5cf68754 | 199 | |
9f65fb29 | 200 | static void x86_amd_ssb_disable(void) |
764f3c21 | 201 | { |
9f65fb29 | 202 | u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; |
764f3c21 | 203 | |
11fb0683 TL |
204 | if (boot_cpu_has(X86_FEATURE_VIRT_SSBD)) |
205 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); | |
206 | else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) | |
764f3c21 KRW |
207 | wrmsrl(MSR_AMD64_LS_CFG, msrval); |
208 | } | |
209 | ||
caf7501a | 210 | #ifdef RETPOLINE |
e383095c TG |
211 | static bool spectre_v2_bad_module; |
212 | ||
caf7501a AK |
213 | bool retpoline_module_ok(bool has_retpoline) |
214 | { | |
215 | if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) | |
216 | return true; | |
217 | ||
e698dcdf | 218 | pr_err("System may be vulnerable to spectre v2\n"); |
caf7501a AK |
219 | spectre_v2_bad_module = true; |
220 | return false; | |
221 | } | |
e383095c TG |
222 | |
223 | static inline const char *spectre_v2_module_string(void) | |
224 | { | |
225 | return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; | |
226 | } | |
227 | #else | |
228 | static inline const char *spectre_v2_module_string(void) { return ""; } | |
caf7501a | 229 | #endif |
da285121 DW |
230 | |
231 | static void __init spec2_print_if_insecure(const char *reason) | |
232 | { | |
233 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
9005c683 | 234 | pr_info("%s selected on command line.\n", reason); |
da285121 DW |
235 | } |
236 | ||
237 | static void __init spec2_print_if_secure(const char *reason) | |
238 | { | |
239 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
9005c683 | 240 | pr_info("%s selected on command line.\n", reason); |
da285121 DW |
241 | } |
242 | ||
243 | static inline bool retp_compiler(void) | |
244 | { | |
245 | return __is_defined(RETPOLINE); | |
246 | } | |
247 | ||
248 | static inline bool match_option(const char *arg, int arglen, const char *opt) | |
249 | { | |
250 | int len = strlen(opt); | |
251 | ||
252 | return len == arglen && !strncmp(arg, opt, len); | |
253 | } | |
254 | ||
9005c683 KA |
255 | static const struct { |
256 | const char *option; | |
257 | enum spectre_v2_mitigation_cmd cmd; | |
258 | bool secure; | |
259 | } mitigation_options[] = { | |
260 | { "off", SPECTRE_V2_CMD_NONE, false }, | |
261 | { "on", SPECTRE_V2_CMD_FORCE, true }, | |
262 | { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, | |
263 | { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false }, | |
264 | { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, | |
265 | { "auto", SPECTRE_V2_CMD_AUTO, false }, | |
266 | }; | |
267 | ||
da285121 DW |
268 | static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) |
269 | { | |
270 | char arg[20]; | |
9005c683 KA |
271 | int ret, i; |
272 | enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; | |
273 | ||
274 | if (cmdline_find_option_bool(boot_command_line, "nospectre_v2")) | |
275 | return SPECTRE_V2_CMD_NONE; | |
276 | else { | |
21e433bd | 277 | ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); |
9005c683 KA |
278 | if (ret < 0) |
279 | return SPECTRE_V2_CMD_AUTO; | |
280 | ||
281 | for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { | |
282 | if (!match_option(arg, ret, mitigation_options[i].option)) | |
283 | continue; | |
284 | cmd = mitigation_options[i].cmd; | |
285 | break; | |
286 | } | |
287 | ||
288 | if (i >= ARRAY_SIZE(mitigation_options)) { | |
9de29eac | 289 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); |
da285121 DW |
290 | return SPECTRE_V2_CMD_AUTO; |
291 | } | |
292 | } | |
293 | ||
9005c683 KA |
294 | if ((cmd == SPECTRE_V2_CMD_RETPOLINE || |
295 | cmd == SPECTRE_V2_CMD_RETPOLINE_AMD || | |
296 | cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) && | |
297 | !IS_ENABLED(CONFIG_RETPOLINE)) { | |
21e433bd | 298 | pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option); |
da285121 | 299 | return SPECTRE_V2_CMD_AUTO; |
9005c683 KA |
300 | } |
301 | ||
302 | if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD && | |
303 | boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { | |
304 | pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n"); | |
305 | return SPECTRE_V2_CMD_AUTO; | |
306 | } | |
307 | ||
308 | if (mitigation_options[i].secure) | |
309 | spec2_print_if_secure(mitigation_options[i].option); | |
310 | else | |
311 | spec2_print_if_insecure(mitigation_options[i].option); | |
312 | ||
313 | return cmd; | |
da285121 DW |
314 | } |
315 | ||
316 | static void __init spectre_v2_select_mitigation(void) | |
317 | { | |
318 | enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); | |
319 | enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; | |
320 | ||
321 | /* | |
322 | * If the CPU is not affected and the command line mode is NONE or AUTO | |
323 | * then nothing to do. | |
324 | */ | |
325 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && | |
326 | (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) | |
327 | return; | |
328 | ||
329 | switch (cmd) { | |
330 | case SPECTRE_V2_CMD_NONE: | |
331 | return; | |
332 | ||
333 | case SPECTRE_V2_CMD_FORCE: | |
da285121 | 334 | case SPECTRE_V2_CMD_AUTO: |
9471eee9 DL |
335 | if (IS_ENABLED(CONFIG_RETPOLINE)) |
336 | goto retpoline_auto; | |
337 | break; | |
da285121 DW |
338 | case SPECTRE_V2_CMD_RETPOLINE_AMD: |
339 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
340 | goto retpoline_amd; | |
341 | break; | |
342 | case SPECTRE_V2_CMD_RETPOLINE_GENERIC: | |
343 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
344 | goto retpoline_generic; | |
345 | break; | |
346 | case SPECTRE_V2_CMD_RETPOLINE: | |
347 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
348 | goto retpoline_auto; | |
349 | break; | |
350 | } | |
21e433bd | 351 | pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!"); |
da285121 DW |
352 | return; |
353 | ||
354 | retpoline_auto: | |
355 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { | |
356 | retpoline_amd: | |
357 | if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { | |
21e433bd | 358 | pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n"); |
da285121 DW |
359 | goto retpoline_generic; |
360 | } | |
361 | mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD : | |
362 | SPECTRE_V2_RETPOLINE_MINIMAL_AMD; | |
363 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD); | |
364 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
365 | } else { | |
366 | retpoline_generic: | |
367 | mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC : | |
368 | SPECTRE_V2_RETPOLINE_MINIMAL; | |
369 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
370 | } | |
371 | ||
372 | spectre_v2_enabled = mode; | |
373 | pr_info("%s\n", spectre_v2_strings[mode]); | |
c995efd5 DW |
374 | |
375 | /* | |
fdf82a78 JK |
376 | * If spectre v2 protection has been enabled, unconditionally fill |
377 | * RSB during a context switch; this protects against two independent | |
378 | * issues: | |
c995efd5 | 379 | * |
fdf82a78 JK |
380 | * - RSB underflow (and switch to BTB) on Skylake+ |
381 | * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs | |
c995efd5 | 382 | */ |
fdf82a78 JK |
383 | setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); |
384 | pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n"); | |
20ffa1ca DW |
385 | |
386 | /* Initialize Indirect Branch Prediction Barrier if supported */ | |
2961298e DW |
387 | if (boot_cpu_has(X86_FEATURE_IBPB)) { |
388 | setup_force_cpu_cap(X86_FEATURE_USE_IBPB); | |
21e433bd | 389 | pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n"); |
20ffa1ca | 390 | } |
dd84441a DW |
391 | |
392 | /* | |
393 | * Retpoline means the kernel is safe because it has no indirect | |
394 | * branches. But firmware isn't, so use IBRS to protect that. | |
395 | */ | |
396 | if (boot_cpu_has(X86_FEATURE_IBRS)) { | |
397 | setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); | |
398 | pr_info("Enabling Restricted Speculation for firmware calls\n"); | |
399 | } | |
da285121 DW |
400 | } |
401 | ||
24f7fc83 KRW |
402 | #undef pr_fmt |
403 | #define pr_fmt(fmt) "Speculative Store Bypass: " fmt | |
404 | ||
f9544b2b | 405 | static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE; |
24f7fc83 KRW |
406 | |
407 | /* The kernel command line selection */ | |
408 | enum ssb_mitigation_cmd { | |
409 | SPEC_STORE_BYPASS_CMD_NONE, | |
410 | SPEC_STORE_BYPASS_CMD_AUTO, | |
411 | SPEC_STORE_BYPASS_CMD_ON, | |
a73ec77e | 412 | SPEC_STORE_BYPASS_CMD_PRCTL, |
f21b53b2 | 413 | SPEC_STORE_BYPASS_CMD_SECCOMP, |
24f7fc83 KRW |
414 | }; |
415 | ||
416 | static const char *ssb_strings[] = { | |
417 | [SPEC_STORE_BYPASS_NONE] = "Vulnerable", | |
a73ec77e | 418 | [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", |
f21b53b2 KC |
419 | [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", |
420 | [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp", | |
24f7fc83 KRW |
421 | }; |
422 | ||
423 | static const struct { | |
424 | const char *option; | |
425 | enum ssb_mitigation_cmd cmd; | |
426 | } ssb_mitigation_options[] = { | |
f21b53b2 KC |
427 | { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ |
428 | { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ | |
429 | { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ | |
430 | { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */ | |
431 | { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */ | |
24f7fc83 KRW |
432 | }; |
433 | ||
434 | static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) | |
435 | { | |
436 | enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO; | |
437 | char arg[20]; | |
438 | int ret, i; | |
439 | ||
440 | if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) { | |
441 | return SPEC_STORE_BYPASS_CMD_NONE; | |
442 | } else { | |
443 | ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", | |
444 | arg, sizeof(arg)); | |
445 | if (ret < 0) | |
446 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
447 | ||
448 | for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { | |
449 | if (!match_option(arg, ret, ssb_mitigation_options[i].option)) | |
450 | continue; | |
451 | ||
452 | cmd = ssb_mitigation_options[i].cmd; | |
453 | break; | |
454 | } | |
455 | ||
456 | if (i >= ARRAY_SIZE(ssb_mitigation_options)) { | |
457 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
458 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
459 | } | |
460 | } | |
461 | ||
462 | return cmd; | |
463 | } | |
464 | ||
d66d8ff3 | 465 | static enum ssb_mitigation __init __ssb_select_mitigation(void) |
24f7fc83 KRW |
466 | { |
467 | enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; | |
468 | enum ssb_mitigation_cmd cmd; | |
469 | ||
9f65fb29 | 470 | if (!boot_cpu_has(X86_FEATURE_SSBD)) |
24f7fc83 KRW |
471 | return mode; |
472 | ||
473 | cmd = ssb_parse_cmdline(); | |
474 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && | |
475 | (cmd == SPEC_STORE_BYPASS_CMD_NONE || | |
476 | cmd == SPEC_STORE_BYPASS_CMD_AUTO)) | |
477 | return mode; | |
478 | ||
479 | switch (cmd) { | |
480 | case SPEC_STORE_BYPASS_CMD_AUTO: | |
f21b53b2 KC |
481 | case SPEC_STORE_BYPASS_CMD_SECCOMP: |
482 | /* | |
483 | * Choose prctl+seccomp as the default mode if seccomp is | |
484 | * enabled. | |
485 | */ | |
486 | if (IS_ENABLED(CONFIG_SECCOMP)) | |
487 | mode = SPEC_STORE_BYPASS_SECCOMP; | |
488 | else | |
489 | mode = SPEC_STORE_BYPASS_PRCTL; | |
a73ec77e | 490 | break; |
24f7fc83 KRW |
491 | case SPEC_STORE_BYPASS_CMD_ON: |
492 | mode = SPEC_STORE_BYPASS_DISABLE; | |
493 | break; | |
a73ec77e TG |
494 | case SPEC_STORE_BYPASS_CMD_PRCTL: |
495 | mode = SPEC_STORE_BYPASS_PRCTL; | |
496 | break; | |
24f7fc83 KRW |
497 | case SPEC_STORE_BYPASS_CMD_NONE: |
498 | break; | |
499 | } | |
500 | ||
77243971 KRW |
501 | /* |
502 | * We have three CPU feature flags that are in play here: | |
503 | * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. | |
9f65fb29 | 504 | * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass |
77243971 KRW |
505 | * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation |
506 | */ | |
a73ec77e | 507 | if (mode == SPEC_STORE_BYPASS_DISABLE) { |
24f7fc83 | 508 | setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); |
77243971 | 509 | /* |
6ac2f49e KRW |
510 | * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may |
511 | * use a completely different MSR and bit dependent on family. | |
77243971 | 512 | */ |
612bc3b3 TL |
513 | if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) && |
514 | !static_cpu_has(X86_FEATURE_AMD_SSBD)) { | |
108fab4b | 515 | x86_amd_ssb_disable(); |
612bc3b3 | 516 | } else { |
9f65fb29 | 517 | x86_spec_ctrl_base |= SPEC_CTRL_SSBD; |
be6fcb54 | 518 | x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; |
4b59bdb5 | 519 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
77243971 KRW |
520 | } |
521 | } | |
522 | ||
24f7fc83 KRW |
523 | return mode; |
524 | } | |
525 | ||
ffed645e | 526 | static void ssb_select_mitigation(void) |
24f7fc83 KRW |
527 | { |
528 | ssb_mode = __ssb_select_mitigation(); | |
529 | ||
530 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
531 | pr_info("%s\n", ssb_strings[ssb_mode]); | |
532 | } | |
533 | ||
da285121 | 534 | #undef pr_fmt |
f21b53b2 | 535 | #define pr_fmt(fmt) "Speculation prctl: " fmt |
da285121 | 536 | |
7bbf1373 | 537 | static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) |
a73ec77e | 538 | { |
356e4bff | 539 | bool update; |
a73ec77e | 540 | |
f21b53b2 KC |
541 | if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && |
542 | ssb_mode != SPEC_STORE_BYPASS_SECCOMP) | |
a73ec77e TG |
543 | return -ENXIO; |
544 | ||
356e4bff TG |
545 | switch (ctrl) { |
546 | case PR_SPEC_ENABLE: | |
547 | /* If speculation is force disabled, enable is not allowed */ | |
548 | if (task_spec_ssb_force_disable(task)) | |
549 | return -EPERM; | |
550 | task_clear_spec_ssb_disable(task); | |
9f65fb29 | 551 | update = test_and_clear_tsk_thread_flag(task, TIF_SSBD); |
356e4bff TG |
552 | break; |
553 | case PR_SPEC_DISABLE: | |
554 | task_set_spec_ssb_disable(task); | |
9f65fb29 | 555 | update = !test_and_set_tsk_thread_flag(task, TIF_SSBD); |
356e4bff TG |
556 | break; |
557 | case PR_SPEC_FORCE_DISABLE: | |
558 | task_set_spec_ssb_disable(task); | |
559 | task_set_spec_ssb_force_disable(task); | |
9f65fb29 | 560 | update = !test_and_set_tsk_thread_flag(task, TIF_SSBD); |
356e4bff TG |
561 | break; |
562 | default: | |
563 | return -ERANGE; | |
564 | } | |
a73ec77e | 565 | |
7bbf1373 KC |
566 | /* |
567 | * If being set on non-current task, delay setting the CPU | |
568 | * mitigation until it is next scheduled. | |
569 | */ | |
356e4bff | 570 | if (task == current && update) |
0270be3e | 571 | speculative_store_bypass_update_current(); |
a73ec77e TG |
572 | |
573 | return 0; | |
574 | } | |
575 | ||
8bf37d8c TG |
576 | int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, |
577 | unsigned long ctrl) | |
578 | { | |
579 | switch (which) { | |
580 | case PR_SPEC_STORE_BYPASS: | |
581 | return ssb_prctl_set(task, ctrl); | |
582 | default: | |
583 | return -ENODEV; | |
584 | } | |
585 | } | |
586 | ||
587 | #ifdef CONFIG_SECCOMP | |
588 | void arch_seccomp_spec_mitigate(struct task_struct *task) | |
589 | { | |
f21b53b2 KC |
590 | if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) |
591 | ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
8bf37d8c TG |
592 | } |
593 | #endif | |
594 | ||
7bbf1373 | 595 | static int ssb_prctl_get(struct task_struct *task) |
a73ec77e TG |
596 | { |
597 | switch (ssb_mode) { | |
598 | case SPEC_STORE_BYPASS_DISABLE: | |
599 | return PR_SPEC_DISABLE; | |
f21b53b2 | 600 | case SPEC_STORE_BYPASS_SECCOMP: |
a73ec77e | 601 | case SPEC_STORE_BYPASS_PRCTL: |
356e4bff TG |
602 | if (task_spec_ssb_force_disable(task)) |
603 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
604 | if (task_spec_ssb_disable(task)) | |
a73ec77e TG |
605 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; |
606 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
607 | default: | |
608 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
609 | return PR_SPEC_ENABLE; | |
610 | return PR_SPEC_NOT_AFFECTED; | |
611 | } | |
612 | } | |
613 | ||
7bbf1373 | 614 | int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) |
a73ec77e TG |
615 | { |
616 | switch (which) { | |
617 | case PR_SPEC_STORE_BYPASS: | |
7bbf1373 | 618 | return ssb_prctl_get(task); |
a73ec77e TG |
619 | default: |
620 | return -ENODEV; | |
621 | } | |
622 | } | |
623 | ||
77243971 KRW |
624 | void x86_spec_ctrl_setup_ap(void) |
625 | { | |
7eb8956a | 626 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
4b59bdb5 | 627 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
764f3c21 KRW |
628 | |
629 | if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) | |
9f65fb29 | 630 | x86_amd_ssb_disable(); |
77243971 KRW |
631 | } |
632 | ||
61dc0f55 | 633 | #ifdef CONFIG_SYSFS |
d1059518 | 634 | |
7bb4d366 | 635 | static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, |
ffed645e | 636 | char *buf, unsigned int bug) |
61dc0f55 | 637 | { |
d1059518 | 638 | if (!boot_cpu_has_bug(bug)) |
61dc0f55 | 639 | return sprintf(buf, "Not affected\n"); |
d1059518 KRW |
640 | |
641 | switch (bug) { | |
642 | case X86_BUG_CPU_MELTDOWN: | |
643 | if (boot_cpu_has(X86_FEATURE_PTI)) | |
644 | return sprintf(buf, "Mitigation: PTI\n"); | |
645 | ||
6cb2b08f JK |
646 | if (hypervisor_is_type(X86_HYPER_XEN_PV)) |
647 | return sprintf(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n"); | |
648 | ||
d1059518 KRW |
649 | break; |
650 | ||
651 | case X86_BUG_SPECTRE_V1: | |
652 | return sprintf(buf, "Mitigation: __user pointer sanitization\n"); | |
653 | ||
654 | case X86_BUG_SPECTRE_V2: | |
655 | return sprintf(buf, "%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], | |
656 | boot_cpu_has(X86_FEATURE_USE_IBPB) ? ", IBPB" : "", | |
657 | boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", | |
658 | spectre_v2_module_string()); | |
659 | ||
24f7fc83 KRW |
660 | case X86_BUG_SPEC_STORE_BYPASS: |
661 | return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); | |
662 | ||
d1059518 KRW |
663 | default: |
664 | break; | |
665 | } | |
666 | ||
61dc0f55 TG |
667 | return sprintf(buf, "Vulnerable\n"); |
668 | } | |
669 | ||
d1059518 KRW |
670 | ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) |
671 | { | |
672 | return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); | |
673 | } | |
674 | ||
21e433bd | 675 | ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 676 | { |
d1059518 | 677 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); |
61dc0f55 TG |
678 | } |
679 | ||
21e433bd | 680 | ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 681 | { |
d1059518 | 682 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); |
61dc0f55 | 683 | } |
c456442c KRW |
684 | |
685 | ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) | |
686 | { | |
687 | return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); | |
688 | } | |
61dc0f55 | 689 | #endif |