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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1353ebb4 | 2 | /* |
1353ebb4 JF |
3 | * Copyright (C) 1994 Linus Torvalds |
4 | * | |
5 | * Cyrix stuff, June 1998 by: | |
6 | * - Rafael R. Reilova (moved everything from head.S), | |
7 | * <rreilova@ececs.uc.edu> | |
8 | * - Channing Corn (tests & fixes), | |
9 | * - Andrew D. Balsa (code cleanup). | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/utsname.h> | |
61dc0f55 | 13 | #include <linux/cpu.h> |
caf7501a | 14 | #include <linux/module.h> |
a73ec77e TG |
15 | #include <linux/nospec.h> |
16 | #include <linux/prctl.h> | |
da285121 | 17 | |
28a27752 | 18 | #include <asm/spec-ctrl.h> |
da285121 | 19 | #include <asm/cmdline.h> |
91eb1b79 | 20 | #include <asm/bugs.h> |
1353ebb4 | 21 | #include <asm/processor.h> |
7ebad705 | 22 | #include <asm/processor-flags.h> |
952f07ec | 23 | #include <asm/fpu/internal.h> |
1353ebb4 | 24 | #include <asm/msr.h> |
72c6d2db | 25 | #include <asm/vmx.h> |
1353ebb4 JF |
26 | #include <asm/paravirt.h> |
27 | #include <asm/alternative.h> | |
62a67e12 | 28 | #include <asm/pgtable.h> |
d1163651 | 29 | #include <asm/set_memory.h> |
c995efd5 | 30 | #include <asm/intel-family.h> |
17dbca11 | 31 | #include <asm/e820/api.h> |
1353ebb4 | 32 | |
da285121 | 33 | static void __init spectre_v2_select_mitigation(void); |
24f7fc83 | 34 | static void __init ssb_select_mitigation(void); |
17dbca11 | 35 | static void __init l1tf_select_mitigation(void); |
da285121 | 36 | |
1b86883c KRW |
37 | /* |
38 | * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any | |
39 | * writes to SPEC_CTRL contain whatever reserved bits have been set. | |
40 | */ | |
885f82bf | 41 | u64 __ro_after_init x86_spec_ctrl_base; |
fa8ac498 | 42 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); |
1b86883c | 43 | |
1115a859 KRW |
44 | /* |
45 | * The vendor and possibly platform specific bits which can be modified in | |
46 | * x86_spec_ctrl_base. | |
47 | */ | |
be6fcb54 | 48 | static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS; |
1115a859 | 49 | |
764f3c21 KRW |
50 | /* |
51 | * AMD specific MSR info for Speculative Store Bypass control. | |
9f65fb29 | 52 | * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). |
764f3c21 KRW |
53 | */ |
54 | u64 __ro_after_init x86_amd_ls_cfg_base; | |
9f65fb29 | 55 | u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; |
764f3c21 | 56 | |
1353ebb4 JF |
57 | void __init check_bugs(void) |
58 | { | |
59 | identify_boot_cpu(); | |
55a36b65 | 60 | |
fee0aede TG |
61 | /* |
62 | * identify_boot_cpu() initialized SMT support information, let the | |
63 | * core code know. | |
64 | */ | |
65 | cpu_smt_check_topology(); | |
66 | ||
62a67e12 BP |
67 | if (!IS_ENABLED(CONFIG_SMP)) { |
68 | pr_info("CPU: "); | |
69 | print_cpu_info(&boot_cpu_data); | |
70 | } | |
71 | ||
1b86883c KRW |
72 | /* |
73 | * Read the SPEC_CTRL MSR to account for reserved bits which may | |
764f3c21 KRW |
74 | * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD |
75 | * init code as it is not enumerated and depends on the family. | |
1b86883c | 76 | */ |
7eb8956a | 77 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
1b86883c KRW |
78 | rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
79 | ||
be6fcb54 TG |
80 | /* Allow STIBP in MSR_SPEC_CTRL if supported */ |
81 | if (boot_cpu_has(X86_FEATURE_STIBP)) | |
82 | x86_spec_ctrl_mask |= SPEC_CTRL_STIBP; | |
83 | ||
da285121 DW |
84 | /* Select the proper spectre mitigation before patching alternatives */ |
85 | spectre_v2_select_mitigation(); | |
86 | ||
24f7fc83 KRW |
87 | /* |
88 | * Select proper mitigation for any exposure to the Speculative Store | |
89 | * Bypass vulnerability. | |
90 | */ | |
91 | ssb_select_mitigation(); | |
92 | ||
17dbca11 AK |
93 | l1tf_select_mitigation(); |
94 | ||
62a67e12 | 95 | #ifdef CONFIG_X86_32 |
55a36b65 BP |
96 | /* |
97 | * Check whether we are able to run this kernel safely on SMP. | |
98 | * | |
99 | * - i386 is no longer supported. | |
100 | * - In order to run on anything without a TSC, we need to be | |
101 | * compiled for a i486. | |
102 | */ | |
103 | if (boot_cpu_data.x86 < 4) | |
104 | panic("Kernel requires i486+ for 'invlpg' and other features"); | |
105 | ||
bfe4bb15 MV |
106 | init_utsname()->machine[1] = |
107 | '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); | |
1353ebb4 | 108 | alternative_instructions(); |
304bceda | 109 | |
4d164092 | 110 | fpu__init_check_bugs(); |
62a67e12 BP |
111 | #else /* CONFIG_X86_64 */ |
112 | alternative_instructions(); | |
113 | ||
114 | /* | |
115 | * Make sure the first 2MB area is not mapped by huge pages | |
116 | * There are typically fixed size MTRRs in there and overlapping | |
117 | * MTRRs into large pages causes slow downs. | |
118 | * | |
119 | * Right now we don't do that with gbpages because there seems | |
120 | * very little benefit for that case. | |
121 | */ | |
122 | if (!direct_gbpages) | |
123 | set_memory_4k((unsigned long)__va(0), 1); | |
124 | #endif | |
1353ebb4 | 125 | } |
61dc0f55 | 126 | |
da285121 DW |
127 | /* The kernel command line selection */ |
128 | enum spectre_v2_mitigation_cmd { | |
129 | SPECTRE_V2_CMD_NONE, | |
130 | SPECTRE_V2_CMD_AUTO, | |
131 | SPECTRE_V2_CMD_FORCE, | |
132 | SPECTRE_V2_CMD_RETPOLINE, | |
133 | SPECTRE_V2_CMD_RETPOLINE_GENERIC, | |
134 | SPECTRE_V2_CMD_RETPOLINE_AMD, | |
135 | }; | |
136 | ||
137 | static const char *spectre_v2_strings[] = { | |
138 | [SPECTRE_V2_NONE] = "Vulnerable", | |
139 | [SPECTRE_V2_RETPOLINE_MINIMAL] = "Vulnerable: Minimal generic ASM retpoline", | |
140 | [SPECTRE_V2_RETPOLINE_MINIMAL_AMD] = "Vulnerable: Minimal AMD ASM retpoline", | |
141 | [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", | |
142 | [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", | |
143 | }; | |
144 | ||
145 | #undef pr_fmt | |
55fa19d3 | 146 | #define pr_fmt(fmt) "Spectre V2 : " fmt |
da285121 | 147 | |
f9544b2b KC |
148 | static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = |
149 | SPECTRE_V2_NONE; | |
caf7501a | 150 | |
cc69b349 BP |
151 | void |
152 | x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) | |
5cf68754 | 153 | { |
be6fcb54 | 154 | u64 msrval, guestval, hostval = x86_spec_ctrl_base; |
cc69b349 | 155 | struct thread_info *ti = current_thread_info(); |
885f82bf | 156 | |
7eb8956a | 157 | /* Is MSR_SPEC_CTRL implemented ? */ |
cc69b349 | 158 | if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { |
be6fcb54 TG |
159 | /* |
160 | * Restrict guest_spec_ctrl to supported values. Clear the | |
161 | * modifiable bits in the host base value and or the | |
162 | * modifiable bits from the guest value. | |
163 | */ | |
164 | guestval = hostval & ~x86_spec_ctrl_mask; | |
165 | guestval |= guest_spec_ctrl & x86_spec_ctrl_mask; | |
166 | ||
cc69b349 BP |
167 | /* SSBD controlled in MSR_SPEC_CTRL */ |
168 | if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD)) | |
be6fcb54 | 169 | hostval |= ssbd_tif_to_spec_ctrl(ti->flags); |
cc69b349 | 170 | |
be6fcb54 TG |
171 | if (hostval != guestval) { |
172 | msrval = setguest ? guestval : hostval; | |
173 | wrmsrl(MSR_IA32_SPEC_CTRL, msrval); | |
cc69b349 BP |
174 | } |
175 | } | |
47c61b39 TG |
176 | |
177 | /* | |
178 | * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update | |
179 | * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported. | |
180 | */ | |
181 | if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) && | |
182 | !static_cpu_has(X86_FEATURE_VIRT_SSBD)) | |
183 | return; | |
184 | ||
185 | /* | |
186 | * If the host has SSBD mitigation enabled, force it in the host's | |
187 | * virtual MSR value. If its not permanently enabled, evaluate | |
188 | * current's TIF_SSBD thread flag. | |
189 | */ | |
190 | if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE)) | |
191 | hostval = SPEC_CTRL_SSBD; | |
192 | else | |
193 | hostval = ssbd_tif_to_spec_ctrl(ti->flags); | |
194 | ||
195 | /* Sanitize the guest value */ | |
196 | guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD; | |
197 | ||
198 | if (hostval != guestval) { | |
199 | unsigned long tif; | |
200 | ||
201 | tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) : | |
202 | ssbd_spec_ctrl_to_tif(hostval); | |
203 | ||
204 | speculative_store_bypass_update(tif); | |
205 | } | |
5cf68754 | 206 | } |
cc69b349 | 207 | EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); |
5cf68754 | 208 | |
9f65fb29 | 209 | static void x86_amd_ssb_disable(void) |
764f3c21 | 210 | { |
9f65fb29 | 211 | u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; |
764f3c21 | 212 | |
11fb0683 TL |
213 | if (boot_cpu_has(X86_FEATURE_VIRT_SSBD)) |
214 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); | |
215 | else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) | |
764f3c21 KRW |
216 | wrmsrl(MSR_AMD64_LS_CFG, msrval); |
217 | } | |
218 | ||
caf7501a | 219 | #ifdef RETPOLINE |
e383095c TG |
220 | static bool spectre_v2_bad_module; |
221 | ||
caf7501a AK |
222 | bool retpoline_module_ok(bool has_retpoline) |
223 | { | |
224 | if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) | |
225 | return true; | |
226 | ||
e698dcdf | 227 | pr_err("System may be vulnerable to spectre v2\n"); |
caf7501a AK |
228 | spectre_v2_bad_module = true; |
229 | return false; | |
230 | } | |
e383095c TG |
231 | |
232 | static inline const char *spectre_v2_module_string(void) | |
233 | { | |
234 | return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; | |
235 | } | |
236 | #else | |
237 | static inline const char *spectre_v2_module_string(void) { return ""; } | |
caf7501a | 238 | #endif |
da285121 DW |
239 | |
240 | static void __init spec2_print_if_insecure(const char *reason) | |
241 | { | |
242 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
9005c683 | 243 | pr_info("%s selected on command line.\n", reason); |
da285121 DW |
244 | } |
245 | ||
246 | static void __init spec2_print_if_secure(const char *reason) | |
247 | { | |
248 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
9005c683 | 249 | pr_info("%s selected on command line.\n", reason); |
da285121 DW |
250 | } |
251 | ||
252 | static inline bool retp_compiler(void) | |
253 | { | |
254 | return __is_defined(RETPOLINE); | |
255 | } | |
256 | ||
257 | static inline bool match_option(const char *arg, int arglen, const char *opt) | |
258 | { | |
259 | int len = strlen(opt); | |
260 | ||
261 | return len == arglen && !strncmp(arg, opt, len); | |
262 | } | |
263 | ||
9005c683 KA |
264 | static const struct { |
265 | const char *option; | |
266 | enum spectre_v2_mitigation_cmd cmd; | |
267 | bool secure; | |
268 | } mitigation_options[] = { | |
269 | { "off", SPECTRE_V2_CMD_NONE, false }, | |
270 | { "on", SPECTRE_V2_CMD_FORCE, true }, | |
271 | { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, | |
272 | { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false }, | |
273 | { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, | |
274 | { "auto", SPECTRE_V2_CMD_AUTO, false }, | |
275 | }; | |
276 | ||
da285121 DW |
277 | static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) |
278 | { | |
279 | char arg[20]; | |
9005c683 KA |
280 | int ret, i; |
281 | enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; | |
282 | ||
283 | if (cmdline_find_option_bool(boot_command_line, "nospectre_v2")) | |
284 | return SPECTRE_V2_CMD_NONE; | |
285 | else { | |
21e433bd | 286 | ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); |
9005c683 KA |
287 | if (ret < 0) |
288 | return SPECTRE_V2_CMD_AUTO; | |
289 | ||
290 | for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { | |
291 | if (!match_option(arg, ret, mitigation_options[i].option)) | |
292 | continue; | |
293 | cmd = mitigation_options[i].cmd; | |
294 | break; | |
295 | } | |
296 | ||
297 | if (i >= ARRAY_SIZE(mitigation_options)) { | |
9de29eac | 298 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); |
da285121 DW |
299 | return SPECTRE_V2_CMD_AUTO; |
300 | } | |
301 | } | |
302 | ||
9005c683 KA |
303 | if ((cmd == SPECTRE_V2_CMD_RETPOLINE || |
304 | cmd == SPECTRE_V2_CMD_RETPOLINE_AMD || | |
305 | cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) && | |
306 | !IS_ENABLED(CONFIG_RETPOLINE)) { | |
21e433bd | 307 | pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option); |
da285121 | 308 | return SPECTRE_V2_CMD_AUTO; |
9005c683 KA |
309 | } |
310 | ||
311 | if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD && | |
312 | boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { | |
313 | pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n"); | |
314 | return SPECTRE_V2_CMD_AUTO; | |
315 | } | |
316 | ||
317 | if (mitigation_options[i].secure) | |
318 | spec2_print_if_secure(mitigation_options[i].option); | |
319 | else | |
320 | spec2_print_if_insecure(mitigation_options[i].option); | |
321 | ||
322 | return cmd; | |
da285121 DW |
323 | } |
324 | ||
c995efd5 DW |
325 | /* Check for Skylake-like CPUs (for RSB handling) */ |
326 | static bool __init is_skylake_era(void) | |
327 | { | |
328 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
329 | boot_cpu_data.x86 == 6) { | |
330 | switch (boot_cpu_data.x86_model) { | |
331 | case INTEL_FAM6_SKYLAKE_MOBILE: | |
332 | case INTEL_FAM6_SKYLAKE_DESKTOP: | |
333 | case INTEL_FAM6_SKYLAKE_X: | |
334 | case INTEL_FAM6_KABYLAKE_MOBILE: | |
335 | case INTEL_FAM6_KABYLAKE_DESKTOP: | |
336 | return true; | |
337 | } | |
338 | } | |
339 | return false; | |
340 | } | |
341 | ||
da285121 DW |
342 | static void __init spectre_v2_select_mitigation(void) |
343 | { | |
344 | enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); | |
345 | enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; | |
346 | ||
347 | /* | |
348 | * If the CPU is not affected and the command line mode is NONE or AUTO | |
349 | * then nothing to do. | |
350 | */ | |
351 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && | |
352 | (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) | |
353 | return; | |
354 | ||
355 | switch (cmd) { | |
356 | case SPECTRE_V2_CMD_NONE: | |
357 | return; | |
358 | ||
359 | case SPECTRE_V2_CMD_FORCE: | |
da285121 | 360 | case SPECTRE_V2_CMD_AUTO: |
9471eee9 DL |
361 | if (IS_ENABLED(CONFIG_RETPOLINE)) |
362 | goto retpoline_auto; | |
363 | break; | |
da285121 DW |
364 | case SPECTRE_V2_CMD_RETPOLINE_AMD: |
365 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
366 | goto retpoline_amd; | |
367 | break; | |
368 | case SPECTRE_V2_CMD_RETPOLINE_GENERIC: | |
369 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
370 | goto retpoline_generic; | |
371 | break; | |
372 | case SPECTRE_V2_CMD_RETPOLINE: | |
373 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
374 | goto retpoline_auto; | |
375 | break; | |
376 | } | |
21e433bd | 377 | pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!"); |
da285121 DW |
378 | return; |
379 | ||
380 | retpoline_auto: | |
381 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { | |
382 | retpoline_amd: | |
383 | if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { | |
21e433bd | 384 | pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n"); |
da285121 DW |
385 | goto retpoline_generic; |
386 | } | |
387 | mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD : | |
388 | SPECTRE_V2_RETPOLINE_MINIMAL_AMD; | |
389 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD); | |
390 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
391 | } else { | |
392 | retpoline_generic: | |
393 | mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC : | |
394 | SPECTRE_V2_RETPOLINE_MINIMAL; | |
395 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
396 | } | |
397 | ||
398 | spectre_v2_enabled = mode; | |
399 | pr_info("%s\n", spectre_v2_strings[mode]); | |
c995efd5 DW |
400 | |
401 | /* | |
21e433bd | 402 | * If neither SMEP nor PTI are available, there is a risk of |
c995efd5 DW |
403 | * hitting userspace addresses in the RSB after a context switch |
404 | * from a shallow call stack to a deeper one. To prevent this fill | |
405 | * the entire RSB, even when using IBRS. | |
406 | * | |
407 | * Skylake era CPUs have a separate issue with *underflow* of the | |
408 | * RSB, when they will predict 'ret' targets from the generic BTB. | |
409 | * The proper mitigation for this is IBRS. If IBRS is not supported | |
410 | * or deactivated in favour of retpolines the RSB fill on context | |
411 | * switch is required. | |
412 | */ | |
413 | if ((!boot_cpu_has(X86_FEATURE_PTI) && | |
414 | !boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) { | |
415 | setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); | |
21e433bd | 416 | pr_info("Spectre v2 mitigation: Filling RSB on context switch\n"); |
c995efd5 | 417 | } |
20ffa1ca DW |
418 | |
419 | /* Initialize Indirect Branch Prediction Barrier if supported */ | |
2961298e DW |
420 | if (boot_cpu_has(X86_FEATURE_IBPB)) { |
421 | setup_force_cpu_cap(X86_FEATURE_USE_IBPB); | |
21e433bd | 422 | pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n"); |
20ffa1ca | 423 | } |
dd84441a DW |
424 | |
425 | /* | |
426 | * Retpoline means the kernel is safe because it has no indirect | |
427 | * branches. But firmware isn't, so use IBRS to protect that. | |
428 | */ | |
429 | if (boot_cpu_has(X86_FEATURE_IBRS)) { | |
430 | setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); | |
431 | pr_info("Enabling Restricted Speculation for firmware calls\n"); | |
432 | } | |
da285121 DW |
433 | } |
434 | ||
24f7fc83 KRW |
435 | #undef pr_fmt |
436 | #define pr_fmt(fmt) "Speculative Store Bypass: " fmt | |
437 | ||
f9544b2b | 438 | static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE; |
24f7fc83 KRW |
439 | |
440 | /* The kernel command line selection */ | |
441 | enum ssb_mitigation_cmd { | |
442 | SPEC_STORE_BYPASS_CMD_NONE, | |
443 | SPEC_STORE_BYPASS_CMD_AUTO, | |
444 | SPEC_STORE_BYPASS_CMD_ON, | |
a73ec77e | 445 | SPEC_STORE_BYPASS_CMD_PRCTL, |
f21b53b2 | 446 | SPEC_STORE_BYPASS_CMD_SECCOMP, |
24f7fc83 KRW |
447 | }; |
448 | ||
449 | static const char *ssb_strings[] = { | |
450 | [SPEC_STORE_BYPASS_NONE] = "Vulnerable", | |
a73ec77e | 451 | [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", |
f21b53b2 KC |
452 | [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", |
453 | [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp", | |
24f7fc83 KRW |
454 | }; |
455 | ||
456 | static const struct { | |
457 | const char *option; | |
458 | enum ssb_mitigation_cmd cmd; | |
459 | } ssb_mitigation_options[] = { | |
f21b53b2 KC |
460 | { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ |
461 | { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ | |
462 | { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ | |
463 | { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */ | |
464 | { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */ | |
24f7fc83 KRW |
465 | }; |
466 | ||
467 | static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) | |
468 | { | |
469 | enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO; | |
470 | char arg[20]; | |
471 | int ret, i; | |
472 | ||
473 | if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) { | |
474 | return SPEC_STORE_BYPASS_CMD_NONE; | |
475 | } else { | |
476 | ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", | |
477 | arg, sizeof(arg)); | |
478 | if (ret < 0) | |
479 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
480 | ||
481 | for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { | |
482 | if (!match_option(arg, ret, ssb_mitigation_options[i].option)) | |
483 | continue; | |
484 | ||
485 | cmd = ssb_mitigation_options[i].cmd; | |
486 | break; | |
487 | } | |
488 | ||
489 | if (i >= ARRAY_SIZE(ssb_mitigation_options)) { | |
490 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
491 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
492 | } | |
493 | } | |
494 | ||
495 | return cmd; | |
496 | } | |
497 | ||
d66d8ff3 | 498 | static enum ssb_mitigation __init __ssb_select_mitigation(void) |
24f7fc83 KRW |
499 | { |
500 | enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; | |
501 | enum ssb_mitigation_cmd cmd; | |
502 | ||
9f65fb29 | 503 | if (!boot_cpu_has(X86_FEATURE_SSBD)) |
24f7fc83 KRW |
504 | return mode; |
505 | ||
506 | cmd = ssb_parse_cmdline(); | |
507 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && | |
508 | (cmd == SPEC_STORE_BYPASS_CMD_NONE || | |
509 | cmd == SPEC_STORE_BYPASS_CMD_AUTO)) | |
510 | return mode; | |
511 | ||
512 | switch (cmd) { | |
513 | case SPEC_STORE_BYPASS_CMD_AUTO: | |
f21b53b2 KC |
514 | case SPEC_STORE_BYPASS_CMD_SECCOMP: |
515 | /* | |
516 | * Choose prctl+seccomp as the default mode if seccomp is | |
517 | * enabled. | |
518 | */ | |
519 | if (IS_ENABLED(CONFIG_SECCOMP)) | |
520 | mode = SPEC_STORE_BYPASS_SECCOMP; | |
521 | else | |
522 | mode = SPEC_STORE_BYPASS_PRCTL; | |
a73ec77e | 523 | break; |
24f7fc83 KRW |
524 | case SPEC_STORE_BYPASS_CMD_ON: |
525 | mode = SPEC_STORE_BYPASS_DISABLE; | |
526 | break; | |
a73ec77e TG |
527 | case SPEC_STORE_BYPASS_CMD_PRCTL: |
528 | mode = SPEC_STORE_BYPASS_PRCTL; | |
529 | break; | |
24f7fc83 KRW |
530 | case SPEC_STORE_BYPASS_CMD_NONE: |
531 | break; | |
532 | } | |
533 | ||
77243971 KRW |
534 | /* |
535 | * We have three CPU feature flags that are in play here: | |
536 | * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. | |
9f65fb29 | 537 | * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass |
77243971 KRW |
538 | * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation |
539 | */ | |
a73ec77e | 540 | if (mode == SPEC_STORE_BYPASS_DISABLE) { |
24f7fc83 | 541 | setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); |
77243971 | 542 | /* |
6ac2f49e KRW |
543 | * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may |
544 | * use a completely different MSR and bit dependent on family. | |
77243971 | 545 | */ |
108fab4b KRW |
546 | if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
547 | x86_amd_ssb_disable(); | |
548 | else { | |
9f65fb29 | 549 | x86_spec_ctrl_base |= SPEC_CTRL_SSBD; |
be6fcb54 | 550 | x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; |
4b59bdb5 | 551 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
77243971 KRW |
552 | } |
553 | } | |
554 | ||
24f7fc83 KRW |
555 | return mode; |
556 | } | |
557 | ||
ffed645e | 558 | static void ssb_select_mitigation(void) |
24f7fc83 KRW |
559 | { |
560 | ssb_mode = __ssb_select_mitigation(); | |
561 | ||
562 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
563 | pr_info("%s\n", ssb_strings[ssb_mode]); | |
564 | } | |
565 | ||
da285121 | 566 | #undef pr_fmt |
f21b53b2 | 567 | #define pr_fmt(fmt) "Speculation prctl: " fmt |
da285121 | 568 | |
7bbf1373 | 569 | static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) |
a73ec77e | 570 | { |
356e4bff | 571 | bool update; |
a73ec77e | 572 | |
f21b53b2 KC |
573 | if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && |
574 | ssb_mode != SPEC_STORE_BYPASS_SECCOMP) | |
a73ec77e TG |
575 | return -ENXIO; |
576 | ||
356e4bff TG |
577 | switch (ctrl) { |
578 | case PR_SPEC_ENABLE: | |
579 | /* If speculation is force disabled, enable is not allowed */ | |
580 | if (task_spec_ssb_force_disable(task)) | |
581 | return -EPERM; | |
582 | task_clear_spec_ssb_disable(task); | |
9f65fb29 | 583 | update = test_and_clear_tsk_thread_flag(task, TIF_SSBD); |
356e4bff TG |
584 | break; |
585 | case PR_SPEC_DISABLE: | |
586 | task_set_spec_ssb_disable(task); | |
9f65fb29 | 587 | update = !test_and_set_tsk_thread_flag(task, TIF_SSBD); |
356e4bff TG |
588 | break; |
589 | case PR_SPEC_FORCE_DISABLE: | |
590 | task_set_spec_ssb_disable(task); | |
591 | task_set_spec_ssb_force_disable(task); | |
9f65fb29 | 592 | update = !test_and_set_tsk_thread_flag(task, TIF_SSBD); |
356e4bff TG |
593 | break; |
594 | default: | |
595 | return -ERANGE; | |
596 | } | |
a73ec77e | 597 | |
7bbf1373 KC |
598 | /* |
599 | * If being set on non-current task, delay setting the CPU | |
600 | * mitigation until it is next scheduled. | |
601 | */ | |
356e4bff | 602 | if (task == current && update) |
0270be3e | 603 | speculative_store_bypass_update_current(); |
a73ec77e TG |
604 | |
605 | return 0; | |
606 | } | |
607 | ||
8bf37d8c TG |
608 | int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, |
609 | unsigned long ctrl) | |
610 | { | |
611 | switch (which) { | |
612 | case PR_SPEC_STORE_BYPASS: | |
613 | return ssb_prctl_set(task, ctrl); | |
614 | default: | |
615 | return -ENODEV; | |
616 | } | |
617 | } | |
618 | ||
619 | #ifdef CONFIG_SECCOMP | |
620 | void arch_seccomp_spec_mitigate(struct task_struct *task) | |
621 | { | |
f21b53b2 KC |
622 | if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) |
623 | ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
8bf37d8c TG |
624 | } |
625 | #endif | |
626 | ||
7bbf1373 | 627 | static int ssb_prctl_get(struct task_struct *task) |
a73ec77e TG |
628 | { |
629 | switch (ssb_mode) { | |
630 | case SPEC_STORE_BYPASS_DISABLE: | |
631 | return PR_SPEC_DISABLE; | |
f21b53b2 | 632 | case SPEC_STORE_BYPASS_SECCOMP: |
a73ec77e | 633 | case SPEC_STORE_BYPASS_PRCTL: |
356e4bff TG |
634 | if (task_spec_ssb_force_disable(task)) |
635 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
636 | if (task_spec_ssb_disable(task)) | |
a73ec77e TG |
637 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; |
638 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
639 | default: | |
640 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
641 | return PR_SPEC_ENABLE; | |
642 | return PR_SPEC_NOT_AFFECTED; | |
643 | } | |
644 | } | |
645 | ||
7bbf1373 | 646 | int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) |
a73ec77e TG |
647 | { |
648 | switch (which) { | |
649 | case PR_SPEC_STORE_BYPASS: | |
7bbf1373 | 650 | return ssb_prctl_get(task); |
a73ec77e TG |
651 | default: |
652 | return -ENODEV; | |
653 | } | |
654 | } | |
655 | ||
77243971 KRW |
656 | void x86_spec_ctrl_setup_ap(void) |
657 | { | |
7eb8956a | 658 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
4b59bdb5 | 659 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
764f3c21 KRW |
660 | |
661 | if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) | |
9f65fb29 | 662 | x86_amd_ssb_disable(); |
77243971 KRW |
663 | } |
664 | ||
56563f53 KRW |
665 | #undef pr_fmt |
666 | #define pr_fmt(fmt) "L1TF: " fmt | |
72c6d2db TG |
667 | |
668 | #if IS_ENABLED(CONFIG_KVM_INTEL) | |
895ae47f | 669 | enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; |
72c6d2db TG |
670 | EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation); |
671 | #endif | |
672 | ||
56563f53 KRW |
673 | static void __init l1tf_select_mitigation(void) |
674 | { | |
675 | u64 half_pa; | |
676 | ||
677 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
678 | return; | |
679 | ||
680 | #if CONFIG_PGTABLE_LEVELS == 2 | |
681 | pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n"); | |
682 | return; | |
683 | #endif | |
684 | ||
685 | /* | |
686 | * This is extremely unlikely to happen because almost all | |
687 | * systems have far more MAX_PA/2 than RAM can be fit into | |
688 | * DIMM slots. | |
689 | */ | |
690 | half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT; | |
691 | if (e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) { | |
692 | pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n"); | |
693 | return; | |
694 | } | |
695 | ||
696 | setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV); | |
697 | } | |
698 | #undef pr_fmt | |
699 | ||
61dc0f55 | 700 | #ifdef CONFIG_SYSFS |
d1059518 | 701 | |
72c6d2db TG |
702 | #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion" |
703 | ||
704 | #if IS_ENABLED(CONFIG_KVM_INTEL) | |
705 | static const char *l1tf_vmx_states[] = { | |
a7b9020b TG |
706 | [VMENTER_L1D_FLUSH_AUTO] = "auto", |
707 | [VMENTER_L1D_FLUSH_NEVER] = "vulnerable", | |
708 | [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes", | |
709 | [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes", | |
710 | [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled", | |
72c6d2db TG |
711 | }; |
712 | ||
713 | static ssize_t l1tf_show_state(char *buf) | |
714 | { | |
715 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) | |
716 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
717 | ||
718 | return sprintf(buf, "%s; VMX: SMT %s, L1D %s\n", L1TF_DEFAULT_MSG, | |
719 | cpu_smt_control == CPU_SMT_ENABLED ? "vulnerable" : "disabled", | |
720 | l1tf_vmx_states[l1tf_vmx_mitigation]); | |
721 | } | |
722 | #else | |
723 | static ssize_t l1tf_show_state(char *buf) | |
724 | { | |
725 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
726 | } | |
727 | #endif | |
728 | ||
7bb4d366 | 729 | static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, |
ffed645e | 730 | char *buf, unsigned int bug) |
61dc0f55 | 731 | { |
d1059518 | 732 | if (!boot_cpu_has_bug(bug)) |
61dc0f55 | 733 | return sprintf(buf, "Not affected\n"); |
d1059518 KRW |
734 | |
735 | switch (bug) { | |
736 | case X86_BUG_CPU_MELTDOWN: | |
737 | if (boot_cpu_has(X86_FEATURE_PTI)) | |
738 | return sprintf(buf, "Mitigation: PTI\n"); | |
739 | ||
740 | break; | |
741 | ||
742 | case X86_BUG_SPECTRE_V1: | |
743 | return sprintf(buf, "Mitigation: __user pointer sanitization\n"); | |
744 | ||
745 | case X86_BUG_SPECTRE_V2: | |
746 | return sprintf(buf, "%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], | |
747 | boot_cpu_has(X86_FEATURE_USE_IBPB) ? ", IBPB" : "", | |
748 | boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", | |
749 | spectre_v2_module_string()); | |
750 | ||
24f7fc83 KRW |
751 | case X86_BUG_SPEC_STORE_BYPASS: |
752 | return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); | |
753 | ||
17dbca11 AK |
754 | case X86_BUG_L1TF: |
755 | if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV)) | |
72c6d2db | 756 | return l1tf_show_state(buf); |
17dbca11 | 757 | break; |
d1059518 KRW |
758 | default: |
759 | break; | |
760 | } | |
761 | ||
61dc0f55 TG |
762 | return sprintf(buf, "Vulnerable\n"); |
763 | } | |
764 | ||
d1059518 KRW |
765 | ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) |
766 | { | |
767 | return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); | |
768 | } | |
769 | ||
21e433bd | 770 | ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 771 | { |
d1059518 | 772 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); |
61dc0f55 TG |
773 | } |
774 | ||
21e433bd | 775 | ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 776 | { |
d1059518 | 777 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); |
61dc0f55 | 778 | } |
c456442c KRW |
779 | |
780 | ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) | |
781 | { | |
782 | return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); | |
783 | } | |
17dbca11 AK |
784 | |
785 | ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf) | |
786 | { | |
787 | return cpu_show_common(dev, attr, buf, X86_BUG_L1TF); | |
788 | } | |
61dc0f55 | 789 | #endif |