]>
Commit | Line | Data |
---|---|---|
b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1353ebb4 | 2 | /* |
1353ebb4 JF |
3 | * Copyright (C) 1994 Linus Torvalds |
4 | * | |
5 | * Cyrix stuff, June 1998 by: | |
6 | * - Rafael R. Reilova (moved everything from head.S), | |
7 | * <rreilova@ececs.uc.edu> | |
8 | * - Channing Corn (tests & fixes), | |
9 | * - Andrew D. Balsa (code cleanup). | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/utsname.h> | |
61dc0f55 | 13 | #include <linux/cpu.h> |
caf7501a | 14 | #include <linux/module.h> |
a73ec77e TG |
15 | #include <linux/nospec.h> |
16 | #include <linux/prctl.h> | |
a74cfffb | 17 | #include <linux/sched/smt.h> |
65fddcfc | 18 | #include <linux/pgtable.h> |
534fcc9a | 19 | #include <linux/bpf.h> |
da285121 | 20 | |
28a27752 | 21 | #include <asm/spec-ctrl.h> |
da285121 | 22 | #include <asm/cmdline.h> |
91eb1b79 | 23 | #include <asm/bugs.h> |
1353ebb4 | 24 | #include <asm/processor.h> |
7ebad705 | 25 | #include <asm/processor-flags.h> |
4e85b53e | 26 | #include <asm/fpu/api.h> |
1353ebb4 | 27 | #include <asm/msr.h> |
72c6d2db | 28 | #include <asm/vmx.h> |
1353ebb4 JF |
29 | #include <asm/paravirt.h> |
30 | #include <asm/alternative.h> | |
d1163651 | 31 | #include <asm/set_memory.h> |
c995efd5 | 32 | #include <asm/intel-family.h> |
17dbca11 | 33 | #include <asm/e820/api.h> |
6cb2b08f | 34 | #include <asm/hypervisor.h> |
f29dfa53 | 35 | #include <asm/tlbflush.h> |
1353ebb4 | 36 | |
ad3bc25a BP |
37 | #include "cpu.h" |
38 | ||
a2059825 | 39 | static void __init spectre_v1_select_mitigation(void); |
da285121 | 40 | static void __init spectre_v2_select_mitigation(void); |
24f7fc83 | 41 | static void __init ssb_select_mitigation(void); |
17dbca11 | 42 | static void __init l1tf_select_mitigation(void); |
bc124170 | 43 | static void __init mds_select_mitigation(void); |
6a9231bf | 44 | static void __init md_clear_update_mitigation(void); |
b9bc1fb8 | 45 | static void __init md_clear_select_mitigation(void); |
1b42f017 | 46 | static void __init taa_select_mitigation(void); |
2418c6b1 | 47 | static void __init mmio_select_mitigation(void); |
7e5b3c26 | 48 | static void __init srbds_select_mitigation(void); |
b5f06f64 | 49 | static void __init l1d_flush_select_mitigation(void); |
da285121 | 50 | |
53c613fe JK |
51 | /* The base value of the SPEC_CTRL MSR that always has to be preserved. */ |
52 | u64 x86_spec_ctrl_base; | |
fa8ac498 | 53 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); |
53c613fe | 54 | static DEFINE_MUTEX(spec_ctrl_mutex); |
1b86883c | 55 | |
1115a859 KRW |
56 | /* |
57 | * The vendor and possibly platform specific bits which can be modified in | |
58 | * x86_spec_ctrl_base. | |
59 | */ | |
be6fcb54 | 60 | static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS; |
1115a859 | 61 | |
764f3c21 KRW |
62 | /* |
63 | * AMD specific MSR info for Speculative Store Bypass control. | |
9f65fb29 | 64 | * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). |
764f3c21 KRW |
65 | */ |
66 | u64 __ro_after_init x86_amd_ls_cfg_base; | |
9f65fb29 | 67 | u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; |
764f3c21 | 68 | |
aa77bfb3 | 69 | /* Control conditional STIBP in switch_to() */ |
fa1202ef | 70 | DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp); |
4c71a2b6 TG |
71 | /* Control conditional IBPB in switch_mm() */ |
72 | DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb); | |
73 | /* Control unconditional IBPB in switch_mm() */ | |
74 | DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb); | |
fa1202ef | 75 | |
04dcbdb8 TG |
76 | /* Control MDS CPU buffer clear before returning to user space */ |
77 | DEFINE_STATIC_KEY_FALSE(mds_user_clear); | |
650b68a0 | 78 | EXPORT_SYMBOL_GPL(mds_user_clear); |
07f07f55 TG |
79 | /* Control MDS CPU buffer clear before idling (halt, mwait) */ |
80 | DEFINE_STATIC_KEY_FALSE(mds_idle_clear); | |
81 | EXPORT_SYMBOL_GPL(mds_idle_clear); | |
04dcbdb8 | 82 | |
b5f06f64 BS |
83 | /* |
84 | * Controls whether l1d flush based mitigations are enabled, | |
85 | * based on hw features and admin setting via boot parameter | |
86 | * defaults to false | |
87 | */ | |
88 | DEFINE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush); | |
89 | ||
2418c6b1 PG |
90 | /* Controls CPU Fill buffer clear before KVM guest MMIO accesses */ |
91 | DEFINE_STATIC_KEY_FALSE(mmio_stale_data_clear); | |
92 | EXPORT_SYMBOL_GPL(mmio_stale_data_clear); | |
93 | ||
1353ebb4 JF |
94 | void __init check_bugs(void) |
95 | { | |
96 | identify_boot_cpu(); | |
55a36b65 | 97 | |
fee0aede TG |
98 | /* |
99 | * identify_boot_cpu() initialized SMT support information, let the | |
100 | * core code know. | |
101 | */ | |
b284909a | 102 | cpu_smt_check_topology(); |
fee0aede | 103 | |
62a67e12 BP |
104 | if (!IS_ENABLED(CONFIG_SMP)) { |
105 | pr_info("CPU: "); | |
106 | print_cpu_info(&boot_cpu_data); | |
107 | } | |
108 | ||
1b86883c KRW |
109 | /* |
110 | * Read the SPEC_CTRL MSR to account for reserved bits which may | |
764f3c21 KRW |
111 | * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD |
112 | * init code as it is not enumerated and depends on the family. | |
1b86883c | 113 | */ |
7eb8956a | 114 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
1b86883c KRW |
115 | rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
116 | ||
be6fcb54 TG |
117 | /* Allow STIBP in MSR_SPEC_CTRL if supported */ |
118 | if (boot_cpu_has(X86_FEATURE_STIBP)) | |
119 | x86_spec_ctrl_mask |= SPEC_CTRL_STIBP; | |
120 | ||
a2059825 JP |
121 | /* Select the proper CPU mitigations before patching alternatives: */ |
122 | spectre_v1_select_mitigation(); | |
da285121 | 123 | spectre_v2_select_mitigation(); |
24f7fc83 | 124 | ssb_select_mitigation(); |
17dbca11 | 125 | l1tf_select_mitigation(); |
b9bc1fb8 | 126 | md_clear_select_mitigation(); |
7e5b3c26 | 127 | srbds_select_mitigation(); |
b5f06f64 | 128 | l1d_flush_select_mitigation(); |
bc124170 | 129 | |
7c3658b2 JP |
130 | arch_smt_update(); |
131 | ||
62a67e12 | 132 | #ifdef CONFIG_X86_32 |
55a36b65 BP |
133 | /* |
134 | * Check whether we are able to run this kernel safely on SMP. | |
135 | * | |
136 | * - i386 is no longer supported. | |
137 | * - In order to run on anything without a TSC, we need to be | |
138 | * compiled for a i486. | |
139 | */ | |
140 | if (boot_cpu_data.x86 < 4) | |
141 | panic("Kernel requires i486+ for 'invlpg' and other features"); | |
142 | ||
bfe4bb15 MV |
143 | init_utsname()->machine[1] = |
144 | '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); | |
1353ebb4 | 145 | alternative_instructions(); |
304bceda | 146 | |
4d164092 | 147 | fpu__init_check_bugs(); |
62a67e12 BP |
148 | #else /* CONFIG_X86_64 */ |
149 | alternative_instructions(); | |
150 | ||
151 | /* | |
152 | * Make sure the first 2MB area is not mapped by huge pages | |
153 | * There are typically fixed size MTRRs in there and overlapping | |
154 | * MTRRs into large pages causes slow downs. | |
155 | * | |
156 | * Right now we don't do that with gbpages because there seems | |
157 | * very little benefit for that case. | |
158 | */ | |
159 | if (!direct_gbpages) | |
160 | set_memory_4k((unsigned long)__va(0), 1); | |
161 | #endif | |
1353ebb4 | 162 | } |
61dc0f55 | 163 | |
cc69b349 BP |
164 | void |
165 | x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) | |
5cf68754 | 166 | { |
be6fcb54 | 167 | u64 msrval, guestval, hostval = x86_spec_ctrl_base; |
cc69b349 | 168 | struct thread_info *ti = current_thread_info(); |
885f82bf | 169 | |
7eb8956a | 170 | /* Is MSR_SPEC_CTRL implemented ? */ |
cc69b349 | 171 | if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { |
be6fcb54 TG |
172 | /* |
173 | * Restrict guest_spec_ctrl to supported values. Clear the | |
174 | * modifiable bits in the host base value and or the | |
175 | * modifiable bits from the guest value. | |
176 | */ | |
177 | guestval = hostval & ~x86_spec_ctrl_mask; | |
178 | guestval |= guest_spec_ctrl & x86_spec_ctrl_mask; | |
179 | ||
cc69b349 | 180 | /* SSBD controlled in MSR_SPEC_CTRL */ |
612bc3b3 TL |
181 | if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || |
182 | static_cpu_has(X86_FEATURE_AMD_SSBD)) | |
be6fcb54 | 183 | hostval |= ssbd_tif_to_spec_ctrl(ti->flags); |
cc69b349 | 184 | |
5bfbe3ad TC |
185 | /* Conditional STIBP enabled? */ |
186 | if (static_branch_unlikely(&switch_to_cond_stibp)) | |
187 | hostval |= stibp_tif_to_spec_ctrl(ti->flags); | |
188 | ||
be6fcb54 TG |
189 | if (hostval != guestval) { |
190 | msrval = setguest ? guestval : hostval; | |
191 | wrmsrl(MSR_IA32_SPEC_CTRL, msrval); | |
cc69b349 BP |
192 | } |
193 | } | |
47c61b39 TG |
194 | |
195 | /* | |
196 | * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update | |
197 | * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported. | |
198 | */ | |
199 | if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) && | |
200 | !static_cpu_has(X86_FEATURE_VIRT_SSBD)) | |
201 | return; | |
202 | ||
203 | /* | |
204 | * If the host has SSBD mitigation enabled, force it in the host's | |
205 | * virtual MSR value. If its not permanently enabled, evaluate | |
206 | * current's TIF_SSBD thread flag. | |
207 | */ | |
208 | if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE)) | |
209 | hostval = SPEC_CTRL_SSBD; | |
210 | else | |
211 | hostval = ssbd_tif_to_spec_ctrl(ti->flags); | |
212 | ||
213 | /* Sanitize the guest value */ | |
214 | guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD; | |
215 | ||
216 | if (hostval != guestval) { | |
217 | unsigned long tif; | |
218 | ||
219 | tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) : | |
220 | ssbd_spec_ctrl_to_tif(hostval); | |
221 | ||
26c4d75b | 222 | speculation_ctrl_update(tif); |
47c61b39 | 223 | } |
5cf68754 | 224 | } |
cc69b349 | 225 | EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); |
5cf68754 | 226 | |
9f65fb29 | 227 | static void x86_amd_ssb_disable(void) |
764f3c21 | 228 | { |
9f65fb29 | 229 | u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; |
764f3c21 | 230 | |
11fb0683 TL |
231 | if (boot_cpu_has(X86_FEATURE_VIRT_SSBD)) |
232 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); | |
233 | else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) | |
764f3c21 KRW |
234 | wrmsrl(MSR_AMD64_LS_CFG, msrval); |
235 | } | |
236 | ||
bc124170 TG |
237 | #undef pr_fmt |
238 | #define pr_fmt(fmt) "MDS: " fmt | |
239 | ||
cae5ec34 | 240 | /* Default mitigation for MDS-affected CPUs */ |
bc124170 | 241 | static enum mds_mitigations mds_mitigation __ro_after_init = MDS_MITIGATION_FULL; |
d71eb0ce | 242 | static bool mds_nosmt __ro_after_init = false; |
bc124170 TG |
243 | |
244 | static const char * const mds_strings[] = { | |
245 | [MDS_MITIGATION_OFF] = "Vulnerable", | |
22dd8365 TG |
246 | [MDS_MITIGATION_FULL] = "Mitigation: Clear CPU buffers", |
247 | [MDS_MITIGATION_VMWERV] = "Vulnerable: Clear CPU buffers attempted, no microcode", | |
bc124170 TG |
248 | }; |
249 | ||
250 | static void __init mds_select_mitigation(void) | |
251 | { | |
5c14068f | 252 | if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) { |
bc124170 TG |
253 | mds_mitigation = MDS_MITIGATION_OFF; |
254 | return; | |
255 | } | |
256 | ||
257 | if (mds_mitigation == MDS_MITIGATION_FULL) { | |
22dd8365 TG |
258 | if (!boot_cpu_has(X86_FEATURE_MD_CLEAR)) |
259 | mds_mitigation = MDS_MITIGATION_VMWERV; | |
d71eb0ce | 260 | |
22dd8365 | 261 | static_branch_enable(&mds_user_clear); |
d71eb0ce | 262 | |
5c14068f JP |
263 | if (!boot_cpu_has(X86_BUG_MSBDS_ONLY) && |
264 | (mds_nosmt || cpu_mitigations_auto_nosmt())) | |
d71eb0ce | 265 | cpu_smt_disable(false); |
bc124170 | 266 | } |
cd5a2aa8 WL |
267 | } |
268 | ||
bc124170 TG |
269 | static int __init mds_cmdline(char *str) |
270 | { | |
271 | if (!boot_cpu_has_bug(X86_BUG_MDS)) | |
272 | return 0; | |
273 | ||
274 | if (!str) | |
275 | return -EINVAL; | |
276 | ||
277 | if (!strcmp(str, "off")) | |
278 | mds_mitigation = MDS_MITIGATION_OFF; | |
279 | else if (!strcmp(str, "full")) | |
280 | mds_mitigation = MDS_MITIGATION_FULL; | |
d71eb0ce JP |
281 | else if (!strcmp(str, "full,nosmt")) { |
282 | mds_mitigation = MDS_MITIGATION_FULL; | |
283 | mds_nosmt = true; | |
284 | } | |
bc124170 TG |
285 | |
286 | return 0; | |
287 | } | |
288 | early_param("mds", mds_cmdline); | |
289 | ||
1b42f017 PG |
290 | #undef pr_fmt |
291 | #define pr_fmt(fmt) "TAA: " fmt | |
292 | ||
72c2ce98 BP |
293 | enum taa_mitigations { |
294 | TAA_MITIGATION_OFF, | |
295 | TAA_MITIGATION_UCODE_NEEDED, | |
296 | TAA_MITIGATION_VERW, | |
297 | TAA_MITIGATION_TSX_DISABLED, | |
298 | }; | |
299 | ||
1b42f017 PG |
300 | /* Default mitigation for TAA-affected CPUs */ |
301 | static enum taa_mitigations taa_mitigation __ro_after_init = TAA_MITIGATION_VERW; | |
302 | static bool taa_nosmt __ro_after_init; | |
303 | ||
304 | static const char * const taa_strings[] = { | |
305 | [TAA_MITIGATION_OFF] = "Vulnerable", | |
306 | [TAA_MITIGATION_UCODE_NEEDED] = "Vulnerable: Clear CPU buffers attempted, no microcode", | |
307 | [TAA_MITIGATION_VERW] = "Mitigation: Clear CPU buffers", | |
308 | [TAA_MITIGATION_TSX_DISABLED] = "Mitigation: TSX disabled", | |
309 | }; | |
310 | ||
311 | static void __init taa_select_mitigation(void) | |
312 | { | |
313 | u64 ia32_cap; | |
314 | ||
315 | if (!boot_cpu_has_bug(X86_BUG_TAA)) { | |
316 | taa_mitigation = TAA_MITIGATION_OFF; | |
317 | return; | |
318 | } | |
319 | ||
320 | /* TSX previously disabled by tsx=off */ | |
321 | if (!boot_cpu_has(X86_FEATURE_RTM)) { | |
322 | taa_mitigation = TAA_MITIGATION_TSX_DISABLED; | |
6a9231bf | 323 | return; |
1b42f017 PG |
324 | } |
325 | ||
326 | if (cpu_mitigations_off()) { | |
327 | taa_mitigation = TAA_MITIGATION_OFF; | |
328 | return; | |
329 | } | |
330 | ||
64870ed1 WL |
331 | /* |
332 | * TAA mitigation via VERW is turned off if both | |
333 | * tsx_async_abort=off and mds=off are specified. | |
334 | */ | |
335 | if (taa_mitigation == TAA_MITIGATION_OFF && | |
336 | mds_mitigation == MDS_MITIGATION_OFF) | |
6a9231bf | 337 | return; |
1b42f017 PG |
338 | |
339 | if (boot_cpu_has(X86_FEATURE_MD_CLEAR)) | |
340 | taa_mitigation = TAA_MITIGATION_VERW; | |
341 | else | |
342 | taa_mitigation = TAA_MITIGATION_UCODE_NEEDED; | |
343 | ||
344 | /* | |
345 | * VERW doesn't clear the CPU buffers when MD_CLEAR=1 and MDS_NO=1. | |
346 | * A microcode update fixes this behavior to clear CPU buffers. It also | |
347 | * adds support for MSR_IA32_TSX_CTRL which is enumerated by the | |
348 | * ARCH_CAP_TSX_CTRL_MSR bit. | |
349 | * | |
350 | * On MDS_NO=1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode | |
351 | * update is required. | |
352 | */ | |
353 | ia32_cap = x86_read_arch_cap_msr(); | |
354 | if ( (ia32_cap & ARCH_CAP_MDS_NO) && | |
355 | !(ia32_cap & ARCH_CAP_TSX_CTRL_MSR)) | |
356 | taa_mitigation = TAA_MITIGATION_UCODE_NEEDED; | |
357 | ||
358 | /* | |
359 | * TSX is enabled, select alternate mitigation for TAA which is | |
360 | * the same as MDS. Enable MDS static branch to clear CPU buffers. | |
361 | * | |
362 | * For guests that can't determine whether the correct microcode is | |
363 | * present on host, enable the mitigation for UCODE_NEEDED as well. | |
364 | */ | |
365 | static_branch_enable(&mds_user_clear); | |
366 | ||
367 | if (taa_nosmt || cpu_mitigations_auto_nosmt()) | |
368 | cpu_smt_disable(false); | |
1b42f017 PG |
369 | } |
370 | ||
371 | static int __init tsx_async_abort_parse_cmdline(char *str) | |
372 | { | |
373 | if (!boot_cpu_has_bug(X86_BUG_TAA)) | |
374 | return 0; | |
375 | ||
376 | if (!str) | |
377 | return -EINVAL; | |
378 | ||
379 | if (!strcmp(str, "off")) { | |
380 | taa_mitigation = TAA_MITIGATION_OFF; | |
381 | } else if (!strcmp(str, "full")) { | |
382 | taa_mitigation = TAA_MITIGATION_VERW; | |
383 | } else if (!strcmp(str, "full,nosmt")) { | |
384 | taa_mitigation = TAA_MITIGATION_VERW; | |
385 | taa_nosmt = true; | |
386 | } | |
387 | ||
388 | return 0; | |
389 | } | |
390 | early_param("tsx_async_abort", tsx_async_abort_parse_cmdline); | |
391 | ||
2418c6b1 PG |
392 | #undef pr_fmt |
393 | #define pr_fmt(fmt) "MMIO Stale Data: " fmt | |
394 | ||
395 | enum mmio_mitigations { | |
396 | MMIO_MITIGATION_OFF, | |
397 | MMIO_MITIGATION_UCODE_NEEDED, | |
398 | MMIO_MITIGATION_VERW, | |
399 | }; | |
400 | ||
401 | /* Default mitigation for Processor MMIO Stale Data vulnerabilities */ | |
402 | static enum mmio_mitigations mmio_mitigation __ro_after_init = MMIO_MITIGATION_VERW; | |
403 | static bool mmio_nosmt __ro_after_init = false; | |
404 | ||
405 | static const char * const mmio_strings[] = { | |
406 | [MMIO_MITIGATION_OFF] = "Vulnerable", | |
407 | [MMIO_MITIGATION_UCODE_NEEDED] = "Vulnerable: Clear CPU buffers attempted, no microcode", | |
408 | [MMIO_MITIGATION_VERW] = "Mitigation: Clear CPU buffers", | |
409 | }; | |
410 | ||
411 | static void __init mmio_select_mitigation(void) | |
412 | { | |
413 | u64 ia32_cap; | |
414 | ||
415 | if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA) || | |
416 | cpu_mitigations_off()) { | |
417 | mmio_mitigation = MMIO_MITIGATION_OFF; | |
418 | return; | |
419 | } | |
420 | ||
421 | if (mmio_mitigation == MMIO_MITIGATION_OFF) | |
422 | return; | |
423 | ||
424 | ia32_cap = x86_read_arch_cap_msr(); | |
425 | ||
426 | /* | |
427 | * Enable CPU buffer clear mitigation for host and VMM, if also affected | |
428 | * by MDS or TAA. Otherwise, enable mitigation for VMM only. | |
429 | */ | |
430 | if (boot_cpu_has_bug(X86_BUG_MDS) || (boot_cpu_has_bug(X86_BUG_TAA) && | |
431 | boot_cpu_has(X86_FEATURE_RTM))) | |
432 | static_branch_enable(&mds_user_clear); | |
433 | else | |
434 | static_branch_enable(&mmio_stale_data_clear); | |
435 | ||
92a2794a PG |
436 | /* |
437 | * If Processor-MMIO-Stale-Data bug is present and Fill Buffer data can | |
438 | * be propagated to uncore buffers, clearing the Fill buffers on idle | |
439 | * is required irrespective of SMT state. | |
440 | */ | |
441 | if (!(ia32_cap & ARCH_CAP_FBSDP_NO)) | |
442 | static_branch_enable(&mds_idle_clear); | |
443 | ||
2418c6b1 PG |
444 | /* |
445 | * Check if the system has the right microcode. | |
446 | * | |
447 | * CPU Fill buffer clear mitigation is enumerated by either an explicit | |
448 | * FB_CLEAR or by the presence of both MD_CLEAR and L1D_FLUSH on MDS | |
449 | * affected systems. | |
450 | */ | |
451 | if ((ia32_cap & ARCH_CAP_FB_CLEAR) || | |
452 | (boot_cpu_has(X86_FEATURE_MD_CLEAR) && | |
453 | boot_cpu_has(X86_FEATURE_FLUSH_L1D) && | |
454 | !(ia32_cap & ARCH_CAP_MDS_NO))) | |
455 | mmio_mitigation = MMIO_MITIGATION_VERW; | |
456 | else | |
457 | mmio_mitigation = MMIO_MITIGATION_UCODE_NEEDED; | |
458 | ||
459 | if (mmio_nosmt || cpu_mitigations_auto_nosmt()) | |
460 | cpu_smt_disable(false); | |
461 | } | |
462 | ||
463 | static int __init mmio_stale_data_parse_cmdline(char *str) | |
464 | { | |
465 | if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) | |
466 | return 0; | |
467 | ||
468 | if (!str) | |
469 | return -EINVAL; | |
470 | ||
471 | if (!strcmp(str, "off")) { | |
472 | mmio_mitigation = MMIO_MITIGATION_OFF; | |
473 | } else if (!strcmp(str, "full")) { | |
474 | mmio_mitigation = MMIO_MITIGATION_VERW; | |
475 | } else if (!strcmp(str, "full,nosmt")) { | |
476 | mmio_mitigation = MMIO_MITIGATION_VERW; | |
477 | mmio_nosmt = true; | |
478 | } | |
479 | ||
480 | return 0; | |
481 | } | |
482 | early_param("mmio_stale_data", mmio_stale_data_parse_cmdline); | |
483 | ||
6a9231bf PG |
484 | #undef pr_fmt |
485 | #define pr_fmt(fmt) "" fmt | |
486 | ||
487 | static void __init md_clear_update_mitigation(void) | |
488 | { | |
489 | if (cpu_mitigations_off()) | |
490 | return; | |
491 | ||
492 | if (!static_key_enabled(&mds_user_clear)) | |
493 | goto out; | |
494 | ||
495 | /* | |
2418c6b1 PG |
496 | * mds_user_clear is now enabled. Update MDS, TAA and MMIO Stale Data |
497 | * mitigation, if necessary. | |
6a9231bf PG |
498 | */ |
499 | if (mds_mitigation == MDS_MITIGATION_OFF && | |
500 | boot_cpu_has_bug(X86_BUG_MDS)) { | |
501 | mds_mitigation = MDS_MITIGATION_FULL; | |
502 | mds_select_mitigation(); | |
503 | } | |
2418c6b1 PG |
504 | if (taa_mitigation == TAA_MITIGATION_OFF && |
505 | boot_cpu_has_bug(X86_BUG_TAA)) { | |
506 | taa_mitigation = TAA_MITIGATION_VERW; | |
507 | taa_select_mitigation(); | |
508 | } | |
509 | if (mmio_mitigation == MMIO_MITIGATION_OFF && | |
510 | boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) { | |
511 | mmio_mitigation = MMIO_MITIGATION_VERW; | |
512 | mmio_select_mitigation(); | |
513 | } | |
6a9231bf PG |
514 | out: |
515 | if (boot_cpu_has_bug(X86_BUG_MDS)) | |
516 | pr_info("MDS: %s\n", mds_strings[mds_mitigation]); | |
517 | if (boot_cpu_has_bug(X86_BUG_TAA)) | |
518 | pr_info("TAA: %s\n", taa_strings[taa_mitigation]); | |
2418c6b1 PG |
519 | if (boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) |
520 | pr_info("MMIO Stale Data: %s\n", mmio_strings[mmio_mitigation]); | |
6a9231bf PG |
521 | } |
522 | ||
b9bc1fb8 PG |
523 | static void __init md_clear_select_mitigation(void) |
524 | { | |
525 | mds_select_mitigation(); | |
526 | taa_select_mitigation(); | |
527 | mmio_select_mitigation(); | |
528 | ||
529 | /* | |
530 | * As MDS, TAA and MMIO Stale Data mitigations are inter-related, update | |
531 | * and print their mitigation after MDS, TAA and MMIO Stale Data | |
532 | * mitigation selection is done. | |
533 | */ | |
534 | md_clear_update_mitigation(); | |
535 | } | |
536 | ||
7e5b3c26 MG |
537 | #undef pr_fmt |
538 | #define pr_fmt(fmt) "SRBDS: " fmt | |
539 | ||
540 | enum srbds_mitigations { | |
541 | SRBDS_MITIGATION_OFF, | |
542 | SRBDS_MITIGATION_UCODE_NEEDED, | |
543 | SRBDS_MITIGATION_FULL, | |
544 | SRBDS_MITIGATION_TSX_OFF, | |
545 | SRBDS_MITIGATION_HYPERVISOR, | |
546 | }; | |
547 | ||
548 | static enum srbds_mitigations srbds_mitigation __ro_after_init = SRBDS_MITIGATION_FULL; | |
549 | ||
550 | static const char * const srbds_strings[] = { | |
551 | [SRBDS_MITIGATION_OFF] = "Vulnerable", | |
552 | [SRBDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode", | |
553 | [SRBDS_MITIGATION_FULL] = "Mitigation: Microcode", | |
554 | [SRBDS_MITIGATION_TSX_OFF] = "Mitigation: TSX disabled", | |
555 | [SRBDS_MITIGATION_HYPERVISOR] = "Unknown: Dependent on hypervisor status", | |
556 | }; | |
557 | ||
558 | static bool srbds_off; | |
559 | ||
560 | void update_srbds_msr(void) | |
561 | { | |
562 | u64 mcu_ctrl; | |
563 | ||
564 | if (!boot_cpu_has_bug(X86_BUG_SRBDS)) | |
565 | return; | |
566 | ||
567 | if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) | |
568 | return; | |
569 | ||
570 | if (srbds_mitigation == SRBDS_MITIGATION_UCODE_NEEDED) | |
571 | return; | |
572 | ||
573 | rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); | |
574 | ||
575 | switch (srbds_mitigation) { | |
576 | case SRBDS_MITIGATION_OFF: | |
577 | case SRBDS_MITIGATION_TSX_OFF: | |
578 | mcu_ctrl |= RNGDS_MITG_DIS; | |
579 | break; | |
580 | case SRBDS_MITIGATION_FULL: | |
581 | mcu_ctrl &= ~RNGDS_MITG_DIS; | |
582 | break; | |
583 | default: | |
584 | break; | |
585 | } | |
586 | ||
587 | wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); | |
588 | } | |
589 | ||
590 | static void __init srbds_select_mitigation(void) | |
591 | { | |
592 | u64 ia32_cap; | |
593 | ||
594 | if (!boot_cpu_has_bug(X86_BUG_SRBDS)) | |
595 | return; | |
596 | ||
597 | /* | |
ee855cd4 PG |
598 | * Check to see if this is one of the MDS_NO systems supporting TSX that |
599 | * are only exposed to SRBDS when TSX is enabled or when CPU is affected | |
600 | * by Processor MMIO Stale Data vulnerability. | |
7e5b3c26 MG |
601 | */ |
602 | ia32_cap = x86_read_arch_cap_msr(); | |
ee855cd4 PG |
603 | if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM) && |
604 | !boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) | |
7e5b3c26 MG |
605 | srbds_mitigation = SRBDS_MITIGATION_TSX_OFF; |
606 | else if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) | |
607 | srbds_mitigation = SRBDS_MITIGATION_HYPERVISOR; | |
608 | else if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL)) | |
609 | srbds_mitigation = SRBDS_MITIGATION_UCODE_NEEDED; | |
610 | else if (cpu_mitigations_off() || srbds_off) | |
611 | srbds_mitigation = SRBDS_MITIGATION_OFF; | |
612 | ||
613 | update_srbds_msr(); | |
614 | pr_info("%s\n", srbds_strings[srbds_mitigation]); | |
615 | } | |
616 | ||
617 | static int __init srbds_parse_cmdline(char *str) | |
618 | { | |
619 | if (!str) | |
620 | return -EINVAL; | |
621 | ||
622 | if (!boot_cpu_has_bug(X86_BUG_SRBDS)) | |
623 | return 0; | |
624 | ||
625 | srbds_off = !strcmp(str, "off"); | |
626 | return 0; | |
627 | } | |
628 | early_param("srbds", srbds_parse_cmdline); | |
629 | ||
b5f06f64 BS |
630 | #undef pr_fmt |
631 | #define pr_fmt(fmt) "L1D Flush : " fmt | |
632 | ||
633 | enum l1d_flush_mitigations { | |
634 | L1D_FLUSH_OFF = 0, | |
635 | L1D_FLUSH_ON, | |
636 | }; | |
637 | ||
638 | static enum l1d_flush_mitigations l1d_flush_mitigation __initdata = L1D_FLUSH_OFF; | |
639 | ||
640 | static void __init l1d_flush_select_mitigation(void) | |
641 | { | |
642 | if (!l1d_flush_mitigation || !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) | |
643 | return; | |
644 | ||
645 | static_branch_enable(&switch_mm_cond_l1d_flush); | |
646 | pr_info("Conditional flush on switch_mm() enabled\n"); | |
647 | } | |
648 | ||
649 | static int __init l1d_flush_parse_cmdline(char *str) | |
650 | { | |
651 | if (!strcmp(str, "on")) | |
652 | l1d_flush_mitigation = L1D_FLUSH_ON; | |
653 | ||
654 | return 0; | |
655 | } | |
656 | early_param("l1d_flush", l1d_flush_parse_cmdline); | |
657 | ||
a2059825 JP |
658 | #undef pr_fmt |
659 | #define pr_fmt(fmt) "Spectre V1 : " fmt | |
660 | ||
661 | enum spectre_v1_mitigation { | |
662 | SPECTRE_V1_MITIGATION_NONE, | |
663 | SPECTRE_V1_MITIGATION_AUTO, | |
664 | }; | |
665 | ||
666 | static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init = | |
667 | SPECTRE_V1_MITIGATION_AUTO; | |
668 | ||
669 | static const char * const spectre_v1_strings[] = { | |
670 | [SPECTRE_V1_MITIGATION_NONE] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers", | |
671 | [SPECTRE_V1_MITIGATION_AUTO] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization", | |
672 | }; | |
673 | ||
a2059825 JP |
674 | /* |
675 | * Does SMAP provide full mitigation against speculative kernel access to | |
676 | * userspace? | |
677 | */ | |
678 | static bool smap_works_speculatively(void) | |
679 | { | |
680 | if (!boot_cpu_has(X86_FEATURE_SMAP)) | |
681 | return false; | |
682 | ||
683 | /* | |
684 | * On CPUs which are vulnerable to Meltdown, SMAP does not | |
685 | * prevent speculative access to user data in the L1 cache. | |
686 | * Consider SMAP to be non-functional as a mitigation on these | |
687 | * CPUs. | |
688 | */ | |
689 | if (boot_cpu_has(X86_BUG_CPU_MELTDOWN)) | |
690 | return false; | |
691 | ||
692 | return true; | |
693 | } | |
694 | ||
695 | static void __init spectre_v1_select_mitigation(void) | |
696 | { | |
697 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) { | |
698 | spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE; | |
699 | return; | |
700 | } | |
701 | ||
702 | if (spectre_v1_mitigation == SPECTRE_V1_MITIGATION_AUTO) { | |
703 | /* | |
704 | * With Spectre v1, a user can speculatively control either | |
705 | * path of a conditional swapgs with a user-controlled GS | |
706 | * value. The mitigation is to add lfences to both code paths. | |
707 | * | |
708 | * If FSGSBASE is enabled, the user can put a kernel address in | |
709 | * GS, in which case SMAP provides no protection. | |
710 | * | |
a2059825 JP |
711 | * If FSGSBASE is disabled, the user can only put a user space |
712 | * address in GS. That makes an attack harder, but still | |
713 | * possible if there's no SMAP protection. | |
714 | */ | |
978e1342 TL |
715 | if (boot_cpu_has(X86_FEATURE_FSGSBASE) || |
716 | !smap_works_speculatively()) { | |
a2059825 JP |
717 | /* |
718 | * Mitigation can be provided from SWAPGS itself or | |
719 | * PTI as the CR3 write in the Meltdown mitigation | |
720 | * is serializing. | |
721 | * | |
f36cf386 TG |
722 | * If neither is there, mitigate with an LFENCE to |
723 | * stop speculation through swapgs. | |
a2059825 | 724 | */ |
f36cf386 TG |
725 | if (boot_cpu_has_bug(X86_BUG_SWAPGS) && |
726 | !boot_cpu_has(X86_FEATURE_PTI)) | |
a2059825 JP |
727 | setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER); |
728 | ||
729 | /* | |
730 | * Enable lfences in the kernel entry (non-swapgs) | |
731 | * paths, to prevent user entry from speculatively | |
732 | * skipping swapgs. | |
733 | */ | |
734 | setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL); | |
735 | } | |
736 | } | |
737 | ||
738 | pr_info("%s\n", spectre_v1_strings[spectre_v1_mitigation]); | |
739 | } | |
740 | ||
741 | static int __init nospectre_v1_cmdline(char *str) | |
742 | { | |
743 | spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE; | |
744 | return 0; | |
745 | } | |
746 | early_param("nospectre_v1", nospectre_v1_cmdline); | |
747 | ||
15d6b7aa TG |
748 | #undef pr_fmt |
749 | #define pr_fmt(fmt) "Spectre V2 : " fmt | |
750 | ||
751 | static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = | |
752 | SPECTRE_V2_NONE; | |
753 | ||
21998a35 AS |
754 | static enum spectre_v2_user_mitigation spectre_v2_user_stibp __ro_after_init = |
755 | SPECTRE_V2_USER_NONE; | |
756 | static enum spectre_v2_user_mitigation spectre_v2_user_ibpb __ro_after_init = | |
fa1202ef TG |
757 | SPECTRE_V2_USER_NONE; |
758 | ||
e4f35891 | 759 | #ifdef CONFIG_RETPOLINE |
e383095c TG |
760 | static bool spectre_v2_bad_module; |
761 | ||
caf7501a AK |
762 | bool retpoline_module_ok(bool has_retpoline) |
763 | { | |
764 | if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) | |
765 | return true; | |
766 | ||
e698dcdf | 767 | pr_err("System may be vulnerable to spectre v2\n"); |
caf7501a AK |
768 | spectre_v2_bad_module = true; |
769 | return false; | |
770 | } | |
e383095c TG |
771 | |
772 | static inline const char *spectre_v2_module_string(void) | |
773 | { | |
774 | return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; | |
775 | } | |
776 | #else | |
777 | static inline const char *spectre_v2_module_string(void) { return ""; } | |
caf7501a | 778 | #endif |
da285121 | 779 | |
92cf97b2 | 780 | #define SPECTRE_V2_LFENCE_MSG "WARNING: LFENCE mitigation is not recommended for this CPU, data leaks possible!\n" |
534fcc9a | 781 | #define SPECTRE_V2_EIBRS_EBPF_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS on, data leaks possible via Spectre v2 BHB attacks!\n" |
810643a7 | 782 | #define SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS+LFENCE mitigation and SMT, data leaks possible via Spectre v2 BHB attacks!\n" |
534fcc9a JP |
783 | |
784 | #ifdef CONFIG_BPF_SYSCALL | |
785 | void unpriv_ebpf_notify(int new_state) | |
786 | { | |
810643a7 JP |
787 | if (new_state) |
788 | return; | |
789 | ||
790 | /* Unprivileged eBPF is enabled */ | |
791 | ||
792 | switch (spectre_v2_enabled) { | |
793 | case SPECTRE_V2_EIBRS: | |
534fcc9a | 794 | pr_err(SPECTRE_V2_EIBRS_EBPF_MSG); |
810643a7 JP |
795 | break; |
796 | case SPECTRE_V2_EIBRS_LFENCE: | |
797 | if (sched_smt_active()) | |
798 | pr_err(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG); | |
799 | break; | |
800 | default: | |
801 | break; | |
802 | } | |
534fcc9a JP |
803 | } |
804 | #endif | |
805 | ||
da285121 DW |
806 | static inline bool match_option(const char *arg, int arglen, const char *opt) |
807 | { | |
808 | int len = strlen(opt); | |
809 | ||
810 | return len == arglen && !strncmp(arg, opt, len); | |
811 | } | |
812 | ||
15d6b7aa TG |
813 | /* The kernel command line selection for spectre v2 */ |
814 | enum spectre_v2_mitigation_cmd { | |
815 | SPECTRE_V2_CMD_NONE, | |
816 | SPECTRE_V2_CMD_AUTO, | |
817 | SPECTRE_V2_CMD_FORCE, | |
818 | SPECTRE_V2_CMD_RETPOLINE, | |
819 | SPECTRE_V2_CMD_RETPOLINE_GENERIC, | |
a24bd1da | 820 | SPECTRE_V2_CMD_RETPOLINE_LFENCE, |
a94faf3f PZ |
821 | SPECTRE_V2_CMD_EIBRS, |
822 | SPECTRE_V2_CMD_EIBRS_RETPOLINE, | |
823 | SPECTRE_V2_CMD_EIBRS_LFENCE, | |
15d6b7aa TG |
824 | }; |
825 | ||
fa1202ef TG |
826 | enum spectre_v2_user_cmd { |
827 | SPECTRE_V2_USER_CMD_NONE, | |
828 | SPECTRE_V2_USER_CMD_AUTO, | |
829 | SPECTRE_V2_USER_CMD_FORCE, | |
7cc765a6 | 830 | SPECTRE_V2_USER_CMD_PRCTL, |
55a97402 | 831 | SPECTRE_V2_USER_CMD_PRCTL_IBPB, |
6b3e64c2 | 832 | SPECTRE_V2_USER_CMD_SECCOMP, |
55a97402 | 833 | SPECTRE_V2_USER_CMD_SECCOMP_IBPB, |
fa1202ef TG |
834 | }; |
835 | ||
836 | static const char * const spectre_v2_user_strings[] = { | |
20c3a2c3 TL |
837 | [SPECTRE_V2_USER_NONE] = "User space: Vulnerable", |
838 | [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection", | |
839 | [SPECTRE_V2_USER_STRICT_PREFERRED] = "User space: Mitigation: STIBP always-on protection", | |
840 | [SPECTRE_V2_USER_PRCTL] = "User space: Mitigation: STIBP via prctl", | |
841 | [SPECTRE_V2_USER_SECCOMP] = "User space: Mitigation: STIBP via seccomp and prctl", | |
fa1202ef TG |
842 | }; |
843 | ||
844 | static const struct { | |
845 | const char *option; | |
846 | enum spectre_v2_user_cmd cmd; | |
847 | bool secure; | |
1de7edbb | 848 | } v2_user_options[] __initconst = { |
55a97402 TG |
849 | { "auto", SPECTRE_V2_USER_CMD_AUTO, false }, |
850 | { "off", SPECTRE_V2_USER_CMD_NONE, false }, | |
851 | { "on", SPECTRE_V2_USER_CMD_FORCE, true }, | |
852 | { "prctl", SPECTRE_V2_USER_CMD_PRCTL, false }, | |
853 | { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB, false }, | |
854 | { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP, false }, | |
855 | { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB, false }, | |
fa1202ef TG |
856 | }; |
857 | ||
858 | static void __init spec_v2_user_print_cond(const char *reason, bool secure) | |
859 | { | |
860 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) | |
861 | pr_info("spectre_v2_user=%s forced on command line.\n", reason); | |
862 | } | |
863 | ||
864 | static enum spectre_v2_user_cmd __init | |
865 | spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd) | |
866 | { | |
867 | char arg[20]; | |
868 | int ret, i; | |
869 | ||
870 | switch (v2_cmd) { | |
871 | case SPECTRE_V2_CMD_NONE: | |
872 | return SPECTRE_V2_USER_CMD_NONE; | |
873 | case SPECTRE_V2_CMD_FORCE: | |
874 | return SPECTRE_V2_USER_CMD_FORCE; | |
875 | default: | |
876 | break; | |
877 | } | |
878 | ||
879 | ret = cmdline_find_option(boot_command_line, "spectre_v2_user", | |
880 | arg, sizeof(arg)); | |
881 | if (ret < 0) | |
882 | return SPECTRE_V2_USER_CMD_AUTO; | |
883 | ||
884 | for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) { | |
885 | if (match_option(arg, ret, v2_user_options[i].option)) { | |
886 | spec_v2_user_print_cond(v2_user_options[i].option, | |
887 | v2_user_options[i].secure); | |
888 | return v2_user_options[i].cmd; | |
889 | } | |
890 | } | |
891 | ||
892 | pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg); | |
893 | return SPECTRE_V2_USER_CMD_AUTO; | |
894 | } | |
895 | ||
a94faf3f PZ |
896 | static inline bool spectre_v2_in_eibrs_mode(enum spectre_v2_mitigation mode) |
897 | { | |
898 | return (mode == SPECTRE_V2_EIBRS || | |
899 | mode == SPECTRE_V2_EIBRS_RETPOLINE || | |
900 | mode == SPECTRE_V2_EIBRS_LFENCE); | |
901 | } | |
902 | ||
fa1202ef TG |
903 | static void __init |
904 | spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd) | |
905 | { | |
906 | enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE; | |
907 | bool smt_possible = IS_ENABLED(CONFIG_SMP); | |
55a97402 | 908 | enum spectre_v2_user_cmd cmd; |
fa1202ef TG |
909 | |
910 | if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP)) | |
911 | return; | |
912 | ||
913 | if (cpu_smt_control == CPU_SMT_FORCE_DISABLED || | |
914 | cpu_smt_control == CPU_SMT_NOT_SUPPORTED) | |
915 | smt_possible = false; | |
916 | ||
55a97402 TG |
917 | cmd = spectre_v2_parse_user_cmdline(v2_cmd); |
918 | switch (cmd) { | |
fa1202ef TG |
919 | case SPECTRE_V2_USER_CMD_NONE: |
920 | goto set_mode; | |
921 | case SPECTRE_V2_USER_CMD_FORCE: | |
922 | mode = SPECTRE_V2_USER_STRICT; | |
923 | break; | |
7cc765a6 | 924 | case SPECTRE_V2_USER_CMD_PRCTL: |
55a97402 | 925 | case SPECTRE_V2_USER_CMD_PRCTL_IBPB: |
7cc765a6 TG |
926 | mode = SPECTRE_V2_USER_PRCTL; |
927 | break; | |
6b3e64c2 TG |
928 | case SPECTRE_V2_USER_CMD_AUTO: |
929 | case SPECTRE_V2_USER_CMD_SECCOMP: | |
55a97402 | 930 | case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: |
6b3e64c2 TG |
931 | if (IS_ENABLED(CONFIG_SECCOMP)) |
932 | mode = SPECTRE_V2_USER_SECCOMP; | |
933 | else | |
934 | mode = SPECTRE_V2_USER_PRCTL; | |
935 | break; | |
fa1202ef TG |
936 | } |
937 | ||
938 | /* Initialize Indirect Branch Prediction Barrier */ | |
939 | if (boot_cpu_has(X86_FEATURE_IBPB)) { | |
940 | setup_force_cpu_cap(X86_FEATURE_USE_IBPB); | |
4c71a2b6 | 941 | |
33fc379d | 942 | spectre_v2_user_ibpb = mode; |
55a97402 TG |
943 | switch (cmd) { |
944 | case SPECTRE_V2_USER_CMD_FORCE: | |
945 | case SPECTRE_V2_USER_CMD_PRCTL_IBPB: | |
946 | case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: | |
4c71a2b6 | 947 | static_branch_enable(&switch_mm_always_ibpb); |
33fc379d | 948 | spectre_v2_user_ibpb = SPECTRE_V2_USER_STRICT; |
4c71a2b6 | 949 | break; |
55a97402 TG |
950 | case SPECTRE_V2_USER_CMD_PRCTL: |
951 | case SPECTRE_V2_USER_CMD_AUTO: | |
952 | case SPECTRE_V2_USER_CMD_SECCOMP: | |
7cc765a6 TG |
953 | static_branch_enable(&switch_mm_cond_ibpb); |
954 | break; | |
4c71a2b6 TG |
955 | default: |
956 | break; | |
957 | } | |
958 | ||
959 | pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n", | |
55a97402 TG |
960 | static_key_enabled(&switch_mm_always_ibpb) ? |
961 | "always-on" : "conditional"); | |
fa1202ef TG |
962 | } |
963 | ||
21998a35 | 964 | /* |
a5ce9f2b | 965 | * If no STIBP, enhanced IBRS is enabled or SMT impossible, STIBP is not |
21998a35 AS |
966 | * required. |
967 | */ | |
a5ce9f2b BP |
968 | if (!boot_cpu_has(X86_FEATURE_STIBP) || |
969 | !smt_possible || | |
a94faf3f | 970 | spectre_v2_in_eibrs_mode(spectre_v2_enabled)) |
fa1202ef TG |
971 | return; |
972 | ||
7cc765a6 | 973 | /* |
21998a35 AS |
974 | * At this point, an STIBP mode other than "off" has been set. |
975 | * If STIBP support is not being forced, check if STIBP always-on | |
976 | * is preferred. | |
7cc765a6 | 977 | */ |
21998a35 AS |
978 | if (mode != SPECTRE_V2_USER_STRICT && |
979 | boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON)) | |
980 | mode = SPECTRE_V2_USER_STRICT_PREFERRED; | |
981 | ||
21998a35 AS |
982 | spectre_v2_user_stibp = mode; |
983 | ||
fa1202ef | 984 | set_mode: |
21998a35 | 985 | pr_info("%s\n", spectre_v2_user_strings[mode]); |
fa1202ef TG |
986 | } |
987 | ||
8770709f | 988 | static const char * const spectre_v2_strings[] = { |
15d6b7aa | 989 | [SPECTRE_V2_NONE] = "Vulnerable", |
a24bd1da PZI |
990 | [SPECTRE_V2_RETPOLINE] = "Mitigation: Retpolines", |
991 | [SPECTRE_V2_LFENCE] = "Mitigation: LFENCE", | |
a94faf3f PZ |
992 | [SPECTRE_V2_EIBRS] = "Mitigation: Enhanced IBRS", |
993 | [SPECTRE_V2_EIBRS_LFENCE] = "Mitigation: Enhanced IBRS + LFENCE", | |
994 | [SPECTRE_V2_EIBRS_RETPOLINE] = "Mitigation: Enhanced IBRS + Retpolines", | |
15d6b7aa TG |
995 | }; |
996 | ||
9005c683 KA |
997 | static const struct { |
998 | const char *option; | |
999 | enum spectre_v2_mitigation_cmd cmd; | |
1000 | bool secure; | |
1de7edbb | 1001 | } mitigation_options[] __initconst = { |
15d6b7aa TG |
1002 | { "off", SPECTRE_V2_CMD_NONE, false }, |
1003 | { "on", SPECTRE_V2_CMD_FORCE, true }, | |
1004 | { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, | |
a24bd1da PZI |
1005 | { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_LFENCE, false }, |
1006 | { "retpoline,lfence", SPECTRE_V2_CMD_RETPOLINE_LFENCE, false }, | |
15d6b7aa | 1007 | { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, |
a94faf3f PZ |
1008 | { "eibrs", SPECTRE_V2_CMD_EIBRS, false }, |
1009 | { "eibrs,lfence", SPECTRE_V2_CMD_EIBRS_LFENCE, false }, | |
1010 | { "eibrs,retpoline", SPECTRE_V2_CMD_EIBRS_RETPOLINE, false }, | |
15d6b7aa | 1011 | { "auto", SPECTRE_V2_CMD_AUTO, false }, |
9005c683 KA |
1012 | }; |
1013 | ||
495d470e | 1014 | static void __init spec_v2_print_cond(const char *reason, bool secure) |
15d6b7aa | 1015 | { |
495d470e | 1016 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) |
15d6b7aa TG |
1017 | pr_info("%s selected on command line.\n", reason); |
1018 | } | |
1019 | ||
da285121 DW |
1020 | static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) |
1021 | { | |
15d6b7aa | 1022 | enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; |
da285121 | 1023 | char arg[20]; |
9005c683 | 1024 | int ret, i; |
9005c683 | 1025 | |
d68be4c4 JP |
1026 | if (cmdline_find_option_bool(boot_command_line, "nospectre_v2") || |
1027 | cpu_mitigations_off()) | |
9005c683 | 1028 | return SPECTRE_V2_CMD_NONE; |
9005c683 | 1029 | |
24848509 TC |
1030 | ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); |
1031 | if (ret < 0) | |
1032 | return SPECTRE_V2_CMD_AUTO; | |
1033 | ||
1034 | for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { | |
1035 | if (!match_option(arg, ret, mitigation_options[i].option)) | |
1036 | continue; | |
1037 | cmd = mitigation_options[i].cmd; | |
1038 | break; | |
1039 | } | |
1040 | ||
1041 | if (i >= ARRAY_SIZE(mitigation_options)) { | |
1042 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
1043 | return SPECTRE_V2_CMD_AUTO; | |
da285121 DW |
1044 | } |
1045 | ||
9005c683 | 1046 | if ((cmd == SPECTRE_V2_CMD_RETPOLINE || |
a24bd1da | 1047 | cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE || |
a94faf3f PZ |
1048 | cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC || |
1049 | cmd == SPECTRE_V2_CMD_EIBRS_LFENCE || | |
1050 | cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) && | |
9005c683 | 1051 | !IS_ENABLED(CONFIG_RETPOLINE)) { |
a94faf3f PZ |
1052 | pr_err("%s selected but not compiled in. Switching to AUTO select\n", |
1053 | mitigation_options[i].option); | |
1054 | return SPECTRE_V2_CMD_AUTO; | |
1055 | } | |
1056 | ||
1057 | if ((cmd == SPECTRE_V2_CMD_EIBRS || | |
1058 | cmd == SPECTRE_V2_CMD_EIBRS_LFENCE || | |
1059 | cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) && | |
1060 | !boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { | |
1061 | pr_err("%s selected but CPU doesn't have eIBRS. Switching to AUTO select\n", | |
1062 | mitigation_options[i].option); | |
da285121 | 1063 | return SPECTRE_V2_CMD_AUTO; |
9005c683 KA |
1064 | } |
1065 | ||
a94faf3f PZ |
1066 | if ((cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE || |
1067 | cmd == SPECTRE_V2_CMD_EIBRS_LFENCE) && | |
a24bd1da | 1068 | !boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { |
a94faf3f PZ |
1069 | pr_err("%s selected, but CPU doesn't have a serializing LFENCE. Switching to AUTO select\n", |
1070 | mitigation_options[i].option); | |
a24bd1da PZI |
1071 | return SPECTRE_V2_CMD_AUTO; |
1072 | } | |
1073 | ||
495d470e TG |
1074 | spec_v2_print_cond(mitigation_options[i].option, |
1075 | mitigation_options[i].secure); | |
9005c683 | 1076 | return cmd; |
da285121 DW |
1077 | } |
1078 | ||
a94faf3f PZ |
1079 | static enum spectre_v2_mitigation __init spectre_v2_select_retpoline(void) |
1080 | { | |
1081 | if (!IS_ENABLED(CONFIG_RETPOLINE)) { | |
1082 | pr_err("Kernel not compiled with retpoline; no mitigation available!"); | |
1083 | return SPECTRE_V2_NONE; | |
1084 | } | |
1085 | ||
a94faf3f PZ |
1086 | return SPECTRE_V2_RETPOLINE; |
1087 | } | |
1088 | ||
da285121 DW |
1089 | static void __init spectre_v2_select_mitigation(void) |
1090 | { | |
1091 | enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); | |
1092 | enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; | |
1093 | ||
1094 | /* | |
1095 | * If the CPU is not affected and the command line mode is NONE or AUTO | |
1096 | * then nothing to do. | |
1097 | */ | |
1098 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && | |
1099 | (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) | |
1100 | return; | |
1101 | ||
1102 | switch (cmd) { | |
1103 | case SPECTRE_V2_CMD_NONE: | |
1104 | return; | |
1105 | ||
1106 | case SPECTRE_V2_CMD_FORCE: | |
da285121 | 1107 | case SPECTRE_V2_CMD_AUTO: |
706d5168 | 1108 | if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { |
a94faf3f PZ |
1109 | mode = SPECTRE_V2_EIBRS; |
1110 | break; | |
706d5168 | 1111 | } |
a94faf3f PZ |
1112 | |
1113 | mode = spectre_v2_select_retpoline(); | |
9471eee9 | 1114 | break; |
a94faf3f | 1115 | |
a24bd1da | 1116 | case SPECTRE_V2_CMD_RETPOLINE_LFENCE: |
92cf97b2 | 1117 | pr_err(SPECTRE_V2_LFENCE_MSG); |
a94faf3f | 1118 | mode = SPECTRE_V2_LFENCE; |
da285121 | 1119 | break; |
a94faf3f | 1120 | |
da285121 | 1121 | case SPECTRE_V2_CMD_RETPOLINE_GENERIC: |
a94faf3f | 1122 | mode = SPECTRE_V2_RETPOLINE; |
da285121 | 1123 | break; |
a94faf3f | 1124 | |
da285121 | 1125 | case SPECTRE_V2_CMD_RETPOLINE: |
a94faf3f PZ |
1126 | mode = spectre_v2_select_retpoline(); |
1127 | break; | |
1128 | ||
1129 | case SPECTRE_V2_CMD_EIBRS: | |
1130 | mode = SPECTRE_V2_EIBRS; | |
1131 | break; | |
1132 | ||
1133 | case SPECTRE_V2_CMD_EIBRS_LFENCE: | |
1134 | mode = SPECTRE_V2_EIBRS_LFENCE; | |
1135 | break; | |
1136 | ||
1137 | case SPECTRE_V2_CMD_EIBRS_RETPOLINE: | |
1138 | mode = SPECTRE_V2_EIBRS_RETPOLINE; | |
da285121 DW |
1139 | break; |
1140 | } | |
da285121 | 1141 | |
534fcc9a JP |
1142 | if (mode == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled()) |
1143 | pr_err(SPECTRE_V2_EIBRS_EBPF_MSG); | |
1144 | ||
a94faf3f PZ |
1145 | if (spectre_v2_in_eibrs_mode(mode)) { |
1146 | /* Force it so VMEXIT will restore correctly */ | |
1147 | x86_spec_ctrl_base |= SPEC_CTRL_IBRS; | |
1148 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); | |
1149 | } | |
1150 | ||
1151 | switch (mode) { | |
1152 | case SPECTRE_V2_NONE: | |
1153 | case SPECTRE_V2_EIBRS: | |
1154 | break; | |
1155 | ||
1156 | case SPECTRE_V2_LFENCE: | |
1157 | case SPECTRE_V2_EIBRS_LFENCE: | |
a24bd1da | 1158 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE_LFENCE); |
a94faf3f PZ |
1159 | fallthrough; |
1160 | ||
1161 | case SPECTRE_V2_RETPOLINE: | |
1162 | case SPECTRE_V2_EIBRS_RETPOLINE: | |
da285121 | 1163 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); |
a94faf3f | 1164 | break; |
da285121 DW |
1165 | } |
1166 | ||
1167 | spectre_v2_enabled = mode; | |
1168 | pr_info("%s\n", spectre_v2_strings[mode]); | |
c995efd5 DW |
1169 | |
1170 | /* | |
fdf82a78 JK |
1171 | * If spectre v2 protection has been enabled, unconditionally fill |
1172 | * RSB during a context switch; this protects against two independent | |
1173 | * issues: | |
c995efd5 | 1174 | * |
fdf82a78 JK |
1175 | * - RSB underflow (and switch to BTB) on Skylake+ |
1176 | * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs | |
c995efd5 | 1177 | */ |
fdf82a78 JK |
1178 | setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); |
1179 | pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n"); | |
20ffa1ca | 1180 | |
dd84441a DW |
1181 | /* |
1182 | * Retpoline means the kernel is safe because it has no indirect | |
706d5168 SP |
1183 | * branches. Enhanced IBRS protects firmware too, so, enable restricted |
1184 | * speculation around firmware calls only when Enhanced IBRS isn't | |
1185 | * supported. | |
1186 | * | |
1187 | * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because | |
1188 | * the user might select retpoline on the kernel command line and if | |
1189 | * the CPU supports Enhanced IBRS, kernel might un-intentionally not | |
1190 | * enable IBRS around firmware calls. | |
dd84441a | 1191 | */ |
a94faf3f | 1192 | if (boot_cpu_has(X86_FEATURE_IBRS) && !spectre_v2_in_eibrs_mode(mode)) { |
dd84441a DW |
1193 | setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); |
1194 | pr_info("Enabling Restricted Speculation for firmware calls\n"); | |
1195 | } | |
53c613fe | 1196 | |
fa1202ef TG |
1197 | /* Set up IBPB and STIBP depending on the general spectre V2 command */ |
1198 | spectre_v2_user_select_mitigation(cmd); | |
da285121 DW |
1199 | } |
1200 | ||
6893a959 | 1201 | static void update_stibp_msr(void * __unused) |
15d6b7aa | 1202 | { |
6893a959 | 1203 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
15d6b7aa TG |
1204 | } |
1205 | ||
6893a959 TG |
1206 | /* Update x86_spec_ctrl_base in case SMT state changed. */ |
1207 | static void update_stibp_strict(void) | |
15d6b7aa | 1208 | { |
6893a959 TG |
1209 | u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP; |
1210 | ||
1211 | if (sched_smt_active()) | |
1212 | mask |= SPEC_CTRL_STIBP; | |
1213 | ||
1214 | if (mask == x86_spec_ctrl_base) | |
1215 | return; | |
1216 | ||
1217 | pr_info("Update user space SMT mitigation: STIBP %s\n", | |
1218 | mask & SPEC_CTRL_STIBP ? "always-on" : "off"); | |
1219 | x86_spec_ctrl_base = mask; | |
1220 | on_each_cpu(update_stibp_msr, NULL, 1); | |
15d6b7aa TG |
1221 | } |
1222 | ||
7cc765a6 TG |
1223 | /* Update the static key controlling the evaluation of TIF_SPEC_IB */ |
1224 | static void update_indir_branch_cond(void) | |
1225 | { | |
1226 | if (sched_smt_active()) | |
1227 | static_branch_enable(&switch_to_cond_stibp); | |
1228 | else | |
1229 | static_branch_disable(&switch_to_cond_stibp); | |
1230 | } | |
1231 | ||
39226ef0 JP |
1232 | #undef pr_fmt |
1233 | #define pr_fmt(fmt) fmt | |
1234 | ||
bc124170 TG |
1235 | /* Update the static key controlling the MDS CPU buffer clear in idle */ |
1236 | static void update_mds_branch_idle(void) | |
1237 | { | |
92a2794a PG |
1238 | u64 ia32_cap = x86_read_arch_cap_msr(); |
1239 | ||
bc124170 TG |
1240 | /* |
1241 | * Enable the idle clearing if SMT is active on CPUs which are | |
1242 | * affected only by MSBDS and not any other MDS variant. | |
1243 | * | |
1244 | * The other variants cannot be mitigated when SMT is enabled, so | |
1245 | * clearing the buffers on idle just to prevent the Store Buffer | |
1246 | * repartitioning leak would be a window dressing exercise. | |
1247 | */ | |
1248 | if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY)) | |
1249 | return; | |
1250 | ||
92a2794a | 1251 | if (sched_smt_active()) { |
bc124170 | 1252 | static_branch_enable(&mds_idle_clear); |
92a2794a PG |
1253 | } else if (mmio_mitigation == MMIO_MITIGATION_OFF || |
1254 | (ia32_cap & ARCH_CAP_FBSDP_NO)) { | |
bc124170 | 1255 | static_branch_disable(&mds_idle_clear); |
92a2794a | 1256 | } |
bc124170 TG |
1257 | } |
1258 | ||
39226ef0 | 1259 | #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n" |
1b42f017 | 1260 | #define TAA_MSG_SMT "TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details.\n" |
db343f8b | 1261 | #define MMIO_MSG_SMT "MMIO Stale Data CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/processor_mmio_stale_data.html for more details.\n" |
39226ef0 | 1262 | |
9c92374b | 1263 | void cpu_bugs_smt_update(void) |
15d6b7aa | 1264 | { |
15d6b7aa TG |
1265 | mutex_lock(&spec_ctrl_mutex); |
1266 | ||
810643a7 JP |
1267 | if (sched_smt_active() && unprivileged_ebpf_enabled() && |
1268 | spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE) | |
1269 | pr_warn_once(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG); | |
1270 | ||
21998a35 | 1271 | switch (spectre_v2_user_stibp) { |
6893a959 TG |
1272 | case SPECTRE_V2_USER_NONE: |
1273 | break; | |
1274 | case SPECTRE_V2_USER_STRICT: | |
20c3a2c3 | 1275 | case SPECTRE_V2_USER_STRICT_PREFERRED: |
6893a959 TG |
1276 | update_stibp_strict(); |
1277 | break; | |
9137bb27 | 1278 | case SPECTRE_V2_USER_PRCTL: |
6b3e64c2 | 1279 | case SPECTRE_V2_USER_SECCOMP: |
7cc765a6 | 1280 | update_indir_branch_cond(); |
9137bb27 | 1281 | break; |
15d6b7aa | 1282 | } |
6893a959 | 1283 | |
22dd8365 TG |
1284 | switch (mds_mitigation) { |
1285 | case MDS_MITIGATION_FULL: | |
1286 | case MDS_MITIGATION_VMWERV: | |
39226ef0 JP |
1287 | if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY)) |
1288 | pr_warn_once(MDS_MSG_SMT); | |
bc124170 | 1289 | update_mds_branch_idle(); |
22dd8365 TG |
1290 | break; |
1291 | case MDS_MITIGATION_OFF: | |
1292 | break; | |
1293 | } | |
bc124170 | 1294 | |
1b42f017 PG |
1295 | switch (taa_mitigation) { |
1296 | case TAA_MITIGATION_VERW: | |
1297 | case TAA_MITIGATION_UCODE_NEEDED: | |
1298 | if (sched_smt_active()) | |
1299 | pr_warn_once(TAA_MSG_SMT); | |
1300 | break; | |
1301 | case TAA_MITIGATION_TSX_DISABLED: | |
1302 | case TAA_MITIGATION_OFF: | |
1303 | break; | |
1304 | } | |
1305 | ||
db343f8b JP |
1306 | switch (mmio_mitigation) { |
1307 | case MMIO_MITIGATION_VERW: | |
1308 | case MMIO_MITIGATION_UCODE_NEEDED: | |
1309 | if (sched_smt_active()) | |
1310 | pr_warn_once(MMIO_MSG_SMT); | |
1311 | break; | |
1312 | case MMIO_MITIGATION_OFF: | |
1313 | break; | |
1314 | } | |
1315 | ||
15d6b7aa TG |
1316 | mutex_unlock(&spec_ctrl_mutex); |
1317 | } | |
1318 | ||
24f7fc83 KRW |
1319 | #undef pr_fmt |
1320 | #define pr_fmt(fmt) "Speculative Store Bypass: " fmt | |
1321 | ||
f9544b2b | 1322 | static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE; |
24f7fc83 KRW |
1323 | |
1324 | /* The kernel command line selection */ | |
1325 | enum ssb_mitigation_cmd { | |
1326 | SPEC_STORE_BYPASS_CMD_NONE, | |
1327 | SPEC_STORE_BYPASS_CMD_AUTO, | |
1328 | SPEC_STORE_BYPASS_CMD_ON, | |
a73ec77e | 1329 | SPEC_STORE_BYPASS_CMD_PRCTL, |
f21b53b2 | 1330 | SPEC_STORE_BYPASS_CMD_SECCOMP, |
24f7fc83 KRW |
1331 | }; |
1332 | ||
8770709f | 1333 | static const char * const ssb_strings[] = { |
24f7fc83 | 1334 | [SPEC_STORE_BYPASS_NONE] = "Vulnerable", |
a73ec77e | 1335 | [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", |
f21b53b2 KC |
1336 | [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", |
1337 | [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp", | |
24f7fc83 KRW |
1338 | }; |
1339 | ||
1340 | static const struct { | |
1341 | const char *option; | |
1342 | enum ssb_mitigation_cmd cmd; | |
1de7edbb | 1343 | } ssb_mitigation_options[] __initconst = { |
f21b53b2 KC |
1344 | { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ |
1345 | { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ | |
1346 | { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ | |
1347 | { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */ | |
1348 | { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */ | |
24f7fc83 KRW |
1349 | }; |
1350 | ||
1351 | static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) | |
1352 | { | |
1353 | enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO; | |
1354 | char arg[20]; | |
1355 | int ret, i; | |
1356 | ||
d68be4c4 JP |
1357 | if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable") || |
1358 | cpu_mitigations_off()) { | |
24f7fc83 KRW |
1359 | return SPEC_STORE_BYPASS_CMD_NONE; |
1360 | } else { | |
1361 | ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", | |
1362 | arg, sizeof(arg)); | |
1363 | if (ret < 0) | |
1364 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
1365 | ||
1366 | for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { | |
1367 | if (!match_option(arg, ret, ssb_mitigation_options[i].option)) | |
1368 | continue; | |
1369 | ||
1370 | cmd = ssb_mitigation_options[i].cmd; | |
1371 | break; | |
1372 | } | |
1373 | ||
1374 | if (i >= ARRAY_SIZE(ssb_mitigation_options)) { | |
1375 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
1376 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
1377 | } | |
1378 | } | |
1379 | ||
1380 | return cmd; | |
1381 | } | |
1382 | ||
d66d8ff3 | 1383 | static enum ssb_mitigation __init __ssb_select_mitigation(void) |
24f7fc83 KRW |
1384 | { |
1385 | enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; | |
1386 | enum ssb_mitigation_cmd cmd; | |
1387 | ||
9f65fb29 | 1388 | if (!boot_cpu_has(X86_FEATURE_SSBD)) |
24f7fc83 KRW |
1389 | return mode; |
1390 | ||
1391 | cmd = ssb_parse_cmdline(); | |
1392 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && | |
1393 | (cmd == SPEC_STORE_BYPASS_CMD_NONE || | |
1394 | cmd == SPEC_STORE_BYPASS_CMD_AUTO)) | |
1395 | return mode; | |
1396 | ||
1397 | switch (cmd) { | |
1398 | case SPEC_STORE_BYPASS_CMD_AUTO: | |
f21b53b2 KC |
1399 | case SPEC_STORE_BYPASS_CMD_SECCOMP: |
1400 | /* | |
1401 | * Choose prctl+seccomp as the default mode if seccomp is | |
1402 | * enabled. | |
1403 | */ | |
1404 | if (IS_ENABLED(CONFIG_SECCOMP)) | |
1405 | mode = SPEC_STORE_BYPASS_SECCOMP; | |
1406 | else | |
1407 | mode = SPEC_STORE_BYPASS_PRCTL; | |
a73ec77e | 1408 | break; |
24f7fc83 KRW |
1409 | case SPEC_STORE_BYPASS_CMD_ON: |
1410 | mode = SPEC_STORE_BYPASS_DISABLE; | |
1411 | break; | |
a73ec77e TG |
1412 | case SPEC_STORE_BYPASS_CMD_PRCTL: |
1413 | mode = SPEC_STORE_BYPASS_PRCTL; | |
1414 | break; | |
24f7fc83 KRW |
1415 | case SPEC_STORE_BYPASS_CMD_NONE: |
1416 | break; | |
1417 | } | |
1418 | ||
c1f7fec1 AJ |
1419 | /* |
1420 | * If SSBD is controlled by the SPEC_CTRL MSR, then set the proper | |
1421 | * bit in the mask to allow guests to use the mitigation even in the | |
1422 | * case where the host does not enable it. | |
1423 | */ | |
1424 | if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || | |
1425 | static_cpu_has(X86_FEATURE_AMD_SSBD)) { | |
1426 | x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; | |
1427 | } | |
1428 | ||
77243971 KRW |
1429 | /* |
1430 | * We have three CPU feature flags that are in play here: | |
1431 | * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. | |
9f65fb29 | 1432 | * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass |
77243971 KRW |
1433 | * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation |
1434 | */ | |
a73ec77e | 1435 | if (mode == SPEC_STORE_BYPASS_DISABLE) { |
24f7fc83 | 1436 | setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); |
77243971 | 1437 | /* |
6ac2f49e KRW |
1438 | * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may |
1439 | * use a completely different MSR and bit dependent on family. | |
77243971 | 1440 | */ |
612bc3b3 TL |
1441 | if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) && |
1442 | !static_cpu_has(X86_FEATURE_AMD_SSBD)) { | |
108fab4b | 1443 | x86_amd_ssb_disable(); |
612bc3b3 | 1444 | } else { |
9f65fb29 | 1445 | x86_spec_ctrl_base |= SPEC_CTRL_SSBD; |
4b59bdb5 | 1446 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
77243971 KRW |
1447 | } |
1448 | } | |
1449 | ||
24f7fc83 KRW |
1450 | return mode; |
1451 | } | |
1452 | ||
ffed645e | 1453 | static void ssb_select_mitigation(void) |
24f7fc83 KRW |
1454 | { |
1455 | ssb_mode = __ssb_select_mitigation(); | |
1456 | ||
1457 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
1458 | pr_info("%s\n", ssb_strings[ssb_mode]); | |
1459 | } | |
1460 | ||
da285121 | 1461 | #undef pr_fmt |
f21b53b2 | 1462 | #define pr_fmt(fmt) "Speculation prctl: " fmt |
da285121 | 1463 | |
6d991ba5 | 1464 | static void task_update_spec_tif(struct task_struct *tsk) |
a73ec77e | 1465 | { |
6d991ba5 TG |
1466 | /* Force the update of the real TIF bits */ |
1467 | set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE); | |
e6da8bb6 TG |
1468 | |
1469 | /* | |
1470 | * Immediately update the speculation control MSRs for the current | |
1471 | * task, but for a non-current task delay setting the CPU | |
1472 | * mitigation until it is scheduled next. | |
1473 | * | |
1474 | * This can only happen for SECCOMP mitigation. For PRCTL it's | |
1475 | * always the current task. | |
1476 | */ | |
6d991ba5 | 1477 | if (tsk == current) |
e6da8bb6 TG |
1478 | speculation_ctrl_update_current(); |
1479 | } | |
1480 | ||
e893bb1b BS |
1481 | static int l1d_flush_prctl_set(struct task_struct *task, unsigned long ctrl) |
1482 | { | |
1483 | ||
1484 | if (!static_branch_unlikely(&switch_mm_cond_l1d_flush)) | |
1485 | return -EPERM; | |
1486 | ||
1487 | switch (ctrl) { | |
1488 | case PR_SPEC_ENABLE: | |
1489 | set_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH); | |
1490 | return 0; | |
1491 | case PR_SPEC_DISABLE: | |
1492 | clear_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH); | |
1493 | return 0; | |
1494 | default: | |
1495 | return -ERANGE; | |
1496 | } | |
1497 | } | |
1498 | ||
e6da8bb6 TG |
1499 | static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) |
1500 | { | |
f21b53b2 KC |
1501 | if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && |
1502 | ssb_mode != SPEC_STORE_BYPASS_SECCOMP) | |
a73ec77e TG |
1503 | return -ENXIO; |
1504 | ||
356e4bff TG |
1505 | switch (ctrl) { |
1506 | case PR_SPEC_ENABLE: | |
1507 | /* If speculation is force disabled, enable is not allowed */ | |
1508 | if (task_spec_ssb_force_disable(task)) | |
1509 | return -EPERM; | |
1510 | task_clear_spec_ssb_disable(task); | |
71368af9 | 1511 | task_clear_spec_ssb_noexec(task); |
6d991ba5 | 1512 | task_update_spec_tif(task); |
356e4bff TG |
1513 | break; |
1514 | case PR_SPEC_DISABLE: | |
1515 | task_set_spec_ssb_disable(task); | |
71368af9 | 1516 | task_clear_spec_ssb_noexec(task); |
6d991ba5 | 1517 | task_update_spec_tif(task); |
356e4bff TG |
1518 | break; |
1519 | case PR_SPEC_FORCE_DISABLE: | |
1520 | task_set_spec_ssb_disable(task); | |
1521 | task_set_spec_ssb_force_disable(task); | |
71368af9 WL |
1522 | task_clear_spec_ssb_noexec(task); |
1523 | task_update_spec_tif(task); | |
1524 | break; | |
1525 | case PR_SPEC_DISABLE_NOEXEC: | |
1526 | if (task_spec_ssb_force_disable(task)) | |
1527 | return -EPERM; | |
1528 | task_set_spec_ssb_disable(task); | |
1529 | task_set_spec_ssb_noexec(task); | |
6d991ba5 | 1530 | task_update_spec_tif(task); |
356e4bff TG |
1531 | break; |
1532 | default: | |
1533 | return -ERANGE; | |
1534 | } | |
a73ec77e TG |
1535 | return 0; |
1536 | } | |
1537 | ||
1978b3a5 AM |
1538 | static bool is_spec_ib_user_controlled(void) |
1539 | { | |
1540 | return spectre_v2_user_ibpb == SPECTRE_V2_USER_PRCTL || | |
1541 | spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP || | |
1542 | spectre_v2_user_stibp == SPECTRE_V2_USER_PRCTL || | |
1543 | spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP; | |
1544 | } | |
1545 | ||
9137bb27 TG |
1546 | static int ib_prctl_set(struct task_struct *task, unsigned long ctrl) |
1547 | { | |
1548 | switch (ctrl) { | |
1549 | case PR_SPEC_ENABLE: | |
21998a35 AS |
1550 | if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE && |
1551 | spectre_v2_user_stibp == SPECTRE_V2_USER_NONE) | |
9137bb27 | 1552 | return 0; |
1978b3a5 | 1553 | |
9137bb27 | 1554 | /* |
1978b3a5 AM |
1555 | * With strict mode for both IBPB and STIBP, the instruction |
1556 | * code paths avoid checking this task flag and instead, | |
1557 | * unconditionally run the instruction. However, STIBP and IBPB | |
1558 | * are independent and either can be set to conditionally | |
1559 | * enabled regardless of the mode of the other. | |
1560 | * | |
1561 | * If either is set to conditional, allow the task flag to be | |
1562 | * updated, unless it was force-disabled by a previous prctl | |
1563 | * call. Currently, this is possible on an AMD CPU which has the | |
1564 | * feature X86_FEATURE_AMD_STIBP_ALWAYS_ON. In this case, if the | |
1565 | * kernel is booted with 'spectre_v2_user=seccomp', then | |
1566 | * spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP and | |
1567 | * spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED. | |
9137bb27 | 1568 | */ |
1978b3a5 | 1569 | if (!is_spec_ib_user_controlled() || |
4d8df8cb | 1570 | task_spec_ib_force_disable(task)) |
9137bb27 | 1571 | return -EPERM; |
1978b3a5 | 1572 | |
9137bb27 TG |
1573 | task_clear_spec_ib_disable(task); |
1574 | task_update_spec_tif(task); | |
1575 | break; | |
1576 | case PR_SPEC_DISABLE: | |
1577 | case PR_SPEC_FORCE_DISABLE: | |
1578 | /* | |
1579 | * Indirect branch speculation is always allowed when | |
1580 | * mitigation is force disabled. | |
1581 | */ | |
21998a35 AS |
1582 | if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE && |
1583 | spectre_v2_user_stibp == SPECTRE_V2_USER_NONE) | |
9137bb27 | 1584 | return -EPERM; |
1978b3a5 AM |
1585 | |
1586 | if (!is_spec_ib_user_controlled()) | |
9137bb27 | 1587 | return 0; |
1978b3a5 | 1588 | |
9137bb27 TG |
1589 | task_set_spec_ib_disable(task); |
1590 | if (ctrl == PR_SPEC_FORCE_DISABLE) | |
1591 | task_set_spec_ib_force_disable(task); | |
1592 | task_update_spec_tif(task); | |
1593 | break; | |
1594 | default: | |
1595 | return -ERANGE; | |
1596 | } | |
1597 | return 0; | |
1598 | } | |
1599 | ||
8bf37d8c TG |
1600 | int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, |
1601 | unsigned long ctrl) | |
1602 | { | |
1603 | switch (which) { | |
1604 | case PR_SPEC_STORE_BYPASS: | |
1605 | return ssb_prctl_set(task, ctrl); | |
9137bb27 TG |
1606 | case PR_SPEC_INDIRECT_BRANCH: |
1607 | return ib_prctl_set(task, ctrl); | |
e893bb1b BS |
1608 | case PR_SPEC_L1D_FLUSH: |
1609 | return l1d_flush_prctl_set(task, ctrl); | |
8bf37d8c TG |
1610 | default: |
1611 | return -ENODEV; | |
1612 | } | |
1613 | } | |
1614 | ||
1615 | #ifdef CONFIG_SECCOMP | |
1616 | void arch_seccomp_spec_mitigate(struct task_struct *task) | |
1617 | { | |
f21b53b2 KC |
1618 | if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) |
1619 | ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
21998a35 AS |
1620 | if (spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP || |
1621 | spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP) | |
6b3e64c2 | 1622 | ib_prctl_set(task, PR_SPEC_FORCE_DISABLE); |
8bf37d8c TG |
1623 | } |
1624 | #endif | |
1625 | ||
e893bb1b BS |
1626 | static int l1d_flush_prctl_get(struct task_struct *task) |
1627 | { | |
1628 | if (!static_branch_unlikely(&switch_mm_cond_l1d_flush)) | |
1629 | return PR_SPEC_FORCE_DISABLE; | |
1630 | ||
1631 | if (test_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH)) | |
1632 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
1633 | else | |
1634 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; | |
1635 | } | |
1636 | ||
7bbf1373 | 1637 | static int ssb_prctl_get(struct task_struct *task) |
a73ec77e TG |
1638 | { |
1639 | switch (ssb_mode) { | |
1640 | case SPEC_STORE_BYPASS_DISABLE: | |
1641 | return PR_SPEC_DISABLE; | |
f21b53b2 | 1642 | case SPEC_STORE_BYPASS_SECCOMP: |
a73ec77e | 1643 | case SPEC_STORE_BYPASS_PRCTL: |
356e4bff TG |
1644 | if (task_spec_ssb_force_disable(task)) |
1645 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
71368af9 WL |
1646 | if (task_spec_ssb_noexec(task)) |
1647 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE_NOEXEC; | |
356e4bff | 1648 | if (task_spec_ssb_disable(task)) |
a73ec77e TG |
1649 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; |
1650 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
1651 | default: | |
1652 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
1653 | return PR_SPEC_ENABLE; | |
1654 | return PR_SPEC_NOT_AFFECTED; | |
1655 | } | |
1656 | } | |
1657 | ||
9137bb27 TG |
1658 | static int ib_prctl_get(struct task_struct *task) |
1659 | { | |
1660 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
1661 | return PR_SPEC_NOT_AFFECTED; | |
1662 | ||
21998a35 AS |
1663 | if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE && |
1664 | spectre_v2_user_stibp == SPECTRE_V2_USER_NONE) | |
9137bb27 | 1665 | return PR_SPEC_ENABLE; |
1978b3a5 | 1666 | else if (is_spec_ib_user_controlled()) { |
9137bb27 TG |
1667 | if (task_spec_ib_force_disable(task)) |
1668 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
1669 | if (task_spec_ib_disable(task)) | |
1670 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; | |
1671 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
1978b3a5 AM |
1672 | } else if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT || |
1673 | spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT || | |
1674 | spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED) | |
1675 | return PR_SPEC_DISABLE; | |
1676 | else | |
9137bb27 | 1677 | return PR_SPEC_NOT_AFFECTED; |
9137bb27 TG |
1678 | } |
1679 | ||
7bbf1373 | 1680 | int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) |
a73ec77e TG |
1681 | { |
1682 | switch (which) { | |
1683 | case PR_SPEC_STORE_BYPASS: | |
7bbf1373 | 1684 | return ssb_prctl_get(task); |
9137bb27 TG |
1685 | case PR_SPEC_INDIRECT_BRANCH: |
1686 | return ib_prctl_get(task); | |
e893bb1b BS |
1687 | case PR_SPEC_L1D_FLUSH: |
1688 | return l1d_flush_prctl_get(task); | |
a73ec77e TG |
1689 | default: |
1690 | return -ENODEV; | |
1691 | } | |
1692 | } | |
1693 | ||
77243971 KRW |
1694 | void x86_spec_ctrl_setup_ap(void) |
1695 | { | |
7eb8956a | 1696 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
4b59bdb5 | 1697 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
764f3c21 KRW |
1698 | |
1699 | if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) | |
9f65fb29 | 1700 | x86_amd_ssb_disable(); |
77243971 KRW |
1701 | } |
1702 | ||
b8e8c830 PB |
1703 | bool itlb_multihit_kvm_mitigation; |
1704 | EXPORT_SYMBOL_GPL(itlb_multihit_kvm_mitigation); | |
1705 | ||
56563f53 KRW |
1706 | #undef pr_fmt |
1707 | #define pr_fmt(fmt) "L1TF: " fmt | |
72c6d2db | 1708 | |
d90a7a0e JK |
1709 | /* Default mitigation for L1TF-affected CPUs */ |
1710 | enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH; | |
72c6d2db | 1711 | #if IS_ENABLED(CONFIG_KVM_INTEL) |
d90a7a0e | 1712 | EXPORT_SYMBOL_GPL(l1tf_mitigation); |
1eb46908 | 1713 | #endif |
895ae47f | 1714 | enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; |
72c6d2db | 1715 | EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation); |
72c6d2db | 1716 | |
cc51e542 AK |
1717 | /* |
1718 | * These CPUs all support 44bits physical address space internally in the | |
1719 | * cache but CPUID can report a smaller number of physical address bits. | |
1720 | * | |
1721 | * The L1TF mitigation uses the top most address bit for the inversion of | |
1722 | * non present PTEs. When the installed memory reaches into the top most | |
1723 | * address bit due to memory holes, which has been observed on machines | |
1724 | * which report 36bits physical address bits and have 32G RAM installed, | |
1725 | * then the mitigation range check in l1tf_select_mitigation() triggers. | |
1726 | * This is a false positive because the mitigation is still possible due to | |
1727 | * the fact that the cache uses 44bit internally. Use the cache bits | |
1728 | * instead of the reported physical bits and adjust them on the affected | |
1729 | * machines to 44bit if the reported bits are less than 44. | |
1730 | */ | |
1731 | static void override_cache_bits(struct cpuinfo_x86 *c) | |
1732 | { | |
1733 | if (c->x86 != 6) | |
1734 | return; | |
1735 | ||
1736 | switch (c->x86_model) { | |
1737 | case INTEL_FAM6_NEHALEM: | |
1738 | case INTEL_FAM6_WESTMERE: | |
1739 | case INTEL_FAM6_SANDYBRIDGE: | |
1740 | case INTEL_FAM6_IVYBRIDGE: | |
c66f78a6 | 1741 | case INTEL_FAM6_HASWELL: |
af239c44 | 1742 | case INTEL_FAM6_HASWELL_L: |
5e741407 | 1743 | case INTEL_FAM6_HASWELL_G: |
c66f78a6 | 1744 | case INTEL_FAM6_BROADWELL: |
5e741407 | 1745 | case INTEL_FAM6_BROADWELL_G: |
af239c44 | 1746 | case INTEL_FAM6_SKYLAKE_L: |
c66f78a6 | 1747 | case INTEL_FAM6_SKYLAKE: |
af239c44 | 1748 | case INTEL_FAM6_KABYLAKE_L: |
c66f78a6 | 1749 | case INTEL_FAM6_KABYLAKE: |
cc51e542 AK |
1750 | if (c->x86_cache_bits < 44) |
1751 | c->x86_cache_bits = 44; | |
1752 | break; | |
1753 | } | |
1754 | } | |
1755 | ||
56563f53 KRW |
1756 | static void __init l1tf_select_mitigation(void) |
1757 | { | |
1758 | u64 half_pa; | |
1759 | ||
1760 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
1761 | return; | |
1762 | ||
d68be4c4 JP |
1763 | if (cpu_mitigations_off()) |
1764 | l1tf_mitigation = L1TF_MITIGATION_OFF; | |
1765 | else if (cpu_mitigations_auto_nosmt()) | |
1766 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; | |
1767 | ||
cc51e542 AK |
1768 | override_cache_bits(&boot_cpu_data); |
1769 | ||
d90a7a0e JK |
1770 | switch (l1tf_mitigation) { |
1771 | case L1TF_MITIGATION_OFF: | |
1772 | case L1TF_MITIGATION_FLUSH_NOWARN: | |
1773 | case L1TF_MITIGATION_FLUSH: | |
1774 | break; | |
1775 | case L1TF_MITIGATION_FLUSH_NOSMT: | |
1776 | case L1TF_MITIGATION_FULL: | |
1777 | cpu_smt_disable(false); | |
1778 | break; | |
1779 | case L1TF_MITIGATION_FULL_FORCE: | |
1780 | cpu_smt_disable(true); | |
1781 | break; | |
1782 | } | |
1783 | ||
56563f53 KRW |
1784 | #if CONFIG_PGTABLE_LEVELS == 2 |
1785 | pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n"); | |
1786 | return; | |
1787 | #endif | |
1788 | ||
56563f53 | 1789 | half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT; |
5b5e4d62 MH |
1790 | if (l1tf_mitigation != L1TF_MITIGATION_OFF && |
1791 | e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) { | |
56563f53 | 1792 | pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n"); |
6a012288 VB |
1793 | pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n", |
1794 | half_pa); | |
1795 | pr_info("However, doing so will make a part of your RAM unusable.\n"); | |
65fd4cb6 | 1796 | pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n"); |
56563f53 KRW |
1797 | return; |
1798 | } | |
1799 | ||
1800 | setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV); | |
1801 | } | |
d90a7a0e JK |
1802 | |
1803 | static int __init l1tf_cmdline(char *str) | |
1804 | { | |
1805 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
1806 | return 0; | |
1807 | ||
1808 | if (!str) | |
1809 | return -EINVAL; | |
1810 | ||
1811 | if (!strcmp(str, "off")) | |
1812 | l1tf_mitigation = L1TF_MITIGATION_OFF; | |
1813 | else if (!strcmp(str, "flush,nowarn")) | |
1814 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN; | |
1815 | else if (!strcmp(str, "flush")) | |
1816 | l1tf_mitigation = L1TF_MITIGATION_FLUSH; | |
1817 | else if (!strcmp(str, "flush,nosmt")) | |
1818 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; | |
1819 | else if (!strcmp(str, "full")) | |
1820 | l1tf_mitigation = L1TF_MITIGATION_FULL; | |
1821 | else if (!strcmp(str, "full,force")) | |
1822 | l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE; | |
1823 | ||
1824 | return 0; | |
1825 | } | |
1826 | early_param("l1tf", l1tf_cmdline); | |
1827 | ||
56563f53 | 1828 | #undef pr_fmt |
39226ef0 | 1829 | #define pr_fmt(fmt) fmt |
56563f53 | 1830 | |
61dc0f55 | 1831 | #ifdef CONFIG_SYSFS |
d1059518 | 1832 | |
72c6d2db TG |
1833 | #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion" |
1834 | ||
1835 | #if IS_ENABLED(CONFIG_KVM_INTEL) | |
8770709f | 1836 | static const char * const l1tf_vmx_states[] = { |
a7b9020b TG |
1837 | [VMENTER_L1D_FLUSH_AUTO] = "auto", |
1838 | [VMENTER_L1D_FLUSH_NEVER] = "vulnerable", | |
1839 | [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes", | |
1840 | [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes", | |
1841 | [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled", | |
8e0b2b91 | 1842 | [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary" |
72c6d2db TG |
1843 | }; |
1844 | ||
1845 | static ssize_t l1tf_show_state(char *buf) | |
1846 | { | |
1847 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) | |
1848 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
1849 | ||
ea156d19 PB |
1850 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED || |
1851 | (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER && | |
130d6f94 | 1852 | sched_smt_active())) { |
ea156d19 PB |
1853 | return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG, |
1854 | l1tf_vmx_states[l1tf_vmx_mitigation]); | |
130d6f94 | 1855 | } |
ea156d19 PB |
1856 | |
1857 | return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG, | |
1858 | l1tf_vmx_states[l1tf_vmx_mitigation], | |
130d6f94 | 1859 | sched_smt_active() ? "vulnerable" : "disabled"); |
72c6d2db | 1860 | } |
b8e8c830 PB |
1861 | |
1862 | static ssize_t itlb_multihit_show_state(char *buf) | |
1863 | { | |
f29dfa53 PG |
1864 | if (!boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || |
1865 | !boot_cpu_has(X86_FEATURE_VMX)) | |
1866 | return sprintf(buf, "KVM: Mitigation: VMX unsupported\n"); | |
1867 | else if (!(cr4_read_shadow() & X86_CR4_VMXE)) | |
1868 | return sprintf(buf, "KVM: Mitigation: VMX disabled\n"); | |
1869 | else if (itlb_multihit_kvm_mitigation) | |
b8e8c830 PB |
1870 | return sprintf(buf, "KVM: Mitigation: Split huge pages\n"); |
1871 | else | |
1872 | return sprintf(buf, "KVM: Vulnerable\n"); | |
1873 | } | |
72c6d2db TG |
1874 | #else |
1875 | static ssize_t l1tf_show_state(char *buf) | |
1876 | { | |
1877 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
1878 | } | |
72c6d2db | 1879 | |
db4d30fb VT |
1880 | static ssize_t itlb_multihit_show_state(char *buf) |
1881 | { | |
1882 | return sprintf(buf, "Processor vulnerable\n"); | |
1883 | } | |
b8e8c830 | 1884 | #endif |
db4d30fb | 1885 | |
8a4b06d3 TG |
1886 | static ssize_t mds_show_state(char *buf) |
1887 | { | |
517c3ba0 | 1888 | if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { |
8a4b06d3 TG |
1889 | return sprintf(buf, "%s; SMT Host state unknown\n", |
1890 | mds_strings[mds_mitigation]); | |
1891 | } | |
1892 | ||
1893 | if (boot_cpu_has(X86_BUG_MSBDS_ONLY)) { | |
1894 | return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation], | |
e2c3c947 KRW |
1895 | (mds_mitigation == MDS_MITIGATION_OFF ? "vulnerable" : |
1896 | sched_smt_active() ? "mitigated" : "disabled")); | |
8a4b06d3 TG |
1897 | } |
1898 | ||
1899 | return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation], | |
1900 | sched_smt_active() ? "vulnerable" : "disabled"); | |
1901 | } | |
1902 | ||
6608b45a PG |
1903 | static ssize_t tsx_async_abort_show_state(char *buf) |
1904 | { | |
1905 | if ((taa_mitigation == TAA_MITIGATION_TSX_DISABLED) || | |
1906 | (taa_mitigation == TAA_MITIGATION_OFF)) | |
1907 | return sprintf(buf, "%s\n", taa_strings[taa_mitigation]); | |
1908 | ||
1909 | if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { | |
1910 | return sprintf(buf, "%s; SMT Host state unknown\n", | |
1911 | taa_strings[taa_mitigation]); | |
1912 | } | |
1913 | ||
1914 | return sprintf(buf, "%s; SMT %s\n", taa_strings[taa_mitigation], | |
1915 | sched_smt_active() ? "vulnerable" : "disabled"); | |
1916 | } | |
1917 | ||
01489569 PG |
1918 | static ssize_t mmio_stale_data_show_state(char *buf) |
1919 | { | |
1920 | if (mmio_mitigation == MMIO_MITIGATION_OFF) | |
1921 | return sysfs_emit(buf, "%s\n", mmio_strings[mmio_mitigation]); | |
1922 | ||
1923 | if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { | |
1924 | return sysfs_emit(buf, "%s; SMT Host state unknown\n", | |
1925 | mmio_strings[mmio_mitigation]); | |
1926 | } | |
1927 | ||
1928 | return sysfs_emit(buf, "%s; SMT %s\n", mmio_strings[mmio_mitigation], | |
1929 | sched_smt_active() ? "vulnerable" : "disabled"); | |
1930 | } | |
1931 | ||
a8f76ae4 TC |
1932 | static char *stibp_state(void) |
1933 | { | |
a94faf3f | 1934 | if (spectre_v2_in_eibrs_mode(spectre_v2_enabled)) |
34bce7c9 TC |
1935 | return ""; |
1936 | ||
21998a35 | 1937 | switch (spectre_v2_user_stibp) { |
fa1202ef TG |
1938 | case SPECTRE_V2_USER_NONE: |
1939 | return ", STIBP: disabled"; | |
1940 | case SPECTRE_V2_USER_STRICT: | |
1941 | return ", STIBP: forced"; | |
20c3a2c3 TL |
1942 | case SPECTRE_V2_USER_STRICT_PREFERRED: |
1943 | return ", STIBP: always-on"; | |
9137bb27 | 1944 | case SPECTRE_V2_USER_PRCTL: |
6b3e64c2 | 1945 | case SPECTRE_V2_USER_SECCOMP: |
7cc765a6 TG |
1946 | if (static_key_enabled(&switch_to_cond_stibp)) |
1947 | return ", STIBP: conditional"; | |
fa1202ef TG |
1948 | } |
1949 | return ""; | |
a8f76ae4 TC |
1950 | } |
1951 | ||
1952 | static char *ibpb_state(void) | |
1953 | { | |
4c71a2b6 | 1954 | if (boot_cpu_has(X86_FEATURE_IBPB)) { |
7cc765a6 | 1955 | if (static_key_enabled(&switch_mm_always_ibpb)) |
4c71a2b6 | 1956 | return ", IBPB: always-on"; |
7cc765a6 TG |
1957 | if (static_key_enabled(&switch_mm_cond_ibpb)) |
1958 | return ", IBPB: conditional"; | |
1959 | return ", IBPB: disabled"; | |
4c71a2b6 TG |
1960 | } |
1961 | return ""; | |
a8f76ae4 TC |
1962 | } |
1963 | ||
534fcc9a JP |
1964 | static ssize_t spectre_v2_show_state(char *buf) |
1965 | { | |
92cf97b2 JP |
1966 | if (spectre_v2_enabled == SPECTRE_V2_LFENCE) |
1967 | return sprintf(buf, "Vulnerable: LFENCE\n"); | |
1968 | ||
534fcc9a | 1969 | if (spectre_v2_enabled == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled()) |
810643a7 JP |
1970 | return sprintf(buf, "Vulnerable: eIBRS with unprivileged eBPF\n"); |
1971 | ||
1972 | if (sched_smt_active() && unprivileged_ebpf_enabled() && | |
1973 | spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE) | |
1974 | return sprintf(buf, "Vulnerable: eIBRS+LFENCE with unprivileged eBPF and SMT\n"); | |
534fcc9a JP |
1975 | |
1976 | return sprintf(buf, "%s%s%s%s%s%s\n", | |
1977 | spectre_v2_strings[spectre_v2_enabled], | |
1978 | ibpb_state(), | |
1979 | boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", | |
1980 | stibp_state(), | |
1981 | boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "", | |
1982 | spectre_v2_module_string()); | |
1983 | } | |
1984 | ||
7e5b3c26 MG |
1985 | static ssize_t srbds_show_state(char *buf) |
1986 | { | |
1987 | return sprintf(buf, "%s\n", srbds_strings[srbds_mitigation]); | |
1988 | } | |
1989 | ||
7bb4d366 | 1990 | static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, |
ffed645e | 1991 | char *buf, unsigned int bug) |
61dc0f55 | 1992 | { |
d1059518 | 1993 | if (!boot_cpu_has_bug(bug)) |
61dc0f55 | 1994 | return sprintf(buf, "Not affected\n"); |
d1059518 KRW |
1995 | |
1996 | switch (bug) { | |
1997 | case X86_BUG_CPU_MELTDOWN: | |
1998 | if (boot_cpu_has(X86_FEATURE_PTI)) | |
1999 | return sprintf(buf, "Mitigation: PTI\n"); | |
2000 | ||
6cb2b08f JK |
2001 | if (hypervisor_is_type(X86_HYPER_XEN_PV)) |
2002 | return sprintf(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n"); | |
2003 | ||
d1059518 KRW |
2004 | break; |
2005 | ||
2006 | case X86_BUG_SPECTRE_V1: | |
a2059825 | 2007 | return sprintf(buf, "%s\n", spectre_v1_strings[spectre_v1_mitigation]); |
d1059518 KRW |
2008 | |
2009 | case X86_BUG_SPECTRE_V2: | |
534fcc9a | 2010 | return spectre_v2_show_state(buf); |
d1059518 | 2011 | |
24f7fc83 KRW |
2012 | case X86_BUG_SPEC_STORE_BYPASS: |
2013 | return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); | |
2014 | ||
17dbca11 AK |
2015 | case X86_BUG_L1TF: |
2016 | if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV)) | |
72c6d2db | 2017 | return l1tf_show_state(buf); |
17dbca11 | 2018 | break; |
8a4b06d3 TG |
2019 | |
2020 | case X86_BUG_MDS: | |
2021 | return mds_show_state(buf); | |
2022 | ||
6608b45a PG |
2023 | case X86_BUG_TAA: |
2024 | return tsx_async_abort_show_state(buf); | |
2025 | ||
db4d30fb VT |
2026 | case X86_BUG_ITLB_MULTIHIT: |
2027 | return itlb_multihit_show_state(buf); | |
2028 | ||
7e5b3c26 MG |
2029 | case X86_BUG_SRBDS: |
2030 | return srbds_show_state(buf); | |
2031 | ||
01489569 PG |
2032 | case X86_BUG_MMIO_STALE_DATA: |
2033 | return mmio_stale_data_show_state(buf); | |
2034 | ||
d1059518 KRW |
2035 | default: |
2036 | break; | |
2037 | } | |
2038 | ||
61dc0f55 TG |
2039 | return sprintf(buf, "Vulnerable\n"); |
2040 | } | |
2041 | ||
d1059518 KRW |
2042 | ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) |
2043 | { | |
2044 | return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); | |
2045 | } | |
2046 | ||
21e433bd | 2047 | ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 2048 | { |
d1059518 | 2049 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); |
61dc0f55 TG |
2050 | } |
2051 | ||
21e433bd | 2052 | ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 2053 | { |
d1059518 | 2054 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); |
61dc0f55 | 2055 | } |
c456442c KRW |
2056 | |
2057 | ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) | |
2058 | { | |
2059 | return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); | |
2060 | } | |
17dbca11 AK |
2061 | |
2062 | ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf) | |
2063 | { | |
2064 | return cpu_show_common(dev, attr, buf, X86_BUG_L1TF); | |
2065 | } | |
8a4b06d3 TG |
2066 | |
2067 | ssize_t cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf) | |
2068 | { | |
2069 | return cpu_show_common(dev, attr, buf, X86_BUG_MDS); | |
2070 | } | |
6608b45a PG |
2071 | |
2072 | ssize_t cpu_show_tsx_async_abort(struct device *dev, struct device_attribute *attr, char *buf) | |
2073 | { | |
2074 | return cpu_show_common(dev, attr, buf, X86_BUG_TAA); | |
2075 | } | |
db4d30fb VT |
2076 | |
2077 | ssize_t cpu_show_itlb_multihit(struct device *dev, struct device_attribute *attr, char *buf) | |
2078 | { | |
2079 | return cpu_show_common(dev, attr, buf, X86_BUG_ITLB_MULTIHIT); | |
2080 | } | |
7e5b3c26 MG |
2081 | |
2082 | ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *buf) | |
2083 | { | |
2084 | return cpu_show_common(dev, attr, buf, X86_BUG_SRBDS); | |
2085 | } | |
01489569 PG |
2086 | |
2087 | ssize_t cpu_show_mmio_stale_data(struct device *dev, struct device_attribute *attr, char *buf) | |
2088 | { | |
2089 | return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_STALE_DATA); | |
2090 | } | |
61dc0f55 | 2091 | #endif |