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Commit | Line | Data |
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48f4c485 | 1 | #include <linux/bitops.h> |
1da177e4 | 2 | #include <linux/kernel.h> |
edc05e6d | 3 | |
cd4d09ec | 4 | #include <asm/cpufeature.h> |
1da177e4 | 5 | #include <asm/e820.h> |
52f4a91a | 6 | #include <asm/mtrr.h> |
48f4c485 | 7 | #include <asm/msr.h> |
edc05e6d | 8 | |
1da177e4 LT |
9 | #include "cpu.h" |
10 | ||
1da177e4 LT |
11 | #define ACE_PRESENT (1 << 6) |
12 | #define ACE_ENABLED (1 << 7) | |
13 | #define ACE_FCR (1 << 28) /* MSR_VIA_FCR */ | |
14 | ||
15 | #define RNG_PRESENT (1 << 2) | |
16 | #define RNG_ENABLED (1 << 3) | |
17 | #define RNG_ENABLE (1 << 6) /* MSR_VIA_RNG */ | |
18 | ||
148f9bb8 | 19 | static void init_c3(struct cpuinfo_x86 *c) |
1da177e4 LT |
20 | { |
21 | u32 lo, hi; | |
22 | ||
23 | /* Test for Centaur Extended Feature Flags presence */ | |
24 | if (cpuid_eax(0xC0000000) >= 0xC0000001) { | |
25 | u32 tmp = cpuid_edx(0xC0000001); | |
26 | ||
27 | /* enable ACE unit, if present and disabled */ | |
28 | if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) { | |
29a9994b | 29 | rdmsr(MSR_VIA_FCR, lo, hi); |
1da177e4 | 30 | lo |= ACE_FCR; /* enable ACE unit */ |
29a9994b | 31 | wrmsr(MSR_VIA_FCR, lo, hi); |
1b74dde7 | 32 | pr_info("CPU: Enabled ACE h/w crypto\n"); |
1da177e4 LT |
33 | } |
34 | ||
35 | /* enable RNG unit, if present and disabled */ | |
36 | if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) { | |
29a9994b | 37 | rdmsr(MSR_VIA_RNG, lo, hi); |
1da177e4 | 38 | lo |= RNG_ENABLE; /* enable RNG unit */ |
29a9994b | 39 | wrmsr(MSR_VIA_RNG, lo, hi); |
1b74dde7 | 40 | pr_info("CPU: Enabled h/w RNG\n"); |
1da177e4 LT |
41 | } |
42 | ||
43 | /* store Centaur Extended Feature Flags as | |
44 | * word 5 of the CPU capability bit array | |
45 | */ | |
39c06df4 | 46 | c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001); |
1da177e4 | 47 | } |
48f4c485 | 48 | #ifdef CONFIG_X86_32 |
27b46d76 | 49 | /* Cyrix III family needs CX8 & PGE explicitly enabled. */ |
cb3f718d | 50 | if (c->x86_model >= 6 && c->x86_model <= 13) { |
29a9994b | 51 | rdmsr(MSR_VIA_FCR, lo, hi); |
1da177e4 | 52 | lo |= (1<<1 | 1<<7); |
29a9994b | 53 | wrmsr(MSR_VIA_FCR, lo, hi); |
e1a94a97 | 54 | set_cpu_cap(c, X86_FEATURE_CX8); |
1da177e4 LT |
55 | } |
56 | ||
57 | /* Before Nehemiah, the C3's had 3dNOW! */ | |
29a9994b | 58 | if (c->x86_model >= 6 && c->x86_model < 9) |
e1a94a97 | 59 | set_cpu_cap(c, X86_FEATURE_3DNOW); |
48f4c485 SAS |
60 | #endif |
61 | if (c->x86 == 0x6 && c->x86_model >= 0xf) { | |
62 | c->x86_cache_alignment = c->x86_clflush_size * 2; | |
63 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); | |
64 | } | |
1da177e4 | 65 | |
27c13ece | 66 | cpu_detect_cache_sizes(c); |
1da177e4 LT |
67 | } |
68 | ||
edc05e6d IM |
69 | enum { |
70 | ECX8 = 1<<1, | |
71 | EIERRINT = 1<<2, | |
72 | DPM = 1<<3, | |
73 | DMCE = 1<<4, | |
74 | DSTPCLK = 1<<5, | |
75 | ELINEAR = 1<<6, | |
76 | DSMC = 1<<7, | |
77 | DTLOCK = 1<<8, | |
78 | EDCTLB = 1<<8, | |
79 | EMMX = 1<<9, | |
80 | DPDC = 1<<11, | |
81 | EBRPRED = 1<<12, | |
82 | DIC = 1<<13, | |
83 | DDC = 1<<14, | |
84 | DNA = 1<<15, | |
85 | ERETSTK = 1<<16, | |
86 | E2MMX = 1<<19, | |
87 | EAMD3D = 1<<20, | |
88 | }; | |
89 | ||
148f9bb8 | 90 | static void early_init_centaur(struct cpuinfo_x86 *c) |
5fef55fd YL |
91 | { |
92 | switch (c->x86) { | |
48f4c485 | 93 | #ifdef CONFIG_X86_32 |
5fef55fd YL |
94 | case 5: |
95 | /* Emulate MTRRs using Centaur's MCR. */ | |
96 | set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR); | |
97 | break; | |
48f4c485 SAS |
98 | #endif |
99 | case 6: | |
100 | if (c->x86_model >= 0xf) | |
101 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); | |
102 | break; | |
5fef55fd | 103 | } |
48f4c485 SAS |
104 | #ifdef CONFIG_X86_64 |
105 | set_cpu_cap(c, X86_FEATURE_SYSENTER32); | |
106 | #endif | |
5fef55fd YL |
107 | } |
108 | ||
148f9bb8 | 109 | static void init_centaur(struct cpuinfo_x86 *c) |
1da177e4 | 110 | { |
48f4c485 | 111 | #ifdef CONFIG_X86_32 |
1da177e4 | 112 | char *name; |
29a9994b PC |
113 | u32 fcr_set = 0; |
114 | u32 fcr_clr = 0; | |
115 | u32 lo, hi, newlo; | |
116 | u32 aa, bb, cc, dd; | |
1da177e4 | 117 | |
edc05e6d IM |
118 | /* |
119 | * Bit 31 in normal CPUID used for nonstandard 3DNow ID; | |
120 | * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway | |
121 | */ | |
e1a94a97 | 122 | clear_cpu_cap(c, 0*32+31); |
48f4c485 SAS |
123 | #endif |
124 | early_init_centaur(c); | |
1da177e4 | 125 | switch (c->x86) { |
48f4c485 | 126 | #ifdef CONFIG_X86_32 |
29a9994b | 127 | case 5: |
edc05e6d IM |
128 | switch (c->x86_model) { |
129 | case 4: | |
130 | name = "C6"; | |
131 | fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK; | |
132 | fcr_clr = DPDC; | |
1b74dde7 | 133 | pr_notice("Disabling bugged TSC.\n"); |
e1a94a97 | 134 | clear_cpu_cap(c, X86_FEATURE_TSC); |
edc05e6d IM |
135 | break; |
136 | case 8: | |
137 | switch (c->x86_mask) { | |
138 | default: | |
139 | name = "2"; | |
1da177e4 | 140 | break; |
edc05e6d IM |
141 | case 7 ... 9: |
142 | name = "2A"; | |
143 | break; | |
144 | case 10 ... 15: | |
145 | name = "2B"; | |
146 | break; | |
147 | } | |
148 | fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK| | |
149 | E2MMX|EAMD3D; | |
150 | fcr_clr = DPDC; | |
edc05e6d IM |
151 | break; |
152 | case 9: | |
153 | name = "3"; | |
154 | fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK| | |
155 | E2MMX|EAMD3D; | |
156 | fcr_clr = DPDC; | |
edc05e6d IM |
157 | break; |
158 | default: | |
159 | name = "??"; | |
160 | } | |
1da177e4 | 161 | |
edc05e6d IM |
162 | rdmsr(MSR_IDT_FCR1, lo, hi); |
163 | newlo = (lo|fcr_set) & (~fcr_clr); | |
1da177e4 | 164 | |
edc05e6d | 165 | if (newlo != lo) { |
1b74dde7 | 166 | pr_info("Centaur FCR was 0x%X now 0x%X\n", |
edc05e6d IM |
167 | lo, newlo); |
168 | wrmsr(MSR_IDT_FCR1, newlo, hi); | |
169 | } else { | |
1b74dde7 | 170 | pr_info("Centaur FCR is 0x%X\n", lo); |
edc05e6d IM |
171 | } |
172 | /* Emulate MTRRs using Centaur's MCR. */ | |
e1a94a97 | 173 | set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR); |
edc05e6d | 174 | /* Report CX8 */ |
e1a94a97 | 175 | set_cpu_cap(c, X86_FEATURE_CX8); |
edc05e6d IM |
176 | /* Set 3DNow! on Winchip 2 and above. */ |
177 | if (c->x86_model >= 8) | |
e1a94a97 | 178 | set_cpu_cap(c, X86_FEATURE_3DNOW); |
edc05e6d IM |
179 | /* See if we can find out some more. */ |
180 | if (cpuid_eax(0x80000000) >= 0x80000005) { | |
181 | /* Yes, we can. */ | |
182 | cpuid(0x80000005, &aa, &bb, &cc, &dd); | |
183 | /* Add L1 data and code cache sizes. */ | |
184 | c->x86_cache_size = (cc>>24)+(dd>>24); | |
185 | } | |
186 | sprintf(c->x86_model_id, "WinChip %s", name); | |
187 | break; | |
48f4c485 | 188 | #endif |
29a9994b | 189 | case 6: |
edc05e6d IM |
190 | init_c3(c); |
191 | break; | |
1da177e4 | 192 | } |
48f4c485 SAS |
193 | #ifdef CONFIG_X86_64 |
194 | set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); | |
195 | #endif | |
1da177e4 LT |
196 | } |
197 | ||
09dc68d9 | 198 | #ifdef CONFIG_X86_32 |
148f9bb8 | 199 | static unsigned int |
edc05e6d | 200 | centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size) |
1da177e4 LT |
201 | { |
202 | /* VIA C3 CPUs (670-68F) need further shifting. */ | |
203 | if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8))) | |
204 | size >>= 8; | |
205 | ||
edc05e6d IM |
206 | /* |
207 | * There's also an erratum in Nehemiah stepping 1, which | |
208 | * returns '65KB' instead of '64KB' | |
209 | * - Note, it seems this may only be in engineering samples. | |
210 | */ | |
211 | if ((c->x86 == 6) && (c->x86_model == 9) && | |
212 | (c->x86_mask == 1) && (size == 65)) | |
29a9994b | 213 | size -= 1; |
1da177e4 LT |
214 | return size; |
215 | } | |
09dc68d9 | 216 | #endif |
1da177e4 | 217 | |
148f9bb8 | 218 | static const struct cpu_dev centaur_cpu_dev = { |
1da177e4 LT |
219 | .c_vendor = "Centaur", |
220 | .c_ident = { "CentaurHauls" }, | |
5fef55fd | 221 | .c_early_init = early_init_centaur, |
1da177e4 | 222 | .c_init = init_centaur, |
09dc68d9 JB |
223 | #ifdef CONFIG_X86_32 |
224 | .legacy_cache_size = centaur_size_cache, | |
225 | #endif | |
10a434fc | 226 | .c_x86_vendor = X86_VENDOR_CENTAUR, |
1da177e4 LT |
227 | }; |
228 | ||
10a434fc | 229 | cpu_dev_register(centaur_cpu_dev); |