[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kernel / cpu / centaur.c

// SPDX-License-Identifier: GPL-2.0

#include <linux/sched.h>
#include <linux/sched/clock.h>

#include <asm/cpufeature.h>
#include <asm/e820/api.h>
#include <asm/mtrr.h>
#include <asm/msr.h>

#include "cpu.h"

#define ACE_PRESENT	(1 << 6)
#define ACE_ENABLED	(1 << 7)
#define ACE_FCR		(1 << 28)	/* MSR_VIA_FCR */

#define RNG_PRESENT	(1 << 2)
#define RNG_ENABLED	(1 << 3)
#define RNG_ENABLE	(1 << 6)	/* MSR_VIA_RNG */

#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW	0x00200000
#define X86_VMX_FEATURE_PROC_CTLS_VNMI		0x00400000
#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS	0x80000000
#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC	0x00000001
#define X86_VMX_FEATURE_PROC_CTLS2_EPT		0x00000002
#define X86_VMX_FEATURE_PROC_CTLS2_VPID		0x00000020

static void init_c3(struct cpuinfo_x86 *c)
{
	u32  lo, hi;

	/* Test for Centaur Extended Feature Flags presence */
	if (cpuid_eax(0xC0000000) >= 0xC0000001) {
		u32 tmp = cpuid_edx(0xC0000001);

		/* enable ACE unit, if present and disabled */
		if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
			rdmsr(MSR_VIA_FCR, lo, hi);
			lo |= ACE_FCR;		/* enable ACE unit */
			wrmsr(MSR_VIA_FCR, lo, hi);
			pr_info("CPU: Enabled ACE h/w crypto\n");
		}

		/* enable RNG unit, if present and disabled */
		if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
			rdmsr(MSR_VIA_RNG, lo, hi);
			lo |= RNG_ENABLE;	/* enable RNG unit */
			wrmsr(MSR_VIA_RNG, lo, hi);
			pr_info("CPU: Enabled h/w RNG\n");
		}

		/* store Centaur Extended Feature Flags as
		 * word 5 of the CPU capability bit array
		 */
		c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001);
	}
#ifdef CONFIG_X86_32
	/* Cyrix III family needs CX8 & PGE explicitly enabled. */
	if (c->x86_model >= 6 && c->x86_model <= 13) {
		rdmsr(MSR_VIA_FCR, lo, hi);
		lo |= (1<<1 | 1<<7);
		wrmsr(MSR_VIA_FCR, lo, hi);
		set_cpu_cap(c, X86_FEATURE_CX8);
	}

	/* Before Nehemiah, the C3's had 3dNOW! */
	if (c->x86_model >= 6 && c->x86_model < 9)
		set_cpu_cap(c, X86_FEATURE_3DNOW);
#endif
	if (c->x86 == 0x6 && c->x86_model >= 0xf) {
		c->x86_cache_alignment = c->x86_clflush_size * 2;
		set_cpu_cap(c, X86_FEATURE_REP_GOOD);
	}

	cpu_detect_cache_sizes(c);
}

enum {
		ECX8		= 1<<1,
		EIERRINT	= 1<<2,
		DPM		= 1<<3,
		DMCE		= 1<<4,
		DSTPCLK		= 1<<5,
		ELINEAR		= 1<<6,
		DSMC		= 1<<7,
		DTLOCK		= 1<<8,
		EDCTLB		= 1<<8,
		EMMX		= 1<<9,
		DPDC		= 1<<11,
		EBRPRED		= 1<<12,
		DIC		= 1<<13,
		DDC		= 1<<14,
		DNA		= 1<<15,
		ERETSTK		= 1<<16,
		E2MMX		= 1<<19,
		EAMD3D		= 1<<20,
};

static void early_init_centaur(struct cpuinfo_x86 *c)
{
	switch (c->x86) {
#ifdef CONFIG_X86_32
	case 5:
		/* Emulate MTRRs using Centaur's MCR. */
		set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
		break;
#endif
	case 6:
		if (c->x86_model >= 0xf)
			set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
		break;
	}
#ifdef CONFIG_X86_64
	set_cpu_cap(c, X86_FEATURE_SYSENTER32);
#endif
}

static void centaur_detect_vmx_virtcap(struct cpuinfo_x86 *c)
{
	u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;

	rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
	msr_ctl = vmx_msr_high | vmx_msr_low;

	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
		set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
		set_cpu_cap(c, X86_FEATURE_VNMI);
	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
		rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
		      vmx_msr_low, vmx_msr_high);
		msr_ctl2 = vmx_msr_high | vmx_msr_low;
		if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
		    (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
			set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
		if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
			set_cpu_cap(c, X86_FEATURE_EPT);
		if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
			set_cpu_cap(c, X86_FEATURE_VPID);
	}
}

static void init_centaur(struct cpuinfo_x86 *c)
{
#ifdef CONFIG_X86_32
	char *name;
	u32  fcr_set = 0;
	u32  fcr_clr = 0;
	u32  lo, hi, newlo;
	u32  aa, bb, cc, dd;

	/*
	 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
	 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
	 */
	clear_cpu_cap(c, 0*32+31);
#endif
	early_init_centaur(c);
	init_intel_cacheinfo(c);
	detect_num_cpu_cores(c);
#ifdef CONFIG_X86_32
	detect_ht(c);
#endif

	if (c->cpuid_level > 9) {
		unsigned int eax = cpuid_eax(10);

		/*
		 * Check for version and the number of counters
		 * Version(eax[7:0]) can't be 0;
		 * Counters(eax[15:8]) should be greater than 1;
		 */
		if ((eax & 0xff) && (((eax >> 8) & 0xff) > 1))
			set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
	}

	switch (c->x86) {
#ifdef CONFIG_X86_32
	case 5:
		switch (c->x86_model) {
		case 4:
			name = "C6";
			fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK;
			fcr_clr = DPDC;
			pr_notice("Disabling bugged TSC.\n");
			clear_cpu_cap(c, X86_FEATURE_TSC);
			break;
		case 8:
			switch (c->x86_stepping) {
			default:
			name = "2";
				break;
			case 7 ... 9:
				name = "2A";
				break;
			case 10 ... 15:
				name = "2B";
				break;
			}
			fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
				  E2MMX|EAMD3D;
			fcr_clr = DPDC;
			break;
		case 9:
			name = "3";
			fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
				  E2MMX|EAMD3D;
			fcr_clr = DPDC;
			break;
		default:
			name = "??";
		}

		rdmsr(MSR_IDT_FCR1, lo, hi);
		newlo = (lo|fcr_set) & (~fcr_clr);

		if (newlo != lo) {
			pr_info("Centaur FCR was 0x%X now 0x%X\n",
				lo, newlo);
			wrmsr(MSR_IDT_FCR1, newlo, hi);
		} else {
			pr_info("Centaur FCR is 0x%X\n", lo);
		}
		/* Emulate MTRRs using Centaur's MCR. */
		set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
		/* Report CX8 */
		set_cpu_cap(c, X86_FEATURE_CX8);
		/* Set 3DNow! on Winchip 2 and above. */
		if (c->x86_model >= 8)
			set_cpu_cap(c, X86_FEATURE_3DNOW);
		/* See if we can find out some more. */
		if (cpuid_eax(0x80000000) >= 0x80000005) {
			/* Yes, we can. */
			cpuid(0x80000005, &aa, &bb, &cc, &dd);
			/* Add L1 data and code cache sizes. */
			c->x86_cache_size = (cc>>24)+(dd>>24);
		}
		sprintf(c->x86_model_id, "WinChip %s", name);
		break;
#endif
	case 6:
		init_c3(c);
		break;
	}
#ifdef CONFIG_X86_64
	set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
#endif

	if (cpu_has(c, X86_FEATURE_VMX))
		centaur_detect_vmx_virtcap(c);
}

#ifdef CONFIG_X86_32
static unsigned int
centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size)
{
	/* VIA C3 CPUs (670-68F) need further shifting. */
	if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8)))
		size >>= 8;

	/*
	 * There's also an erratum in Nehemiah stepping 1, which
	 * returns '65KB' instead of '64KB'
	 *  - Note, it seems this may only be in engineering samples.
	 */
	if ((c->x86 == 6) && (c->x86_model == 9) &&
				(c->x86_stepping == 1) && (size == 65))
		size -= 1;
	return size;
}
#endif

static const struct cpu_dev centaur_cpu_dev = {
	.c_vendor	= "Centaur",
	.c_ident	= { "CentaurHauls" },
	.c_early_init	= early_init_centaur,
	.c_init		= init_centaur,
#ifdef CONFIG_X86_32
	.legacy_cache_size = centaur_size_cache,
#endif
	.c_x86_vendor	= X86_VENDOR_CENTAUR,
};

cpu_dev_register(centaur_cpu_dev);
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
acb04058 PZ	2
acb04058 PZ	3	#include <linux/sched.h>
e6017571	4	#include <linux/sched/clock.h>
edc05e6d	5
cd4d09ec	6	#include <asm/cpufeature.h>
66441bd3	7	#include <asm/e820/api.h>
52f4a91a	8	#include <asm/mtrr.h>
48f4c485	9	#include <asm/msr.h>
edc05e6d	10
1da177e4 LT	11	#include "cpu.h"
1da177e4 LT	12
1da177e4 LT	13	#define ACE_PRESENT (1 << 6)
	14	#define ACE_ENABLED (1 << 7)
	15	#define ACE_FCR (1 << 28) /* MSR_VIA_FCR */
	16
	17	#define RNG_PRESENT (1 << 2)
	18	#define RNG_ENABLED (1 << 3)
	19	#define RNG_ENABLE (1 << 6) /* MSR_VIA_RNG */
	20
2997fdbb DW	21	#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
	22	#define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
	23	#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
	24	#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
	25	#define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
	26	#define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
	27
148f9bb8	28	static void init_c3(struct cpuinfo_x86 *c)
1da177e4 LT	29	{
	30	u32 lo, hi;
	31
	32	/* Test for Centaur Extended Feature Flags presence */
	33	if (cpuid_eax(0xC0000000) >= 0xC0000001) {
	34	u32 tmp = cpuid_edx(0xC0000001);
	35
	36	/* enable ACE unit, if present and disabled */
	37	if ((tmp & (ACE_PRESENT \| ACE_ENABLED)) == ACE_PRESENT) {
29a9994b	38	rdmsr(MSR_VIA_FCR, lo, hi);
1da177e4	39	lo \|= ACE_FCR; /* enable ACE unit */
29a9994b	40	wrmsr(MSR_VIA_FCR, lo, hi);
1b74dde7	41	pr_info("CPU: Enabled ACE h/w crypto\n");
1da177e4 LT	42	}
	43
	44	/* enable RNG unit, if present and disabled */
	45	if ((tmp & (RNG_PRESENT \| RNG_ENABLED)) == RNG_PRESENT) {
29a9994b	46	rdmsr(MSR_VIA_RNG, lo, hi);
1da177e4	47	lo \|= RNG_ENABLE; /* enable RNG unit */
29a9994b	48	wrmsr(MSR_VIA_RNG, lo, hi);
1b74dde7	49	pr_info("CPU: Enabled h/w RNG\n");
1da177e4 LT	50	}
	51
	52	/* store Centaur Extended Feature Flags as
	53	* word 5 of the CPU capability bit array
	54	*/
39c06df4	55	c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001);
1da177e4	56	}
48f4c485	57	#ifdef CONFIG_X86_32
27b46d76	58	/* Cyrix III family needs CX8 & PGE explicitly enabled. */
cb3f718d	59	if (c->x86_model >= 6 && c->x86_model <= 13) {
29a9994b	60	rdmsr(MSR_VIA_FCR, lo, hi);
1da177e4	61	lo \|= (1<<1 \| 1<<7);
29a9994b	62	wrmsr(MSR_VIA_FCR, lo, hi);
e1a94a97	63	set_cpu_cap(c, X86_FEATURE_CX8);
1da177e4 LT	64	}
	65
	66	/* Before Nehemiah, the C3's had 3dNOW! */
29a9994b	67	if (c->x86_model >= 6 && c->x86_model < 9)
e1a94a97	68	set_cpu_cap(c, X86_FEATURE_3DNOW);
48f4c485 SAS	69	#endif
	70	if (c->x86 == 0x6 && c->x86_model >= 0xf) {
	71	c->x86_cache_alignment = c->x86_clflush_size * 2;
	72	set_cpu_cap(c, X86_FEATURE_REP_GOOD);
	73	}
1da177e4	74
27c13ece	75	cpu_detect_cache_sizes(c);
1da177e4 LT	76	}
1da177e4 LT	77
edc05e6d IM	78	enum {
	79	ECX8 = 1<<1,
	80	EIERRINT = 1<<2,
	81	DPM = 1<<3,
	82	DMCE = 1<<4,
	83	DSTPCLK = 1<<5,
	84	ELINEAR = 1<<6,
	85	DSMC = 1<<7,
	86	DTLOCK = 1<<8,
	87	EDCTLB = 1<<8,
	88	EMMX = 1<<9,
	89	DPDC = 1<<11,
	90	EBRPRED = 1<<12,
	91	DIC = 1<<13,
	92	DDC = 1<<14,
	93	DNA = 1<<15,
	94	ERETSTK = 1<<16,
	95	E2MMX = 1<<19,
	96	EAMD3D = 1<<20,
	97	};
	98
148f9bb8	99	static void early_init_centaur(struct cpuinfo_x86 *c)
5fef55fd YL	100	{
5fef55fd YL	101	switch (c->x86) {
48f4c485	102	#ifdef CONFIG_X86_32
5fef55fd YL	103	case 5:
	104	/* Emulate MTRRs using Centaur's MCR. */
	105	set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
	106	break;
48f4c485 SAS	107	#endif
	108	case 6:
	109	if (c->x86_model >= 0xf)
	110	set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
	111	break;
5fef55fd	112	}
48f4c485 SAS	113	#ifdef CONFIG_X86_64
	114	set_cpu_cap(c, X86_FEATURE_SYSENTER32);
	115	#endif
5fef55fd YL	116	}
5fef55fd YL	117
2997fdbb DW	118	static void centaur_detect_vmx_virtcap(struct cpuinfo_x86 *c)
	119	{
	120	u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
	121
	122	rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
	123	msr_ctl = vmx_msr_high \| vmx_msr_low;
	124
	125	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
	126	set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
	127	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
	128	set_cpu_cap(c, X86_FEATURE_VNMI);
	129	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
	130	rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
	131	vmx_msr_low, vmx_msr_high);
	132	msr_ctl2 = vmx_msr_high \| vmx_msr_low;
	133	if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
	134	(msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
	135	set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
	136	if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
	137	set_cpu_cap(c, X86_FEATURE_EPT);
	138	if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
	139	set_cpu_cap(c, X86_FEATURE_VPID);
	140	}
	141	}
	142
148f9bb8	143	static void init_centaur(struct cpuinfo_x86 *c)
1da177e4	144	{
48f4c485	145	#ifdef CONFIG_X86_32
1da177e4	146	char *name;
29a9994b PC	147	u32 fcr_set = 0;
	148	u32 fcr_clr = 0;
	149	u32 lo, hi, newlo;
	150	u32 aa, bb, cc, dd;
1da177e4	151
edc05e6d IM	152	/*
	153	* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
	154	* 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
	155	*/
e1a94a97	156	clear_cpu_cap(c, 0*32+31);
48f4c485 SAS	157	#endif
48f4c485 SAS	158	early_init_centaur(c);
e9b953ae	159	init_intel_cacheinfo(c);
b72c9c97	160	detect_num_cpu_cores(c);
e9b953ae DW	161	#ifdef CONFIG_X86_32
	162	detect_ht(c);
	163	#endif
2997fdbb DW	164
	165	if (c->cpuid_level > 9) {
	166	unsigned int eax = cpuid_eax(10);
	167
	168	/*
	169	* Check for version and the number of counters
	170	* Version(eax[7:0]) can't be 0;
	171	* Counters(eax[15:8]) should be greater than 1;
	172	*/
	173	if ((eax & 0xff) && (((eax >> 8) & 0xff) > 1))
	174	set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
	175	}
	176
1da177e4	177	switch (c->x86) {
48f4c485	178	#ifdef CONFIG_X86_32
29a9994b	179	case 5:
edc05e6d IM	180	switch (c->x86_model) {
	181	case 4:
	182	name = "C6";
	183	fcr_set = ECX8\|DSMC\|EDCTLB\|EMMX\|ERETSTK;
	184	fcr_clr = DPDC;
1b74dde7	185	pr_notice("Disabling bugged TSC.\n");
e1a94a97	186	clear_cpu_cap(c, X86_FEATURE_TSC);
edc05e6d IM	187	break;
edc05e6d IM	188	case 8:
dd7cc466	189	switch (c->x86_stepping) {
edc05e6d IM	190	default:
edc05e6d IM	191	name = "2";
1da177e4	192	break;
edc05e6d IM	193	case 7 ... 9:
	194	name = "2A";
	195	break;
	196	case 10 ... 15:
	197	name = "2B";
	198	break;
	199	}
	200	fcr_set = ECX8\|DSMC\|DTLOCK\|EMMX\|EBRPRED\|ERETSTK\|
	201	E2MMX\|EAMD3D;
	202	fcr_clr = DPDC;
edc05e6d IM	203	break;
	204	case 9:
	205	name = "3";
	206	fcr_set = ECX8\|DSMC\|DTLOCK\|EMMX\|EBRPRED\|ERETSTK\|
	207	E2MMX\|EAMD3D;
	208	fcr_clr = DPDC;
edc05e6d IM	209	break;
	210	default:
	211	name = "??";
	212	}
1da177e4	213
edc05e6d IM	214	rdmsr(MSR_IDT_FCR1, lo, hi);
edc05e6d IM	215	newlo = (lo\|fcr_set) & (~fcr_clr);
1da177e4	216
edc05e6d	217	if (newlo != lo) {
1b74dde7	218	pr_info("Centaur FCR was 0x%X now 0x%X\n",
edc05e6d IM	219	lo, newlo);
	220	wrmsr(MSR_IDT_FCR1, newlo, hi);
	221	} else {
1b74dde7	222	pr_info("Centaur FCR is 0x%X\n", lo);
edc05e6d IM	223	}
edc05e6d IM	224	/* Emulate MTRRs using Centaur's MCR. */
e1a94a97	225	set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
edc05e6d	226	/* Report CX8 */
e1a94a97	227	set_cpu_cap(c, X86_FEATURE_CX8);
edc05e6d IM	228	/* Set 3DNow! on Winchip 2 and above. */
edc05e6d IM	229	if (c->x86_model >= 8)
e1a94a97	230	set_cpu_cap(c, X86_FEATURE_3DNOW);
edc05e6d IM	231	/* See if we can find out some more. */
	232	if (cpuid_eax(0x80000000) >= 0x80000005) {
	233	/* Yes, we can. */
	234	cpuid(0x80000005, &aa, &bb, &cc, &dd);
	235	/* Add L1 data and code cache sizes. */
	236	c->x86_cache_size = (cc>>24)+(dd>>24);
	237	}
	238	sprintf(c->x86_model_id, "WinChip %s", name);
	239	break;
48f4c485	240	#endif
29a9994b	241	case 6:
edc05e6d IM	242	init_c3(c);
edc05e6d IM	243	break;
1da177e4	244	}
48f4c485 SAS	245	#ifdef CONFIG_X86_64
	246	set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
	247	#endif
2997fdbb DW	248
	249	if (cpu_has(c, X86_FEATURE_VMX))
	250	centaur_detect_vmx_virtcap(c);
1da177e4 LT	251	}
1da177e4 LT	252
09dc68d9	253	#ifdef CONFIG_X86_32
148f9bb8	254	static unsigned int
edc05e6d	255	centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size)
1da177e4 LT	256	{
	257	/* VIA C3 CPUs (670-68F) need further shifting. */
	258	if ((c->x86 == 6) && ((c->x86_model == 7) \|\| (c->x86_model == 8)))
	259	size >>= 8;
	260
edc05e6d IM	261	/*
	262	* There's also an erratum in Nehemiah stepping 1, which
	263	* returns '65KB' instead of '64KB'
	264	* - Note, it seems this may only be in engineering samples.
	265	*/
	266	if ((c->x86 == 6) && (c->x86_model == 9) &&
dd7cc466	267	(c->x86_stepping == 1) && (size == 65))
29a9994b	268	size -= 1;
1da177e4 LT	269	return size;
1da177e4 LT	270	}
09dc68d9	271	#endif
1da177e4	272
148f9bb8	273	static const struct cpu_dev centaur_cpu_dev = {
1da177e4 LT	274	.c_vendor = "Centaur",
1da177e4 LT	275	.c_ident = { "CentaurHauls" },
5fef55fd	276	.c_early_init = early_init_centaur,
1da177e4	277	.c_init = init_centaur,
09dc68d9 JB	278	#ifdef CONFIG_X86_32
	279	.legacy_cache_size = centaur_size_cache,
	280	#endif
10a434fc	281	.c_x86_vendor = X86_VENDOR_CENTAUR,
1da177e4 LT	282	};
1da177e4 LT	283
10a434fc	284	cpu_dev_register(centaur_cpu_dev);