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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
acb04058 PZ |
2 | |
3 | #include <linux/sched.h> | |
e6017571 | 4 | #include <linux/sched/clock.h> |
edc05e6d | 5 | |
cd4d09ec | 6 | #include <asm/cpufeature.h> |
66441bd3 | 7 | #include <asm/e820/api.h> |
52f4a91a | 8 | #include <asm/mtrr.h> |
48f4c485 | 9 | #include <asm/msr.h> |
edc05e6d | 10 | |
1da177e4 LT |
11 | #include "cpu.h" |
12 | ||
1da177e4 LT |
13 | #define ACE_PRESENT (1 << 6) |
14 | #define ACE_ENABLED (1 << 7) | |
15 | #define ACE_FCR (1 << 28) /* MSR_VIA_FCR */ | |
16 | ||
17 | #define RNG_PRESENT (1 << 2) | |
18 | #define RNG_ENABLED (1 << 3) | |
19 | #define RNG_ENABLE (1 << 6) /* MSR_VIA_RNG */ | |
20 | ||
2997fdbb DW |
21 | #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000 |
22 | #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000 | |
23 | #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000 | |
24 | #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001 | |
25 | #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002 | |
26 | #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020 | |
27 | ||
148f9bb8 | 28 | static void init_c3(struct cpuinfo_x86 *c) |
1da177e4 LT |
29 | { |
30 | u32 lo, hi; | |
31 | ||
32 | /* Test for Centaur Extended Feature Flags presence */ | |
33 | if (cpuid_eax(0xC0000000) >= 0xC0000001) { | |
34 | u32 tmp = cpuid_edx(0xC0000001); | |
35 | ||
36 | /* enable ACE unit, if present and disabled */ | |
37 | if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) { | |
29a9994b | 38 | rdmsr(MSR_VIA_FCR, lo, hi); |
1da177e4 | 39 | lo |= ACE_FCR; /* enable ACE unit */ |
29a9994b | 40 | wrmsr(MSR_VIA_FCR, lo, hi); |
1b74dde7 | 41 | pr_info("CPU: Enabled ACE h/w crypto\n"); |
1da177e4 LT |
42 | } |
43 | ||
44 | /* enable RNG unit, if present and disabled */ | |
45 | if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) { | |
29a9994b | 46 | rdmsr(MSR_VIA_RNG, lo, hi); |
1da177e4 | 47 | lo |= RNG_ENABLE; /* enable RNG unit */ |
29a9994b | 48 | wrmsr(MSR_VIA_RNG, lo, hi); |
1b74dde7 | 49 | pr_info("CPU: Enabled h/w RNG\n"); |
1da177e4 LT |
50 | } |
51 | ||
52 | /* store Centaur Extended Feature Flags as | |
53 | * word 5 of the CPU capability bit array | |
54 | */ | |
39c06df4 | 55 | c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001); |
1da177e4 | 56 | } |
48f4c485 | 57 | #ifdef CONFIG_X86_32 |
27b46d76 | 58 | /* Cyrix III family needs CX8 & PGE explicitly enabled. */ |
cb3f718d | 59 | if (c->x86_model >= 6 && c->x86_model <= 13) { |
29a9994b | 60 | rdmsr(MSR_VIA_FCR, lo, hi); |
1da177e4 | 61 | lo |= (1<<1 | 1<<7); |
29a9994b | 62 | wrmsr(MSR_VIA_FCR, lo, hi); |
e1a94a97 | 63 | set_cpu_cap(c, X86_FEATURE_CX8); |
1da177e4 LT |
64 | } |
65 | ||
66 | /* Before Nehemiah, the C3's had 3dNOW! */ | |
29a9994b | 67 | if (c->x86_model >= 6 && c->x86_model < 9) |
e1a94a97 | 68 | set_cpu_cap(c, X86_FEATURE_3DNOW); |
48f4c485 SAS |
69 | #endif |
70 | if (c->x86 == 0x6 && c->x86_model >= 0xf) { | |
71 | c->x86_cache_alignment = c->x86_clflush_size * 2; | |
72 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); | |
73 | } | |
1da177e4 | 74 | |
27c13ece | 75 | cpu_detect_cache_sizes(c); |
1da177e4 LT |
76 | } |
77 | ||
edc05e6d IM |
78 | enum { |
79 | ECX8 = 1<<1, | |
80 | EIERRINT = 1<<2, | |
81 | DPM = 1<<3, | |
82 | DMCE = 1<<4, | |
83 | DSTPCLK = 1<<5, | |
84 | ELINEAR = 1<<6, | |
85 | DSMC = 1<<7, | |
86 | DTLOCK = 1<<8, | |
87 | EDCTLB = 1<<8, | |
88 | EMMX = 1<<9, | |
89 | DPDC = 1<<11, | |
90 | EBRPRED = 1<<12, | |
91 | DIC = 1<<13, | |
92 | DDC = 1<<14, | |
93 | DNA = 1<<15, | |
94 | ERETSTK = 1<<16, | |
95 | E2MMX = 1<<19, | |
96 | EAMD3D = 1<<20, | |
97 | }; | |
98 | ||
148f9bb8 | 99 | static void early_init_centaur(struct cpuinfo_x86 *c) |
5fef55fd YL |
100 | { |
101 | switch (c->x86) { | |
48f4c485 | 102 | #ifdef CONFIG_X86_32 |
5fef55fd YL |
103 | case 5: |
104 | /* Emulate MTRRs using Centaur's MCR. */ | |
105 | set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR); | |
106 | break; | |
48f4c485 SAS |
107 | #endif |
108 | case 6: | |
109 | if (c->x86_model >= 0xf) | |
110 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); | |
111 | break; | |
5fef55fd | 112 | } |
48f4c485 SAS |
113 | #ifdef CONFIG_X86_64 |
114 | set_cpu_cap(c, X86_FEATURE_SYSENTER32); | |
115 | #endif | |
5fef55fd YL |
116 | } |
117 | ||
2997fdbb DW |
118 | static void centaur_detect_vmx_virtcap(struct cpuinfo_x86 *c) |
119 | { | |
120 | u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2; | |
121 | ||
122 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high); | |
123 | msr_ctl = vmx_msr_high | vmx_msr_low; | |
124 | ||
125 | if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW) | |
126 | set_cpu_cap(c, X86_FEATURE_TPR_SHADOW); | |
127 | if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI) | |
128 | set_cpu_cap(c, X86_FEATURE_VNMI); | |
129 | if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) { | |
130 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, | |
131 | vmx_msr_low, vmx_msr_high); | |
132 | msr_ctl2 = vmx_msr_high | vmx_msr_low; | |
133 | if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) && | |
134 | (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)) | |
135 | set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); | |
136 | if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT) | |
137 | set_cpu_cap(c, X86_FEATURE_EPT); | |
138 | if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID) | |
139 | set_cpu_cap(c, X86_FEATURE_VPID); | |
140 | } | |
141 | } | |
142 | ||
148f9bb8 | 143 | static void init_centaur(struct cpuinfo_x86 *c) |
1da177e4 | 144 | { |
48f4c485 | 145 | #ifdef CONFIG_X86_32 |
1da177e4 | 146 | char *name; |
29a9994b PC |
147 | u32 fcr_set = 0; |
148 | u32 fcr_clr = 0; | |
149 | u32 lo, hi, newlo; | |
150 | u32 aa, bb, cc, dd; | |
1da177e4 | 151 | |
edc05e6d IM |
152 | /* |
153 | * Bit 31 in normal CPUID used for nonstandard 3DNow ID; | |
154 | * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway | |
155 | */ | |
e1a94a97 | 156 | clear_cpu_cap(c, 0*32+31); |
48f4c485 SAS |
157 | #endif |
158 | early_init_centaur(c); | |
2997fdbb DW |
159 | |
160 | if (c->cpuid_level > 9) { | |
161 | unsigned int eax = cpuid_eax(10); | |
162 | ||
163 | /* | |
164 | * Check for version and the number of counters | |
165 | * Version(eax[7:0]) can't be 0; | |
166 | * Counters(eax[15:8]) should be greater than 1; | |
167 | */ | |
168 | if ((eax & 0xff) && (((eax >> 8) & 0xff) > 1)) | |
169 | set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); | |
170 | } | |
171 | ||
1da177e4 | 172 | switch (c->x86) { |
48f4c485 | 173 | #ifdef CONFIG_X86_32 |
29a9994b | 174 | case 5: |
edc05e6d IM |
175 | switch (c->x86_model) { |
176 | case 4: | |
177 | name = "C6"; | |
178 | fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK; | |
179 | fcr_clr = DPDC; | |
1b74dde7 | 180 | pr_notice("Disabling bugged TSC.\n"); |
e1a94a97 | 181 | clear_cpu_cap(c, X86_FEATURE_TSC); |
edc05e6d IM |
182 | break; |
183 | case 8: | |
dd7cc466 | 184 | switch (c->x86_stepping) { |
edc05e6d IM |
185 | default: |
186 | name = "2"; | |
1da177e4 | 187 | break; |
edc05e6d IM |
188 | case 7 ... 9: |
189 | name = "2A"; | |
190 | break; | |
191 | case 10 ... 15: | |
192 | name = "2B"; | |
193 | break; | |
194 | } | |
195 | fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK| | |
196 | E2MMX|EAMD3D; | |
197 | fcr_clr = DPDC; | |
edc05e6d IM |
198 | break; |
199 | case 9: | |
200 | name = "3"; | |
201 | fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK| | |
202 | E2MMX|EAMD3D; | |
203 | fcr_clr = DPDC; | |
edc05e6d IM |
204 | break; |
205 | default: | |
206 | name = "??"; | |
207 | } | |
1da177e4 | 208 | |
edc05e6d IM |
209 | rdmsr(MSR_IDT_FCR1, lo, hi); |
210 | newlo = (lo|fcr_set) & (~fcr_clr); | |
1da177e4 | 211 | |
edc05e6d | 212 | if (newlo != lo) { |
1b74dde7 | 213 | pr_info("Centaur FCR was 0x%X now 0x%X\n", |
edc05e6d IM |
214 | lo, newlo); |
215 | wrmsr(MSR_IDT_FCR1, newlo, hi); | |
216 | } else { | |
1b74dde7 | 217 | pr_info("Centaur FCR is 0x%X\n", lo); |
edc05e6d IM |
218 | } |
219 | /* Emulate MTRRs using Centaur's MCR. */ | |
e1a94a97 | 220 | set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR); |
edc05e6d | 221 | /* Report CX8 */ |
e1a94a97 | 222 | set_cpu_cap(c, X86_FEATURE_CX8); |
edc05e6d IM |
223 | /* Set 3DNow! on Winchip 2 and above. */ |
224 | if (c->x86_model >= 8) | |
e1a94a97 | 225 | set_cpu_cap(c, X86_FEATURE_3DNOW); |
edc05e6d IM |
226 | /* See if we can find out some more. */ |
227 | if (cpuid_eax(0x80000000) >= 0x80000005) { | |
228 | /* Yes, we can. */ | |
229 | cpuid(0x80000005, &aa, &bb, &cc, &dd); | |
230 | /* Add L1 data and code cache sizes. */ | |
231 | c->x86_cache_size = (cc>>24)+(dd>>24); | |
232 | } | |
233 | sprintf(c->x86_model_id, "WinChip %s", name); | |
234 | break; | |
48f4c485 | 235 | #endif |
29a9994b | 236 | case 6: |
edc05e6d IM |
237 | init_c3(c); |
238 | break; | |
1da177e4 | 239 | } |
48f4c485 SAS |
240 | #ifdef CONFIG_X86_64 |
241 | set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); | |
242 | #endif | |
2997fdbb DW |
243 | |
244 | if (cpu_has(c, X86_FEATURE_VMX)) | |
245 | centaur_detect_vmx_virtcap(c); | |
1da177e4 LT |
246 | } |
247 | ||
09dc68d9 | 248 | #ifdef CONFIG_X86_32 |
148f9bb8 | 249 | static unsigned int |
edc05e6d | 250 | centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size) |
1da177e4 LT |
251 | { |
252 | /* VIA C3 CPUs (670-68F) need further shifting. */ | |
253 | if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8))) | |
254 | size >>= 8; | |
255 | ||
edc05e6d IM |
256 | /* |
257 | * There's also an erratum in Nehemiah stepping 1, which | |
258 | * returns '65KB' instead of '64KB' | |
259 | * - Note, it seems this may only be in engineering samples. | |
260 | */ | |
261 | if ((c->x86 == 6) && (c->x86_model == 9) && | |
dd7cc466 | 262 | (c->x86_stepping == 1) && (size == 65)) |
29a9994b | 263 | size -= 1; |
1da177e4 LT |
264 | return size; |
265 | } | |
09dc68d9 | 266 | #endif |
1da177e4 | 267 | |
148f9bb8 | 268 | static const struct cpu_dev centaur_cpu_dev = { |
1da177e4 LT |
269 | .c_vendor = "Centaur", |
270 | .c_ident = { "CentaurHauls" }, | |
5fef55fd | 271 | .c_early_init = early_init_centaur, |
1da177e4 | 272 | .c_init = init_centaur, |
09dc68d9 JB |
273 | #ifdef CONFIG_X86_32 |
274 | .legacy_cache_size = centaur_size_cache, | |
275 | #endif | |
10a434fc | 276 | .c_x86_vendor = X86_VENDOR_CENTAUR, |
1da177e4 LT |
277 | }; |
278 | ||
10a434fc | 279 | cpu_dev_register(centaur_cpu_dev); |