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Commit | Line | Data |
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1da177e4 LT |
1 | #include <linux/kernel.h> |
2 | #include <linux/init.h> | |
3 | #include <linux/bitops.h> | |
4 | #include <asm/processor.h> | |
5 | #include <asm/msr.h> | |
6 | #include <asm/e820.h> | |
52f4a91a | 7 | #include <asm/mtrr.h> |
1da177e4 LT |
8 | #include "cpu.h" |
9 | ||
10 | #ifdef CONFIG_X86_OOSTORE | |
11 | ||
b4af3f7c | 12 | static u32 __cpuinit power2(u32 x) |
1da177e4 | 13 | { |
29a9994b PC |
14 | u32 s = 1; |
15 | while(s <= x) | |
16 | s <<= 1; | |
17 | return s >>= 1; | |
1da177e4 LT |
18 | } |
19 | ||
20 | ||
21 | /* | |
22 | * Set up an actual MCR | |
23 | */ | |
29a9994b | 24 | |
b4af3f7c | 25 | static void __cpuinit centaur_mcr_insert(int reg, u32 base, u32 size, int key) |
1da177e4 LT |
26 | { |
27 | u32 lo, hi; | |
29a9994b | 28 | |
1da177e4 LT |
29 | hi = base & ~0xFFF; |
30 | lo = ~(size-1); /* Size is a power of 2 so this makes a mask */ | |
31 | lo &= ~0xFFF; /* Remove the ctrl value bits */ | |
32 | lo |= key; /* Attribute we wish to set */ | |
33 | wrmsr(reg+MSR_IDT_MCR0, lo, hi); | |
34 | mtrr_centaur_report_mcr(reg, lo, hi); /* Tell the mtrr driver */ | |
35 | } | |
36 | ||
37 | /* | |
38 | * Figure what we can cover with MCR's | |
39 | * | |
40 | * Shortcut: We know you can't put 4Gig of RAM on a winchip | |
41 | */ | |
42 | ||
b4af3f7c | 43 | static u32 __cpuinit ramtop(void) /* 16388 */ |
1da177e4 LT |
44 | { |
45 | int i; | |
46 | u32 top = 0; | |
47 | u32 clip = 0xFFFFFFFFUL; | |
29a9994b | 48 | |
1da177e4 LT |
49 | for (i = 0; i < e820.nr_map; i++) { |
50 | unsigned long start, end; | |
51 | ||
52 | if (e820.map[i].addr > 0xFFFFFFFFUL) | |
53 | continue; | |
54 | /* | |
55 | * Don't MCR over reserved space. Ignore the ISA hole | |
27b46d76 | 56 | * we frob around that catastrophe already |
1da177e4 | 57 | */ |
29a9994b | 58 | |
1da177e4 LT |
59 | if (e820.map[i].type == E820_RESERVED) |
60 | { | |
29a9994b | 61 | if (e820.map[i].addr >= 0x100000UL && e820.map[i].addr < clip) |
1da177e4 LT |
62 | clip = e820.map[i].addr; |
63 | continue; | |
64 | } | |
65 | start = e820.map[i].addr; | |
66 | end = e820.map[i].addr + e820.map[i].size; | |
67 | if (start >= end) | |
68 | continue; | |
69 | if (end > top) | |
70 | top = end; | |
71 | } | |
72 | /* Everything below 'top' should be RAM except for the ISA hole. | |
73 | Because of the limited MCR's we want to map NV/ACPI into our | |
29a9994b PC |
74 | MCR range for gunk in RAM |
75 | ||
1da177e4 LT |
76 | Clip might cause us to MCR insufficient RAM but that is an |
77 | acceptable failure mode and should only bite obscure boxes with | |
78 | a VESA hole at 15Mb | |
29a9994b | 79 | |
1da177e4 LT |
80 | The second case Clip sometimes kicks in is when the EBDA is marked |
81 | as reserved. Again we fail safe with reasonable results | |
82 | */ | |
29a9994b PC |
83 | |
84 | if(top > clip) | |
85 | top = clip; | |
86 | ||
1da177e4 LT |
87 | return top; |
88 | } | |
89 | ||
90 | /* | |
91 | * Compute a set of MCR's to give maximum coverage | |
92 | */ | |
93 | ||
b4af3f7c | 94 | static int __cpuinit centaur_mcr_compute(int nr, int key) |
1da177e4 LT |
95 | { |
96 | u32 mem = ramtop(); | |
97 | u32 root = power2(mem); | |
98 | u32 base = root; | |
99 | u32 top = root; | |
100 | u32 floor = 0; | |
101 | int ct = 0; | |
29a9994b PC |
102 | |
103 | while (ct < nr) | |
1da177e4 LT |
104 | { |
105 | u32 fspace = 0; | |
106 | ||
107 | /* | |
108 | * Find the largest block we will fill going upwards | |
109 | */ | |
110 | ||
29a9994b | 111 | u32 high = power2(mem-top); |
1da177e4 LT |
112 | |
113 | /* | |
114 | * Find the largest block we will fill going downwards | |
115 | */ | |
116 | ||
117 | u32 low = base/2; | |
118 | ||
119 | /* | |
120 | * Don't fill below 1Mb going downwards as there | |
121 | * is an ISA hole in the way. | |
29a9994b PC |
122 | */ |
123 | ||
124 | if (base <= 1024*1024) | |
1da177e4 | 125 | low = 0; |
29a9994b | 126 | |
1da177e4 LT |
127 | /* |
128 | * See how much space we could cover by filling below | |
129 | * the ISA hole | |
130 | */ | |
29a9994b PC |
131 | |
132 | if (floor == 0) | |
1da177e4 | 133 | fspace = 512*1024; |
29a9994b | 134 | else if (floor == 512*1024) |
1da177e4 LT |
135 | fspace = 128*1024; |
136 | ||
137 | /* And forget ROM space */ | |
29a9994b | 138 | |
1da177e4 LT |
139 | /* |
140 | * Now install the largest coverage we get | |
141 | */ | |
29a9994b PC |
142 | |
143 | if (fspace > high && fspace > low) | |
1da177e4 LT |
144 | { |
145 | centaur_mcr_insert(ct, floor, fspace, key); | |
146 | floor += fspace; | |
147 | } | |
29a9994b | 148 | else if (high > low) { |
1da177e4 LT |
149 | centaur_mcr_insert(ct, top, high, key); |
150 | top += high; | |
151 | } | |
29a9994b | 152 | else if (low > 0) { |
1da177e4 LT |
153 | base -= low; |
154 | centaur_mcr_insert(ct, base, low, key); | |
155 | } | |
156 | else break; | |
157 | ct++; | |
158 | } | |
159 | /* | |
160 | * We loaded ct values. We now need to set the mask. The caller | |
161 | * must do this bit. | |
162 | */ | |
29a9994b | 163 | |
1da177e4 LT |
164 | return ct; |
165 | } | |
166 | ||
b4af3f7c | 167 | static void __cpuinit centaur_create_optimal_mcr(void) |
1da177e4 LT |
168 | { |
169 | int i; | |
170 | /* | |
171 | * Allocate up to 6 mcrs to mark as much of ram as possible | |
172 | * as write combining and weak write ordered. | |
173 | * | |
29a9994b | 174 | * To experiment with: Linux never uses stack operations for |
1da177e4 LT |
175 | * mmio spaces so we could globally enable stack operation wc |
176 | * | |
177 | * Load the registers with type 31 - full write combining, all | |
178 | * writes weakly ordered. | |
179 | */ | |
180 | int used = centaur_mcr_compute(6, 31); | |
181 | ||
182 | /* | |
183 | * Wipe unused MCRs | |
184 | */ | |
29a9994b PC |
185 | |
186 | for (i = used; i < 8; i++) | |
1da177e4 LT |
187 | wrmsr(MSR_IDT_MCR0+i, 0, 0); |
188 | } | |
189 | ||
b4af3f7c | 190 | static void __cpuinit winchip2_create_optimal_mcr(void) |
1da177e4 LT |
191 | { |
192 | u32 lo, hi; | |
193 | int i; | |
194 | ||
195 | /* | |
196 | * Allocate up to 6 mcrs to mark as much of ram as possible | |
197 | * as write combining, weak store ordered. | |
198 | * | |
199 | * Load the registers with type 25 | |
200 | * 8 - weak write ordering | |
201 | * 16 - weak read ordering | |
202 | * 1 - write combining | |
203 | */ | |
204 | ||
205 | int used = centaur_mcr_compute(6, 25); | |
29a9994b | 206 | |
1da177e4 LT |
207 | /* |
208 | * Mark the registers we are using. | |
209 | */ | |
29a9994b | 210 | |
1da177e4 | 211 | rdmsr(MSR_IDT_MCR_CTRL, lo, hi); |
29a9994b PC |
212 | for (i = 0; i < used; i++) |
213 | lo |= 1<<(9+i); | |
1da177e4 | 214 | wrmsr(MSR_IDT_MCR_CTRL, lo, hi); |
29a9994b | 215 | |
1da177e4 LT |
216 | /* |
217 | * Wipe unused MCRs | |
218 | */ | |
29a9994b PC |
219 | |
220 | for (i = used; i < 8; i++) | |
1da177e4 LT |
221 | wrmsr(MSR_IDT_MCR0+i, 0, 0); |
222 | } | |
223 | ||
224 | /* | |
225 | * Handle the MCR key on the Winchip 2. | |
226 | */ | |
227 | ||
b4af3f7c | 228 | static void __cpuinit winchip2_unprotect_mcr(void) |
1da177e4 LT |
229 | { |
230 | u32 lo, hi; | |
231 | u32 key; | |
29a9994b | 232 | |
1da177e4 | 233 | rdmsr(MSR_IDT_MCR_CTRL, lo, hi); |
29a9994b | 234 | lo &= ~0x1C0; /* blank bits 8-6 */ |
1da177e4 LT |
235 | key = (lo>>17) & 7; |
236 | lo |= key<<6; /* replace with unlock key */ | |
237 | wrmsr(MSR_IDT_MCR_CTRL, lo, hi); | |
238 | } | |
239 | ||
b4af3f7c | 240 | static void __cpuinit winchip2_protect_mcr(void) |
1da177e4 LT |
241 | { |
242 | u32 lo, hi; | |
29a9994b | 243 | |
1da177e4 | 244 | rdmsr(MSR_IDT_MCR_CTRL, lo, hi); |
29a9994b | 245 | lo &= ~0x1C0; /* blank bits 8-6 */ |
1da177e4 LT |
246 | wrmsr(MSR_IDT_MCR_CTRL, lo, hi); |
247 | } | |
248 | #endif /* CONFIG_X86_OOSTORE */ | |
249 | ||
250 | #define ACE_PRESENT (1 << 6) | |
251 | #define ACE_ENABLED (1 << 7) | |
252 | #define ACE_FCR (1 << 28) /* MSR_VIA_FCR */ | |
253 | ||
254 | #define RNG_PRESENT (1 << 2) | |
255 | #define RNG_ENABLED (1 << 3) | |
256 | #define RNG_ENABLE (1 << 6) /* MSR_VIA_RNG */ | |
257 | ||
b4af3f7c | 258 | static void __cpuinit init_c3(struct cpuinfo_x86 *c) |
1da177e4 LT |
259 | { |
260 | u32 lo, hi; | |
261 | ||
262 | /* Test for Centaur Extended Feature Flags presence */ | |
263 | if (cpuid_eax(0xC0000000) >= 0xC0000001) { | |
264 | u32 tmp = cpuid_edx(0xC0000001); | |
265 | ||
266 | /* enable ACE unit, if present and disabled */ | |
267 | if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) { | |
29a9994b | 268 | rdmsr(MSR_VIA_FCR, lo, hi); |
1da177e4 | 269 | lo |= ACE_FCR; /* enable ACE unit */ |
29a9994b | 270 | wrmsr(MSR_VIA_FCR, lo, hi); |
1da177e4 LT |
271 | printk(KERN_INFO "CPU: Enabled ACE h/w crypto\n"); |
272 | } | |
273 | ||
274 | /* enable RNG unit, if present and disabled */ | |
275 | if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) { | |
29a9994b | 276 | rdmsr(MSR_VIA_RNG, lo, hi); |
1da177e4 | 277 | lo |= RNG_ENABLE; /* enable RNG unit */ |
29a9994b | 278 | wrmsr(MSR_VIA_RNG, lo, hi); |
1da177e4 LT |
279 | printk(KERN_INFO "CPU: Enabled h/w RNG\n"); |
280 | } | |
281 | ||
282 | /* store Centaur Extended Feature Flags as | |
283 | * word 5 of the CPU capability bit array | |
284 | */ | |
285 | c->x86_capability[5] = cpuid_edx(0xC0000001); | |
286 | } | |
287 | ||
27b46d76 | 288 | /* Cyrix III family needs CX8 & PGE explicitly enabled. */ |
29a9994b PC |
289 | if (c->x86_model >= 6 && c->x86_model <= 9) { |
290 | rdmsr(MSR_VIA_FCR, lo, hi); | |
1da177e4 | 291 | lo |= (1<<1 | 1<<7); |
29a9994b | 292 | wrmsr(MSR_VIA_FCR, lo, hi); |
1da177e4 LT |
293 | set_bit(X86_FEATURE_CX8, c->x86_capability); |
294 | } | |
295 | ||
296 | /* Before Nehemiah, the C3's had 3dNOW! */ | |
29a9994b | 297 | if (c->x86_model >= 6 && c->x86_model < 9) |
1da177e4 LT |
298 | set_bit(X86_FEATURE_3DNOW, c->x86_capability); |
299 | ||
300 | get_model_name(c); | |
301 | display_cacheinfo(c); | |
302 | } | |
303 | ||
b4af3f7c | 304 | static void __cpuinit init_centaur(struct cpuinfo_x86 *c) |
1da177e4 LT |
305 | { |
306 | enum { | |
29a9994b PC |
307 | ECX8 = 1<<1, |
308 | EIERRINT = 1<<2, | |
309 | DPM = 1<<3, | |
310 | DMCE = 1<<4, | |
311 | DSTPCLK = 1<<5, | |
312 | ELINEAR = 1<<6, | |
313 | DSMC = 1<<7, | |
314 | DTLOCK = 1<<8, | |
315 | EDCTLB = 1<<8, | |
316 | EMMX = 1<<9, | |
317 | DPDC = 1<<11, | |
318 | EBRPRED = 1<<12, | |
319 | DIC = 1<<13, | |
320 | DDC = 1<<14, | |
321 | DNA = 1<<15, | |
322 | ERETSTK = 1<<16, | |
323 | E2MMX = 1<<19, | |
324 | EAMD3D = 1<<20, | |
1da177e4 LT |
325 | }; |
326 | ||
327 | char *name; | |
29a9994b PC |
328 | u32 fcr_set = 0; |
329 | u32 fcr_clr = 0; | |
330 | u32 lo, hi, newlo; | |
331 | u32 aa, bb, cc, dd; | |
1da177e4 LT |
332 | |
333 | /* Bit 31 in normal CPUID used for nonstandard 3DNow ID; | |
334 | 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */ | |
335 | clear_bit(0*32+31, c->x86_capability); | |
336 | ||
337 | switch (c->x86) { | |
338 | ||
29a9994b PC |
339 | case 5: |
340 | switch (c->x86_model) { | |
1da177e4 | 341 | case 4: |
29a9994b PC |
342 | name = "C6"; |
343 | fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK; | |
344 | fcr_clr = DPDC; | |
1da177e4 LT |
345 | printk(KERN_NOTICE "Disabling bugged TSC.\n"); |
346 | clear_bit(X86_FEATURE_TSC, c->x86_capability); | |
347 | #ifdef CONFIG_X86_OOSTORE | |
348 | centaur_create_optimal_mcr(); | |
349 | /* Enable | |
350 | write combining on non-stack, non-string | |
351 | write combining on string, all types | |
29a9994b PC |
352 | weak write ordering |
353 | ||
354 | The C6 original lacks weak read order | |
355 | ||
1da177e4 | 356 | Note 0x120 is write only on Winchip 1 */ |
29a9994b | 357 | |
1da177e4 | 358 | wrmsr(MSR_IDT_MCR_CTRL, 0x01F0001F, 0); |
29a9994b | 359 | #endif |
1da177e4 LT |
360 | break; |
361 | case 8: | |
29a9994b | 362 | switch (c->x86_mask) { |
1da177e4 | 363 | default: |
29a9994b | 364 | name = "2"; |
1da177e4 LT |
365 | break; |
366 | case 7 ... 9: | |
29a9994b | 367 | name = "2A"; |
1da177e4 LT |
368 | break; |
369 | case 10 ... 15: | |
29a9994b | 370 | name = "2B"; |
1da177e4 LT |
371 | break; |
372 | } | |
29a9994b PC |
373 | fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|E2MMX|EAMD3D; |
374 | fcr_clr = DPDC; | |
1da177e4 LT |
375 | #ifdef CONFIG_X86_OOSTORE |
376 | winchip2_unprotect_mcr(); | |
377 | winchip2_create_optimal_mcr(); | |
378 | rdmsr(MSR_IDT_MCR_CTRL, lo, hi); | |
379 | /* Enable | |
380 | write combining on non-stack, non-string | |
381 | write combining on string, all types | |
29a9994b | 382 | weak write ordering |
1da177e4 | 383 | */ |
29a9994b | 384 | lo |= 31; |
1da177e4 LT |
385 | wrmsr(MSR_IDT_MCR_CTRL, lo, hi); |
386 | winchip2_protect_mcr(); | |
387 | #endif | |
388 | break; | |
389 | case 9: | |
29a9994b PC |
390 | name = "3"; |
391 | fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|E2MMX|EAMD3D; | |
392 | fcr_clr = DPDC; | |
1da177e4 LT |
393 | #ifdef CONFIG_X86_OOSTORE |
394 | winchip2_unprotect_mcr(); | |
395 | winchip2_create_optimal_mcr(); | |
396 | rdmsr(MSR_IDT_MCR_CTRL, lo, hi); | |
397 | /* Enable | |
398 | write combining on non-stack, non-string | |
399 | write combining on string, all types | |
29a9994b | 400 | weak write ordering |
1da177e4 | 401 | */ |
29a9994b | 402 | lo |= 31; |
1da177e4 LT |
403 | wrmsr(MSR_IDT_MCR_CTRL, lo, hi); |
404 | winchip2_protect_mcr(); | |
405 | #endif | |
406 | break; | |
1da177e4 | 407 | default: |
29a9994b | 408 | name = "??"; |
1da177e4 LT |
409 | } |
410 | ||
411 | rdmsr(MSR_IDT_FCR1, lo, hi); | |
29a9994b | 412 | newlo = (lo|fcr_set) & (~fcr_clr); |
1da177e4 | 413 | |
29a9994b PC |
414 | if (newlo != lo) { |
415 | printk(KERN_INFO "Centaur FCR was 0x%X now 0x%X\n", lo, newlo); | |
416 | wrmsr(MSR_IDT_FCR1, newlo, hi); | |
1da177e4 | 417 | } else { |
29a9994b | 418 | printk(KERN_INFO "Centaur FCR is 0x%X\n", lo); |
1da177e4 LT |
419 | } |
420 | /* Emulate MTRRs using Centaur's MCR. */ | |
421 | set_bit(X86_FEATURE_CENTAUR_MCR, c->x86_capability); | |
422 | /* Report CX8 */ | |
423 | set_bit(X86_FEATURE_CX8, c->x86_capability); | |
424 | /* Set 3DNow! on Winchip 2 and above. */ | |
29a9994b | 425 | if (c->x86_model >= 8) |
1da177e4 LT |
426 | set_bit(X86_FEATURE_3DNOW, c->x86_capability); |
427 | /* See if we can find out some more. */ | |
29a9994b | 428 | if (cpuid_eax(0x80000000) >= 0x80000005) { |
1da177e4 | 429 | /* Yes, we can. */ |
29a9994b | 430 | cpuid(0x80000005, &aa, &bb, &cc, &dd); |
1da177e4 LT |
431 | /* Add L1 data and code cache sizes. */ |
432 | c->x86_cache_size = (cc>>24)+(dd>>24); | |
433 | } | |
29a9994b | 434 | sprintf(c->x86_model_id, "WinChip %s", name); |
1da177e4 LT |
435 | break; |
436 | ||
29a9994b | 437 | case 6: |
1da177e4 LT |
438 | init_c3(c); |
439 | break; | |
440 | } | |
441 | } | |
442 | ||
29a9994b | 443 | static unsigned int __cpuinit centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size) |
1da177e4 LT |
444 | { |
445 | /* VIA C3 CPUs (670-68F) need further shifting. */ | |
446 | if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8))) | |
447 | size >>= 8; | |
448 | ||
449 | /* VIA also screwed up Nehemiah stepping 1, and made | |
450 | it return '65KB' instead of '64KB' | |
451 | - Note, it seems this may only be in engineering samples. */ | |
29a9994b PC |
452 | if ((c->x86 == 6) && (c->x86_model == 9) && (c->x86_mask == 1) && (size == 65)) |
453 | size -= 1; | |
1da177e4 LT |
454 | |
455 | return size; | |
456 | } | |
457 | ||
95414930 | 458 | static struct cpu_dev centaur_cpu_dev __cpuinitdata = { |
1da177e4 LT |
459 | .c_vendor = "Centaur", |
460 | .c_ident = { "CentaurHauls" }, | |
461 | .c_init = init_centaur, | |
462 | .c_size_cache = centaur_size_cache, | |
463 | }; | |
464 | ||
03ae5768 | 465 | cpu_vendor_dev_register(X86_VENDOR_CENTAUR, ¢aur_cpu_dev); |