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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
acb04058 PZ |
2 | |
3 | #include <linux/sched.h> | |
e6017571 | 4 | #include <linux/sched/clock.h> |
edc05e6d | 5 | |
cd4d09ec | 6 | #include <asm/cpufeature.h> |
66441bd3 | 7 | #include <asm/e820/api.h> |
52f4a91a | 8 | #include <asm/mtrr.h> |
48f4c485 | 9 | #include <asm/msr.h> |
edc05e6d | 10 | |
1da177e4 LT |
11 | #include "cpu.h" |
12 | ||
1da177e4 LT |
13 | #define ACE_PRESENT (1 << 6) |
14 | #define ACE_ENABLED (1 << 7) | |
15 | #define ACE_FCR (1 << 28) /* MSR_VIA_FCR */ | |
16 | ||
17 | #define RNG_PRESENT (1 << 2) | |
18 | #define RNG_ENABLED (1 << 3) | |
19 | #define RNG_ENABLE (1 << 6) /* MSR_VIA_RNG */ | |
20 | ||
148f9bb8 | 21 | static void init_c3(struct cpuinfo_x86 *c) |
1da177e4 LT |
22 | { |
23 | u32 lo, hi; | |
24 | ||
25 | /* Test for Centaur Extended Feature Flags presence */ | |
26 | if (cpuid_eax(0xC0000000) >= 0xC0000001) { | |
27 | u32 tmp = cpuid_edx(0xC0000001); | |
28 | ||
29 | /* enable ACE unit, if present and disabled */ | |
30 | if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) { | |
29a9994b | 31 | rdmsr(MSR_VIA_FCR, lo, hi); |
1da177e4 | 32 | lo |= ACE_FCR; /* enable ACE unit */ |
29a9994b | 33 | wrmsr(MSR_VIA_FCR, lo, hi); |
1b74dde7 | 34 | pr_info("CPU: Enabled ACE h/w crypto\n"); |
1da177e4 LT |
35 | } |
36 | ||
37 | /* enable RNG unit, if present and disabled */ | |
38 | if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) { | |
29a9994b | 39 | rdmsr(MSR_VIA_RNG, lo, hi); |
1da177e4 | 40 | lo |= RNG_ENABLE; /* enable RNG unit */ |
29a9994b | 41 | wrmsr(MSR_VIA_RNG, lo, hi); |
1b74dde7 | 42 | pr_info("CPU: Enabled h/w RNG\n"); |
1da177e4 LT |
43 | } |
44 | ||
45 | /* store Centaur Extended Feature Flags as | |
46 | * word 5 of the CPU capability bit array | |
47 | */ | |
39c06df4 | 48 | c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001); |
1da177e4 | 49 | } |
48f4c485 | 50 | #ifdef CONFIG_X86_32 |
27b46d76 | 51 | /* Cyrix III family needs CX8 & PGE explicitly enabled. */ |
cb3f718d | 52 | if (c->x86_model >= 6 && c->x86_model <= 13) { |
29a9994b | 53 | rdmsr(MSR_VIA_FCR, lo, hi); |
1da177e4 | 54 | lo |= (1<<1 | 1<<7); |
29a9994b | 55 | wrmsr(MSR_VIA_FCR, lo, hi); |
e1a94a97 | 56 | set_cpu_cap(c, X86_FEATURE_CX8); |
1da177e4 LT |
57 | } |
58 | ||
59 | /* Before Nehemiah, the C3's had 3dNOW! */ | |
29a9994b | 60 | if (c->x86_model >= 6 && c->x86_model < 9) |
e1a94a97 | 61 | set_cpu_cap(c, X86_FEATURE_3DNOW); |
48f4c485 SAS |
62 | #endif |
63 | if (c->x86 == 0x6 && c->x86_model >= 0xf) { | |
64 | c->x86_cache_alignment = c->x86_clflush_size * 2; | |
65 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); | |
66 | } | |
1da177e4 | 67 | |
27c13ece | 68 | cpu_detect_cache_sizes(c); |
1da177e4 LT |
69 | } |
70 | ||
edc05e6d IM |
71 | enum { |
72 | ECX8 = 1<<1, | |
73 | EIERRINT = 1<<2, | |
74 | DPM = 1<<3, | |
75 | DMCE = 1<<4, | |
76 | DSTPCLK = 1<<5, | |
77 | ELINEAR = 1<<6, | |
78 | DSMC = 1<<7, | |
79 | DTLOCK = 1<<8, | |
80 | EDCTLB = 1<<8, | |
81 | EMMX = 1<<9, | |
82 | DPDC = 1<<11, | |
83 | EBRPRED = 1<<12, | |
84 | DIC = 1<<13, | |
85 | DDC = 1<<14, | |
86 | DNA = 1<<15, | |
87 | ERETSTK = 1<<16, | |
88 | E2MMX = 1<<19, | |
89 | EAMD3D = 1<<20, | |
90 | }; | |
91 | ||
148f9bb8 | 92 | static void early_init_centaur(struct cpuinfo_x86 *c) |
5fef55fd YL |
93 | { |
94 | switch (c->x86) { | |
48f4c485 | 95 | #ifdef CONFIG_X86_32 |
5fef55fd YL |
96 | case 5: |
97 | /* Emulate MTRRs using Centaur's MCR. */ | |
98 | set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR); | |
99 | break; | |
48f4c485 SAS |
100 | #endif |
101 | case 6: | |
102 | if (c->x86_model >= 0xf) | |
103 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); | |
104 | break; | |
5fef55fd | 105 | } |
48f4c485 SAS |
106 | #ifdef CONFIG_X86_64 |
107 | set_cpu_cap(c, X86_FEATURE_SYSENTER32); | |
108 | #endif | |
5fef55fd YL |
109 | } |
110 | ||
148f9bb8 | 111 | static void init_centaur(struct cpuinfo_x86 *c) |
1da177e4 | 112 | { |
48f4c485 | 113 | #ifdef CONFIG_X86_32 |
1da177e4 | 114 | char *name; |
29a9994b PC |
115 | u32 fcr_set = 0; |
116 | u32 fcr_clr = 0; | |
117 | u32 lo, hi, newlo; | |
118 | u32 aa, bb, cc, dd; | |
1da177e4 | 119 | |
edc05e6d IM |
120 | /* |
121 | * Bit 31 in normal CPUID used for nonstandard 3DNow ID; | |
122 | * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway | |
123 | */ | |
e1a94a97 | 124 | clear_cpu_cap(c, 0*32+31); |
48f4c485 SAS |
125 | #endif |
126 | early_init_centaur(c); | |
1da177e4 | 127 | switch (c->x86) { |
48f4c485 | 128 | #ifdef CONFIG_X86_32 |
29a9994b | 129 | case 5: |
edc05e6d IM |
130 | switch (c->x86_model) { |
131 | case 4: | |
132 | name = "C6"; | |
133 | fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK; | |
134 | fcr_clr = DPDC; | |
1b74dde7 | 135 | pr_notice("Disabling bugged TSC.\n"); |
e1a94a97 | 136 | clear_cpu_cap(c, X86_FEATURE_TSC); |
edc05e6d IM |
137 | break; |
138 | case 8: | |
139 | switch (c->x86_mask) { | |
140 | default: | |
141 | name = "2"; | |
1da177e4 | 142 | break; |
edc05e6d IM |
143 | case 7 ... 9: |
144 | name = "2A"; | |
145 | break; | |
146 | case 10 ... 15: | |
147 | name = "2B"; | |
148 | break; | |
149 | } | |
150 | fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK| | |
151 | E2MMX|EAMD3D; | |
152 | fcr_clr = DPDC; | |
edc05e6d IM |
153 | break; |
154 | case 9: | |
155 | name = "3"; | |
156 | fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK| | |
157 | E2MMX|EAMD3D; | |
158 | fcr_clr = DPDC; | |
edc05e6d IM |
159 | break; |
160 | default: | |
161 | name = "??"; | |
162 | } | |
1da177e4 | 163 | |
edc05e6d IM |
164 | rdmsr(MSR_IDT_FCR1, lo, hi); |
165 | newlo = (lo|fcr_set) & (~fcr_clr); | |
1da177e4 | 166 | |
edc05e6d | 167 | if (newlo != lo) { |
1b74dde7 | 168 | pr_info("Centaur FCR was 0x%X now 0x%X\n", |
edc05e6d IM |
169 | lo, newlo); |
170 | wrmsr(MSR_IDT_FCR1, newlo, hi); | |
171 | } else { | |
1b74dde7 | 172 | pr_info("Centaur FCR is 0x%X\n", lo); |
edc05e6d IM |
173 | } |
174 | /* Emulate MTRRs using Centaur's MCR. */ | |
e1a94a97 | 175 | set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR); |
edc05e6d | 176 | /* Report CX8 */ |
e1a94a97 | 177 | set_cpu_cap(c, X86_FEATURE_CX8); |
edc05e6d IM |
178 | /* Set 3DNow! on Winchip 2 and above. */ |
179 | if (c->x86_model >= 8) | |
e1a94a97 | 180 | set_cpu_cap(c, X86_FEATURE_3DNOW); |
edc05e6d IM |
181 | /* See if we can find out some more. */ |
182 | if (cpuid_eax(0x80000000) >= 0x80000005) { | |
183 | /* Yes, we can. */ | |
184 | cpuid(0x80000005, &aa, &bb, &cc, &dd); | |
185 | /* Add L1 data and code cache sizes. */ | |
186 | c->x86_cache_size = (cc>>24)+(dd>>24); | |
187 | } | |
188 | sprintf(c->x86_model_id, "WinChip %s", name); | |
189 | break; | |
48f4c485 | 190 | #endif |
29a9994b | 191 | case 6: |
edc05e6d IM |
192 | init_c3(c); |
193 | break; | |
1da177e4 | 194 | } |
48f4c485 SAS |
195 | #ifdef CONFIG_X86_64 |
196 | set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); | |
197 | #endif | |
1da177e4 LT |
198 | } |
199 | ||
09dc68d9 | 200 | #ifdef CONFIG_X86_32 |
148f9bb8 | 201 | static unsigned int |
edc05e6d | 202 | centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size) |
1da177e4 LT |
203 | { |
204 | /* VIA C3 CPUs (670-68F) need further shifting. */ | |
205 | if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8))) | |
206 | size >>= 8; | |
207 | ||
edc05e6d IM |
208 | /* |
209 | * There's also an erratum in Nehemiah stepping 1, which | |
210 | * returns '65KB' instead of '64KB' | |
211 | * - Note, it seems this may only be in engineering samples. | |
212 | */ | |
213 | if ((c->x86 == 6) && (c->x86_model == 9) && | |
214 | (c->x86_mask == 1) && (size == 65)) | |
29a9994b | 215 | size -= 1; |
1da177e4 LT |
216 | return size; |
217 | } | |
09dc68d9 | 218 | #endif |
1da177e4 | 219 | |
148f9bb8 | 220 | static const struct cpu_dev centaur_cpu_dev = { |
1da177e4 LT |
221 | .c_vendor = "Centaur", |
222 | .c_ident = { "CentaurHauls" }, | |
5fef55fd | 223 | .c_early_init = early_init_centaur, |
1da177e4 | 224 | .c_init = init_centaur, |
09dc68d9 JB |
225 | #ifdef CONFIG_X86_32 |
226 | .legacy_cache_size = centaur_size_cache, | |
227 | #endif | |
10a434fc | 228 | .c_x86_vendor = X86_VENDOR_CENTAUR, |
1da177e4 LT |
229 | }; |
230 | ||
10a434fc | 231 | cpu_dev_register(centaur_cpu_dev); |