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1da177e4 LT |
1 | #include <linux/init.h> |
2 | #include <linux/string.h> | |
3 | #include <linux/delay.h> | |
4 | #include <linux/smp.h> | |
5 | #include <linux/module.h> | |
6 | #include <linux/percpu.h> | |
2b932f6c | 7 | #include <linux/bootmem.h> |
1da177e4 LT |
8 | #include <asm/processor.h> |
9 | #include <asm/i387.h> | |
10 | #include <asm/msr.h> | |
11 | #include <asm/io.h> | |
12 | #include <asm/mmu_context.h> | |
27b07da7 | 13 | #include <asm/mtrr.h> |
a03a3e28 | 14 | #include <asm/mce.h> |
8d4a4300 | 15 | #include <asm/pat.h> |
7e00df58 | 16 | #include <asm/asm.h> |
1da177e4 LT |
17 | #ifdef CONFIG_X86_LOCAL_APIC |
18 | #include <asm/mpspec.h> | |
19 | #include <asm/apic.h> | |
20 | #include <mach_apic.h> | |
21 | #endif | |
22 | ||
23 | #include "cpu.h" | |
24 | ||
0a488a53 YL |
25 | static struct cpu_dev *this_cpu __cpuinitdata; |
26 | ||
63cc8c75 | 27 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
6842ef0e GOC |
28 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, |
29 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, | |
30 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, | |
31 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, | |
bf504672 RR |
32 | /* |
33 | * Segments used for calling PnP BIOS have byte granularity. | |
34 | * They code segments and data segments have fixed 64k limits, | |
35 | * the transfer segment sizes are set at run time. | |
36 | */ | |
6842ef0e GOC |
37 | /* 32-bit code */ |
38 | [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, | |
39 | /* 16-bit code */ | |
40 | [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, | |
41 | /* 16-bit data */ | |
42 | [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, | |
43 | /* 16-bit data */ | |
44 | [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, | |
45 | /* 16-bit data */ | |
46 | [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, | |
bf504672 RR |
47 | /* |
48 | * The APM segments have byte granularity and their bases | |
49 | * are set at run time. All have 64k limits. | |
50 | */ | |
6842ef0e GOC |
51 | /* 32-bit code */ |
52 | [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, | |
bf504672 | 53 | /* 16-bit code */ |
6842ef0e GOC |
54 | [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, |
55 | /* data */ | |
56 | [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, | |
bf504672 | 57 | |
6842ef0e GOC |
58 | [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, |
59 | [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } }, | |
7a61d35d JF |
60 | } }; |
61 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); | |
ae1ee11b | 62 | |
3bc9b76b | 63 | static int cachesize_override __cpuinitdata = -1; |
3bc9b76b | 64 | static int disable_x86_serial_nr __cpuinitdata = 1; |
1da177e4 | 65 | |
0a488a53 YL |
66 | static int __init cachesize_setup(char *str) |
67 | { | |
68 | get_option(&str, &cachesize_override); | |
69 | return 1; | |
70 | } | |
71 | __setup("cachesize=", cachesize_setup); | |
72 | ||
73 | /* | |
74 | * Naming convention should be: <Name> [(<Codename>)] | |
75 | * This table only is used unless init_<vendor>() below doesn't set it; | |
76 | * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used | |
77 | * | |
78 | */ | |
79 | ||
80 | /* Look up CPU names by table lookup. */ | |
81 | static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c) | |
82 | { | |
83 | struct cpu_model_info *info; | |
84 | ||
85 | if (c->x86_model >= 16) | |
86 | return NULL; /* Range check */ | |
87 | ||
88 | if (!this_cpu) | |
89 | return NULL; | |
90 | ||
91 | info = this_cpu->c_models; | |
92 | ||
93 | while (info && info->family) { | |
94 | if (info->family == c->x86) | |
95 | return info->model_names[c->x86_model]; | |
96 | info++; | |
97 | } | |
98 | return NULL; /* Not found */ | |
99 | } | |
100 | ||
101 | static int __init x86_fxsr_setup(char *s) | |
102 | { | |
103 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
104 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
105 | return 1; | |
106 | } | |
107 | __setup("nofxsr", x86_fxsr_setup); | |
108 | ||
109 | static int __init x86_sep_setup(char *s) | |
110 | { | |
111 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
112 | return 1; | |
113 | } | |
114 | __setup("nosep", x86_sep_setup); | |
115 | ||
116 | /* Standard macro to see if a specific flag is changeable */ | |
117 | static inline int flag_is_changeable_p(u32 flag) | |
118 | { | |
119 | u32 f1, f2; | |
120 | ||
121 | asm("pushfl\n\t" | |
122 | "pushfl\n\t" | |
123 | "popl %0\n\t" | |
124 | "movl %0,%1\n\t" | |
125 | "xorl %2,%0\n\t" | |
126 | "pushl %0\n\t" | |
127 | "popfl\n\t" | |
128 | "pushfl\n\t" | |
129 | "popl %0\n\t" | |
130 | "popfl\n\t" | |
131 | : "=&r" (f1), "=&r" (f2) | |
132 | : "ir" (flag)); | |
133 | ||
134 | return ((f1^f2) & flag) != 0; | |
135 | } | |
136 | ||
137 | /* Probe for the CPUID instruction */ | |
138 | static int __cpuinit have_cpuid_p(void) | |
139 | { | |
140 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
141 | } | |
142 | ||
143 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
144 | { | |
145 | if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) { | |
146 | /* Disable processor serial number */ | |
147 | unsigned long lo, hi; | |
148 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
149 | lo |= 0x200000; | |
150 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
151 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
152 | clear_cpu_cap(c, X86_FEATURE_PN); | |
153 | ||
154 | /* Disabling the serial number may affect the cpuid level */ | |
155 | c->cpuid_level = cpuid_eax(0); | |
156 | } | |
157 | } | |
158 | ||
159 | static int __init x86_serial_nr_setup(char *s) | |
160 | { | |
161 | disable_x86_serial_nr = 0; | |
162 | return 1; | |
163 | } | |
164 | __setup("serialnumber", x86_serial_nr_setup); | |
165 | ||
7d851c8d AK |
166 | __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; |
167 | ||
9d31d35b YL |
168 | /* Current gdt points %fs at the "master" per-cpu area: after this, |
169 | * it's on the real one. */ | |
170 | void switch_to_new_gdt(void) | |
171 | { | |
172 | struct desc_ptr gdt_descr; | |
173 | ||
174 | gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id()); | |
175 | gdt_descr.size = GDT_SIZE - 1; | |
176 | load_gdt(&gdt_descr); | |
177 | asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory"); | |
178 | } | |
179 | ||
10a434fc | 180 | static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 181 | |
34048c9e | 182 | static void __cpuinit default_init(struct cpuinfo_x86 *c) |
1da177e4 LT |
183 | { |
184 | /* Not much we can do here... */ | |
185 | /* Check if at least it has cpuid */ | |
186 | if (c->cpuid_level == -1) { | |
187 | /* No cpuid. It must be an ancient CPU */ | |
188 | if (c->x86 == 4) | |
189 | strcpy(c->x86_model_id, "486"); | |
190 | else if (c->x86 == 3) | |
191 | strcpy(c->x86_model_id, "386"); | |
192 | } | |
193 | } | |
194 | ||
95414930 | 195 | static struct cpu_dev __cpuinitdata default_cpu = { |
1da177e4 | 196 | .c_init = default_init, |
fe38d855 | 197 | .c_vendor = "Unknown", |
10a434fc | 198 | .c_x86_vendor = X86_VENDOR_UNKNOWN, |
1da177e4 | 199 | }; |
1da177e4 | 200 | |
3bc9b76b | 201 | int __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
202 | { |
203 | unsigned int *v; | |
204 | char *p, *q; | |
205 | ||
3da99c97 | 206 | if (c->extended_cpuid_level < 0x80000004) |
1da177e4 LT |
207 | return 0; |
208 | ||
209 | v = (unsigned int *) c->x86_model_id; | |
210 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
211 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
212 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
213 | c->x86_model_id[48] = 0; | |
214 | ||
215 | /* Intel chips right-justify this string for some dumb reason; | |
216 | undo that brain damage */ | |
217 | p = q = &c->x86_model_id[0]; | |
34048c9e | 218 | while (*p == ' ') |
1da177e4 | 219 | p++; |
34048c9e PC |
220 | if (p != q) { |
221 | while (*p) | |
1da177e4 | 222 | *q++ = *p++; |
34048c9e | 223 | while (q <= &c->x86_model_id[48]) |
1da177e4 LT |
224 | *q++ = '\0'; /* Zero-pad the rest */ |
225 | } | |
226 | ||
227 | return 1; | |
228 | } | |
229 | ||
3bc9b76b | 230 | void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) |
1da177e4 | 231 | { |
9d31d35b | 232 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 233 | |
3da99c97 | 234 | n = c->extended_cpuid_level; |
1da177e4 LT |
235 | |
236 | if (n >= 0x80000005) { | |
9d31d35b | 237 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 238 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", |
9d31d35b YL |
239 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); |
240 | c->x86_cache_size = (ecx>>24) + (edx>>24); | |
1da177e4 LT |
241 | } |
242 | ||
243 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
244 | return; | |
245 | ||
0a488a53 | 246 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 247 | l2size = ecx >> 16; |
34048c9e | 248 | |
1da177e4 LT |
249 | /* do processor-specific cache resizing */ |
250 | if (this_cpu->c_size_cache) | |
34048c9e | 251 | l2size = this_cpu->c_size_cache(c, l2size); |
1da177e4 LT |
252 | |
253 | /* Allow user to override all this if necessary. */ | |
254 | if (cachesize_override != -1) | |
255 | l2size = cachesize_override; | |
256 | ||
34048c9e | 257 | if (l2size == 0) |
1da177e4 LT |
258 | return; /* Again, no L2 cache is possible */ |
259 | ||
260 | c->x86_cache_size = l2size; | |
261 | ||
262 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
0a488a53 | 263 | l2size, ecx & 0xFF); |
1da177e4 LT |
264 | } |
265 | ||
9d31d35b YL |
266 | #ifdef CONFIG_X86_HT |
267 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) | |
1da177e4 | 268 | { |
0a488a53 YL |
269 | u32 eax, ebx, ecx, edx; |
270 | int index_msb, core_bits; | |
1da177e4 | 271 | |
0a488a53 | 272 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 273 | return; |
1da177e4 | 274 | |
0a488a53 YL |
275 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
276 | goto out; | |
1da177e4 | 277 | |
0a488a53 | 278 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 279 | |
9d31d35b YL |
280 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
281 | ||
282 | if (smp_num_siblings == 1) { | |
283 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
284 | } else if (smp_num_siblings > 1) { | |
285 | ||
286 | if (smp_num_siblings > NR_CPUS) { | |
287 | printk(KERN_WARNING "CPU: Unsupported number of siblings %d", | |
288 | smp_num_siblings); | |
289 | smp_num_siblings = 1; | |
290 | return; | |
291 | } | |
292 | ||
293 | index_msb = get_count_order(smp_num_siblings); | |
294 | c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb); | |
295 | ||
9d31d35b YL |
296 | |
297 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; | |
298 | ||
299 | index_msb = get_count_order(smp_num_siblings); | |
300 | ||
301 | core_bits = get_count_order(c->x86_max_cores); | |
302 | ||
303 | c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) & | |
304 | ((1 << core_bits) - 1); | |
1da177e4 | 305 | } |
1da177e4 | 306 | |
0a488a53 YL |
307 | out: |
308 | if ((c->x86_max_cores * smp_num_siblings) > 1) { | |
309 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
310 | c->phys_proc_id); | |
311 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
312 | c->cpu_core_id); | |
9d31d35b YL |
313 | } |
314 | } | |
315 | #endif | |
1da177e4 | 316 | |
3da99c97 | 317 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
318 | { |
319 | char *v = c->x86_vendor_id; | |
320 | int i; | |
fe38d855 | 321 | static int printed; |
1da177e4 LT |
322 | |
323 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
324 | if (!cpu_devs[i]) |
325 | break; | |
326 | ||
327 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
328 | (cpu_devs[i]->c_ident[1] && | |
329 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
330 | this_cpu = cpu_devs[i]; | |
331 | c->x86_vendor = this_cpu->c_x86_vendor; | |
332 | return; | |
1da177e4 LT |
333 | } |
334 | } | |
10a434fc | 335 | |
fe38d855 CE |
336 | if (!printed) { |
337 | printed++; | |
338 | printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n"); | |
339 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); | |
340 | } | |
10a434fc | 341 | |
fe38d855 CE |
342 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
343 | this_cpu = &default_cpu; | |
1da177e4 LT |
344 | } |
345 | ||
9d31d35b | 346 | void __cpuinit cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 347 | { |
1da177e4 | 348 | /* Get vendor name */ |
4a148513 HH |
349 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
350 | (unsigned int *)&c->x86_vendor_id[0], | |
351 | (unsigned int *)&c->x86_vendor_id[8], | |
352 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 353 | |
1da177e4 | 354 | c->x86 = 4; |
9d31d35b | 355 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
356 | if (c->cpuid_level >= 0x00000001) { |
357 | u32 junk, tfms, cap0, misc; | |
358 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
9d31d35b YL |
359 | c->x86 = (tfms >> 8) & 0xf; |
360 | c->x86_model = (tfms >> 4) & 0xf; | |
361 | c->x86_mask = tfms & 0xf; | |
f5f786d0 | 362 | if (c->x86 == 0xf) |
1da177e4 | 363 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 364 | if (c->x86 >= 0x6) |
9d31d35b | 365 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
d4387bd3 | 366 | if (cap0 & (1<<19)) { |
d4387bd3 | 367 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 368 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 369 | } |
1da177e4 | 370 | } |
1da177e4 | 371 | } |
3da99c97 YL |
372 | |
373 | static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) | |
093af8d7 YL |
374 | { |
375 | u32 tfms, xlvl; | |
3da99c97 | 376 | u32 ebx; |
093af8d7 | 377 | |
3da99c97 YL |
378 | /* Intel-defined flags: level 0x00000001 */ |
379 | if (c->cpuid_level >= 0x00000001) { | |
380 | u32 capability, excap; | |
381 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); | |
382 | c->x86_capability[0] = capability; | |
383 | c->x86_capability[4] = excap; | |
384 | } | |
093af8d7 | 385 | |
3da99c97 YL |
386 | /* AMD-defined flags: level 0x80000001 */ |
387 | xlvl = cpuid_eax(0x80000000); | |
388 | c->extended_cpuid_level = xlvl; | |
389 | if ((xlvl & 0xffff0000) == 0x80000000) { | |
390 | if (xlvl >= 0x80000001) { | |
391 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
392 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 393 | } |
093af8d7 | 394 | } |
093af8d7 | 395 | } |
34048c9e PC |
396 | /* |
397 | * Do minimum CPU detection early. | |
398 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
399 | * cache alignment. | |
400 | * The others are not touched to avoid unwanted side effects. | |
401 | * | |
402 | * WARNING: this function is only called on the BP. Don't add code here | |
403 | * that is supposed to run on all CPUs. | |
404 | */ | |
3da99c97 | 405 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 406 | { |
d4387bd3 | 407 | c->x86_clflush_size = 32; |
0a488a53 | 408 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 RR |
409 | |
410 | if (!have_cpuid_p()) | |
411 | return; | |
412 | ||
3da99c97 YL |
413 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
414 | ||
0a488a53 YL |
415 | c->extended_cpuid_level = 0; |
416 | ||
d7cd5611 RR |
417 | cpu_detect(c); |
418 | ||
3da99c97 | 419 | get_cpu_vendor(c); |
2b16a235 | 420 | |
3da99c97 | 421 | get_cpu_cap(c); |
2b16a235 | 422 | |
10a434fc YL |
423 | if (this_cpu->c_early_init) |
424 | this_cpu->c_early_init(c); | |
093af8d7 | 425 | |
3da99c97 | 426 | validate_pat_support(c); |
d7cd5611 RR |
427 | } |
428 | ||
9d31d35b YL |
429 | void __init early_cpu_init(void) |
430 | { | |
10a434fc YL |
431 | struct cpu_dev **cdev; |
432 | int count = 0; | |
433 | ||
434 | printk("KERNEL supported cpus:\n"); | |
435 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { | |
436 | struct cpu_dev *cpudev = *cdev; | |
437 | unsigned int j; | |
9d31d35b | 438 | |
10a434fc YL |
439 | if (count >= X86_VENDOR_NUM) |
440 | break; | |
441 | cpu_devs[count] = cpudev; | |
442 | count++; | |
443 | ||
444 | for (j = 0; j < 2; j++) { | |
445 | if (!cpudev->c_ident[j]) | |
446 | continue; | |
447 | printk(" %s %s\n", cpudev->c_vendor, | |
448 | cpudev->c_ident[j]); | |
449 | } | |
450 | } | |
9d31d35b | 451 | |
9d31d35b | 452 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 RR |
453 | } |
454 | ||
7e00df58 PA |
455 | /* |
456 | * The NOPL instruction is supposed to exist on all CPUs with | |
457 | * family >= 6, unfortunately, that's not true in practice because | |
458 | * of early VIA chips and (more importantly) broken virtualizers that | |
459 | * are not easy to detect. Hence, probe for it based on first | |
460 | * principles. | |
461 | */ | |
462 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
463 | { | |
464 | const u32 nopl_signature = 0x888c53b1; /* Random number */ | |
465 | u32 has_nopl = nopl_signature; | |
466 | ||
467 | clear_cpu_cap(c, X86_FEATURE_NOPL); | |
468 | if (c->x86 >= 6) { | |
469 | asm volatile("\n" | |
470 | "1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */ | |
471 | "2:\n" | |
472 | " .section .fixup,\"ax\"\n" | |
473 | "3: xor %0,%0\n" | |
474 | " jmp 2b\n" | |
475 | " .previous\n" | |
476 | _ASM_EXTABLE(1b,3b) | |
477 | : "+a" (has_nopl)); | |
478 | ||
479 | if (has_nopl == nopl_signature) | |
480 | set_cpu_cap(c, X86_FEATURE_NOPL); | |
481 | } | |
482 | } | |
483 | ||
34048c9e | 484 | static void __cpuinit generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 485 | { |
3da99c97 YL |
486 | if (!have_cpuid_p()) |
487 | return; | |
1da177e4 | 488 | |
3da99c97 | 489 | c->extended_cpuid_level = 0; |
1d67953f | 490 | |
3da99c97 | 491 | cpu_detect(c); |
1da177e4 | 492 | |
3da99c97 | 493 | get_cpu_vendor(c); |
1da177e4 | 494 | |
3da99c97 | 495 | get_cpu_cap(c); |
1da177e4 | 496 | |
3da99c97 YL |
497 | if (c->cpuid_level >= 0x00000001) { |
498 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
96c52749 | 499 | #ifdef CONFIG_X86_HT |
3da99c97 YL |
500 | c->apicid = phys_pkg_id(c->initial_apicid, 0); |
501 | c->phys_proc_id = c->initial_apicid; | |
1e9f28fa | 502 | #else |
3da99c97 | 503 | c->apicid = c->initial_apicid; |
1e9f28fa | 504 | #endif |
3da99c97 | 505 | } |
1da177e4 | 506 | |
3da99c97 YL |
507 | if (c->extended_cpuid_level >= 0x80000004) |
508 | get_model_name(c); /* Default name */ | |
1da177e4 | 509 | |
3da99c97 YL |
510 | init_scattered_cpuid_features(c); |
511 | detect_nopl(c); | |
1da177e4 | 512 | } |
1da177e4 LT |
513 | |
514 | /* | |
515 | * This does the hard work of actually picking apart the CPU stuff... | |
516 | */ | |
9a250347 | 517 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
518 | { |
519 | int i; | |
520 | ||
521 | c->loops_per_jiffy = loops_per_jiffy; | |
522 | c->x86_cache_size = -1; | |
523 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
524 | c->cpuid_level = -1; /* CPUID not detected */ | |
525 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ | |
526 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
527 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 528 | c->x86_max_cores = 1; |
770d132f | 529 | c->x86_clflush_size = 32; |
1da177e4 LT |
530 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
531 | ||
532 | if (!have_cpuid_p()) { | |
34048c9e PC |
533 | /* |
534 | * First of all, decide if this is a 486 or higher | |
535 | * It's a 486 if we can modify the AC flag | |
536 | */ | |
537 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
1da177e4 LT |
538 | c->x86 = 4; |
539 | else | |
540 | c->x86 = 3; | |
541 | } | |
542 | ||
543 | generic_identify(c); | |
544 | ||
3898534d | 545 | if (this_cpu->c_identify) |
1da177e4 LT |
546 | this_cpu->c_identify(c); |
547 | ||
1da177e4 LT |
548 | /* |
549 | * Vendor-specific initialization. In this section we | |
550 | * canonicalize the feature flags, meaning if there are | |
551 | * features a certain CPU supports which CPUID doesn't | |
552 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
553 | * we handle them here. | |
554 | * | |
555 | * At the end of this section, c->x86_capability better | |
556 | * indicate the features this CPU genuinely supports! | |
557 | */ | |
558 | if (this_cpu->c_init) | |
559 | this_cpu->c_init(c); | |
560 | ||
561 | /* Disable the PN if appropriate */ | |
562 | squash_the_stupid_serial_number(c); | |
563 | ||
564 | /* | |
565 | * The vendor-specific functions might have changed features. Now | |
566 | * we do "generic changes." | |
567 | */ | |
568 | ||
1da177e4 | 569 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 570 | if (!c->x86_model_id[0]) { |
1da177e4 LT |
571 | char *p; |
572 | p = table_lookup_model(c); | |
34048c9e | 573 | if (p) |
1da177e4 LT |
574 | strcpy(c->x86_model_id, p); |
575 | else | |
576 | /* Last resort... */ | |
577 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 578 | c->x86, c->x86_model); |
1da177e4 LT |
579 | } |
580 | ||
1da177e4 LT |
581 | /* |
582 | * On SMP, boot_cpu_data holds the common feature set between | |
583 | * all CPUs; so make sure that we indicate which features are | |
584 | * common between the CPUs. The first time this routine gets | |
585 | * executed, c == &boot_cpu_data. | |
586 | */ | |
34048c9e | 587 | if (c != &boot_cpu_data) { |
1da177e4 | 588 | /* AND the already accumulated flags with these */ |
9d31d35b | 589 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 LT |
590 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
591 | } | |
592 | ||
7d851c8d AK |
593 | /* Clear all flags overriden by options */ |
594 | for (i = 0; i < NCAPINTS; i++) | |
12c247a6 | 595 | c->x86_capability[i] &= ~cleared_cpu_caps[i]; |
7d851c8d | 596 | |
1da177e4 | 597 | /* Init Machine Check Exception if available. */ |
1da177e4 | 598 | mcheck_init(c); |
30d432df AK |
599 | |
600 | select_idle_routine(c); | |
a6c4e076 | 601 | } |
31ab269a | 602 | |
a6c4e076 JF |
603 | void __init identify_boot_cpu(void) |
604 | { | |
605 | identify_cpu(&boot_cpu_data); | |
606 | sysenter_setup(); | |
6fe940d6 | 607 | enable_sep_cpu(); |
a6c4e076 | 608 | } |
3b520b23 | 609 | |
a6c4e076 JF |
610 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) |
611 | { | |
612 | BUG_ON(c == &boot_cpu_data); | |
613 | identify_cpu(c); | |
614 | enable_sep_cpu(); | |
615 | mtrr_ap_init(); | |
1da177e4 LT |
616 | } |
617 | ||
a0854a46 YL |
618 | struct msr_range { |
619 | unsigned min; | |
620 | unsigned max; | |
621 | }; | |
1da177e4 | 622 | |
a0854a46 YL |
623 | static struct msr_range msr_range_array[] __cpuinitdata = { |
624 | { 0x00000000, 0x00000418}, | |
625 | { 0xc0000000, 0xc000040b}, | |
626 | { 0xc0010000, 0xc0010142}, | |
627 | { 0xc0011000, 0xc001103b}, | |
628 | }; | |
1da177e4 | 629 | |
a0854a46 YL |
630 | static void __cpuinit print_cpu_msr(void) |
631 | { | |
632 | unsigned index; | |
633 | u64 val; | |
634 | int i; | |
635 | unsigned index_min, index_max; | |
636 | ||
637 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
638 | index_min = msr_range_array[i].min; | |
639 | index_max = msr_range_array[i].max; | |
640 | for (index = index_min; index < index_max; index++) { | |
641 | if (rdmsrl_amd_safe(index, &val)) | |
642 | continue; | |
643 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1da177e4 | 644 | } |
a0854a46 YL |
645 | } |
646 | } | |
94605eff | 647 | |
a0854a46 YL |
648 | static int show_msr __cpuinitdata; |
649 | static __init int setup_show_msr(char *arg) | |
650 | { | |
651 | int num; | |
3dd9d514 | 652 | |
a0854a46 | 653 | get_option(&arg, &num); |
3dd9d514 | 654 | |
a0854a46 YL |
655 | if (num > 0) |
656 | show_msr = num; | |
657 | return 1; | |
1da177e4 | 658 | } |
a0854a46 | 659 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 660 | |
191679fd AK |
661 | static __init int setup_noclflush(char *arg) |
662 | { | |
663 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
664 | return 1; | |
665 | } | |
666 | __setup("noclflush", setup_noclflush); | |
667 | ||
3bc9b76b | 668 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 LT |
669 | { |
670 | char *vendor = NULL; | |
671 | ||
672 | if (c->x86_vendor < X86_VENDOR_NUM) | |
673 | vendor = this_cpu->c_vendor; | |
674 | else if (c->cpuid_level >= 0) | |
675 | vendor = c->x86_vendor_id; | |
676 | ||
677 | if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor))) | |
9d31d35b | 678 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 679 | |
9d31d35b YL |
680 | if (c->x86_model_id[0]) |
681 | printk(KERN_CONT "%s", c->x86_model_id); | |
1da177e4 | 682 | else |
9d31d35b | 683 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 684 | |
34048c9e | 685 | if (c->x86_mask || c->cpuid_level >= 0) |
9d31d35b | 686 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); |
1da177e4 | 687 | else |
9d31d35b | 688 | printk(KERN_CONT "\n"); |
a0854a46 YL |
689 | |
690 | #ifdef CONFIG_SMP | |
691 | if (c->cpu_index < show_msr) | |
692 | print_cpu_msr(); | |
693 | #else | |
694 | if (show_msr) | |
695 | print_cpu_msr(); | |
696 | #endif | |
1da177e4 LT |
697 | } |
698 | ||
ac72e788 AK |
699 | static __init int setup_disablecpuid(char *arg) |
700 | { | |
701 | int bit; | |
702 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) | |
703 | setup_clear_cpu_cap(bit); | |
704 | else | |
705 | return 0; | |
706 | return 1; | |
707 | } | |
708 | __setup("clearcpuid=", setup_disablecpuid); | |
709 | ||
3bc9b76b | 710 | cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE; |
1da177e4 | 711 | |
7c3576d2 | 712 | /* Make sure %fs is initialized properly in idle threads */ |
6b2fb3c6 | 713 | struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) |
f95d47ca JF |
714 | { |
715 | memset(regs, 0, sizeof(struct pt_regs)); | |
65ea5b03 | 716 | regs->fs = __KERNEL_PERCPU; |
f95d47ca JF |
717 | return regs; |
718 | } | |
719 | ||
d2cbcc49 RR |
720 | /* |
721 | * cpu_init() initializes state that is per-CPU. Some data is already | |
722 | * initialized (naturally) in the bootstrap process, such as the GDT | |
723 | * and IDT. We reload them nevertheless, this function acts as a | |
724 | * 'CPU state barrier', nothing should get across. | |
725 | */ | |
726 | void __cpuinit cpu_init(void) | |
9ee79a3d | 727 | { |
d2cbcc49 RR |
728 | int cpu = smp_processor_id(); |
729 | struct task_struct *curr = current; | |
34048c9e | 730 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 731 | struct thread_struct *thread = &curr->thread; |
62111195 JF |
732 | |
733 | if (cpu_test_and_set(cpu, cpu_initialized)) { | |
734 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); | |
735 | for (;;) local_irq_enable(); | |
736 | } | |
737 | ||
738 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
739 | ||
740 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
741 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 742 | |
4d37e7e3 | 743 | load_idt(&idt_descr); |
c5413fbe | 744 | switch_to_new_gdt(); |
1da177e4 | 745 | |
1da177e4 LT |
746 | /* |
747 | * Set up and load the per-CPU TSS and LDT | |
748 | */ | |
749 | atomic_inc(&init_mm.mm_count); | |
62111195 JF |
750 | curr->active_mm = &init_mm; |
751 | if (curr->mm) | |
752 | BUG(); | |
753 | enter_lazy_tlb(&init_mm, curr); | |
1da177e4 | 754 | |
faca6227 | 755 | load_sp0(t, thread); |
34048c9e | 756 | set_tss_desc(cpu, t); |
1da177e4 LT |
757 | load_TR_desc(); |
758 | load_LDT(&init_mm.context); | |
759 | ||
22c4e308 | 760 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
761 | /* Set up doublefault TSS pointer in the GDT */ |
762 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 763 | #endif |
1da177e4 | 764 | |
464d1a78 JF |
765 | /* Clear %gs. */ |
766 | asm volatile ("mov %0, %%gs" : : "r" (0)); | |
1da177e4 LT |
767 | |
768 | /* Clear all 6 debug registers: */ | |
4bb0d3ec ZA |
769 | set_debugreg(0, 0); |
770 | set_debugreg(0, 1); | |
771 | set_debugreg(0, 2); | |
772 | set_debugreg(0, 3); | |
773 | set_debugreg(0, 6); | |
774 | set_debugreg(0, 7); | |
1da177e4 LT |
775 | |
776 | /* | |
777 | * Force FPU initialization: | |
778 | */ | |
b359e8a4 SS |
779 | if (cpu_has_xsave) |
780 | current_thread_info()->status = TS_XSAVE; | |
781 | else | |
782 | current_thread_info()->status = 0; | |
1da177e4 LT |
783 | clear_used_math(); |
784 | mxcsr_feature_mask_init(); | |
dc1e35c6 SS |
785 | |
786 | /* | |
787 | * Boot processor to setup the FP and extended state context info. | |
788 | */ | |
789 | if (!smp_processor_id()) | |
790 | init_thread_xstate(); | |
791 | ||
792 | xsave_init(); | |
1da177e4 | 793 | } |
e1367daf LS |
794 | |
795 | #ifdef CONFIG_HOTPLUG_CPU | |
3bc9b76b | 796 | void __cpuinit cpu_uninit(void) |
e1367daf LS |
797 | { |
798 | int cpu = raw_smp_processor_id(); | |
799 | cpu_clear(cpu, cpu_initialized); | |
800 | ||
801 | /* lazy TLB state */ | |
802 | per_cpu(cpu_tlbstate, cpu).state = 0; | |
803 | per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm; | |
804 | } | |
805 | #endif |