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1da177e4 | 1 | #include <linux/init.h> |
f0fc4aff YL |
2 | #include <linux/kernel.h> |
3 | #include <linux/sched.h> | |
1da177e4 | 4 | #include <linux/string.h> |
f0fc4aff YL |
5 | #include <linux/bootmem.h> |
6 | #include <linux/bitops.h> | |
7 | #include <linux/module.h> | |
8 | #include <linux/kgdb.h> | |
9 | #include <linux/topology.h> | |
1da177e4 LT |
10 | #include <linux/delay.h> |
11 | #include <linux/smp.h> | |
1da177e4 | 12 | #include <linux/percpu.h> |
1da177e4 LT |
13 | #include <asm/i387.h> |
14 | #include <asm/msr.h> | |
15 | #include <asm/io.h> | |
f0fc4aff | 16 | #include <asm/linkage.h> |
1da177e4 | 17 | #include <asm/mmu_context.h> |
27b07da7 | 18 | #include <asm/mtrr.h> |
a03a3e28 | 19 | #include <asm/mce.h> |
8d4a4300 | 20 | #include <asm/pat.h> |
7e00df58 | 21 | #include <asm/asm.h> |
f0fc4aff | 22 | #include <asm/numa.h> |
1da177e4 LT |
23 | #ifdef CONFIG_X86_LOCAL_APIC |
24 | #include <asm/mpspec.h> | |
25 | #include <asm/apic.h> | |
26 | #include <mach_apic.h> | |
f0fc4aff | 27 | #include <asm/genapic.h> |
1da177e4 LT |
28 | #endif |
29 | ||
f0fc4aff YL |
30 | #include <asm/pda.h> |
31 | #include <asm/pgtable.h> | |
32 | #include <asm/processor.h> | |
33 | #include <asm/desc.h> | |
34 | #include <asm/atomic.h> | |
35 | #include <asm/proto.h> | |
36 | #include <asm/sections.h> | |
37 | #include <asm/setup.h> | |
38 | ||
1da177e4 LT |
39 | #include "cpu.h" |
40 | ||
0a488a53 YL |
41 | static struct cpu_dev *this_cpu __cpuinitdata; |
42 | ||
950ad7ff YL |
43 | #ifdef CONFIG_X86_64 |
44 | /* We need valid kernel segments for data and code in long mode too | |
45 | * IRET will check the segment types kkeil 2000/10/28 | |
46 | * Also sysret mandates a special GDT layout | |
47 | */ | |
48 | /* The TLS descriptors are currently at a different place compared to i386. | |
49 | Hopefully nobody expects them at a fixed place (Wine?) */ | |
50 | DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = { | |
51 | [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } }, | |
52 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } }, | |
53 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } }, | |
54 | [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } }, | |
55 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } }, | |
56 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } }, | |
57 | } }; | |
58 | #else | |
63cc8c75 | 59 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
6842ef0e GOC |
60 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, |
61 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, | |
62 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, | |
63 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, | |
bf504672 RR |
64 | /* |
65 | * Segments used for calling PnP BIOS have byte granularity. | |
66 | * They code segments and data segments have fixed 64k limits, | |
67 | * the transfer segment sizes are set at run time. | |
68 | */ | |
6842ef0e GOC |
69 | /* 32-bit code */ |
70 | [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, | |
71 | /* 16-bit code */ | |
72 | [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, | |
73 | /* 16-bit data */ | |
74 | [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, | |
75 | /* 16-bit data */ | |
76 | [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, | |
77 | /* 16-bit data */ | |
78 | [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, | |
bf504672 RR |
79 | /* |
80 | * The APM segments have byte granularity and their bases | |
81 | * are set at run time. All have 64k limits. | |
82 | */ | |
6842ef0e GOC |
83 | /* 32-bit code */ |
84 | [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, | |
bf504672 | 85 | /* 16-bit code */ |
6842ef0e GOC |
86 | [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, |
87 | /* data */ | |
88 | [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, | |
bf504672 | 89 | |
6842ef0e GOC |
90 | [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, |
91 | [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } }, | |
7a61d35d | 92 | } }; |
950ad7ff | 93 | #endif |
7a61d35d | 94 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 95 | |
ba51dced | 96 | #ifdef CONFIG_X86_32 |
3bc9b76b | 97 | static int cachesize_override __cpuinitdata = -1; |
3bc9b76b | 98 | static int disable_x86_serial_nr __cpuinitdata = 1; |
1da177e4 | 99 | |
0a488a53 YL |
100 | static int __init cachesize_setup(char *str) |
101 | { | |
102 | get_option(&str, &cachesize_override); | |
103 | return 1; | |
104 | } | |
105 | __setup("cachesize=", cachesize_setup); | |
106 | ||
107 | /* | |
108 | * Naming convention should be: <Name> [(<Codename>)] | |
109 | * This table only is used unless init_<vendor>() below doesn't set it; | |
110 | * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used | |
111 | * | |
112 | */ | |
113 | ||
114 | /* Look up CPU names by table lookup. */ | |
115 | static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c) | |
116 | { | |
117 | struct cpu_model_info *info; | |
118 | ||
119 | if (c->x86_model >= 16) | |
120 | return NULL; /* Range check */ | |
121 | ||
122 | if (!this_cpu) | |
123 | return NULL; | |
124 | ||
125 | info = this_cpu->c_models; | |
126 | ||
127 | while (info && info->family) { | |
128 | if (info->family == c->x86) | |
129 | return info->model_names[c->x86_model]; | |
130 | info++; | |
131 | } | |
132 | return NULL; /* Not found */ | |
133 | } | |
134 | ||
135 | static int __init x86_fxsr_setup(char *s) | |
136 | { | |
137 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
138 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
139 | return 1; | |
140 | } | |
141 | __setup("nofxsr", x86_fxsr_setup); | |
142 | ||
143 | static int __init x86_sep_setup(char *s) | |
144 | { | |
145 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
146 | return 1; | |
147 | } | |
148 | __setup("nosep", x86_sep_setup); | |
149 | ||
150 | /* Standard macro to see if a specific flag is changeable */ | |
151 | static inline int flag_is_changeable_p(u32 flag) | |
152 | { | |
153 | u32 f1, f2; | |
154 | ||
155 | asm("pushfl\n\t" | |
156 | "pushfl\n\t" | |
157 | "popl %0\n\t" | |
158 | "movl %0,%1\n\t" | |
159 | "xorl %2,%0\n\t" | |
160 | "pushl %0\n\t" | |
161 | "popfl\n\t" | |
162 | "pushfl\n\t" | |
163 | "popl %0\n\t" | |
164 | "popfl\n\t" | |
165 | : "=&r" (f1), "=&r" (f2) | |
166 | : "ir" (flag)); | |
167 | ||
168 | return ((f1^f2) & flag) != 0; | |
169 | } | |
170 | ||
171 | /* Probe for the CPUID instruction */ | |
172 | static int __cpuinit have_cpuid_p(void) | |
173 | { | |
174 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
175 | } | |
176 | ||
177 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
178 | { | |
179 | if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) { | |
180 | /* Disable processor serial number */ | |
181 | unsigned long lo, hi; | |
182 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
183 | lo |= 0x200000; | |
184 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
185 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
186 | clear_cpu_cap(c, X86_FEATURE_PN); | |
187 | ||
188 | /* Disabling the serial number may affect the cpuid level */ | |
189 | c->cpuid_level = cpuid_eax(0); | |
190 | } | |
191 | } | |
192 | ||
193 | static int __init x86_serial_nr_setup(char *s) | |
194 | { | |
195 | disable_x86_serial_nr = 0; | |
196 | return 1; | |
197 | } | |
198 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced YL |
199 | #else |
200 | /* Probe for the CPUID instruction */ | |
201 | static inline int have_cpuid_p(void) | |
202 | { | |
203 | return 1; | |
204 | } | |
205 | #endif | |
0a488a53 | 206 | |
7d851c8d AK |
207 | __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; |
208 | ||
9d31d35b YL |
209 | /* Current gdt points %fs at the "master" per-cpu area: after this, |
210 | * it's on the real one. */ | |
211 | void switch_to_new_gdt(void) | |
212 | { | |
213 | struct desc_ptr gdt_descr; | |
214 | ||
215 | gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id()); | |
216 | gdt_descr.size = GDT_SIZE - 1; | |
217 | load_gdt(&gdt_descr); | |
fab334c1 | 218 | #ifdef CONFIG_X86_32 |
9d31d35b | 219 | asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory"); |
fab334c1 | 220 | #endif |
9d31d35b YL |
221 | } |
222 | ||
10a434fc | 223 | static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 224 | |
34048c9e | 225 | static void __cpuinit default_init(struct cpuinfo_x86 *c) |
1da177e4 | 226 | { |
b9e67f00 YL |
227 | #ifdef CONFIG_X86_64 |
228 | display_cacheinfo(c); | |
229 | #else | |
1da177e4 LT |
230 | /* Not much we can do here... */ |
231 | /* Check if at least it has cpuid */ | |
232 | if (c->cpuid_level == -1) { | |
233 | /* No cpuid. It must be an ancient CPU */ | |
234 | if (c->x86 == 4) | |
235 | strcpy(c->x86_model_id, "486"); | |
236 | else if (c->x86 == 3) | |
237 | strcpy(c->x86_model_id, "386"); | |
238 | } | |
b9e67f00 | 239 | #endif |
1da177e4 LT |
240 | } |
241 | ||
95414930 | 242 | static struct cpu_dev __cpuinitdata default_cpu = { |
1da177e4 | 243 | .c_init = default_init, |
fe38d855 | 244 | .c_vendor = "Unknown", |
10a434fc | 245 | .c_x86_vendor = X86_VENDOR_UNKNOWN, |
1da177e4 | 246 | }; |
1da177e4 | 247 | |
3bc9b76b | 248 | int __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
249 | { |
250 | unsigned int *v; | |
251 | char *p, *q; | |
252 | ||
3da99c97 | 253 | if (c->extended_cpuid_level < 0x80000004) |
1da177e4 LT |
254 | return 0; |
255 | ||
256 | v = (unsigned int *) c->x86_model_id; | |
257 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
258 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
259 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
260 | c->x86_model_id[48] = 0; | |
261 | ||
262 | /* Intel chips right-justify this string for some dumb reason; | |
263 | undo that brain damage */ | |
264 | p = q = &c->x86_model_id[0]; | |
34048c9e | 265 | while (*p == ' ') |
1da177e4 | 266 | p++; |
34048c9e PC |
267 | if (p != q) { |
268 | while (*p) | |
1da177e4 | 269 | *q++ = *p++; |
34048c9e | 270 | while (q <= &c->x86_model_id[48]) |
1da177e4 LT |
271 | *q++ = '\0'; /* Zero-pad the rest */ |
272 | } | |
273 | ||
274 | return 1; | |
275 | } | |
276 | ||
3bc9b76b | 277 | void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) |
1da177e4 | 278 | { |
9d31d35b | 279 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 280 | |
3da99c97 | 281 | n = c->extended_cpuid_level; |
1da177e4 LT |
282 | |
283 | if (n >= 0x80000005) { | |
9d31d35b | 284 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 285 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", |
9d31d35b YL |
286 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); |
287 | c->x86_cache_size = (ecx>>24) + (edx>>24); | |
140fc727 YL |
288 | #ifdef CONFIG_X86_64 |
289 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
290 | c->x86_tlbsize = 0; | |
291 | #endif | |
1da177e4 LT |
292 | } |
293 | ||
294 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
295 | return; | |
296 | ||
0a488a53 | 297 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 298 | l2size = ecx >> 16; |
34048c9e | 299 | |
140fc727 YL |
300 | #ifdef CONFIG_X86_64 |
301 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
302 | #else | |
1da177e4 LT |
303 | /* do processor-specific cache resizing */ |
304 | if (this_cpu->c_size_cache) | |
34048c9e | 305 | l2size = this_cpu->c_size_cache(c, l2size); |
1da177e4 LT |
306 | |
307 | /* Allow user to override all this if necessary. */ | |
308 | if (cachesize_override != -1) | |
309 | l2size = cachesize_override; | |
310 | ||
34048c9e | 311 | if (l2size == 0) |
1da177e4 | 312 | return; /* Again, no L2 cache is possible */ |
140fc727 | 313 | #endif |
1da177e4 LT |
314 | |
315 | c->x86_cache_size = l2size; | |
316 | ||
317 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
0a488a53 | 318 | l2size, ecx & 0xFF); |
1da177e4 LT |
319 | } |
320 | ||
9d31d35b | 321 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 322 | { |
97e4db7c | 323 | #ifdef CONFIG_X86_HT |
0a488a53 YL |
324 | u32 eax, ebx, ecx, edx; |
325 | int index_msb, core_bits; | |
1da177e4 | 326 | |
0a488a53 | 327 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 328 | return; |
1da177e4 | 329 | |
0a488a53 YL |
330 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
331 | goto out; | |
1da177e4 | 332 | |
0a488a53 | 333 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 334 | |
9d31d35b YL |
335 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
336 | ||
337 | if (smp_num_siblings == 1) { | |
338 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
339 | } else if (smp_num_siblings > 1) { | |
340 | ||
341 | if (smp_num_siblings > NR_CPUS) { | |
342 | printk(KERN_WARNING "CPU: Unsupported number of siblings %d", | |
343 | smp_num_siblings); | |
344 | smp_num_siblings = 1; | |
345 | return; | |
346 | } | |
347 | ||
348 | index_msb = get_count_order(smp_num_siblings); | |
349 | c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb); | |
350 | ||
9d31d35b YL |
351 | |
352 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; | |
353 | ||
354 | index_msb = get_count_order(smp_num_siblings); | |
355 | ||
356 | core_bits = get_count_order(c->x86_max_cores); | |
357 | ||
358 | c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) & | |
359 | ((1 << core_bits) - 1); | |
1da177e4 | 360 | } |
1da177e4 | 361 | |
0a488a53 YL |
362 | out: |
363 | if ((c->x86_max_cores * smp_num_siblings) > 1) { | |
364 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
365 | c->phys_proc_id); | |
366 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
367 | c->cpu_core_id); | |
9d31d35b | 368 | } |
9d31d35b | 369 | #endif |
97e4db7c | 370 | } |
1da177e4 | 371 | |
3da99c97 | 372 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
373 | { |
374 | char *v = c->x86_vendor_id; | |
375 | int i; | |
fe38d855 | 376 | static int printed; |
1da177e4 LT |
377 | |
378 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
379 | if (!cpu_devs[i]) |
380 | break; | |
381 | ||
382 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
383 | (cpu_devs[i]->c_ident[1] && | |
384 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
385 | this_cpu = cpu_devs[i]; | |
386 | c->x86_vendor = this_cpu->c_x86_vendor; | |
387 | return; | |
1da177e4 LT |
388 | } |
389 | } | |
10a434fc | 390 | |
fe38d855 CE |
391 | if (!printed) { |
392 | printed++; | |
393 | printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n"); | |
394 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); | |
395 | } | |
10a434fc | 396 | |
fe38d855 CE |
397 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
398 | this_cpu = &default_cpu; | |
1da177e4 LT |
399 | } |
400 | ||
9d31d35b | 401 | void __cpuinit cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 402 | { |
1da177e4 | 403 | /* Get vendor name */ |
4a148513 HH |
404 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
405 | (unsigned int *)&c->x86_vendor_id[0], | |
406 | (unsigned int *)&c->x86_vendor_id[8], | |
407 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 408 | |
1da177e4 | 409 | c->x86 = 4; |
9d31d35b | 410 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
411 | if (c->cpuid_level >= 0x00000001) { |
412 | u32 junk, tfms, cap0, misc; | |
413 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
9d31d35b YL |
414 | c->x86 = (tfms >> 8) & 0xf; |
415 | c->x86_model = (tfms >> 4) & 0xf; | |
416 | c->x86_mask = tfms & 0xf; | |
f5f786d0 | 417 | if (c->x86 == 0xf) |
1da177e4 | 418 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 419 | if (c->x86 >= 0x6) |
9d31d35b | 420 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
d4387bd3 | 421 | if (cap0 & (1<<19)) { |
d4387bd3 | 422 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 423 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 424 | } |
1da177e4 | 425 | } |
1da177e4 | 426 | } |
3da99c97 YL |
427 | |
428 | static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) | |
093af8d7 YL |
429 | { |
430 | u32 tfms, xlvl; | |
3da99c97 | 431 | u32 ebx; |
093af8d7 | 432 | |
3da99c97 YL |
433 | /* Intel-defined flags: level 0x00000001 */ |
434 | if (c->cpuid_level >= 0x00000001) { | |
435 | u32 capability, excap; | |
436 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); | |
437 | c->x86_capability[0] = capability; | |
438 | c->x86_capability[4] = excap; | |
439 | } | |
093af8d7 | 440 | |
3da99c97 YL |
441 | /* AMD-defined flags: level 0x80000001 */ |
442 | xlvl = cpuid_eax(0x80000000); | |
443 | c->extended_cpuid_level = xlvl; | |
444 | if ((xlvl & 0xffff0000) == 0x80000000) { | |
445 | if (xlvl >= 0x80000001) { | |
446 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
447 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 448 | } |
093af8d7 | 449 | } |
093af8d7 | 450 | } |
34048c9e PC |
451 | /* |
452 | * Do minimum CPU detection early. | |
453 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
454 | * cache alignment. | |
455 | * The others are not touched to avoid unwanted side effects. | |
456 | * | |
457 | * WARNING: this function is only called on the BP. Don't add code here | |
458 | * that is supposed to run on all CPUs. | |
459 | */ | |
3da99c97 | 460 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 461 | { |
d4387bd3 | 462 | c->x86_clflush_size = 32; |
0a488a53 | 463 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 RR |
464 | |
465 | if (!have_cpuid_p()) | |
466 | return; | |
467 | ||
3da99c97 YL |
468 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
469 | ||
0a488a53 YL |
470 | c->extended_cpuid_level = 0; |
471 | ||
d7cd5611 RR |
472 | cpu_detect(c); |
473 | ||
3da99c97 | 474 | get_cpu_vendor(c); |
2b16a235 | 475 | |
3da99c97 | 476 | get_cpu_cap(c); |
2b16a235 | 477 | |
10a434fc YL |
478 | if (this_cpu->c_early_init) |
479 | this_cpu->c_early_init(c); | |
093af8d7 | 480 | |
3da99c97 | 481 | validate_pat_support(c); |
d7cd5611 RR |
482 | } |
483 | ||
9d31d35b YL |
484 | void __init early_cpu_init(void) |
485 | { | |
10a434fc YL |
486 | struct cpu_dev **cdev; |
487 | int count = 0; | |
488 | ||
489 | printk("KERNEL supported cpus:\n"); | |
490 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { | |
491 | struct cpu_dev *cpudev = *cdev; | |
492 | unsigned int j; | |
9d31d35b | 493 | |
10a434fc YL |
494 | if (count >= X86_VENDOR_NUM) |
495 | break; | |
496 | cpu_devs[count] = cpudev; | |
497 | count++; | |
498 | ||
499 | for (j = 0; j < 2; j++) { | |
500 | if (!cpudev->c_ident[j]) | |
501 | continue; | |
502 | printk(" %s %s\n", cpudev->c_vendor, | |
503 | cpudev->c_ident[j]); | |
504 | } | |
505 | } | |
9d31d35b | 506 | |
9d31d35b | 507 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 RR |
508 | } |
509 | ||
7e00df58 PA |
510 | /* |
511 | * The NOPL instruction is supposed to exist on all CPUs with | |
512 | * family >= 6, unfortunately, that's not true in practice because | |
513 | * of early VIA chips and (more importantly) broken virtualizers that | |
514 | * are not easy to detect. Hence, probe for it based on first | |
515 | * principles. | |
516 | */ | |
517 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
518 | { | |
519 | const u32 nopl_signature = 0x888c53b1; /* Random number */ | |
520 | u32 has_nopl = nopl_signature; | |
521 | ||
522 | clear_cpu_cap(c, X86_FEATURE_NOPL); | |
523 | if (c->x86 >= 6) { | |
524 | asm volatile("\n" | |
525 | "1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */ | |
526 | "2:\n" | |
527 | " .section .fixup,\"ax\"\n" | |
528 | "3: xor %0,%0\n" | |
529 | " jmp 2b\n" | |
530 | " .previous\n" | |
531 | _ASM_EXTABLE(1b,3b) | |
532 | : "+a" (has_nopl)); | |
533 | ||
534 | if (has_nopl == nopl_signature) | |
535 | set_cpu_cap(c, X86_FEATURE_NOPL); | |
536 | } | |
537 | } | |
538 | ||
34048c9e | 539 | static void __cpuinit generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 540 | { |
3da99c97 YL |
541 | if (!have_cpuid_p()) |
542 | return; | |
1da177e4 | 543 | |
3da99c97 | 544 | c->extended_cpuid_level = 0; |
1d67953f | 545 | |
3da99c97 | 546 | cpu_detect(c); |
1da177e4 | 547 | |
3da99c97 | 548 | get_cpu_vendor(c); |
1da177e4 | 549 | |
3da99c97 | 550 | get_cpu_cap(c); |
1da177e4 | 551 | |
3da99c97 YL |
552 | if (c->cpuid_level >= 0x00000001) { |
553 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
96c52749 | 554 | #ifdef CONFIG_X86_HT |
3da99c97 YL |
555 | c->apicid = phys_pkg_id(c->initial_apicid, 0); |
556 | c->phys_proc_id = c->initial_apicid; | |
1e9f28fa | 557 | #else |
3da99c97 | 558 | c->apicid = c->initial_apicid; |
1e9f28fa | 559 | #endif |
3da99c97 | 560 | } |
1da177e4 | 561 | |
3da99c97 YL |
562 | if (c->extended_cpuid_level >= 0x80000004) |
563 | get_model_name(c); /* Default name */ | |
1da177e4 | 564 | |
3da99c97 YL |
565 | init_scattered_cpuid_features(c); |
566 | detect_nopl(c); | |
1da177e4 | 567 | } |
1da177e4 LT |
568 | |
569 | /* | |
570 | * This does the hard work of actually picking apart the CPU stuff... | |
571 | */ | |
9a250347 | 572 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
573 | { |
574 | int i; | |
575 | ||
576 | c->loops_per_jiffy = loops_per_jiffy; | |
577 | c->x86_cache_size = -1; | |
578 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
579 | c->cpuid_level = -1; /* CPUID not detected */ | |
580 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ | |
581 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
582 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 583 | c->x86_max_cores = 1; |
770d132f | 584 | c->x86_clflush_size = 32; |
1da177e4 LT |
585 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
586 | ||
587 | if (!have_cpuid_p()) { | |
34048c9e PC |
588 | /* |
589 | * First of all, decide if this is a 486 or higher | |
590 | * It's a 486 if we can modify the AC flag | |
591 | */ | |
592 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
1da177e4 LT |
593 | c->x86 = 4; |
594 | else | |
595 | c->x86 = 3; | |
596 | } | |
597 | ||
598 | generic_identify(c); | |
599 | ||
3898534d | 600 | if (this_cpu->c_identify) |
1da177e4 LT |
601 | this_cpu->c_identify(c); |
602 | ||
1da177e4 LT |
603 | /* |
604 | * Vendor-specific initialization. In this section we | |
605 | * canonicalize the feature flags, meaning if there are | |
606 | * features a certain CPU supports which CPUID doesn't | |
607 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
608 | * we handle them here. | |
609 | * | |
610 | * At the end of this section, c->x86_capability better | |
611 | * indicate the features this CPU genuinely supports! | |
612 | */ | |
613 | if (this_cpu->c_init) | |
614 | this_cpu->c_init(c); | |
615 | ||
616 | /* Disable the PN if appropriate */ | |
617 | squash_the_stupid_serial_number(c); | |
618 | ||
619 | /* | |
620 | * The vendor-specific functions might have changed features. Now | |
621 | * we do "generic changes." | |
622 | */ | |
623 | ||
1da177e4 | 624 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 625 | if (!c->x86_model_id[0]) { |
1da177e4 LT |
626 | char *p; |
627 | p = table_lookup_model(c); | |
34048c9e | 628 | if (p) |
1da177e4 LT |
629 | strcpy(c->x86_model_id, p); |
630 | else | |
631 | /* Last resort... */ | |
632 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 633 | c->x86, c->x86_model); |
1da177e4 LT |
634 | } |
635 | ||
1da177e4 LT |
636 | /* |
637 | * On SMP, boot_cpu_data holds the common feature set between | |
638 | * all CPUs; so make sure that we indicate which features are | |
639 | * common between the CPUs. The first time this routine gets | |
640 | * executed, c == &boot_cpu_data. | |
641 | */ | |
34048c9e | 642 | if (c != &boot_cpu_data) { |
1da177e4 | 643 | /* AND the already accumulated flags with these */ |
9d31d35b | 644 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 LT |
645 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
646 | } | |
647 | ||
7d851c8d AK |
648 | /* Clear all flags overriden by options */ |
649 | for (i = 0; i < NCAPINTS; i++) | |
12c247a6 | 650 | c->x86_capability[i] &= ~cleared_cpu_caps[i]; |
7d851c8d | 651 | |
1da177e4 | 652 | /* Init Machine Check Exception if available. */ |
1da177e4 | 653 | mcheck_init(c); |
30d432df AK |
654 | |
655 | select_idle_routine(c); | |
a6c4e076 | 656 | } |
31ab269a | 657 | |
a6c4e076 JF |
658 | void __init identify_boot_cpu(void) |
659 | { | |
660 | identify_cpu(&boot_cpu_data); | |
661 | sysenter_setup(); | |
6fe940d6 | 662 | enable_sep_cpu(); |
a6c4e076 | 663 | } |
3b520b23 | 664 | |
a6c4e076 JF |
665 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) |
666 | { | |
667 | BUG_ON(c == &boot_cpu_data); | |
668 | identify_cpu(c); | |
669 | enable_sep_cpu(); | |
670 | mtrr_ap_init(); | |
1da177e4 LT |
671 | } |
672 | ||
a0854a46 YL |
673 | struct msr_range { |
674 | unsigned min; | |
675 | unsigned max; | |
676 | }; | |
1da177e4 | 677 | |
a0854a46 YL |
678 | static struct msr_range msr_range_array[] __cpuinitdata = { |
679 | { 0x00000000, 0x00000418}, | |
680 | { 0xc0000000, 0xc000040b}, | |
681 | { 0xc0010000, 0xc0010142}, | |
682 | { 0xc0011000, 0xc001103b}, | |
683 | }; | |
1da177e4 | 684 | |
a0854a46 YL |
685 | static void __cpuinit print_cpu_msr(void) |
686 | { | |
687 | unsigned index; | |
688 | u64 val; | |
689 | int i; | |
690 | unsigned index_min, index_max; | |
691 | ||
692 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
693 | index_min = msr_range_array[i].min; | |
694 | index_max = msr_range_array[i].max; | |
695 | for (index = index_min; index < index_max; index++) { | |
696 | if (rdmsrl_amd_safe(index, &val)) | |
697 | continue; | |
698 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1da177e4 | 699 | } |
a0854a46 YL |
700 | } |
701 | } | |
94605eff | 702 | |
a0854a46 YL |
703 | static int show_msr __cpuinitdata; |
704 | static __init int setup_show_msr(char *arg) | |
705 | { | |
706 | int num; | |
3dd9d514 | 707 | |
a0854a46 | 708 | get_option(&arg, &num); |
3dd9d514 | 709 | |
a0854a46 YL |
710 | if (num > 0) |
711 | show_msr = num; | |
712 | return 1; | |
1da177e4 | 713 | } |
a0854a46 | 714 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 715 | |
191679fd AK |
716 | static __init int setup_noclflush(char *arg) |
717 | { | |
718 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
719 | return 1; | |
720 | } | |
721 | __setup("noclflush", setup_noclflush); | |
722 | ||
3bc9b76b | 723 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 LT |
724 | { |
725 | char *vendor = NULL; | |
726 | ||
727 | if (c->x86_vendor < X86_VENDOR_NUM) | |
728 | vendor = this_cpu->c_vendor; | |
729 | else if (c->cpuid_level >= 0) | |
730 | vendor = c->x86_vendor_id; | |
731 | ||
732 | if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor))) | |
9d31d35b | 733 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 734 | |
9d31d35b YL |
735 | if (c->x86_model_id[0]) |
736 | printk(KERN_CONT "%s", c->x86_model_id); | |
1da177e4 | 737 | else |
9d31d35b | 738 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 739 | |
34048c9e | 740 | if (c->x86_mask || c->cpuid_level >= 0) |
9d31d35b | 741 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); |
1da177e4 | 742 | else |
9d31d35b | 743 | printk(KERN_CONT "\n"); |
a0854a46 YL |
744 | |
745 | #ifdef CONFIG_SMP | |
746 | if (c->cpu_index < show_msr) | |
747 | print_cpu_msr(); | |
748 | #else | |
749 | if (show_msr) | |
750 | print_cpu_msr(); | |
751 | #endif | |
1da177e4 LT |
752 | } |
753 | ||
ac72e788 AK |
754 | static __init int setup_disablecpuid(char *arg) |
755 | { | |
756 | int bit; | |
757 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) | |
758 | setup_clear_cpu_cap(bit); | |
759 | else | |
760 | return 0; | |
761 | return 1; | |
762 | } | |
763 | __setup("clearcpuid=", setup_disablecpuid); | |
764 | ||
3bc9b76b | 765 | cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE; |
1da177e4 | 766 | |
d5494d4f YL |
767 | #ifdef CONFIG_X86_64 |
768 | struct x8664_pda **_cpu_pda __read_mostly; | |
769 | EXPORT_SYMBOL(_cpu_pda); | |
770 | ||
771 | struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; | |
772 | ||
773 | char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss; | |
774 | ||
775 | unsigned long __supported_pte_mask __read_mostly = ~0UL; | |
776 | EXPORT_SYMBOL_GPL(__supported_pte_mask); | |
777 | ||
778 | static int do_not_nx __cpuinitdata; | |
779 | ||
780 | /* noexec=on|off | |
781 | Control non executable mappings for 64bit processes. | |
782 | ||
783 | on Enable(default) | |
784 | off Disable | |
785 | */ | |
786 | static int __init nonx_setup(char *str) | |
787 | { | |
788 | if (!str) | |
789 | return -EINVAL; | |
790 | if (!strncmp(str, "on", 2)) { | |
791 | __supported_pte_mask |= _PAGE_NX; | |
792 | do_not_nx = 0; | |
793 | } else if (!strncmp(str, "off", 3)) { | |
794 | do_not_nx = 1; | |
795 | __supported_pte_mask &= ~_PAGE_NX; | |
796 | } | |
797 | return 0; | |
798 | } | |
799 | early_param("noexec", nonx_setup); | |
800 | ||
801 | int force_personality32; | |
802 | ||
803 | /* noexec32=on|off | |
804 | Control non executable heap for 32bit processes. | |
805 | To control the stack too use noexec=off | |
806 | ||
807 | on PROT_READ does not imply PROT_EXEC for 32bit processes (default) | |
808 | off PROT_READ implies PROT_EXEC | |
809 | */ | |
810 | static int __init nonx32_setup(char *str) | |
811 | { | |
812 | if (!strcmp(str, "on")) | |
813 | force_personality32 &= ~READ_IMPLIES_EXEC; | |
814 | else if (!strcmp(str, "off")) | |
815 | force_personality32 |= READ_IMPLIES_EXEC; | |
816 | return 1; | |
817 | } | |
818 | __setup("noexec32=", nonx32_setup); | |
819 | ||
820 | void pda_init(int cpu) | |
821 | { | |
822 | struct x8664_pda *pda = cpu_pda(cpu); | |
823 | ||
824 | /* Setup up data that may be needed in __get_free_pages early */ | |
825 | loadsegment(fs, 0); | |
826 | loadsegment(gs, 0); | |
827 | /* Memory clobbers used to order PDA accessed */ | |
828 | mb(); | |
829 | wrmsrl(MSR_GS_BASE, pda); | |
830 | mb(); | |
831 | ||
832 | pda->cpunumber = cpu; | |
833 | pda->irqcount = -1; | |
834 | pda->kernelstack = (unsigned long)stack_thread_info() - | |
835 | PDA_STACKOFFSET + THREAD_SIZE; | |
836 | pda->active_mm = &init_mm; | |
837 | pda->mmu_state = 0; | |
838 | ||
839 | if (cpu == 0) { | |
840 | /* others are initialized in smpboot.c */ | |
841 | pda->pcurrent = &init_task; | |
842 | pda->irqstackptr = boot_cpu_stack; | |
843 | pda->irqstackptr += IRQSTACKSIZE - 64; | |
844 | } else { | |
845 | if (!pda->irqstackptr) { | |
846 | pda->irqstackptr = (char *) | |
847 | __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER); | |
848 | if (!pda->irqstackptr) | |
849 | panic("cannot allocate irqstack for cpu %d", | |
850 | cpu); | |
851 | pda->irqstackptr += IRQSTACKSIZE - 64; | |
852 | } | |
853 | ||
854 | if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE) | |
855 | pda->nodenumber = cpu_to_node(cpu); | |
856 | } | |
857 | } | |
858 | ||
859 | char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + | |
860 | DEBUG_STKSZ] __page_aligned_bss; | |
861 | ||
862 | extern asmlinkage void ignore_sysret(void); | |
863 | ||
864 | /* May not be marked __init: used by software suspend */ | |
865 | void syscall_init(void) | |
866 | { | |
867 | /* | |
868 | * LSTAR and STAR live in a bit strange symbiosis. | |
869 | * They both write to the same internal register. STAR allows to | |
870 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
871 | */ | |
872 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
873 | wrmsrl(MSR_LSTAR, system_call); | |
874 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
875 | ||
876 | #ifdef CONFIG_IA32_EMULATION | |
877 | syscall32_cpu_init(); | |
878 | #endif | |
879 | ||
880 | /* Flags to clear on syscall */ | |
881 | wrmsrl(MSR_SYSCALL_MASK, | |
882 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); | |
883 | } | |
884 | ||
885 | void __cpuinit check_efer(void) | |
886 | { | |
887 | unsigned long efer; | |
888 | ||
889 | rdmsrl(MSR_EFER, efer); | |
890 | if (!(efer & EFER_NX) || do_not_nx) | |
891 | __supported_pte_mask &= ~_PAGE_NX; | |
892 | } | |
893 | ||
894 | unsigned long kernel_eflags; | |
895 | ||
896 | /* | |
897 | * Copies of the original ist values from the tss are only accessed during | |
898 | * debugging, no special alignment required. | |
899 | */ | |
900 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
901 | ||
902 | #else | |
903 | ||
7c3576d2 | 904 | /* Make sure %fs is initialized properly in idle threads */ |
6b2fb3c6 | 905 | struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) |
f95d47ca JF |
906 | { |
907 | memset(regs, 0, sizeof(struct pt_regs)); | |
65ea5b03 | 908 | regs->fs = __KERNEL_PERCPU; |
f95d47ca JF |
909 | return regs; |
910 | } | |
d5494d4f | 911 | #endif |
f95d47ca | 912 | |
d2cbcc49 RR |
913 | /* |
914 | * cpu_init() initializes state that is per-CPU. Some data is already | |
915 | * initialized (naturally) in the bootstrap process, such as the GDT | |
916 | * and IDT. We reload them nevertheless, this function acts as a | |
917 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 918 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 919 | */ |
1ba76586 YL |
920 | #ifdef CONFIG_X86_64 |
921 | void __cpuinit cpu_init(void) | |
922 | { | |
923 | int cpu = stack_smp_processor_id(); | |
924 | struct tss_struct *t = &per_cpu(init_tss, cpu); | |
925 | struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu); | |
926 | unsigned long v; | |
927 | char *estacks = NULL; | |
928 | struct task_struct *me; | |
929 | int i; | |
930 | ||
931 | /* CPU 0 is initialised in head64.c */ | |
932 | if (cpu != 0) | |
933 | pda_init(cpu); | |
934 | else | |
935 | estacks = boot_exception_stacks; | |
936 | ||
937 | me = current; | |
938 | ||
939 | if (cpu_test_and_set(cpu, cpu_initialized)) | |
940 | panic("CPU#%d already initialized!\n", cpu); | |
941 | ||
942 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
943 | ||
944 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
945 | ||
946 | /* | |
947 | * Initialize the per-CPU GDT with the boot GDT, | |
948 | * and set up the GDT descriptor: | |
949 | */ | |
950 | ||
951 | switch_to_new_gdt(); | |
952 | load_idt((const struct desc_ptr *)&idt_descr); | |
953 | ||
954 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
955 | syscall_init(); | |
956 | ||
957 | wrmsrl(MSR_FS_BASE, 0); | |
958 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
959 | barrier(); | |
960 | ||
961 | check_efer(); | |
962 | if (cpu != 0 && x2apic) | |
963 | enable_x2apic(); | |
964 | ||
965 | /* | |
966 | * set up and load the per-CPU TSS | |
967 | */ | |
968 | if (!orig_ist->ist[0]) { | |
969 | static const unsigned int order[N_EXCEPTION_STACKS] = { | |
970 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER, | |
971 | [DEBUG_STACK - 1] = DEBUG_STACK_ORDER | |
972 | }; | |
973 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { | |
974 | if (cpu) { | |
975 | estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]); | |
976 | if (!estacks) | |
977 | panic("Cannot allocate exception " | |
978 | "stack %ld %d\n", v, cpu); | |
979 | } | |
980 | estacks += PAGE_SIZE << order[v]; | |
981 | orig_ist->ist[v] = t->x86_tss.ist[v] = | |
982 | (unsigned long)estacks; | |
983 | } | |
984 | } | |
985 | ||
986 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
987 | /* | |
988 | * <= is required because the CPU will access up to | |
989 | * 8 bits beyond the end of the IO permission bitmap. | |
990 | */ | |
991 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
992 | t->io_bitmap[i] = ~0UL; | |
993 | ||
994 | atomic_inc(&init_mm.mm_count); | |
995 | me->active_mm = &init_mm; | |
996 | if (me->mm) | |
997 | BUG(); | |
998 | enter_lazy_tlb(&init_mm, me); | |
999 | ||
1000 | load_sp0(t, ¤t->thread); | |
1001 | set_tss_desc(cpu, t); | |
1002 | load_TR_desc(); | |
1003 | load_LDT(&init_mm.context); | |
1004 | ||
1005 | #ifdef CONFIG_KGDB | |
1006 | /* | |
1007 | * If the kgdb is connected no debug regs should be altered. This | |
1008 | * is only applicable when KGDB and a KGDB I/O module are built | |
1009 | * into the kernel and you are using early debugging with | |
1010 | * kgdbwait. KGDB will control the kernel HW breakpoint registers. | |
1011 | */ | |
1012 | if (kgdb_connected && arch_kgdb_ops.correct_hw_break) | |
1013 | arch_kgdb_ops.correct_hw_break(); | |
1014 | else { | |
1015 | #endif | |
1016 | /* | |
1017 | * Clear all 6 debug registers: | |
1018 | */ | |
1019 | ||
1020 | set_debugreg(0UL, 0); | |
1021 | set_debugreg(0UL, 1); | |
1022 | set_debugreg(0UL, 2); | |
1023 | set_debugreg(0UL, 3); | |
1024 | set_debugreg(0UL, 6); | |
1025 | set_debugreg(0UL, 7); | |
1026 | #ifdef CONFIG_KGDB | |
1027 | /* If the kgdb is connected no debug regs should be altered. */ | |
1028 | } | |
1029 | #endif | |
1030 | ||
1031 | fpu_init(); | |
1032 | ||
1033 | raw_local_save_flags(kernel_eflags); | |
1034 | ||
1035 | if (is_uv_system()) | |
1036 | uv_cpu_init(); | |
1037 | } | |
1038 | ||
1039 | #else | |
1040 | ||
d2cbcc49 | 1041 | void __cpuinit cpu_init(void) |
9ee79a3d | 1042 | { |
d2cbcc49 RR |
1043 | int cpu = smp_processor_id(); |
1044 | struct task_struct *curr = current; | |
34048c9e | 1045 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 1046 | struct thread_struct *thread = &curr->thread; |
62111195 JF |
1047 | |
1048 | if (cpu_test_and_set(cpu, cpu_initialized)) { | |
1049 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); | |
1050 | for (;;) local_irq_enable(); | |
1051 | } | |
1052 | ||
1053 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1054 | ||
1055 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
1056 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 1057 | |
4d37e7e3 | 1058 | load_idt(&idt_descr); |
c5413fbe | 1059 | switch_to_new_gdt(); |
1da177e4 | 1060 | |
1da177e4 LT |
1061 | /* |
1062 | * Set up and load the per-CPU TSS and LDT | |
1063 | */ | |
1064 | atomic_inc(&init_mm.mm_count); | |
62111195 JF |
1065 | curr->active_mm = &init_mm; |
1066 | if (curr->mm) | |
1067 | BUG(); | |
1068 | enter_lazy_tlb(&init_mm, curr); | |
1da177e4 | 1069 | |
faca6227 | 1070 | load_sp0(t, thread); |
34048c9e | 1071 | set_tss_desc(cpu, t); |
1da177e4 LT |
1072 | load_TR_desc(); |
1073 | load_LDT(&init_mm.context); | |
1074 | ||
22c4e308 | 1075 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1076 | /* Set up doublefault TSS pointer in the GDT */ |
1077 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1078 | #endif |
1da177e4 | 1079 | |
464d1a78 JF |
1080 | /* Clear %gs. */ |
1081 | asm volatile ("mov %0, %%gs" : : "r" (0)); | |
1da177e4 LT |
1082 | |
1083 | /* Clear all 6 debug registers: */ | |
4bb0d3ec ZA |
1084 | set_debugreg(0, 0); |
1085 | set_debugreg(0, 1); | |
1086 | set_debugreg(0, 2); | |
1087 | set_debugreg(0, 3); | |
1088 | set_debugreg(0, 6); | |
1089 | set_debugreg(0, 7); | |
1da177e4 LT |
1090 | |
1091 | /* | |
1092 | * Force FPU initialization: | |
1093 | */ | |
b359e8a4 SS |
1094 | if (cpu_has_xsave) |
1095 | current_thread_info()->status = TS_XSAVE; | |
1096 | else | |
1097 | current_thread_info()->status = 0; | |
1da177e4 LT |
1098 | clear_used_math(); |
1099 | mxcsr_feature_mask_init(); | |
dc1e35c6 SS |
1100 | |
1101 | /* | |
1102 | * Boot processor to setup the FP and extended state context info. | |
1103 | */ | |
1104 | if (!smp_processor_id()) | |
1105 | init_thread_xstate(); | |
1106 | ||
1107 | xsave_init(); | |
1da177e4 | 1108 | } |
e1367daf LS |
1109 | |
1110 | #ifdef CONFIG_HOTPLUG_CPU | |
3bc9b76b | 1111 | void __cpuinit cpu_uninit(void) |
e1367daf LS |
1112 | { |
1113 | int cpu = raw_smp_processor_id(); | |
1114 | cpu_clear(cpu, cpu_initialized); | |
1115 | ||
1116 | /* lazy TLB state */ | |
1117 | per_cpu(cpu_tlbstate, cpu).state = 0; | |
1118 | per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm; | |
1119 | } | |
1120 | #endif | |
1ba76586 YL |
1121 | |
1122 | #endif |