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Commit | Line | Data |
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457c8996 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
2458e53f KS |
2 | /* cpu_feature_enabled() cannot be used this early */ |
3 | #define USE_EARLY_PGTABLE_L5 | |
4 | ||
57c8a661 | 5 | #include <linux/memblock.h> |
9766cdbc | 6 | #include <linux/linkage.h> |
f0fc4aff | 7 | #include <linux/bitops.h> |
9766cdbc | 8 | #include <linux/kernel.h> |
186f4360 | 9 | #include <linux/export.h> |
9766cdbc JSR |
10 | #include <linux/percpu.h> |
11 | #include <linux/string.h> | |
ee098e1a | 12 | #include <linux/ctype.h> |
1da177e4 | 13 | #include <linux/delay.h> |
68e21be2 | 14 | #include <linux/sched/mm.h> |
e6017571 | 15 | #include <linux/sched/clock.h> |
9164bb4a | 16 | #include <linux/sched/task.h> |
9766cdbc | 17 | #include <linux/init.h> |
0f46efeb | 18 | #include <linux/kprobes.h> |
9766cdbc | 19 | #include <linux/kgdb.h> |
1da177e4 | 20 | #include <linux/smp.h> |
9766cdbc | 21 | #include <linux/io.h> |
b51ef52d | 22 | #include <linux/syscore_ops.h> |
9766cdbc JSR |
23 | |
24 | #include <asm/stackprotector.h> | |
cdd6c482 | 25 | #include <asm/perf_event.h> |
1da177e4 | 26 | #include <asm/mmu_context.h> |
49d859d7 | 27 | #include <asm/archrandom.h> |
9766cdbc JSR |
28 | #include <asm/hypervisor.h> |
29 | #include <asm/processor.h> | |
1e02ce4c | 30 | #include <asm/tlbflush.h> |
f649e938 | 31 | #include <asm/debugreg.h> |
9766cdbc | 32 | #include <asm/sections.h> |
f40c3300 | 33 | #include <asm/vsyscall.h> |
8bdbd962 AC |
34 | #include <linux/topology.h> |
35 | #include <linux/cpumask.h> | |
9766cdbc | 36 | #include <asm/pgtable.h> |
60063497 | 37 | #include <linux/atomic.h> |
9766cdbc JSR |
38 | #include <asm/proto.h> |
39 | #include <asm/setup.h> | |
40 | #include <asm/apic.h> | |
41 | #include <asm/desc.h> | |
78f7f1e5 | 42 | #include <asm/fpu/internal.h> |
27b07da7 | 43 | #include <asm/mtrr.h> |
0274f955 | 44 | #include <asm/hwcap2.h> |
8bdbd962 | 45 | #include <linux/numa.h> |
9766cdbc | 46 | #include <asm/asm.h> |
0f6ff2bc | 47 | #include <asm/bugs.h> |
9766cdbc | 48 | #include <asm/cpu.h> |
a03a3e28 | 49 | #include <asm/mce.h> |
9766cdbc | 50 | #include <asm/msr.h> |
8d4a4300 | 51 | #include <asm/pat.h> |
d288e1cf FY |
52 | #include <asm/microcode.h> |
53 | #include <asm/microcode_intel.h> | |
fec9434a DW |
54 | #include <asm/intel-family.h> |
55 | #include <asm/cpu_device_id.h> | |
e641f5f5 IM |
56 | |
57 | #ifdef CONFIG_X86_LOCAL_APIC | |
bdbcdd48 | 58 | #include <asm/uv/uv.h> |
1da177e4 LT |
59 | #endif |
60 | ||
61 | #include "cpu.h" | |
62 | ||
0274f955 GA |
63 | u32 elf_hwcap2 __read_mostly; |
64 | ||
c2d1cec1 | 65 | /* all of these masks are initialized in setup_cpu_local_masks() */ |
c2d1cec1 | 66 | cpumask_var_t cpu_initialized_mask; |
9766cdbc JSR |
67 | cpumask_var_t cpu_callout_mask; |
68 | cpumask_var_t cpu_callin_mask; | |
c2d1cec1 MT |
69 | |
70 | /* representing cpus for which sibling maps can be computed */ | |
71 | cpumask_var_t cpu_sibling_setup_mask; | |
72 | ||
f8b64d08 BP |
73 | /* Number of siblings per CPU package */ |
74 | int smp_num_siblings = 1; | |
75 | EXPORT_SYMBOL(smp_num_siblings); | |
76 | ||
77 | /* Last level cache ID of each logical CPU */ | |
78 | DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; | |
79 | ||
2f2f52ba | 80 | /* correctly size the local cpu masks */ |
4369f1fb | 81 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
82 | { |
83 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
84 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
85 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
86 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
87 | } | |
88 | ||
148f9bb8 | 89 | static void default_init(struct cpuinfo_x86 *c) |
e8055139 OZ |
90 | { |
91 | #ifdef CONFIG_X86_64 | |
27c13ece | 92 | cpu_detect_cache_sizes(c); |
e8055139 OZ |
93 | #else |
94 | /* Not much we can do here... */ | |
95 | /* Check if at least it has cpuid */ | |
96 | if (c->cpuid_level == -1) { | |
97 | /* No cpuid. It must be an ancient CPU */ | |
98 | if (c->x86 == 4) | |
99 | strcpy(c->x86_model_id, "486"); | |
100 | else if (c->x86 == 3) | |
101 | strcpy(c->x86_model_id, "386"); | |
102 | } | |
103 | #endif | |
104 | } | |
105 | ||
148f9bb8 | 106 | static const struct cpu_dev default_cpu = { |
e8055139 OZ |
107 | .c_init = default_init, |
108 | .c_vendor = "Unknown", | |
109 | .c_x86_vendor = X86_VENDOR_UNKNOWN, | |
110 | }; | |
111 | ||
148f9bb8 | 112 | static const struct cpu_dev *this_cpu = &default_cpu; |
0a488a53 | 113 | |
06deef89 | 114 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 115 | #ifdef CONFIG_X86_64 |
06deef89 BG |
116 | /* |
117 | * We need valid kernel segments for data and code in long mode too | |
118 | * IRET will check the segment types kkeil 2000/10/28 | |
119 | * Also sysret mandates a special GDT layout | |
120 | * | |
9766cdbc | 121 | * TLS descriptors are currently at a different place compared to i386. |
06deef89 BG |
122 | * Hopefully nobody expects them at a fixed place (Wine?) |
123 | */ | |
1e5de182 AM |
124 | [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), |
125 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), | |
126 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), | |
127 | [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), | |
128 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), | |
129 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), | |
950ad7ff | 130 | #else |
1e5de182 AM |
131 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), |
132 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
133 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), | |
134 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), | |
bf504672 RR |
135 | /* |
136 | * Segments used for calling PnP BIOS have byte granularity. | |
137 | * They code segments and data segments have fixed 64k limits, | |
138 | * the transfer segment sizes are set at run time. | |
139 | */ | |
6842ef0e | 140 | /* 32-bit code */ |
1e5de182 | 141 | [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
6842ef0e | 142 | /* 16-bit code */ |
1e5de182 | 143 | [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 144 | /* 16-bit data */ |
1e5de182 | 145 | [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), |
6842ef0e | 146 | /* 16-bit data */ |
1e5de182 | 147 | [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), |
6842ef0e | 148 | /* 16-bit data */ |
1e5de182 | 149 | [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), |
bf504672 RR |
150 | /* |
151 | * The APM segments have byte granularity and their bases | |
152 | * are set at run time. All have 64k limits. | |
153 | */ | |
6842ef0e | 154 | /* 32-bit code */ |
1e5de182 | 155 | [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
bf504672 | 156 | /* 16-bit code */ |
1e5de182 | 157 | [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 158 | /* data */ |
72c4d853 | 159 | [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), |
bf504672 | 160 | |
1e5de182 AM |
161 | [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), |
162 | [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
60a5317f | 163 | GDT_STACK_CANARY_INIT |
950ad7ff | 164 | #endif |
06deef89 | 165 | } }; |
7a61d35d | 166 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 167 | |
8c3641e9 | 168 | static int __init x86_mpx_setup(char *s) |
0c752a93 | 169 | { |
8c3641e9 | 170 | /* require an exact match without trailing characters */ |
2cd3949f DH |
171 | if (strlen(s)) |
172 | return 0; | |
0c752a93 | 173 | |
8c3641e9 DH |
174 | /* do not emit a message if the feature is not present */ |
175 | if (!boot_cpu_has(X86_FEATURE_MPX)) | |
176 | return 1; | |
6bad06b7 | 177 | |
8c3641e9 DH |
178 | setup_clear_cpu_cap(X86_FEATURE_MPX); |
179 | pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); | |
b6f42a4a FY |
180 | return 1; |
181 | } | |
8c3641e9 | 182 | __setup("nompx", x86_mpx_setup); |
b6f42a4a | 183 | |
0790c9aa | 184 | #ifdef CONFIG_X86_64 |
c7ad5ad2 | 185 | static int __init x86_nopcid_setup(char *s) |
0790c9aa | 186 | { |
c7ad5ad2 AL |
187 | /* nopcid doesn't accept parameters */ |
188 | if (s) | |
189 | return -EINVAL; | |
0790c9aa AL |
190 | |
191 | /* do not emit a message if the feature is not present */ | |
192 | if (!boot_cpu_has(X86_FEATURE_PCID)) | |
c7ad5ad2 | 193 | return 0; |
0790c9aa AL |
194 | |
195 | setup_clear_cpu_cap(X86_FEATURE_PCID); | |
196 | pr_info("nopcid: PCID feature disabled\n"); | |
c7ad5ad2 | 197 | return 0; |
0790c9aa | 198 | } |
c7ad5ad2 | 199 | early_param("nopcid", x86_nopcid_setup); |
0790c9aa AL |
200 | #endif |
201 | ||
d12a72b8 AL |
202 | static int __init x86_noinvpcid_setup(char *s) |
203 | { | |
204 | /* noinvpcid doesn't accept parameters */ | |
205 | if (s) | |
206 | return -EINVAL; | |
207 | ||
208 | /* do not emit a message if the feature is not present */ | |
209 | if (!boot_cpu_has(X86_FEATURE_INVPCID)) | |
210 | return 0; | |
211 | ||
212 | setup_clear_cpu_cap(X86_FEATURE_INVPCID); | |
213 | pr_info("noinvpcid: INVPCID feature disabled\n"); | |
214 | return 0; | |
215 | } | |
216 | early_param("noinvpcid", x86_noinvpcid_setup); | |
217 | ||
ba51dced | 218 | #ifdef CONFIG_X86_32 |
148f9bb8 PG |
219 | static int cachesize_override = -1; |
220 | static int disable_x86_serial_nr = 1; | |
1da177e4 | 221 | |
0a488a53 YL |
222 | static int __init cachesize_setup(char *str) |
223 | { | |
224 | get_option(&str, &cachesize_override); | |
225 | return 1; | |
226 | } | |
227 | __setup("cachesize=", cachesize_setup); | |
228 | ||
0a488a53 YL |
229 | static int __init x86_sep_setup(char *s) |
230 | { | |
231 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
232 | return 1; | |
233 | } | |
234 | __setup("nosep", x86_sep_setup); | |
235 | ||
236 | /* Standard macro to see if a specific flag is changeable */ | |
237 | static inline int flag_is_changeable_p(u32 flag) | |
238 | { | |
239 | u32 f1, f2; | |
240 | ||
94f6bac1 KH |
241 | /* |
242 | * Cyrix and IDT cpus allow disabling of CPUID | |
243 | * so the code below may return different results | |
244 | * when it is executed before and after enabling | |
245 | * the CPUID. Add "volatile" to not allow gcc to | |
246 | * optimize the subsequent calls to this function. | |
247 | */ | |
0f3fa48a IM |
248 | asm volatile ("pushfl \n\t" |
249 | "pushfl \n\t" | |
250 | "popl %0 \n\t" | |
251 | "movl %0, %1 \n\t" | |
252 | "xorl %2, %0 \n\t" | |
253 | "pushl %0 \n\t" | |
254 | "popfl \n\t" | |
255 | "pushfl \n\t" | |
256 | "popl %0 \n\t" | |
257 | "popfl \n\t" | |
258 | ||
94f6bac1 KH |
259 | : "=&r" (f1), "=&r" (f2) |
260 | : "ir" (flag)); | |
0a488a53 YL |
261 | |
262 | return ((f1^f2) & flag) != 0; | |
263 | } | |
264 | ||
265 | /* Probe for the CPUID instruction */ | |
148f9bb8 | 266 | int have_cpuid_p(void) |
0a488a53 YL |
267 | { |
268 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
269 | } | |
270 | ||
148f9bb8 | 271 | static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
0a488a53 | 272 | { |
0f3fa48a IM |
273 | unsigned long lo, hi; |
274 | ||
275 | if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) | |
276 | return; | |
277 | ||
278 | /* Disable processor serial number: */ | |
279 | ||
280 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
281 | lo |= 0x200000; | |
282 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
283 | ||
1b74dde7 | 284 | pr_notice("CPU serial number disabled.\n"); |
0f3fa48a IM |
285 | clear_cpu_cap(c, X86_FEATURE_PN); |
286 | ||
287 | /* Disabling the serial number may affect the cpuid level */ | |
288 | c->cpuid_level = cpuid_eax(0); | |
0a488a53 YL |
289 | } |
290 | ||
291 | static int __init x86_serial_nr_setup(char *s) | |
292 | { | |
293 | disable_x86_serial_nr = 0; | |
294 | return 1; | |
295 | } | |
296 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 297 | #else |
102bbe3a YL |
298 | static inline int flag_is_changeable_p(u32 flag) |
299 | { | |
300 | return 1; | |
301 | } | |
102bbe3a YL |
302 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
303 | { | |
304 | } | |
ba51dced | 305 | #endif |
0a488a53 | 306 | |
de5397ad FY |
307 | static __init int setup_disable_smep(char *arg) |
308 | { | |
b2cc2a07 | 309 | setup_clear_cpu_cap(X86_FEATURE_SMEP); |
0f6ff2bc DH |
310 | /* Check for things that depend on SMEP being enabled: */ |
311 | check_mpx_erratum(&boot_cpu_data); | |
de5397ad FY |
312 | return 1; |
313 | } | |
314 | __setup("nosmep", setup_disable_smep); | |
315 | ||
b2cc2a07 | 316 | static __always_inline void setup_smep(struct cpuinfo_x86 *c) |
de5397ad | 317 | { |
b2cc2a07 | 318 | if (cpu_has(c, X86_FEATURE_SMEP)) |
375074cc | 319 | cr4_set_bits(X86_CR4_SMEP); |
de5397ad FY |
320 | } |
321 | ||
52b6179a PA |
322 | static __init int setup_disable_smap(char *arg) |
323 | { | |
b2cc2a07 | 324 | setup_clear_cpu_cap(X86_FEATURE_SMAP); |
52b6179a PA |
325 | return 1; |
326 | } | |
327 | __setup("nosmap", setup_disable_smap); | |
328 | ||
b2cc2a07 PA |
329 | static __always_inline void setup_smap(struct cpuinfo_x86 *c) |
330 | { | |
581b7f15 | 331 | unsigned long eflags = native_save_fl(); |
b2cc2a07 PA |
332 | |
333 | /* This should have been cleared long ago */ | |
b2cc2a07 PA |
334 | BUG_ON(eflags & X86_EFLAGS_AC); |
335 | ||
03bbd596 PA |
336 | if (cpu_has(c, X86_FEATURE_SMAP)) { |
337 | #ifdef CONFIG_X86_SMAP | |
375074cc | 338 | cr4_set_bits(X86_CR4_SMAP); |
03bbd596 | 339 | #else |
375074cc | 340 | cr4_clear_bits(X86_CR4_SMAP); |
03bbd596 PA |
341 | #endif |
342 | } | |
de5397ad FY |
343 | } |
344 | ||
aa35f896 RN |
345 | static __always_inline void setup_umip(struct cpuinfo_x86 *c) |
346 | { | |
347 | /* Check the boot processor, plus build option for UMIP. */ | |
348 | if (!cpu_feature_enabled(X86_FEATURE_UMIP)) | |
349 | goto out; | |
350 | ||
351 | /* Check the current processor's cpuid bits. */ | |
352 | if (!cpu_has(c, X86_FEATURE_UMIP)) | |
353 | goto out; | |
354 | ||
355 | cr4_set_bits(X86_CR4_UMIP); | |
356 | ||
438cbf88 | 357 | pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n"); |
770c7755 | 358 | |
aa35f896 RN |
359 | return; |
360 | ||
361 | out: | |
362 | /* | |
363 | * Make sure UMIP is disabled in case it was enabled in a | |
364 | * previous boot (e.g., via kexec). | |
365 | */ | |
366 | cr4_clear_bits(X86_CR4_UMIP); | |
367 | } | |
368 | ||
873d50d5 KC |
369 | DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); |
370 | EXPORT_SYMBOL(cr_pinning); | |
371 | unsigned long cr4_pinned_bits __ro_after_init; | |
372 | EXPORT_SYMBOL(cr4_pinned_bits); | |
373 | ||
374 | /* | |
375 | * Once CPU feature detection is finished (and boot params have been | |
376 | * parsed), record any of the sensitive CR bits that are set, and | |
377 | * enable CR pinning. | |
378 | */ | |
379 | static void __init setup_cr_pinning(void) | |
380 | { | |
381 | unsigned long mask; | |
382 | ||
383 | mask = (X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP); | |
384 | cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & mask; | |
385 | static_key_enable(&cr_pinning.key); | |
386 | } | |
387 | ||
06976945 DH |
388 | /* |
389 | * Protection Keys are not available in 32-bit mode. | |
390 | */ | |
391 | static bool pku_disabled; | |
392 | ||
393 | static __always_inline void setup_pku(struct cpuinfo_x86 *c) | |
394 | { | |
a5eff725 SAS |
395 | struct pkru_state *pk; |
396 | ||
e8df1a95 DH |
397 | /* check the boot processor, plus compile options for PKU: */ |
398 | if (!cpu_feature_enabled(X86_FEATURE_PKU)) | |
399 | return; | |
400 | /* checks the actual processor's cpuid bits: */ | |
06976945 DH |
401 | if (!cpu_has(c, X86_FEATURE_PKU)) |
402 | return; | |
403 | if (pku_disabled) | |
404 | return; | |
405 | ||
406 | cr4_set_bits(X86_CR4_PKE); | |
a5eff725 SAS |
407 | pk = get_xsave_addr(&init_fpstate.xsave, XFEATURE_PKRU); |
408 | if (pk) | |
409 | pk->pkru = init_pkru_value; | |
06976945 DH |
410 | /* |
411 | * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE | |
412 | * cpuid bit to be set. We need to ensure that we | |
413 | * update that bit in this CPU's "cpu_info". | |
414 | */ | |
415 | get_cpu_cap(c); | |
416 | } | |
417 | ||
418 | #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS | |
419 | static __init int setup_disable_pku(char *arg) | |
420 | { | |
421 | /* | |
422 | * Do not clear the X86_FEATURE_PKU bit. All of the | |
423 | * runtime checks are against OSPKE so clearing the | |
424 | * bit does nothing. | |
425 | * | |
426 | * This way, we will see "pku" in cpuinfo, but not | |
427 | * "ospke", which is exactly what we want. It shows | |
428 | * that the CPU has PKU, but the OS has not enabled it. | |
429 | * This happens to be exactly how a system would look | |
430 | * if we disabled the config option. | |
431 | */ | |
432 | pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); | |
433 | pku_disabled = true; | |
434 | return 1; | |
435 | } | |
436 | __setup("nopku", setup_disable_pku); | |
437 | #endif /* CONFIG_X86_64 */ | |
438 | ||
b38b0665 PA |
439 | /* |
440 | * Some CPU features depend on higher CPUID levels, which may not always | |
441 | * be available due to CPUID level capping or broken virtualization | |
442 | * software. Add those features to this table to auto-disable them. | |
443 | */ | |
444 | struct cpuid_dependent_feature { | |
445 | u32 feature; | |
446 | u32 level; | |
447 | }; | |
0f3fa48a | 448 | |
148f9bb8 | 449 | static const struct cpuid_dependent_feature |
b38b0665 PA |
450 | cpuid_dependent_features[] = { |
451 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
452 | { X86_FEATURE_DCA, 0x00000009 }, | |
453 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
454 | { 0, 0 } | |
455 | }; | |
456 | ||
148f9bb8 | 457 | static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) |
b38b0665 PA |
458 | { |
459 | const struct cpuid_dependent_feature *df; | |
9766cdbc | 460 | |
b38b0665 | 461 | for (df = cpuid_dependent_features; df->feature; df++) { |
0f3fa48a IM |
462 | |
463 | if (!cpu_has(c, df->feature)) | |
464 | continue; | |
b38b0665 PA |
465 | /* |
466 | * Note: cpuid_level is set to -1 if unavailable, but | |
467 | * extended_extended_level is set to 0 if unavailable | |
468 | * and the legitimate extended levels are all negative | |
469 | * when signed; hence the weird messing around with | |
470 | * signs here... | |
471 | */ | |
0f3fa48a | 472 | if (!((s32)df->level < 0 ? |
f6db44df | 473 | (u32)df->level > (u32)c->extended_cpuid_level : |
0f3fa48a IM |
474 | (s32)df->level > (s32)c->cpuid_level)) |
475 | continue; | |
476 | ||
477 | clear_cpu_cap(c, df->feature); | |
478 | if (!warn) | |
479 | continue; | |
480 | ||
1b74dde7 CY |
481 | pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", |
482 | x86_cap_flag(df->feature), df->level); | |
b38b0665 | 483 | } |
f6db44df | 484 | } |
b38b0665 | 485 | |
102bbe3a YL |
486 | /* |
487 | * Naming convention should be: <Name> [(<Codename>)] | |
488 | * This table only is used unless init_<vendor>() below doesn't set it; | |
0f3fa48a IM |
489 | * in particular, if CPUID levels 0x80000002..4 are supported, this |
490 | * isn't used | |
102bbe3a YL |
491 | */ |
492 | ||
493 | /* Look up CPU names by table lookup. */ | |
148f9bb8 | 494 | static const char *table_lookup_model(struct cpuinfo_x86 *c) |
102bbe3a | 495 | { |
09dc68d9 JB |
496 | #ifdef CONFIG_X86_32 |
497 | const struct legacy_cpu_model_info *info; | |
102bbe3a YL |
498 | |
499 | if (c->x86_model >= 16) | |
500 | return NULL; /* Range check */ | |
501 | ||
502 | if (!this_cpu) | |
503 | return NULL; | |
504 | ||
09dc68d9 | 505 | info = this_cpu->legacy_models; |
102bbe3a | 506 | |
09dc68d9 | 507 | while (info->family) { |
102bbe3a YL |
508 | if (info->family == c->x86) |
509 | return info->model_names[c->x86_model]; | |
510 | info++; | |
511 | } | |
09dc68d9 | 512 | #endif |
102bbe3a YL |
513 | return NULL; /* Not found */ |
514 | } | |
515 | ||
6cbd2171 TG |
516 | __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; |
517 | __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; | |
7d851c8d | 518 | |
11e3a840 JF |
519 | void load_percpu_segment(int cpu) |
520 | { | |
521 | #ifdef CONFIG_X86_32 | |
522 | loadsegment(fs, __KERNEL_PERCPU); | |
523 | #else | |
45e876f7 | 524 | __loadsegment_simple(gs, 0); |
35060ed6 | 525 | wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); |
11e3a840 | 526 | #endif |
60a5317f | 527 | load_stack_canary_segment(); |
11e3a840 JF |
528 | } |
529 | ||
72f5e08d AL |
530 | #ifdef CONFIG_X86_32 |
531 | /* The 32-bit entry code needs to find cpu_entry_area. */ | |
532 | DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); | |
533 | #endif | |
534 | ||
45fc8757 TG |
535 | /* Load the original GDT from the per-cpu structure */ |
536 | void load_direct_gdt(int cpu) | |
537 | { | |
538 | struct desc_ptr gdt_descr; | |
539 | ||
540 | gdt_descr.address = (long)get_cpu_gdt_rw(cpu); | |
541 | gdt_descr.size = GDT_SIZE - 1; | |
542 | load_gdt(&gdt_descr); | |
543 | } | |
544 | EXPORT_SYMBOL_GPL(load_direct_gdt); | |
545 | ||
69218e47 TG |
546 | /* Load a fixmap remapping of the per-cpu GDT */ |
547 | void load_fixmap_gdt(int cpu) | |
548 | { | |
549 | struct desc_ptr gdt_descr; | |
550 | ||
551 | gdt_descr.address = (long)get_cpu_gdt_ro(cpu); | |
552 | gdt_descr.size = GDT_SIZE - 1; | |
553 | load_gdt(&gdt_descr); | |
554 | } | |
45fc8757 | 555 | EXPORT_SYMBOL_GPL(load_fixmap_gdt); |
69218e47 | 556 | |
0f3fa48a IM |
557 | /* |
558 | * Current gdt points %fs at the "master" per-cpu area: after this, | |
559 | * it's on the real one. | |
560 | */ | |
552be871 | 561 | void switch_to_new_gdt(int cpu) |
9d31d35b | 562 | { |
45fc8757 TG |
563 | /* Load the original GDT */ |
564 | load_direct_gdt(cpu); | |
2697fbd5 | 565 | /* Reload the per-cpu base */ |
11e3a840 | 566 | load_percpu_segment(cpu); |
9d31d35b YL |
567 | } |
568 | ||
148f9bb8 | 569 | static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 570 | |
148f9bb8 | 571 | static void get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
572 | { |
573 | unsigned int *v; | |
ee098e1a | 574 | char *p, *q, *s; |
1da177e4 | 575 | |
3da99c97 | 576 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 577 | return; |
1da177e4 | 578 | |
0f3fa48a | 579 | v = (unsigned int *)c->x86_model_id; |
1da177e4 LT |
580 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); |
581 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
582 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
583 | c->x86_model_id[48] = 0; | |
584 | ||
ee098e1a BP |
585 | /* Trim whitespace */ |
586 | p = q = s = &c->x86_model_id[0]; | |
587 | ||
588 | while (*p == ' ') | |
589 | p++; | |
590 | ||
591 | while (*p) { | |
592 | /* Note the last non-whitespace index */ | |
593 | if (!isspace(*p)) | |
594 | s = q; | |
595 | ||
596 | *q++ = *p++; | |
597 | } | |
598 | ||
599 | *(s + 1) = '\0'; | |
1da177e4 LT |
600 | } |
601 | ||
9305bd6c | 602 | void detect_num_cpu_cores(struct cpuinfo_x86 *c) |
2cc61be6 DW |
603 | { |
604 | unsigned int eax, ebx, ecx, edx; | |
605 | ||
9305bd6c | 606 | c->x86_max_cores = 1; |
2cc61be6 | 607 | if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) |
9305bd6c | 608 | return; |
2cc61be6 DW |
609 | |
610 | cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); | |
611 | if (eax & 0x1f) | |
9305bd6c | 612 | c->x86_max_cores = (eax >> 26) + 1; |
2cc61be6 DW |
613 | } |
614 | ||
148f9bb8 | 615 | void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) |
1da177e4 | 616 | { |
9d31d35b | 617 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 618 | |
3da99c97 | 619 | n = c->extended_cpuid_level; |
1da177e4 LT |
620 | |
621 | if (n >= 0x80000005) { | |
9d31d35b | 622 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
9d31d35b | 623 | c->x86_cache_size = (ecx>>24) + (edx>>24); |
140fc727 YL |
624 | #ifdef CONFIG_X86_64 |
625 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
626 | c->x86_tlbsize = 0; | |
627 | #endif | |
1da177e4 LT |
628 | } |
629 | ||
630 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
631 | return; | |
632 | ||
0a488a53 | 633 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 634 | l2size = ecx >> 16; |
34048c9e | 635 | |
140fc727 YL |
636 | #ifdef CONFIG_X86_64 |
637 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
638 | #else | |
1da177e4 | 639 | /* do processor-specific cache resizing */ |
09dc68d9 JB |
640 | if (this_cpu->legacy_cache_size) |
641 | l2size = this_cpu->legacy_cache_size(c, l2size); | |
1da177e4 LT |
642 | |
643 | /* Allow user to override all this if necessary. */ | |
644 | if (cachesize_override != -1) | |
645 | l2size = cachesize_override; | |
646 | ||
34048c9e | 647 | if (l2size == 0) |
1da177e4 | 648 | return; /* Again, no L2 cache is possible */ |
140fc727 | 649 | #endif |
1da177e4 LT |
650 | |
651 | c->x86_cache_size = l2size; | |
1da177e4 LT |
652 | } |
653 | ||
e0ba94f1 AS |
654 | u16 __read_mostly tlb_lli_4k[NR_INFO]; |
655 | u16 __read_mostly tlb_lli_2m[NR_INFO]; | |
656 | u16 __read_mostly tlb_lli_4m[NR_INFO]; | |
657 | u16 __read_mostly tlb_lld_4k[NR_INFO]; | |
658 | u16 __read_mostly tlb_lld_2m[NR_INFO]; | |
659 | u16 __read_mostly tlb_lld_4m[NR_INFO]; | |
dd360393 | 660 | u16 __read_mostly tlb_lld_1g[NR_INFO]; |
e0ba94f1 | 661 | |
f94fe119 | 662 | static void cpu_detect_tlb(struct cpuinfo_x86 *c) |
e0ba94f1 AS |
663 | { |
664 | if (this_cpu->c_detect_tlb) | |
665 | this_cpu->c_detect_tlb(c); | |
666 | ||
f94fe119 | 667 | pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", |
e0ba94f1 | 668 | tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], |
f94fe119 SH |
669 | tlb_lli_4m[ENTRIES]); |
670 | ||
671 | pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", | |
672 | tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], | |
673 | tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); | |
e0ba94f1 AS |
674 | } |
675 | ||
545401f4 | 676 | int detect_ht_early(struct cpuinfo_x86 *c) |
1da177e4 | 677 | { |
c8e56d20 | 678 | #ifdef CONFIG_SMP |
0a488a53 | 679 | u32 eax, ebx, ecx, edx; |
1da177e4 | 680 | |
0a488a53 | 681 | if (!cpu_has(c, X86_FEATURE_HT)) |
545401f4 | 682 | return -1; |
1da177e4 | 683 | |
0a488a53 | 684 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
545401f4 | 685 | return -1; |
1da177e4 | 686 | |
1cd78776 | 687 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
545401f4 | 688 | return -1; |
1da177e4 | 689 | |
0a488a53 | 690 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 691 | |
9d31d35b | 692 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
545401f4 | 693 | if (smp_num_siblings == 1) |
1b74dde7 | 694 | pr_info_once("CPU0: Hyper-Threading is disabled\n"); |
545401f4 TG |
695 | #endif |
696 | return 0; | |
697 | } | |
9d31d35b | 698 | |
545401f4 TG |
699 | void detect_ht(struct cpuinfo_x86 *c) |
700 | { | |
701 | #ifdef CONFIG_SMP | |
702 | int index_msb, core_bits; | |
55e6d279 | 703 | |
545401f4 | 704 | if (detect_ht_early(c) < 0) |
55e6d279 | 705 | return; |
9d31d35b | 706 | |
0f3fa48a IM |
707 | index_msb = get_count_order(smp_num_siblings); |
708 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); | |
9d31d35b | 709 | |
0f3fa48a | 710 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
9d31d35b | 711 | |
0f3fa48a | 712 | index_msb = get_count_order(smp_num_siblings); |
9d31d35b | 713 | |
0f3fa48a | 714 | core_bits = get_count_order(c->x86_max_cores); |
9d31d35b | 715 | |
0f3fa48a IM |
716 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & |
717 | ((1 << core_bits) - 1); | |
9d31d35b | 718 | #endif |
97e4db7c | 719 | } |
1da177e4 | 720 | |
148f9bb8 | 721 | static void get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
722 | { |
723 | char *v = c->x86_vendor_id; | |
0f3fa48a | 724 | int i; |
1da177e4 LT |
725 | |
726 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
727 | if (!cpu_devs[i]) |
728 | break; | |
729 | ||
730 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
731 | (cpu_devs[i]->c_ident[1] && | |
732 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
0f3fa48a | 733 | |
10a434fc YL |
734 | this_cpu = cpu_devs[i]; |
735 | c->x86_vendor = this_cpu->c_x86_vendor; | |
736 | return; | |
1da177e4 LT |
737 | } |
738 | } | |
10a434fc | 739 | |
1b74dde7 CY |
740 | pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ |
741 | "CPU: Your system may be unstable.\n", v); | |
10a434fc | 742 | |
fe38d855 CE |
743 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
744 | this_cpu = &default_cpu; | |
1da177e4 LT |
745 | } |
746 | ||
148f9bb8 | 747 | void cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 748 | { |
1da177e4 | 749 | /* Get vendor name */ |
4a148513 HH |
750 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
751 | (unsigned int *)&c->x86_vendor_id[0], | |
752 | (unsigned int *)&c->x86_vendor_id[8], | |
753 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 754 | |
1da177e4 | 755 | c->x86 = 4; |
9d31d35b | 756 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
757 | if (c->cpuid_level >= 0x00000001) { |
758 | u32 junk, tfms, cap0, misc; | |
0f3fa48a | 759 | |
1da177e4 | 760 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
99f925ce BP |
761 | c->x86 = x86_family(tfms); |
762 | c->x86_model = x86_model(tfms); | |
b399151c | 763 | c->x86_stepping = x86_stepping(tfms); |
0f3fa48a | 764 | |
d4387bd3 | 765 | if (cap0 & (1<<19)) { |
d4387bd3 | 766 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 767 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 768 | } |
1da177e4 | 769 | } |
1da177e4 | 770 | } |
3da99c97 | 771 | |
8bf1ebca AL |
772 | static void apply_forced_caps(struct cpuinfo_x86 *c) |
773 | { | |
774 | int i; | |
775 | ||
6cbd2171 | 776 | for (i = 0; i < NCAPINTS + NBUGINTS; i++) { |
8bf1ebca AL |
777 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; |
778 | c->x86_capability[i] |= cpu_caps_set[i]; | |
779 | } | |
780 | } | |
781 | ||
7fcae111 DW |
782 | static void init_speculation_control(struct cpuinfo_x86 *c) |
783 | { | |
784 | /* | |
785 | * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, | |
786 | * and they also have a different bit for STIBP support. Also, | |
787 | * a hypervisor might have set the individual AMD bits even on | |
788 | * Intel CPUs, for finer-grained selection of what's available. | |
7fcae111 DW |
789 | */ |
790 | if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { | |
791 | set_cpu_cap(c, X86_FEATURE_IBRS); | |
792 | set_cpu_cap(c, X86_FEATURE_IBPB); | |
7eb8956a | 793 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); |
7fcae111 | 794 | } |
e7c587da | 795 | |
7fcae111 DW |
796 | if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) |
797 | set_cpu_cap(c, X86_FEATURE_STIBP); | |
e7c587da | 798 | |
bc226f07 TL |
799 | if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || |
800 | cpu_has(c, X86_FEATURE_VIRT_SSBD)) | |
52817587 TG |
801 | set_cpu_cap(c, X86_FEATURE_SSBD); |
802 | ||
7eb8956a | 803 | if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { |
e7c587da | 804 | set_cpu_cap(c, X86_FEATURE_IBRS); |
7eb8956a TG |
805 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); |
806 | } | |
e7c587da BP |
807 | |
808 | if (cpu_has(c, X86_FEATURE_AMD_IBPB)) | |
809 | set_cpu_cap(c, X86_FEATURE_IBPB); | |
810 | ||
7eb8956a | 811 | if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { |
e7c587da | 812 | set_cpu_cap(c, X86_FEATURE_STIBP); |
7eb8956a TG |
813 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); |
814 | } | |
6ac2f49e KRW |
815 | |
816 | if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { | |
817 | set_cpu_cap(c, X86_FEATURE_SSBD); | |
818 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); | |
819 | clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); | |
820 | } | |
7fcae111 DW |
821 | } |
822 | ||
45fc56e6 BP |
823 | static void init_cqm(struct cpuinfo_x86 *c) |
824 | { | |
acec0ce0 FY |
825 | if (!cpu_has(c, X86_FEATURE_CQM_LLC)) { |
826 | c->x86_cache_max_rmid = -1; | |
827 | c->x86_cache_occ_scale = -1; | |
828 | return; | |
829 | } | |
45fc56e6 | 830 | |
acec0ce0 FY |
831 | /* will be overridden if occupancy monitoring exists */ |
832 | c->x86_cache_max_rmid = cpuid_ebx(0xf); | |
833 | ||
834 | if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC) || | |
835 | cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL) || | |
836 | cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)) { | |
837 | u32 eax, ebx, ecx, edx; | |
838 | ||
839 | /* QoS sub-leaf, EAX=0Fh, ECX=1 */ | |
840 | cpuid_count(0xf, 1, &eax, &ebx, &ecx, &edx); | |
841 | ||
842 | c->x86_cache_max_rmid = ecx; | |
843 | c->x86_cache_occ_scale = ebx; | |
45fc56e6 BP |
844 | } |
845 | } | |
846 | ||
148f9bb8 | 847 | void get_cpu_cap(struct cpuinfo_x86 *c) |
093af8d7 | 848 | { |
39c06df4 | 849 | u32 eax, ebx, ecx, edx; |
093af8d7 | 850 | |
3da99c97 YL |
851 | /* Intel-defined flags: level 0x00000001 */ |
852 | if (c->cpuid_level >= 0x00000001) { | |
39c06df4 | 853 | cpuid(0x00000001, &eax, &ebx, &ecx, &edx); |
0f3fa48a | 854 | |
39c06df4 BP |
855 | c->x86_capability[CPUID_1_ECX] = ecx; |
856 | c->x86_capability[CPUID_1_EDX] = edx; | |
3da99c97 | 857 | } |
093af8d7 | 858 | |
3df8d920 AL |
859 | /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ |
860 | if (c->cpuid_level >= 0x00000006) | |
861 | c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); | |
862 | ||
bdc802dc PA |
863 | /* Additional Intel-defined flags: level 0x00000007 */ |
864 | if (c->cpuid_level >= 0x00000007) { | |
bdc802dc | 865 | cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); |
39c06df4 | 866 | c->x86_capability[CPUID_7_0_EBX] = ebx; |
dfb4a70f | 867 | c->x86_capability[CPUID_7_ECX] = ecx; |
95ca0ee8 | 868 | c->x86_capability[CPUID_7_EDX] = edx; |
b302e4b1 FY |
869 | |
870 | /* Check valid sub-leaf index before accessing it */ | |
871 | if (eax >= 1) { | |
872 | cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx); | |
873 | c->x86_capability[CPUID_7_1_EAX] = eax; | |
874 | } | |
bdc802dc PA |
875 | } |
876 | ||
6229ad27 FY |
877 | /* Extended state features: level 0x0000000d */ |
878 | if (c->cpuid_level >= 0x0000000d) { | |
6229ad27 FY |
879 | cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); |
880 | ||
39c06df4 | 881 | c->x86_capability[CPUID_D_1_EAX] = eax; |
6229ad27 FY |
882 | } |
883 | ||
3da99c97 | 884 | /* AMD-defined flags: level 0x80000001 */ |
39c06df4 BP |
885 | eax = cpuid_eax(0x80000000); |
886 | c->extended_cpuid_level = eax; | |
887 | ||
888 | if ((eax & 0xffff0000) == 0x80000000) { | |
889 | if (eax >= 0x80000001) { | |
890 | cpuid(0x80000001, &eax, &ebx, &ecx, &edx); | |
0f3fa48a | 891 | |
39c06df4 BP |
892 | c->x86_capability[CPUID_8000_0001_ECX] = ecx; |
893 | c->x86_capability[CPUID_8000_0001_EDX] = edx; | |
093af8d7 | 894 | } |
093af8d7 | 895 | } |
093af8d7 | 896 | |
71faad43 YG |
897 | if (c->extended_cpuid_level >= 0x80000007) { |
898 | cpuid(0x80000007, &eax, &ebx, &ecx, &edx); | |
899 | ||
900 | c->x86_capability[CPUID_8000_0007_EBX] = ebx; | |
901 | c->x86_power = edx; | |
902 | } | |
903 | ||
c65732e4 TG |
904 | if (c->extended_cpuid_level >= 0x80000008) { |
905 | cpuid(0x80000008, &eax, &ebx, &ecx, &edx); | |
906 | c->x86_capability[CPUID_8000_0008_EBX] = ebx; | |
907 | } | |
908 | ||
2ccd71f1 | 909 | if (c->extended_cpuid_level >= 0x8000000a) |
39c06df4 | 910 | c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); |
093af8d7 | 911 | |
1dedefd1 | 912 | init_scattered_cpuid_features(c); |
7fcae111 | 913 | init_speculation_control(c); |
45fc56e6 | 914 | init_cqm(c); |
60d34501 AL |
915 | |
916 | /* | |
917 | * Clear/Set all flags overridden by options, after probe. | |
918 | * This needs to happen each time we re-probe, which may happen | |
919 | * several times during CPU initialization. | |
920 | */ | |
921 | apply_forced_caps(c); | |
093af8d7 | 922 | } |
1da177e4 | 923 | |
405c018a | 924 | void get_cpu_address_sizes(struct cpuinfo_x86 *c) |
d94a155c KS |
925 | { |
926 | u32 eax, ebx, ecx, edx; | |
927 | ||
928 | if (c->extended_cpuid_level >= 0x80000008) { | |
929 | cpuid(0x80000008, &eax, &ebx, &ecx, &edx); | |
930 | ||
931 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
932 | c->x86_phys_bits = eax & 0xff; | |
d94a155c KS |
933 | } |
934 | #ifdef CONFIG_X86_32 | |
935 | else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) | |
936 | c->x86_phys_bits = 36; | |
937 | #endif | |
cc51e542 | 938 | c->x86_cache_bits = c->x86_phys_bits; |
d94a155c KS |
939 | } |
940 | ||
148f9bb8 | 941 | static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
aef93c8b YL |
942 | { |
943 | #ifdef CONFIG_X86_32 | |
944 | int i; | |
945 | ||
946 | /* | |
947 | * First of all, decide if this is a 486 or higher | |
948 | * It's a 486 if we can modify the AC flag | |
949 | */ | |
950 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
951 | c->x86 = 4; | |
952 | else | |
953 | c->x86 = 3; | |
954 | ||
955 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
956 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
957 | c->x86_vendor_id[0] = 0; | |
958 | cpu_devs[i]->c_identify(c); | |
959 | if (c->x86_vendor_id[0]) { | |
960 | get_cpu_vendor(c); | |
961 | break; | |
962 | } | |
963 | } | |
964 | #endif | |
965 | } | |
966 | ||
36ad3513 TG |
967 | #define NO_SPECULATION BIT(0) |
968 | #define NO_MELTDOWN BIT(1) | |
969 | #define NO_SSB BIT(2) | |
970 | #define NO_L1TF BIT(3) | |
ed5194c2 | 971 | #define NO_MDS BIT(4) |
e261f209 | 972 | #define MSBDS_ONLY BIT(5) |
36ad3513 TG |
973 | |
974 | #define VULNWL(_vendor, _family, _model, _whitelist) \ | |
975 | { X86_VENDOR_##_vendor, _family, _model, X86_FEATURE_ANY, _whitelist } | |
976 | ||
977 | #define VULNWL_INTEL(model, whitelist) \ | |
978 | VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist) | |
979 | ||
980 | #define VULNWL_AMD(family, whitelist) \ | |
981 | VULNWL(AMD, family, X86_MODEL_ANY, whitelist) | |
982 | ||
983 | #define VULNWL_HYGON(family, whitelist) \ | |
984 | VULNWL(HYGON, family, X86_MODEL_ANY, whitelist) | |
985 | ||
986 | static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { | |
987 | VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), | |
988 | VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), | |
989 | VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), | |
990 | VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), | |
991 | ||
ed5194c2 | 992 | /* Intel Family 6 */ |
36ad3513 TG |
993 | VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION), |
994 | VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION), | |
995 | VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION), | |
996 | VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION), | |
997 | VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION), | |
998 | ||
e261f209 TG |
999 | VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY), |
1000 | VULNWL_INTEL(ATOM_SILVERMONT_X, NO_SSB | NO_L1TF | MSBDS_ONLY), | |
1001 | VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY), | |
1002 | VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY), | |
1003 | VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY), | |
1004 | VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY), | |
36ad3513 TG |
1005 | |
1006 | VULNWL_INTEL(CORE_YONAH, NO_SSB), | |
1007 | ||
e261f209 | 1008 | VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY), |
36ad3513 | 1009 | |
ed5194c2 AK |
1010 | VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF), |
1011 | VULNWL_INTEL(ATOM_GOLDMONT_X, NO_MDS | NO_L1TF), | |
1012 | VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF), | |
1013 | ||
1014 | /* AMD Family 0xf - 0x12 */ | |
1015 | VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS), | |
1016 | VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS), | |
1017 | VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS), | |
1018 | VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS), | |
36ad3513 TG |
1019 | |
1020 | /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ | |
ed5194c2 AK |
1021 | VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS), |
1022 | VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS), | |
fec9434a DW |
1023 | {} |
1024 | }; | |
1025 | ||
36ad3513 TG |
1026 | static bool __init cpu_matches(unsigned long which) |
1027 | { | |
1028 | const struct x86_cpu_id *m = x86_match_cpu(cpu_vuln_whitelist); | |
c456442c | 1029 | |
36ad3513 TG |
1030 | return m && !!(m->driver_data & which); |
1031 | } | |
17dbca11 | 1032 | |
4a28bfe3 | 1033 | static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) |
fec9434a DW |
1034 | { |
1035 | u64 ia32_cap = 0; | |
1036 | ||
36ad3513 | 1037 | if (cpu_matches(NO_SPECULATION)) |
8ecc4979 DB |
1038 | return; |
1039 | ||
1040 | setup_force_cpu_bug(X86_BUG_SPECTRE_V1); | |
1041 | setup_force_cpu_bug(X86_BUG_SPECTRE_V2); | |
1042 | ||
77243971 KRW |
1043 | if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES)) |
1044 | rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); | |
1045 | ||
36ad3513 | 1046 | if (!cpu_matches(NO_SSB) && !(ia32_cap & ARCH_CAP_SSB_NO) && |
24809860 | 1047 | !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) |
c456442c KRW |
1048 | setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); |
1049 | ||
706d5168 SP |
1050 | if (ia32_cap & ARCH_CAP_IBRS_ALL) |
1051 | setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); | |
1052 | ||
e261f209 | 1053 | if (!cpu_matches(NO_MDS) && !(ia32_cap & ARCH_CAP_MDS_NO)) { |
ed5194c2 | 1054 | setup_force_cpu_bug(X86_BUG_MDS); |
e261f209 TG |
1055 | if (cpu_matches(MSBDS_ONLY)) |
1056 | setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); | |
1057 | } | |
ed5194c2 | 1058 | |
36ad3513 | 1059 | if (cpu_matches(NO_MELTDOWN)) |
4a28bfe3 | 1060 | return; |
fec9434a | 1061 | |
fec9434a DW |
1062 | /* Rogue Data Cache Load? No! */ |
1063 | if (ia32_cap & ARCH_CAP_RDCL_NO) | |
4a28bfe3 | 1064 | return; |
fec9434a | 1065 | |
4a28bfe3 | 1066 | setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); |
17dbca11 | 1067 | |
36ad3513 | 1068 | if (cpu_matches(NO_L1TF)) |
17dbca11 AK |
1069 | return; |
1070 | ||
1071 | setup_force_cpu_bug(X86_BUG_L1TF); | |
fec9434a DW |
1072 | } |
1073 | ||
8990cac6 PT |
1074 | /* |
1075 | * The NOPL instruction is supposed to exist on all CPUs of family >= 6; | |
1076 | * unfortunately, that's not true in practice because of early VIA | |
1077 | * chips and (more importantly) broken virtualizers that are not easy | |
1078 | * to detect. In the latter case it doesn't even *fail* reliably, so | |
1079 | * probing for it doesn't even work. Disable it completely on 32-bit | |
1080 | * unless we can find a reliable way to detect all the broken cases. | |
1081 | * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). | |
1082 | */ | |
9b3661cd | 1083 | static void detect_nopl(void) |
8990cac6 PT |
1084 | { |
1085 | #ifdef CONFIG_X86_32 | |
9b3661cd | 1086 | setup_clear_cpu_cap(X86_FEATURE_NOPL); |
8990cac6 | 1087 | #else |
9b3661cd | 1088 | setup_force_cpu_cap(X86_FEATURE_NOPL); |
8990cac6 PT |
1089 | #endif |
1090 | } | |
1091 | ||
34048c9e PC |
1092 | /* |
1093 | * Do minimum CPU detection early. | |
1094 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
1095 | * cache alignment. | |
1096 | * The others are not touched to avoid unwanted side effects. | |
1097 | * | |
a1652bb8 JD |
1098 | * WARNING: this function is only called on the boot CPU. Don't add code |
1099 | * here that is supposed to run on all CPUs. | |
34048c9e | 1100 | */ |
3da99c97 | 1101 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 1102 | { |
6627d242 YL |
1103 | #ifdef CONFIG_X86_64 |
1104 | c->x86_clflush_size = 64; | |
13c6c532 JB |
1105 | c->x86_phys_bits = 36; |
1106 | c->x86_virt_bits = 48; | |
6627d242 | 1107 | #else |
d4387bd3 | 1108 | c->x86_clflush_size = 32; |
13c6c532 JB |
1109 | c->x86_phys_bits = 32; |
1110 | c->x86_virt_bits = 32; | |
6627d242 | 1111 | #endif |
0a488a53 | 1112 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 1113 | |
0e96f31e | 1114 | memset(&c->x86_capability, 0, sizeof(c->x86_capability)); |
0a488a53 | 1115 | c->extended_cpuid_level = 0; |
d7cd5611 | 1116 | |
2893cc8f MW |
1117 | if (!have_cpuid_p()) |
1118 | identify_cpu_without_cpuid(c); | |
1119 | ||
aef93c8b | 1120 | /* cyrix could have cpuid enabled via c_identify()*/ |
05fb3c19 AL |
1121 | if (have_cpuid_p()) { |
1122 | cpu_detect(c); | |
1123 | get_cpu_vendor(c); | |
1124 | get_cpu_cap(c); | |
d94a155c | 1125 | get_cpu_address_sizes(c); |
78d1b296 | 1126 | setup_force_cpu_cap(X86_FEATURE_CPUID); |
d7cd5611 | 1127 | |
05fb3c19 AL |
1128 | if (this_cpu->c_early_init) |
1129 | this_cpu->c_early_init(c); | |
12cf105c | 1130 | |
05fb3c19 AL |
1131 | c->cpu_index = 0; |
1132 | filter_cpuid_features(c, false); | |
093af8d7 | 1133 | |
05fb3c19 AL |
1134 | if (this_cpu->c_bsp_init) |
1135 | this_cpu->c_bsp_init(c); | |
78d1b296 | 1136 | } else { |
78d1b296 | 1137 | setup_clear_cpu_cap(X86_FEATURE_CPUID); |
05fb3c19 | 1138 | } |
c3b83598 BP |
1139 | |
1140 | setup_force_cpu_cap(X86_FEATURE_ALWAYS); | |
a89f040f | 1141 | |
4a28bfe3 | 1142 | cpu_set_bug_bits(c); |
99c6fa25 | 1143 | |
db52ef74 | 1144 | fpu__init_system(c); |
b8b7abae AL |
1145 | |
1146 | #ifdef CONFIG_X86_32 | |
1147 | /* | |
1148 | * Regardless of whether PCID is enumerated, the SDM says | |
1149 | * that it can't be enabled in 32-bit mode. | |
1150 | */ | |
1151 | setup_clear_cpu_cap(X86_FEATURE_PCID); | |
1152 | #endif | |
372fddf7 KS |
1153 | |
1154 | /* | |
1155 | * Later in the boot process pgtable_l5_enabled() relies on | |
1156 | * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not | |
1157 | * enabled by this point we need to clear the feature bit to avoid | |
1158 | * false-positives at the later stage. | |
1159 | * | |
1160 | * pgtable_l5_enabled() can be false here for several reasons: | |
1161 | * - 5-level paging is disabled compile-time; | |
1162 | * - it's 32-bit kernel; | |
1163 | * - machine doesn't support 5-level paging; | |
1164 | * - user specified 'no5lvl' in kernel command line. | |
1165 | */ | |
1166 | if (!pgtable_l5_enabled()) | |
1167 | setup_clear_cpu_cap(X86_FEATURE_LA57); | |
8990cac6 | 1168 | |
9b3661cd | 1169 | detect_nopl(); |
d7cd5611 RR |
1170 | } |
1171 | ||
9d31d35b YL |
1172 | void __init early_cpu_init(void) |
1173 | { | |
02dde8b4 | 1174 | const struct cpu_dev *const *cdev; |
10a434fc YL |
1175 | int count = 0; |
1176 | ||
ac23f253 | 1177 | #ifdef CONFIG_PROCESSOR_SELECT |
1b74dde7 | 1178 | pr_info("KERNEL supported cpus:\n"); |
31c997ca IM |
1179 | #endif |
1180 | ||
10a434fc | 1181 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { |
02dde8b4 | 1182 | const struct cpu_dev *cpudev = *cdev; |
9d31d35b | 1183 | |
10a434fc YL |
1184 | if (count >= X86_VENDOR_NUM) |
1185 | break; | |
1186 | cpu_devs[count] = cpudev; | |
1187 | count++; | |
1188 | ||
ac23f253 | 1189 | #ifdef CONFIG_PROCESSOR_SELECT |
31c997ca IM |
1190 | { |
1191 | unsigned int j; | |
1192 | ||
1193 | for (j = 0; j < 2; j++) { | |
1194 | if (!cpudev->c_ident[j]) | |
1195 | continue; | |
1b74dde7 | 1196 | pr_info(" %s %s\n", cpudev->c_vendor, |
31c997ca IM |
1197 | cpudev->c_ident[j]); |
1198 | } | |
10a434fc | 1199 | } |
0388423d | 1200 | #endif |
10a434fc | 1201 | } |
9d31d35b | 1202 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 1203 | } |
093af8d7 | 1204 | |
7a5d6704 AL |
1205 | static void detect_null_seg_behavior(struct cpuinfo_x86 *c) |
1206 | { | |
1207 | #ifdef CONFIG_X86_64 | |
58a5aac5 | 1208 | /* |
7a5d6704 AL |
1209 | * Empirically, writing zero to a segment selector on AMD does |
1210 | * not clear the base, whereas writing zero to a segment | |
1211 | * selector on Intel does clear the base. Intel's behavior | |
1212 | * allows slightly faster context switches in the common case | |
1213 | * where GS is unused by the prev and next threads. | |
58a5aac5 | 1214 | * |
7a5d6704 AL |
1215 | * Since neither vendor documents this anywhere that I can see, |
1216 | * detect it directly instead of hardcoding the choice by | |
1217 | * vendor. | |
1218 | * | |
1219 | * I've designated AMD's behavior as the "bug" because it's | |
1220 | * counterintuitive and less friendly. | |
58a5aac5 | 1221 | */ |
7a5d6704 AL |
1222 | |
1223 | unsigned long old_base, tmp; | |
1224 | rdmsrl(MSR_FS_BASE, old_base); | |
1225 | wrmsrl(MSR_FS_BASE, 1); | |
1226 | loadsegment(fs, 0); | |
1227 | rdmsrl(MSR_FS_BASE, tmp); | |
1228 | if (tmp != 0) | |
1229 | set_cpu_bug(c, X86_BUG_NULL_SEG); | |
1230 | wrmsrl(MSR_FS_BASE, old_base); | |
366d4a43 | 1231 | #endif |
d7cd5611 RR |
1232 | } |
1233 | ||
148f9bb8 | 1234 | static void generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 1235 | { |
aef93c8b | 1236 | c->extended_cpuid_level = 0; |
1da177e4 | 1237 | |
3da99c97 | 1238 | if (!have_cpuid_p()) |
aef93c8b | 1239 | identify_cpu_without_cpuid(c); |
1d67953f | 1240 | |
aef93c8b | 1241 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 1242 | if (!have_cpuid_p()) |
aef93c8b | 1243 | return; |
1da177e4 | 1244 | |
3da99c97 | 1245 | cpu_detect(c); |
1da177e4 | 1246 | |
3da99c97 | 1247 | get_cpu_vendor(c); |
1da177e4 | 1248 | |
3da99c97 | 1249 | get_cpu_cap(c); |
1da177e4 | 1250 | |
d94a155c KS |
1251 | get_cpu_address_sizes(c); |
1252 | ||
3da99c97 YL |
1253 | if (c->cpuid_level >= 0x00000001) { |
1254 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e | 1255 | #ifdef CONFIG_X86_32 |
c8e56d20 | 1256 | # ifdef CONFIG_SMP |
cb8cc442 | 1257 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 1258 | # else |
3da99c97 | 1259 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
1260 | # endif |
1261 | #endif | |
b89d3b3e | 1262 | c->phys_proc_id = c->initial_apicid; |
3da99c97 | 1263 | } |
1da177e4 | 1264 | |
1b05d60d | 1265 | get_model_name(c); /* Default name */ |
1da177e4 | 1266 | |
7a5d6704 | 1267 | detect_null_seg_behavior(c); |
0230bb03 AL |
1268 | |
1269 | /* | |
1270 | * ESPFIX is a strange bug. All real CPUs have it. Paravirt | |
1271 | * systems that run Linux at CPL > 0 may or may not have the | |
1272 | * issue, but, even if they have the issue, there's absolutely | |
1273 | * nothing we can do about it because we can't use the real IRET | |
1274 | * instruction. | |
1275 | * | |
1276 | * NB: For the time being, only 32-bit kernels support | |
1277 | * X86_BUG_ESPFIX as such. 64-bit kernels directly choose | |
1278 | * whether to apply espfix using paravirt hooks. If any | |
1279 | * non-paravirt system ever shows up that does *not* have the | |
1280 | * ESPFIX issue, we can change this. | |
1281 | */ | |
1282 | #ifdef CONFIG_X86_32 | |
9bad5658 | 1283 | # ifdef CONFIG_PARAVIRT_XXL |
0230bb03 AL |
1284 | do { |
1285 | extern void native_iret(void); | |
5c83511b | 1286 | if (pv_ops.cpu.iret == native_iret) |
0230bb03 AL |
1287 | set_cpu_bug(c, X86_BUG_ESPFIX); |
1288 | } while (0); | |
1289 | # else | |
1290 | set_cpu_bug(c, X86_BUG_ESPFIX); | |
1291 | # endif | |
1292 | #endif | |
1da177e4 | 1293 | } |
1da177e4 | 1294 | |
cbc82b17 PWJ |
1295 | static void x86_init_cache_qos(struct cpuinfo_x86 *c) |
1296 | { | |
1297 | /* | |
1298 | * The heavy lifting of max_rmid and cache_occ_scale are handled | |
1299 | * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu | |
1300 | * in case CQM bits really aren't there in this CPU. | |
1301 | */ | |
1302 | if (c != &boot_cpu_data) { | |
1303 | boot_cpu_data.x86_cache_max_rmid = | |
1304 | min(boot_cpu_data.x86_cache_max_rmid, | |
1305 | c->x86_cache_max_rmid); | |
1306 | } | |
1307 | } | |
1308 | ||
d49597fd | 1309 | /* |
9d85eb91 TG |
1310 | * Validate that ACPI/mptables have the same information about the |
1311 | * effective APIC id and update the package map. | |
d49597fd | 1312 | */ |
9d85eb91 | 1313 | static void validate_apic_and_package_id(struct cpuinfo_x86 *c) |
d49597fd TG |
1314 | { |
1315 | #ifdef CONFIG_SMP | |
9d85eb91 | 1316 | unsigned int apicid, cpu = smp_processor_id(); |
d49597fd TG |
1317 | |
1318 | apicid = apic->cpu_present_to_apicid(cpu); | |
d49597fd | 1319 | |
9d85eb91 TG |
1320 | if (apicid != c->apicid) { |
1321 | pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", | |
d49597fd | 1322 | cpu, apicid, c->initial_apicid); |
d49597fd | 1323 | } |
9d85eb91 | 1324 | BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); |
212bf4fd | 1325 | BUG_ON(topology_update_die_map(c->cpu_die_id, cpu)); |
d49597fd TG |
1326 | #else |
1327 | c->logical_proc_id = 0; | |
1328 | #endif | |
1329 | } | |
1330 | ||
1da177e4 LT |
1331 | /* |
1332 | * This does the hard work of actually picking apart the CPU stuff... | |
1333 | */ | |
148f9bb8 | 1334 | static void identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
1335 | { |
1336 | int i; | |
1337 | ||
1338 | c->loops_per_jiffy = loops_per_jiffy; | |
24dbc600 | 1339 | c->x86_cache_size = 0; |
1da177e4 | 1340 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
b399151c | 1341 | c->x86_model = c->x86_stepping = 0; /* So far unknown... */ |
1da177e4 LT |
1342 | c->x86_vendor_id[0] = '\0'; /* Unset */ |
1343 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 1344 | c->x86_max_cores = 1; |
102bbe3a | 1345 | c->x86_coreid_bits = 0; |
79a8b9aa | 1346 | c->cu_id = 0xff; |
11fdd252 | 1347 | #ifdef CONFIG_X86_64 |
102bbe3a | 1348 | c->x86_clflush_size = 64; |
13c6c532 JB |
1349 | c->x86_phys_bits = 36; |
1350 | c->x86_virt_bits = 48; | |
102bbe3a YL |
1351 | #else |
1352 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 1353 | c->x86_clflush_size = 32; |
13c6c532 JB |
1354 | c->x86_phys_bits = 32; |
1355 | c->x86_virt_bits = 32; | |
102bbe3a YL |
1356 | #endif |
1357 | c->x86_cache_alignment = c->x86_clflush_size; | |
0e96f31e | 1358 | memset(&c->x86_capability, 0, sizeof(c->x86_capability)); |
1da177e4 | 1359 | |
1da177e4 LT |
1360 | generic_identify(c); |
1361 | ||
3898534d | 1362 | if (this_cpu->c_identify) |
1da177e4 LT |
1363 | this_cpu->c_identify(c); |
1364 | ||
6a6256f9 | 1365 | /* Clear/Set all flags overridden by options, after probe */ |
8bf1ebca | 1366 | apply_forced_caps(c); |
2759c328 | 1367 | |
102bbe3a | 1368 | #ifdef CONFIG_X86_64 |
cb8cc442 | 1369 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
1370 | #endif |
1371 | ||
1da177e4 LT |
1372 | /* |
1373 | * Vendor-specific initialization. In this section we | |
1374 | * canonicalize the feature flags, meaning if there are | |
1375 | * features a certain CPU supports which CPUID doesn't | |
1376 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
1377 | * we handle them here. | |
1378 | * | |
1379 | * At the end of this section, c->x86_capability better | |
1380 | * indicate the features this CPU genuinely supports! | |
1381 | */ | |
1382 | if (this_cpu->c_init) | |
1383 | this_cpu->c_init(c); | |
1384 | ||
1385 | /* Disable the PN if appropriate */ | |
1386 | squash_the_stupid_serial_number(c); | |
1387 | ||
aa35f896 | 1388 | /* Set up SMEP/SMAP/UMIP */ |
b2cc2a07 PA |
1389 | setup_smep(c); |
1390 | setup_smap(c); | |
aa35f896 | 1391 | setup_umip(c); |
b2cc2a07 | 1392 | |
1da177e4 | 1393 | /* |
0f3fa48a IM |
1394 | * The vendor-specific functions might have changed features. |
1395 | * Now we do "generic changes." | |
1da177e4 LT |
1396 | */ |
1397 | ||
b38b0665 PA |
1398 | /* Filter out anything that depends on CPUID levels we don't have */ |
1399 | filter_cpuid_features(c, true); | |
1400 | ||
1da177e4 | 1401 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 1402 | if (!c->x86_model_id[0]) { |
02dde8b4 | 1403 | const char *p; |
1da177e4 | 1404 | p = table_lookup_model(c); |
34048c9e | 1405 | if (p) |
1da177e4 LT |
1406 | strcpy(c->x86_model_id, p); |
1407 | else | |
1408 | /* Last resort... */ | |
1409 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 1410 | c->x86, c->x86_model); |
1da177e4 LT |
1411 | } |
1412 | ||
102bbe3a YL |
1413 | #ifdef CONFIG_X86_64 |
1414 | detect_ht(c); | |
1415 | #endif | |
1416 | ||
49d859d7 | 1417 | x86_init_rdrand(c); |
cbc82b17 | 1418 | x86_init_cache_qos(c); |
06976945 | 1419 | setup_pku(c); |
3e0c3737 YL |
1420 | |
1421 | /* | |
6a6256f9 | 1422 | * Clear/Set all flags overridden by options, need do it |
3e0c3737 YL |
1423 | * before following smp all cpus cap AND. |
1424 | */ | |
8bf1ebca | 1425 | apply_forced_caps(c); |
3e0c3737 | 1426 | |
1da177e4 LT |
1427 | /* |
1428 | * On SMP, boot_cpu_data holds the common feature set between | |
1429 | * all CPUs; so make sure that we indicate which features are | |
1430 | * common between the CPUs. The first time this routine gets | |
1431 | * executed, c == &boot_cpu_data. | |
1432 | */ | |
34048c9e | 1433 | if (c != &boot_cpu_data) { |
1da177e4 | 1434 | /* AND the already accumulated flags with these */ |
9d31d35b | 1435 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 | 1436 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
65fc985b BP |
1437 | |
1438 | /* OR, i.e. replicate the bug flags */ | |
1439 | for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) | |
1440 | c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; | |
1da177e4 LT |
1441 | } |
1442 | ||
1443 | /* Init Machine Check Exception if available. */ | |
5e09954a | 1444 | mcheck_cpu_init(c); |
30d432df AK |
1445 | |
1446 | select_idle_routine(c); | |
102bbe3a | 1447 | |
de2d9445 | 1448 | #ifdef CONFIG_NUMA |
102bbe3a YL |
1449 | numa_add_cpu(smp_processor_id()); |
1450 | #endif | |
a6c4e076 | 1451 | } |
31ab269a | 1452 | |
8b6c0ab1 IM |
1453 | /* |
1454 | * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions | |
1455 | * on 32-bit kernels: | |
1456 | */ | |
cfda7bb9 AL |
1457 | #ifdef CONFIG_X86_32 |
1458 | void enable_sep_cpu(void) | |
1459 | { | |
8b6c0ab1 IM |
1460 | struct tss_struct *tss; |
1461 | int cpu; | |
cfda7bb9 | 1462 | |
b3edfda4 BP |
1463 | if (!boot_cpu_has(X86_FEATURE_SEP)) |
1464 | return; | |
1465 | ||
8b6c0ab1 | 1466 | cpu = get_cpu(); |
c482feef | 1467 | tss = &per_cpu(cpu_tss_rw, cpu); |
8b6c0ab1 | 1468 | |
8b6c0ab1 | 1469 | /* |
cf9328cc AL |
1470 | * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- |
1471 | * see the big comment in struct x86_hw_tss's definition. | |
8b6c0ab1 | 1472 | */ |
cfda7bb9 AL |
1473 | |
1474 | tss->x86_tss.ss1 = __KERNEL_CS; | |
8b6c0ab1 | 1475 | wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); |
4fe2d8b1 | 1476 | wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); |
4c8cd0c5 | 1477 | wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); |
8b6c0ab1 | 1478 | |
cfda7bb9 AL |
1479 | put_cpu(); |
1480 | } | |
e04d645f GC |
1481 | #endif |
1482 | ||
a6c4e076 JF |
1483 | void __init identify_boot_cpu(void) |
1484 | { | |
1485 | identify_cpu(&boot_cpu_data); | |
102bbe3a | 1486 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1487 | sysenter_setup(); |
6fe940d6 | 1488 | enable_sep_cpu(); |
102bbe3a | 1489 | #endif |
5b556332 | 1490 | cpu_detect_tlb(&boot_cpu_data); |
873d50d5 | 1491 | setup_cr_pinning(); |
a6c4e076 | 1492 | } |
3b520b23 | 1493 | |
148f9bb8 | 1494 | void identify_secondary_cpu(struct cpuinfo_x86 *c) |
a6c4e076 JF |
1495 | { |
1496 | BUG_ON(c == &boot_cpu_data); | |
1497 | identify_cpu(c); | |
102bbe3a | 1498 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1499 | enable_sep_cpu(); |
102bbe3a | 1500 | #endif |
a6c4e076 | 1501 | mtrr_ap_init(); |
9d85eb91 | 1502 | validate_apic_and_package_id(c); |
77243971 | 1503 | x86_spec_ctrl_setup_ap(); |
1da177e4 LT |
1504 | } |
1505 | ||
191679fd AK |
1506 | static __init int setup_noclflush(char *arg) |
1507 | { | |
840d2830 | 1508 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); |
da4aaa7d | 1509 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); |
191679fd AK |
1510 | return 1; |
1511 | } | |
1512 | __setup("noclflush", setup_noclflush); | |
1513 | ||
148f9bb8 | 1514 | void print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 | 1515 | { |
02dde8b4 | 1516 | const char *vendor = NULL; |
1da177e4 | 1517 | |
0f3fa48a | 1518 | if (c->x86_vendor < X86_VENDOR_NUM) { |
1da177e4 | 1519 | vendor = this_cpu->c_vendor; |
0f3fa48a IM |
1520 | } else { |
1521 | if (c->cpuid_level >= 0) | |
1522 | vendor = c->x86_vendor_id; | |
1523 | } | |
1da177e4 | 1524 | |
bd32a8cf | 1525 | if (vendor && !strstr(c->x86_model_id, vendor)) |
1b74dde7 | 1526 | pr_cont("%s ", vendor); |
1da177e4 | 1527 | |
9d31d35b | 1528 | if (c->x86_model_id[0]) |
1b74dde7 | 1529 | pr_cont("%s", c->x86_model_id); |
1da177e4 | 1530 | else |
1b74dde7 | 1531 | pr_cont("%d86", c->x86); |
1da177e4 | 1532 | |
1b74dde7 | 1533 | pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); |
924e101a | 1534 | |
b399151c JZ |
1535 | if (c->x86_stepping || c->cpuid_level >= 0) |
1536 | pr_cont(", stepping: 0x%x)\n", c->x86_stepping); | |
1da177e4 | 1537 | else |
1b74dde7 | 1538 | pr_cont(")\n"); |
1da177e4 LT |
1539 | } |
1540 | ||
0c2a3913 AK |
1541 | /* |
1542 | * clearcpuid= was already parsed in fpu__init_parse_early_param. | |
1543 | * But we need to keep a dummy __setup around otherwise it would | |
1544 | * show up as an environment variable for init. | |
1545 | */ | |
1546 | static __init int setup_clearcpuid(char *arg) | |
ac72e788 | 1547 | { |
ac72e788 AK |
1548 | return 1; |
1549 | } | |
0c2a3913 | 1550 | __setup("clearcpuid=", setup_clearcpuid); |
ac72e788 | 1551 | |
d5494d4f | 1552 | #ifdef CONFIG_X86_64 |
e6401c13 AL |
1553 | DEFINE_PER_CPU_FIRST(struct fixed_percpu_data, |
1554 | fixed_percpu_data) __aligned(PAGE_SIZE) __visible; | |
1555 | EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data); | |
0f3fa48a | 1556 | |
bdf977b3 | 1557 | /* |
a7fcf28d AL |
1558 | * The following percpu variables are hot. Align current_task to |
1559 | * cacheline size such that they fall in the same cacheline. | |
bdf977b3 TH |
1560 | */ |
1561 | DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = | |
1562 | &init_task; | |
1563 | EXPORT_PER_CPU_SYMBOL(current_task); | |
d5494d4f | 1564 | |
e6401c13 | 1565 | DEFINE_PER_CPU(struct irq_stack *, hardirq_stack_ptr); |
277d5b40 | 1566 | DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; |
d5494d4f | 1567 | |
c2daa3be PZ |
1568 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1569 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
1570 | ||
d5494d4f YL |
1571 | /* May not be marked __init: used by software suspend */ |
1572 | void syscall_init(void) | |
1da177e4 | 1573 | { |
31ac34ca | 1574 | wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); |
bf904d27 | 1575 | wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); |
d56fe4bf IM |
1576 | |
1577 | #ifdef CONFIG_IA32_EMULATION | |
47edb651 | 1578 | wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); |
a76c7f46 | 1579 | /* |
487d1edb DV |
1580 | * This only works on Intel CPUs. |
1581 | * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. | |
1582 | * This does not cause SYSENTER to jump to the wrong location, because | |
1583 | * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). | |
a76c7f46 DV |
1584 | */ |
1585 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); | |
8e6b65a1 | 1586 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, |
1587 | (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); | |
4c8cd0c5 | 1588 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); |
d56fe4bf | 1589 | #else |
47edb651 | 1590 | wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); |
6b51311c | 1591 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); |
d56fe4bf IM |
1592 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); |
1593 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); | |
d5494d4f | 1594 | #endif |
03ae5768 | 1595 | |
d5494d4f YL |
1596 | /* Flags to clear on syscall */ |
1597 | wrmsrl(MSR_SYSCALL_MASK, | |
63bcff2a | 1598 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| |
8c7aa698 | 1599 | X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); |
1da177e4 | 1600 | } |
62111195 | 1601 | |
42181186 | 1602 | DEFINE_PER_CPU(int, debug_stack_usage); |
629f4f9d | 1603 | DEFINE_PER_CPU(u32, debug_idt_ctr); |
f8988175 | 1604 | |
228bdaa9 SR |
1605 | void debug_stack_set_zero(void) |
1606 | { | |
629f4f9d SA |
1607 | this_cpu_inc(debug_idt_ctr); |
1608 | load_current_idt(); | |
228bdaa9 | 1609 | } |
0f46efeb | 1610 | NOKPROBE_SYMBOL(debug_stack_set_zero); |
228bdaa9 SR |
1611 | |
1612 | void debug_stack_reset(void) | |
1613 | { | |
629f4f9d | 1614 | if (WARN_ON(!this_cpu_read(debug_idt_ctr))) |
f8988175 | 1615 | return; |
629f4f9d SA |
1616 | if (this_cpu_dec_return(debug_idt_ctr) == 0) |
1617 | load_current_idt(); | |
228bdaa9 | 1618 | } |
0f46efeb | 1619 | NOKPROBE_SYMBOL(debug_stack_reset); |
228bdaa9 | 1620 | |
0f3fa48a | 1621 | #else /* CONFIG_X86_64 */ |
d5494d4f | 1622 | |
bdf977b3 TH |
1623 | DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; |
1624 | EXPORT_PER_CPU_SYMBOL(current_task); | |
c2daa3be PZ |
1625 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1626 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
bdf977b3 | 1627 | |
a7fcf28d AL |
1628 | /* |
1629 | * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find | |
1630 | * the top of the kernel stack. Use an extra percpu variable to track the | |
1631 | * top of the kernel stack directly. | |
1632 | */ | |
1633 | DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = | |
1634 | (unsigned long)&init_thread_union + THREAD_SIZE; | |
1635 | EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); | |
1636 | ||
050e9baa | 1637 | #ifdef CONFIG_STACKPROTECTOR |
53f82452 | 1638 | DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); |
60a5317f | 1639 | #endif |
d5494d4f | 1640 | |
0f3fa48a | 1641 | #endif /* CONFIG_X86_64 */ |
c5413fbe | 1642 | |
9766cdbc JSR |
1643 | /* |
1644 | * Clear all 6 debug registers: | |
1645 | */ | |
1646 | static void clear_all_debug_regs(void) | |
1647 | { | |
1648 | int i; | |
1649 | ||
1650 | for (i = 0; i < 8; i++) { | |
1651 | /* Ignore db4, db5 */ | |
1652 | if ((i == 4) || (i == 5)) | |
1653 | continue; | |
1654 | ||
1655 | set_debugreg(0, i); | |
1656 | } | |
1657 | } | |
c5413fbe | 1658 | |
0bb9fef9 JW |
1659 | #ifdef CONFIG_KGDB |
1660 | /* | |
1661 | * Restore debug regs if using kgdbwait and you have a kernel debugger | |
1662 | * connection established. | |
1663 | */ | |
1664 | static void dbg_restore_debug_regs(void) | |
1665 | { | |
1666 | if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) | |
1667 | arch_kgdb_ops.correct_hw_break(); | |
1668 | } | |
1669 | #else /* ! CONFIG_KGDB */ | |
1670 | #define dbg_restore_debug_regs() | |
1671 | #endif /* ! CONFIG_KGDB */ | |
1672 | ||
ce4b1b16 IM |
1673 | static void wait_for_master_cpu(int cpu) |
1674 | { | |
1675 | #ifdef CONFIG_SMP | |
1676 | /* | |
1677 | * wait for ACK from master CPU before continuing | |
1678 | * with AP initialization | |
1679 | */ | |
1680 | WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); | |
1681 | while (!cpumask_test_cpu(cpu, cpu_callout_mask)) | |
1682 | cpu_relax(); | |
1683 | #endif | |
1684 | } | |
1685 | ||
b2e2ba57 CB |
1686 | #ifdef CONFIG_X86_64 |
1687 | static void setup_getcpu(int cpu) | |
1688 | { | |
22245bdf | 1689 | unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu)); |
b2e2ba57 CB |
1690 | struct desc_struct d = { }; |
1691 | ||
67e87d43 | 1692 | if (boot_cpu_has(X86_FEATURE_RDTSCP)) |
b2e2ba57 CB |
1693 | write_rdtscp_aux(cpudata); |
1694 | ||
1695 | /* Store CPU and node number in limit. */ | |
1696 | d.limit0 = cpudata; | |
1697 | d.limit1 = cpudata >> 16; | |
1698 | ||
1699 | d.type = 5; /* RO data, expand down, accessed */ | |
1700 | d.dpl = 3; /* Visible to user code */ | |
1701 | d.s = 1; /* Not a system segment */ | |
1702 | d.p = 1; /* Present */ | |
1703 | d.d = 1; /* 32-bit */ | |
1704 | ||
22245bdf | 1705 | write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S); |
b2e2ba57 CB |
1706 | } |
1707 | #endif | |
1708 | ||
d2cbcc49 RR |
1709 | /* |
1710 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1711 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1712 | * and IDT. We reload them nevertheless, this function acts as a | |
1713 | * 'CPU state barrier', nothing should get across. | |
1714 | */ | |
1ba76586 | 1715 | #ifdef CONFIG_X86_64 |
0f3fa48a | 1716 | |
148f9bb8 | 1717 | void cpu_init(void) |
1ba76586 | 1718 | { |
f6ef7322 | 1719 | int cpu = raw_smp_processor_id(); |
1ba76586 | 1720 | struct task_struct *me; |
0f3fa48a | 1721 | struct tss_struct *t; |
1ba76586 YL |
1722 | int i; |
1723 | ||
ce4b1b16 IM |
1724 | wait_for_master_cpu(cpu); |
1725 | ||
1e02ce4c AL |
1726 | /* |
1727 | * Initialize the CR4 shadow before doing anything that could | |
1728 | * try to read it. | |
1729 | */ | |
1730 | cr4_init_shadow(); | |
1731 | ||
777284b6 BP |
1732 | if (cpu) |
1733 | load_ucode_ap(); | |
e6ebf5de | 1734 | |
c482feef | 1735 | t = &per_cpu(cpu_tss_rw, cpu); |
0f3fa48a | 1736 | |
e7a22c1e | 1737 | #ifdef CONFIG_NUMA |
27fd185f | 1738 | if (this_cpu_read(numa_node) == 0 && |
e534c7c5 LS |
1739 | early_cpu_to_node(cpu) != NUMA_NO_NODE) |
1740 | set_numa_node(early_cpu_to_node(cpu)); | |
e7a22c1e | 1741 | #endif |
b2e2ba57 | 1742 | setup_getcpu(cpu); |
1ba76586 YL |
1743 | |
1744 | me = current; | |
1745 | ||
2eaad1fd | 1746 | pr_debug("Initializing CPU#%d\n", cpu); |
1ba76586 | 1747 | |
375074cc | 1748 | cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); |
1ba76586 YL |
1749 | |
1750 | /* | |
1751 | * Initialize the per-CPU GDT with the boot GDT, | |
1752 | * and set up the GDT descriptor: | |
1753 | */ | |
1754 | ||
552be871 | 1755 | switch_to_new_gdt(cpu); |
2697fbd5 BG |
1756 | loadsegment(fs, 0); |
1757 | ||
cf910e83 | 1758 | load_current_idt(); |
1ba76586 YL |
1759 | |
1760 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1761 | syscall_init(); | |
1762 | ||
1763 | wrmsrl(MSR_FS_BASE, 0); | |
1764 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1765 | barrier(); | |
1766 | ||
4763ed4d | 1767 | x86_configure_nx(); |
659006bf | 1768 | x2apic_setup(); |
1ba76586 YL |
1769 | |
1770 | /* | |
1771 | * set up and load the per-CPU TSS | |
1772 | */ | |
f6ef7322 | 1773 | if (!t->x86_tss.ist[0]) { |
32074269 TG |
1774 | t->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF); |
1775 | t->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI); | |
1776 | t->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB); | |
1777 | t->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE); | |
1ba76586 YL |
1778 | } |
1779 | ||
7fb983b4 | 1780 | t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; |
0f3fa48a | 1781 | |
1ba76586 YL |
1782 | /* |
1783 | * <= is required because the CPU will access up to | |
1784 | * 8 bits beyond the end of the IO permission bitmap. | |
1785 | */ | |
1786 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1787 | t->io_bitmap[i] = ~0UL; | |
1788 | ||
f1f10076 | 1789 | mmgrab(&init_mm); |
1ba76586 | 1790 | me->active_mm = &init_mm; |
8c5dfd25 | 1791 | BUG_ON(me->mm); |
72c0098d | 1792 | initialize_tlbstate_and_flush(); |
1ba76586 YL |
1793 | enter_lazy_tlb(&init_mm, me); |
1794 | ||
20bb8344 | 1795 | /* |
7f2590a1 AL |
1796 | * Initialize the TSS. sp0 points to the entry trampoline stack |
1797 | * regardless of what task is running. | |
20bb8344 | 1798 | */ |
72f5e08d | 1799 | set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); |
1ba76586 | 1800 | load_TR_desc(); |
4fe2d8b1 | 1801 | load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); |
20bb8344 | 1802 | |
37868fe1 | 1803 | load_mm_ldt(&init_mm); |
1ba76586 | 1804 | |
0bb9fef9 JW |
1805 | clear_all_debug_regs(); |
1806 | dbg_restore_debug_regs(); | |
1ba76586 | 1807 | |
21c4cd10 | 1808 | fpu__init_cpu(); |
1ba76586 | 1809 | |
1ba76586 YL |
1810 | if (is_uv_system()) |
1811 | uv_cpu_init(); | |
69218e47 | 1812 | |
69218e47 | 1813 | load_fixmap_gdt(cpu); |
1ba76586 YL |
1814 | } |
1815 | ||
1816 | #else | |
1817 | ||
148f9bb8 | 1818 | void cpu_init(void) |
9ee79a3d | 1819 | { |
d2cbcc49 RR |
1820 | int cpu = smp_processor_id(); |
1821 | struct task_struct *curr = current; | |
c482feef | 1822 | struct tss_struct *t = &per_cpu(cpu_tss_rw, cpu); |
62111195 | 1823 | |
ce4b1b16 | 1824 | wait_for_master_cpu(cpu); |
e6ebf5de | 1825 | |
5b2bdbc8 SR |
1826 | /* |
1827 | * Initialize the CR4 shadow before doing anything that could | |
1828 | * try to read it. | |
1829 | */ | |
1830 | cr4_init_shadow(); | |
1831 | ||
ce4b1b16 | 1832 | show_ucode_info_early(); |
62111195 | 1833 | |
1b74dde7 | 1834 | pr_info("Initializing CPU#%d\n", cpu); |
62111195 | 1835 | |
362f924b | 1836 | if (cpu_feature_enabled(X86_FEATURE_VME) || |
59e21e3d | 1837 | boot_cpu_has(X86_FEATURE_TSC) || |
362f924b | 1838 | boot_cpu_has(X86_FEATURE_DE)) |
375074cc | 1839 | cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); |
62111195 | 1840 | |
cf910e83 | 1841 | load_current_idt(); |
552be871 | 1842 | switch_to_new_gdt(cpu); |
1da177e4 | 1843 | |
1da177e4 LT |
1844 | /* |
1845 | * Set up and load the per-CPU TSS and LDT | |
1846 | */ | |
f1f10076 | 1847 | mmgrab(&init_mm); |
62111195 | 1848 | curr->active_mm = &init_mm; |
8c5dfd25 | 1849 | BUG_ON(curr->mm); |
72c0098d | 1850 | initialize_tlbstate_and_flush(); |
62111195 | 1851 | enter_lazy_tlb(&init_mm, curr); |
1da177e4 | 1852 | |
20bb8344 | 1853 | /* |
45d7b255 JR |
1854 | * Initialize the TSS. sp0 points to the entry trampoline stack |
1855 | * regardless of what task is running. | |
20bb8344 | 1856 | */ |
72f5e08d | 1857 | set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); |
1da177e4 | 1858 | load_TR_desc(); |
45d7b255 | 1859 | load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); |
20bb8344 | 1860 | |
37868fe1 | 1861 | load_mm_ldt(&init_mm); |
1da177e4 | 1862 | |
7fb983b4 | 1863 | t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; |
f9a196b8 | 1864 | |
22c4e308 | 1865 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1866 | /* Set up doublefault TSS pointer in the GDT */ |
1867 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1868 | #endif |
1da177e4 | 1869 | |
9766cdbc | 1870 | clear_all_debug_regs(); |
0bb9fef9 | 1871 | dbg_restore_debug_regs(); |
1da177e4 | 1872 | |
21c4cd10 | 1873 | fpu__init_cpu(); |
69218e47 | 1874 | |
69218e47 | 1875 | load_fixmap_gdt(cpu); |
1da177e4 | 1876 | } |
1ba76586 | 1877 | #endif |
5700f743 | 1878 | |
1008c52c BP |
1879 | /* |
1880 | * The microcode loader calls this upon late microcode load to recheck features, | |
1881 | * only when microcode has been updated. Caller holds microcode_mutex and CPU | |
1882 | * hotplug lock. | |
1883 | */ | |
1884 | void microcode_check(void) | |
1885 | { | |
42ca8082 BP |
1886 | struct cpuinfo_x86 info; |
1887 | ||
1008c52c | 1888 | perf_check_microcode(); |
42ca8082 BP |
1889 | |
1890 | /* Reload CPUID max function as it might've changed. */ | |
1891 | info.cpuid_level = cpuid_eax(0); | |
1892 | ||
1893 | /* | |
1894 | * Copy all capability leafs to pick up the synthetic ones so that | |
1895 | * memcmp() below doesn't fail on that. The ones coming from CPUID will | |
1896 | * get overwritten in get_cpu_cap(). | |
1897 | */ | |
1898 | memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); | |
1899 | ||
1900 | get_cpu_cap(&info); | |
1901 | ||
1902 | if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) | |
1903 | return; | |
1904 | ||
1905 | pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); | |
1906 | pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); | |
1008c52c | 1907 | } |