]>
Commit | Line | Data |
---|---|---|
1da177e4 | 1 | #include <linux/init.h> |
f0fc4aff YL |
2 | #include <linux/kernel.h> |
3 | #include <linux/sched.h> | |
1da177e4 | 4 | #include <linux/string.h> |
f0fc4aff YL |
5 | #include <linux/bootmem.h> |
6 | #include <linux/bitops.h> | |
7 | #include <linux/module.h> | |
8 | #include <linux/kgdb.h> | |
9 | #include <linux/topology.h> | |
1da177e4 LT |
10 | #include <linux/delay.h> |
11 | #include <linux/smp.h> | |
1da177e4 | 12 | #include <linux/percpu.h> |
1da177e4 LT |
13 | #include <asm/i387.h> |
14 | #include <asm/msr.h> | |
15 | #include <asm/io.h> | |
f0fc4aff | 16 | #include <asm/linkage.h> |
1da177e4 | 17 | #include <asm/mmu_context.h> |
27b07da7 | 18 | #include <asm/mtrr.h> |
a03a3e28 | 19 | #include <asm/mce.h> |
8d4a4300 | 20 | #include <asm/pat.h> |
b6734c35 | 21 | #include <asm/asm.h> |
f0fc4aff | 22 | #include <asm/numa.h> |
b342797c | 23 | #include <asm/smp.h> |
f472cdba | 24 | #include <asm/cpu.h> |
06879033 | 25 | #include <asm/cpumask.h> |
1da177e4 LT |
26 | #ifdef CONFIG_X86_LOCAL_APIC |
27 | #include <asm/mpspec.h> | |
28 | #include <asm/apic.h> | |
29 | #include <mach_apic.h> | |
f0fc4aff | 30 | #include <asm/genapic.h> |
bdbcdd48 | 31 | #include <asm/uv/uv.h> |
1da177e4 LT |
32 | #endif |
33 | ||
f0fc4aff YL |
34 | #include <asm/pgtable.h> |
35 | #include <asm/processor.h> | |
36 | #include <asm/desc.h> | |
37 | #include <asm/atomic.h> | |
38 | #include <asm/proto.h> | |
39 | #include <asm/sections.h> | |
40 | #include <asm/setup.h> | |
88b094fb | 41 | #include <asm/hypervisor.h> |
f0fc4aff | 42 | |
1da177e4 LT |
43 | #include "cpu.h" |
44 | ||
c2d1cec1 MT |
45 | #ifdef CONFIG_X86_64 |
46 | ||
47 | /* all of these masks are initialized in setup_cpu_local_masks() */ | |
48 | cpumask_var_t cpu_callin_mask; | |
49 | cpumask_var_t cpu_callout_mask; | |
50 | cpumask_var_t cpu_initialized_mask; | |
51 | ||
52 | /* representing cpus for which sibling maps can be computed */ | |
53 | cpumask_var_t cpu_sibling_setup_mask; | |
54 | ||
2f2f52ba | 55 | /* correctly size the local cpu masks */ |
4369f1fb | 56 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
57 | { |
58 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
59 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
60 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
61 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
62 | } | |
63 | ||
c2d1cec1 MT |
64 | #else /* CONFIG_X86_32 */ |
65 | ||
66 | cpumask_t cpu_callin_map; | |
67 | cpumask_t cpu_callout_map; | |
68 | cpumask_t cpu_initialized; | |
69 | cpumask_t cpu_sibling_setup_map; | |
70 | ||
71 | #endif /* CONFIG_X86_32 */ | |
72 | ||
73 | ||
0a488a53 YL |
74 | static struct cpu_dev *this_cpu __cpuinitdata; |
75 | ||
06deef89 | 76 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 77 | #ifdef CONFIG_X86_64 |
06deef89 BG |
78 | /* |
79 | * We need valid kernel segments for data and code in long mode too | |
80 | * IRET will check the segment types kkeil 2000/10/28 | |
81 | * Also sysret mandates a special GDT layout | |
82 | * | |
83 | * The TLS descriptors are currently at a different place compared to i386. | |
84 | * Hopefully nobody expects them at a fixed place (Wine?) | |
85 | */ | |
950ad7ff YL |
86 | [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } }, |
87 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } }, | |
88 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } }, | |
89 | [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } }, | |
90 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } }, | |
91 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } }, | |
950ad7ff | 92 | #else |
6842ef0e GOC |
93 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, |
94 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, | |
95 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, | |
96 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, | |
bf504672 RR |
97 | /* |
98 | * Segments used for calling PnP BIOS have byte granularity. | |
99 | * They code segments and data segments have fixed 64k limits, | |
100 | * the transfer segment sizes are set at run time. | |
101 | */ | |
6842ef0e GOC |
102 | /* 32-bit code */ |
103 | [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, | |
104 | /* 16-bit code */ | |
105 | [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, | |
106 | /* 16-bit data */ | |
107 | [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, | |
108 | /* 16-bit data */ | |
109 | [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, | |
110 | /* 16-bit data */ | |
111 | [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, | |
bf504672 RR |
112 | /* |
113 | * The APM segments have byte granularity and their bases | |
114 | * are set at run time. All have 64k limits. | |
115 | */ | |
6842ef0e GOC |
116 | /* 32-bit code */ |
117 | [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, | |
bf504672 | 118 | /* 16-bit code */ |
6842ef0e GOC |
119 | [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, |
120 | /* data */ | |
121 | [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, | |
bf504672 | 122 | |
6842ef0e | 123 | [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, |
0dd76d73 | 124 | [GDT_ENTRY_PERCPU] = { { { 0x0000ffff, 0x00cf9200 } } }, |
950ad7ff | 125 | #endif |
06deef89 | 126 | } }; |
7a61d35d | 127 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 128 | |
ba51dced | 129 | #ifdef CONFIG_X86_32 |
3bc9b76b | 130 | static int cachesize_override __cpuinitdata = -1; |
3bc9b76b | 131 | static int disable_x86_serial_nr __cpuinitdata = 1; |
1da177e4 | 132 | |
0a488a53 YL |
133 | static int __init cachesize_setup(char *str) |
134 | { | |
135 | get_option(&str, &cachesize_override); | |
136 | return 1; | |
137 | } | |
138 | __setup("cachesize=", cachesize_setup); | |
139 | ||
0a488a53 YL |
140 | static int __init x86_fxsr_setup(char *s) |
141 | { | |
142 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
143 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
144 | return 1; | |
145 | } | |
146 | __setup("nofxsr", x86_fxsr_setup); | |
147 | ||
148 | static int __init x86_sep_setup(char *s) | |
149 | { | |
150 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
151 | return 1; | |
152 | } | |
153 | __setup("nosep", x86_sep_setup); | |
154 | ||
155 | /* Standard macro to see if a specific flag is changeable */ | |
156 | static inline int flag_is_changeable_p(u32 flag) | |
157 | { | |
158 | u32 f1, f2; | |
159 | ||
94f6bac1 KH |
160 | /* |
161 | * Cyrix and IDT cpus allow disabling of CPUID | |
162 | * so the code below may return different results | |
163 | * when it is executed before and after enabling | |
164 | * the CPUID. Add "volatile" to not allow gcc to | |
165 | * optimize the subsequent calls to this function. | |
166 | */ | |
167 | asm volatile ("pushfl\n\t" | |
168 | "pushfl\n\t" | |
169 | "popl %0\n\t" | |
170 | "movl %0,%1\n\t" | |
171 | "xorl %2,%0\n\t" | |
172 | "pushl %0\n\t" | |
173 | "popfl\n\t" | |
174 | "pushfl\n\t" | |
175 | "popl %0\n\t" | |
176 | "popfl\n\t" | |
177 | : "=&r" (f1), "=&r" (f2) | |
178 | : "ir" (flag)); | |
0a488a53 YL |
179 | |
180 | return ((f1^f2) & flag) != 0; | |
181 | } | |
182 | ||
183 | /* Probe for the CPUID instruction */ | |
184 | static int __cpuinit have_cpuid_p(void) | |
185 | { | |
186 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
187 | } | |
188 | ||
189 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
190 | { | |
191 | if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) { | |
192 | /* Disable processor serial number */ | |
193 | unsigned long lo, hi; | |
194 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
195 | lo |= 0x200000; | |
196 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
197 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
198 | clear_cpu_cap(c, X86_FEATURE_PN); | |
199 | ||
200 | /* Disabling the serial number may affect the cpuid level */ | |
201 | c->cpuid_level = cpuid_eax(0); | |
202 | } | |
203 | } | |
204 | ||
205 | static int __init x86_serial_nr_setup(char *s) | |
206 | { | |
207 | disable_x86_serial_nr = 0; | |
208 | return 1; | |
209 | } | |
210 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 211 | #else |
102bbe3a YL |
212 | static inline int flag_is_changeable_p(u32 flag) |
213 | { | |
214 | return 1; | |
215 | } | |
ba51dced YL |
216 | /* Probe for the CPUID instruction */ |
217 | static inline int have_cpuid_p(void) | |
218 | { | |
219 | return 1; | |
220 | } | |
102bbe3a YL |
221 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
222 | { | |
223 | } | |
ba51dced | 224 | #endif |
0a488a53 | 225 | |
102bbe3a YL |
226 | /* |
227 | * Naming convention should be: <Name> [(<Codename>)] | |
228 | * This table only is used unless init_<vendor>() below doesn't set it; | |
229 | * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used | |
230 | * | |
231 | */ | |
232 | ||
233 | /* Look up CPU names by table lookup. */ | |
234 | static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c) | |
235 | { | |
236 | struct cpu_model_info *info; | |
237 | ||
238 | if (c->x86_model >= 16) | |
239 | return NULL; /* Range check */ | |
240 | ||
241 | if (!this_cpu) | |
242 | return NULL; | |
243 | ||
244 | info = this_cpu->c_models; | |
245 | ||
246 | while (info && info->family) { | |
247 | if (info->family == c->x86) | |
248 | return info->model_names[c->x86_model]; | |
249 | info++; | |
250 | } | |
251 | return NULL; /* Not found */ | |
252 | } | |
253 | ||
7d851c8d AK |
254 | __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; |
255 | ||
9d31d35b YL |
256 | /* Current gdt points %fs at the "master" per-cpu area: after this, |
257 | * it's on the real one. */ | |
258 | void switch_to_new_gdt(void) | |
259 | { | |
260 | struct desc_ptr gdt_descr; | |
2697fbd5 | 261 | int cpu = smp_processor_id(); |
9d31d35b | 262 | |
2697fbd5 | 263 | gdt_descr.address = (long)get_cpu_gdt_table(cpu); |
9d31d35b YL |
264 | gdt_descr.size = GDT_SIZE - 1; |
265 | load_gdt(&gdt_descr); | |
2697fbd5 | 266 | /* Reload the per-cpu base */ |
fab334c1 | 267 | #ifdef CONFIG_X86_32 |
2697fbd5 BG |
268 | loadsegment(fs, __KERNEL_PERCPU); |
269 | #else | |
270 | loadsegment(gs, 0); | |
271 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); | |
fab334c1 | 272 | #endif |
9d31d35b YL |
273 | } |
274 | ||
10a434fc | 275 | static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 276 | |
34048c9e | 277 | static void __cpuinit default_init(struct cpuinfo_x86 *c) |
1da177e4 | 278 | { |
b9e67f00 YL |
279 | #ifdef CONFIG_X86_64 |
280 | display_cacheinfo(c); | |
281 | #else | |
1da177e4 LT |
282 | /* Not much we can do here... */ |
283 | /* Check if at least it has cpuid */ | |
284 | if (c->cpuid_level == -1) { | |
285 | /* No cpuid. It must be an ancient CPU */ | |
286 | if (c->x86 == 4) | |
287 | strcpy(c->x86_model_id, "486"); | |
288 | else if (c->x86 == 3) | |
289 | strcpy(c->x86_model_id, "386"); | |
290 | } | |
b9e67f00 | 291 | #endif |
1da177e4 LT |
292 | } |
293 | ||
95414930 | 294 | static struct cpu_dev __cpuinitdata default_cpu = { |
1da177e4 | 295 | .c_init = default_init, |
fe38d855 | 296 | .c_vendor = "Unknown", |
10a434fc | 297 | .c_x86_vendor = X86_VENDOR_UNKNOWN, |
1da177e4 | 298 | }; |
1da177e4 | 299 | |
1b05d60d | 300 | static void __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
301 | { |
302 | unsigned int *v; | |
303 | char *p, *q; | |
304 | ||
3da99c97 | 305 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 306 | return; |
1da177e4 LT |
307 | |
308 | v = (unsigned int *) c->x86_model_id; | |
309 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
310 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
311 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
312 | c->x86_model_id[48] = 0; | |
313 | ||
314 | /* Intel chips right-justify this string for some dumb reason; | |
315 | undo that brain damage */ | |
316 | p = q = &c->x86_model_id[0]; | |
34048c9e | 317 | while (*p == ' ') |
1da177e4 | 318 | p++; |
34048c9e PC |
319 | if (p != q) { |
320 | while (*p) | |
1da177e4 | 321 | *q++ = *p++; |
34048c9e | 322 | while (q <= &c->x86_model_id[48]) |
1da177e4 LT |
323 | *q++ = '\0'; /* Zero-pad the rest */ |
324 | } | |
1da177e4 LT |
325 | } |
326 | ||
3bc9b76b | 327 | void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) |
1da177e4 | 328 | { |
9d31d35b | 329 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 330 | |
3da99c97 | 331 | n = c->extended_cpuid_level; |
1da177e4 LT |
332 | |
333 | if (n >= 0x80000005) { | |
9d31d35b | 334 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 335 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", |
9d31d35b YL |
336 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); |
337 | c->x86_cache_size = (ecx>>24) + (edx>>24); | |
140fc727 YL |
338 | #ifdef CONFIG_X86_64 |
339 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
340 | c->x86_tlbsize = 0; | |
341 | #endif | |
1da177e4 LT |
342 | } |
343 | ||
344 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
345 | return; | |
346 | ||
0a488a53 | 347 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 348 | l2size = ecx >> 16; |
34048c9e | 349 | |
140fc727 YL |
350 | #ifdef CONFIG_X86_64 |
351 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
352 | #else | |
1da177e4 LT |
353 | /* do processor-specific cache resizing */ |
354 | if (this_cpu->c_size_cache) | |
34048c9e | 355 | l2size = this_cpu->c_size_cache(c, l2size); |
1da177e4 LT |
356 | |
357 | /* Allow user to override all this if necessary. */ | |
358 | if (cachesize_override != -1) | |
359 | l2size = cachesize_override; | |
360 | ||
34048c9e | 361 | if (l2size == 0) |
1da177e4 | 362 | return; /* Again, no L2 cache is possible */ |
140fc727 | 363 | #endif |
1da177e4 LT |
364 | |
365 | c->x86_cache_size = l2size; | |
366 | ||
367 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
0a488a53 | 368 | l2size, ecx & 0xFF); |
1da177e4 LT |
369 | } |
370 | ||
9d31d35b | 371 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 372 | { |
97e4db7c | 373 | #ifdef CONFIG_X86_HT |
0a488a53 YL |
374 | u32 eax, ebx, ecx, edx; |
375 | int index_msb, core_bits; | |
1da177e4 | 376 | |
0a488a53 | 377 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 378 | return; |
1da177e4 | 379 | |
0a488a53 YL |
380 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
381 | goto out; | |
1da177e4 | 382 | |
1cd78776 YL |
383 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
384 | return; | |
1da177e4 | 385 | |
0a488a53 | 386 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 387 | |
9d31d35b YL |
388 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
389 | ||
390 | if (smp_num_siblings == 1) { | |
391 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
392 | } else if (smp_num_siblings > 1) { | |
393 | ||
9628937d | 394 | if (smp_num_siblings > nr_cpu_ids) { |
9d31d35b YL |
395 | printk(KERN_WARNING "CPU: Unsupported number of siblings %d", |
396 | smp_num_siblings); | |
397 | smp_num_siblings = 1; | |
398 | return; | |
399 | } | |
400 | ||
401 | index_msb = get_count_order(smp_num_siblings); | |
1cd78776 YL |
402 | #ifdef CONFIG_X86_64 |
403 | c->phys_proc_id = phys_pkg_id(index_msb); | |
404 | #else | |
9d31d35b | 405 | c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb); |
1cd78776 | 406 | #endif |
9d31d35b YL |
407 | |
408 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; | |
409 | ||
410 | index_msb = get_count_order(smp_num_siblings); | |
411 | ||
412 | core_bits = get_count_order(c->x86_max_cores); | |
413 | ||
1cd78776 YL |
414 | #ifdef CONFIG_X86_64 |
415 | c->cpu_core_id = phys_pkg_id(index_msb) & | |
416 | ((1 << core_bits) - 1); | |
417 | #else | |
9d31d35b YL |
418 | c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) & |
419 | ((1 << core_bits) - 1); | |
1cd78776 | 420 | #endif |
1da177e4 | 421 | } |
1da177e4 | 422 | |
0a488a53 YL |
423 | out: |
424 | if ((c->x86_max_cores * smp_num_siblings) > 1) { | |
425 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
426 | c->phys_proc_id); | |
427 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
428 | c->cpu_core_id); | |
9d31d35b | 429 | } |
9d31d35b | 430 | #endif |
97e4db7c | 431 | } |
1da177e4 | 432 | |
3da99c97 | 433 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
434 | { |
435 | char *v = c->x86_vendor_id; | |
436 | int i; | |
fe38d855 | 437 | static int printed; |
1da177e4 LT |
438 | |
439 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
440 | if (!cpu_devs[i]) |
441 | break; | |
442 | ||
443 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
444 | (cpu_devs[i]->c_ident[1] && | |
445 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
446 | this_cpu = cpu_devs[i]; | |
447 | c->x86_vendor = this_cpu->c_x86_vendor; | |
448 | return; | |
1da177e4 LT |
449 | } |
450 | } | |
10a434fc | 451 | |
fe38d855 CE |
452 | if (!printed) { |
453 | printed++; | |
43603c8d | 454 | printk(KERN_ERR "CPU: vendor_id '%s' unknown, using generic init.\n", v); |
fe38d855 CE |
455 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); |
456 | } | |
10a434fc | 457 | |
fe38d855 CE |
458 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
459 | this_cpu = &default_cpu; | |
1da177e4 LT |
460 | } |
461 | ||
9d31d35b | 462 | void __cpuinit cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 463 | { |
1da177e4 | 464 | /* Get vendor name */ |
4a148513 HH |
465 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
466 | (unsigned int *)&c->x86_vendor_id[0], | |
467 | (unsigned int *)&c->x86_vendor_id[8], | |
468 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 469 | |
1da177e4 | 470 | c->x86 = 4; |
9d31d35b | 471 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
472 | if (c->cpuid_level >= 0x00000001) { |
473 | u32 junk, tfms, cap0, misc; | |
474 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
9d31d35b YL |
475 | c->x86 = (tfms >> 8) & 0xf; |
476 | c->x86_model = (tfms >> 4) & 0xf; | |
477 | c->x86_mask = tfms & 0xf; | |
f5f786d0 | 478 | if (c->x86 == 0xf) |
1da177e4 | 479 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 480 | if (c->x86 >= 0x6) |
9d31d35b | 481 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
d4387bd3 | 482 | if (cap0 & (1<<19)) { |
d4387bd3 | 483 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 484 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 485 | } |
1da177e4 | 486 | } |
1da177e4 | 487 | } |
3da99c97 YL |
488 | |
489 | static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) | |
093af8d7 YL |
490 | { |
491 | u32 tfms, xlvl; | |
3da99c97 | 492 | u32 ebx; |
093af8d7 | 493 | |
3da99c97 YL |
494 | /* Intel-defined flags: level 0x00000001 */ |
495 | if (c->cpuid_level >= 0x00000001) { | |
496 | u32 capability, excap; | |
497 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); | |
498 | c->x86_capability[0] = capability; | |
499 | c->x86_capability[4] = excap; | |
500 | } | |
093af8d7 | 501 | |
3da99c97 YL |
502 | /* AMD-defined flags: level 0x80000001 */ |
503 | xlvl = cpuid_eax(0x80000000); | |
504 | c->extended_cpuid_level = xlvl; | |
505 | if ((xlvl & 0xffff0000) == 0x80000000) { | |
506 | if (xlvl >= 0x80000001) { | |
507 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
508 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 509 | } |
093af8d7 | 510 | } |
093af8d7 | 511 | |
5122c890 | 512 | #ifdef CONFIG_X86_64 |
5122c890 YL |
513 | if (c->extended_cpuid_level >= 0x80000008) { |
514 | u32 eax = cpuid_eax(0x80000008); | |
515 | ||
516 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
517 | c->x86_phys_bits = eax & 0xff; | |
093af8d7 | 518 | } |
5122c890 | 519 | #endif |
e3224234 YL |
520 | |
521 | if (c->extended_cpuid_level >= 0x80000007) | |
522 | c->x86_power = cpuid_edx(0x80000007); | |
093af8d7 YL |
523 | |
524 | } | |
1da177e4 | 525 | |
aef93c8b YL |
526 | static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
527 | { | |
528 | #ifdef CONFIG_X86_32 | |
529 | int i; | |
530 | ||
531 | /* | |
532 | * First of all, decide if this is a 486 or higher | |
533 | * It's a 486 if we can modify the AC flag | |
534 | */ | |
535 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
536 | c->x86 = 4; | |
537 | else | |
538 | c->x86 = 3; | |
539 | ||
540 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
541 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
542 | c->x86_vendor_id[0] = 0; | |
543 | cpu_devs[i]->c_identify(c); | |
544 | if (c->x86_vendor_id[0]) { | |
545 | get_cpu_vendor(c); | |
546 | break; | |
547 | } | |
548 | } | |
549 | #endif | |
550 | } | |
551 | ||
34048c9e PC |
552 | /* |
553 | * Do minimum CPU detection early. | |
554 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
555 | * cache alignment. | |
556 | * The others are not touched to avoid unwanted side effects. | |
557 | * | |
558 | * WARNING: this function is only called on the BP. Don't add code here | |
559 | * that is supposed to run on all CPUs. | |
560 | */ | |
3da99c97 | 561 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 562 | { |
6627d242 YL |
563 | #ifdef CONFIG_X86_64 |
564 | c->x86_clflush_size = 64; | |
565 | #else | |
d4387bd3 | 566 | c->x86_clflush_size = 32; |
6627d242 | 567 | #endif |
0a488a53 | 568 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 569 | |
3da99c97 | 570 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 571 | c->extended_cpuid_level = 0; |
d7cd5611 | 572 | |
aef93c8b YL |
573 | if (!have_cpuid_p()) |
574 | identify_cpu_without_cpuid(c); | |
575 | ||
576 | /* cyrix could have cpuid enabled via c_identify()*/ | |
d7cd5611 RR |
577 | if (!have_cpuid_p()) |
578 | return; | |
579 | ||
580 | cpu_detect(c); | |
581 | ||
3da99c97 | 582 | get_cpu_vendor(c); |
2b16a235 | 583 | |
3da99c97 | 584 | get_cpu_cap(c); |
12cf105c | 585 | |
10a434fc YL |
586 | if (this_cpu->c_early_init) |
587 | this_cpu->c_early_init(c); | |
093af8d7 | 588 | |
3da99c97 | 589 | validate_pat_support(c); |
bfcb4c1b | 590 | |
1c4acdb4 | 591 | #ifdef CONFIG_SMP |
bfcb4c1b | 592 | c->cpu_index = boot_cpu_id; |
1c4acdb4 | 593 | #endif |
d7cd5611 RR |
594 | } |
595 | ||
9d31d35b YL |
596 | void __init early_cpu_init(void) |
597 | { | |
10a434fc YL |
598 | struct cpu_dev **cdev; |
599 | int count = 0; | |
600 | ||
601 | printk("KERNEL supported cpus:\n"); | |
602 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { | |
603 | struct cpu_dev *cpudev = *cdev; | |
604 | unsigned int j; | |
9d31d35b | 605 | |
10a434fc YL |
606 | if (count >= X86_VENDOR_NUM) |
607 | break; | |
608 | cpu_devs[count] = cpudev; | |
609 | count++; | |
610 | ||
611 | for (j = 0; j < 2; j++) { | |
612 | if (!cpudev->c_ident[j]) | |
613 | continue; | |
614 | printk(" %s %s\n", cpudev->c_vendor, | |
615 | cpudev->c_ident[j]); | |
616 | } | |
617 | } | |
9d31d35b | 618 | |
9d31d35b | 619 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 620 | } |
093af8d7 | 621 | |
b6734c35 PA |
622 | /* |
623 | * The NOPL instruction is supposed to exist on all CPUs with | |
ba0593bf | 624 | * family >= 6; unfortunately, that's not true in practice because |
b6734c35 | 625 | * of early VIA chips and (more importantly) broken virtualizers that |
ba0593bf PA |
626 | * are not easy to detect. In the latter case it doesn't even *fail* |
627 | * reliably, so probing for it doesn't even work. Disable it completely | |
628 | * unless we can find a reliable way to detect all the broken cases. | |
b6734c35 PA |
629 | */ |
630 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
631 | { | |
b6734c35 | 632 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
d7cd5611 RR |
633 | } |
634 | ||
34048c9e | 635 | static void __cpuinit generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 636 | { |
aef93c8b | 637 | c->extended_cpuid_level = 0; |
1da177e4 | 638 | |
3da99c97 | 639 | if (!have_cpuid_p()) |
aef93c8b | 640 | identify_cpu_without_cpuid(c); |
1d67953f | 641 | |
aef93c8b | 642 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 643 | if (!have_cpuid_p()) |
aef93c8b | 644 | return; |
1da177e4 | 645 | |
3da99c97 | 646 | cpu_detect(c); |
1da177e4 | 647 | |
3da99c97 | 648 | get_cpu_vendor(c); |
1da177e4 | 649 | |
3da99c97 | 650 | get_cpu_cap(c); |
1da177e4 | 651 | |
3da99c97 YL |
652 | if (c->cpuid_level >= 0x00000001) { |
653 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e YL |
654 | #ifdef CONFIG_X86_32 |
655 | # ifdef CONFIG_X86_HT | |
3da99c97 | 656 | c->apicid = phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 657 | # else |
3da99c97 | 658 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
659 | # endif |
660 | #endif | |
1da177e4 | 661 | |
b89d3b3e YL |
662 | #ifdef CONFIG_X86_HT |
663 | c->phys_proc_id = c->initial_apicid; | |
1e9f28fa | 664 | #endif |
3da99c97 | 665 | } |
1da177e4 | 666 | |
1b05d60d | 667 | get_model_name(c); /* Default name */ |
1da177e4 | 668 | |
3da99c97 YL |
669 | init_scattered_cpuid_features(c); |
670 | detect_nopl(c); | |
1da177e4 | 671 | } |
1da177e4 LT |
672 | |
673 | /* | |
674 | * This does the hard work of actually picking apart the CPU stuff... | |
675 | */ | |
9a250347 | 676 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
677 | { |
678 | int i; | |
679 | ||
680 | c->loops_per_jiffy = loops_per_jiffy; | |
681 | c->x86_cache_size = -1; | |
682 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
683 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
684 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
685 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 686 | c->x86_max_cores = 1; |
102bbe3a | 687 | c->x86_coreid_bits = 0; |
11fdd252 | 688 | #ifdef CONFIG_X86_64 |
102bbe3a YL |
689 | c->x86_clflush_size = 64; |
690 | #else | |
691 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 692 | c->x86_clflush_size = 32; |
102bbe3a YL |
693 | #endif |
694 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
695 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
696 | ||
1da177e4 LT |
697 | generic_identify(c); |
698 | ||
3898534d | 699 | if (this_cpu->c_identify) |
1da177e4 LT |
700 | this_cpu->c_identify(c); |
701 | ||
102bbe3a YL |
702 | #ifdef CONFIG_X86_64 |
703 | c->apicid = phys_pkg_id(0); | |
704 | #endif | |
705 | ||
1da177e4 LT |
706 | /* |
707 | * Vendor-specific initialization. In this section we | |
708 | * canonicalize the feature flags, meaning if there are | |
709 | * features a certain CPU supports which CPUID doesn't | |
710 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
711 | * we handle them here. | |
712 | * | |
713 | * At the end of this section, c->x86_capability better | |
714 | * indicate the features this CPU genuinely supports! | |
715 | */ | |
716 | if (this_cpu->c_init) | |
717 | this_cpu->c_init(c); | |
718 | ||
719 | /* Disable the PN if appropriate */ | |
720 | squash_the_stupid_serial_number(c); | |
721 | ||
722 | /* | |
723 | * The vendor-specific functions might have changed features. Now | |
724 | * we do "generic changes." | |
725 | */ | |
726 | ||
1da177e4 | 727 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 728 | if (!c->x86_model_id[0]) { |
1da177e4 LT |
729 | char *p; |
730 | p = table_lookup_model(c); | |
34048c9e | 731 | if (p) |
1da177e4 LT |
732 | strcpy(c->x86_model_id, p); |
733 | else | |
734 | /* Last resort... */ | |
735 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 736 | c->x86, c->x86_model); |
1da177e4 LT |
737 | } |
738 | ||
102bbe3a YL |
739 | #ifdef CONFIG_X86_64 |
740 | detect_ht(c); | |
741 | #endif | |
742 | ||
88b094fb | 743 | init_hypervisor(c); |
1da177e4 LT |
744 | /* |
745 | * On SMP, boot_cpu_data holds the common feature set between | |
746 | * all CPUs; so make sure that we indicate which features are | |
747 | * common between the CPUs. The first time this routine gets | |
748 | * executed, c == &boot_cpu_data. | |
749 | */ | |
34048c9e | 750 | if (c != &boot_cpu_data) { |
1da177e4 | 751 | /* AND the already accumulated flags with these */ |
9d31d35b | 752 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 LT |
753 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
754 | } | |
755 | ||
7d851c8d AK |
756 | /* Clear all flags overriden by options */ |
757 | for (i = 0; i < NCAPINTS; i++) | |
12c247a6 | 758 | c->x86_capability[i] &= ~cleared_cpu_caps[i]; |
7d851c8d | 759 | |
102bbe3a | 760 | #ifdef CONFIG_X86_MCE |
1da177e4 | 761 | /* Init Machine Check Exception if available. */ |
1da177e4 | 762 | mcheck_init(c); |
102bbe3a | 763 | #endif |
30d432df AK |
764 | |
765 | select_idle_routine(c); | |
102bbe3a YL |
766 | |
767 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) | |
768 | numa_add_cpu(smp_processor_id()); | |
769 | #endif | |
a6c4e076 | 770 | } |
31ab269a | 771 | |
e04d645f GC |
772 | #ifdef CONFIG_X86_64 |
773 | static void vgetcpu_set_mode(void) | |
774 | { | |
775 | if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) | |
776 | vgetcpu_mode = VGETCPU_RDTSCP; | |
777 | else | |
778 | vgetcpu_mode = VGETCPU_LSL; | |
779 | } | |
780 | #endif | |
781 | ||
a6c4e076 JF |
782 | void __init identify_boot_cpu(void) |
783 | { | |
784 | identify_cpu(&boot_cpu_data); | |
102bbe3a | 785 | #ifdef CONFIG_X86_32 |
a6c4e076 | 786 | sysenter_setup(); |
6fe940d6 | 787 | enable_sep_cpu(); |
e04d645f GC |
788 | #else |
789 | vgetcpu_set_mode(); | |
102bbe3a | 790 | #endif |
a6c4e076 | 791 | } |
3b520b23 | 792 | |
a6c4e076 JF |
793 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) |
794 | { | |
795 | BUG_ON(c == &boot_cpu_data); | |
796 | identify_cpu(c); | |
102bbe3a | 797 | #ifdef CONFIG_X86_32 |
a6c4e076 | 798 | enable_sep_cpu(); |
102bbe3a | 799 | #endif |
a6c4e076 | 800 | mtrr_ap_init(); |
1da177e4 LT |
801 | } |
802 | ||
a0854a46 YL |
803 | struct msr_range { |
804 | unsigned min; | |
805 | unsigned max; | |
806 | }; | |
1da177e4 | 807 | |
a0854a46 YL |
808 | static struct msr_range msr_range_array[] __cpuinitdata = { |
809 | { 0x00000000, 0x00000418}, | |
810 | { 0xc0000000, 0xc000040b}, | |
811 | { 0xc0010000, 0xc0010142}, | |
812 | { 0xc0011000, 0xc001103b}, | |
813 | }; | |
1da177e4 | 814 | |
a0854a46 YL |
815 | static void __cpuinit print_cpu_msr(void) |
816 | { | |
817 | unsigned index; | |
818 | u64 val; | |
819 | int i; | |
820 | unsigned index_min, index_max; | |
821 | ||
822 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
823 | index_min = msr_range_array[i].min; | |
824 | index_max = msr_range_array[i].max; | |
825 | for (index = index_min; index < index_max; index++) { | |
826 | if (rdmsrl_amd_safe(index, &val)) | |
827 | continue; | |
828 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1da177e4 | 829 | } |
a0854a46 YL |
830 | } |
831 | } | |
94605eff | 832 | |
a0854a46 YL |
833 | static int show_msr __cpuinitdata; |
834 | static __init int setup_show_msr(char *arg) | |
835 | { | |
836 | int num; | |
3dd9d514 | 837 | |
a0854a46 | 838 | get_option(&arg, &num); |
3dd9d514 | 839 | |
a0854a46 YL |
840 | if (num > 0) |
841 | show_msr = num; | |
842 | return 1; | |
1da177e4 | 843 | } |
a0854a46 | 844 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 845 | |
191679fd AK |
846 | static __init int setup_noclflush(char *arg) |
847 | { | |
848 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
849 | return 1; | |
850 | } | |
851 | __setup("noclflush", setup_noclflush); | |
852 | ||
3bc9b76b | 853 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 LT |
854 | { |
855 | char *vendor = NULL; | |
856 | ||
857 | if (c->x86_vendor < X86_VENDOR_NUM) | |
858 | vendor = this_cpu->c_vendor; | |
859 | else if (c->cpuid_level >= 0) | |
860 | vendor = c->x86_vendor_id; | |
861 | ||
bd32a8cf | 862 | if (vendor && !strstr(c->x86_model_id, vendor)) |
9d31d35b | 863 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 864 | |
9d31d35b YL |
865 | if (c->x86_model_id[0]) |
866 | printk(KERN_CONT "%s", c->x86_model_id); | |
1da177e4 | 867 | else |
9d31d35b | 868 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 869 | |
34048c9e | 870 | if (c->x86_mask || c->cpuid_level >= 0) |
9d31d35b | 871 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); |
1da177e4 | 872 | else |
9d31d35b | 873 | printk(KERN_CONT "\n"); |
a0854a46 YL |
874 | |
875 | #ifdef CONFIG_SMP | |
876 | if (c->cpu_index < show_msr) | |
877 | print_cpu_msr(); | |
878 | #else | |
879 | if (show_msr) | |
880 | print_cpu_msr(); | |
881 | #endif | |
1da177e4 LT |
882 | } |
883 | ||
ac72e788 AK |
884 | static __init int setup_disablecpuid(char *arg) |
885 | { | |
886 | int bit; | |
887 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) | |
888 | setup_clear_cpu_cap(bit); | |
889 | else | |
890 | return 0; | |
891 | return 1; | |
892 | } | |
893 | __setup("clearcpuid=", setup_disablecpuid); | |
894 | ||
d5494d4f | 895 | #ifdef CONFIG_X86_64 |
d5494d4f YL |
896 | struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; |
897 | ||
947e76cd BG |
898 | DEFINE_PER_CPU_FIRST(union irq_stack_union, |
899 | irq_stack_union) __aligned(PAGE_SIZE); | |
26f80bd6 BG |
900 | #ifdef CONFIG_SMP |
901 | DEFINE_PER_CPU(char *, irq_stack_ptr); /* will be set during per cpu init */ | |
902 | #else | |
903 | DEFINE_PER_CPU(char *, irq_stack_ptr) = | |
947e76cd | 904 | per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; |
26f80bd6 | 905 | #endif |
d5494d4f | 906 | |
9af45651 BG |
907 | DEFINE_PER_CPU(unsigned long, kernel_stack) = |
908 | (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; | |
909 | EXPORT_PER_CPU_SYMBOL(kernel_stack); | |
910 | ||
56895530 BG |
911 | DEFINE_PER_CPU(unsigned int, irq_count) = -1; |
912 | ||
92d65b23 BG |
913 | static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks |
914 | [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]) | |
915 | __aligned(PAGE_SIZE); | |
d5494d4f YL |
916 | |
917 | extern asmlinkage void ignore_sysret(void); | |
918 | ||
919 | /* May not be marked __init: used by software suspend */ | |
920 | void syscall_init(void) | |
1da177e4 | 921 | { |
d5494d4f YL |
922 | /* |
923 | * LSTAR and STAR live in a bit strange symbiosis. | |
924 | * They both write to the same internal register. STAR allows to | |
925 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
926 | */ | |
927 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
928 | wrmsrl(MSR_LSTAR, system_call); | |
929 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
03ae5768 | 930 | |
d5494d4f YL |
931 | #ifdef CONFIG_IA32_EMULATION |
932 | syscall32_cpu_init(); | |
933 | #endif | |
03ae5768 | 934 | |
d5494d4f YL |
935 | /* Flags to clear on syscall */ |
936 | wrmsrl(MSR_SYSCALL_MASK, | |
937 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); | |
1da177e4 | 938 | } |
62111195 | 939 | |
d5494d4f YL |
940 | unsigned long kernel_eflags; |
941 | ||
942 | /* | |
943 | * Copies of the original ist values from the tss are only accessed during | |
944 | * debugging, no special alignment required. | |
945 | */ | |
946 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
947 | ||
948 | #else | |
949 | ||
7c3576d2 | 950 | /* Make sure %fs is initialized properly in idle threads */ |
6b2fb3c6 | 951 | struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) |
f95d47ca JF |
952 | { |
953 | memset(regs, 0, sizeof(struct pt_regs)); | |
65ea5b03 | 954 | regs->fs = __KERNEL_PERCPU; |
f95d47ca JF |
955 | return regs; |
956 | } | |
d5494d4f | 957 | #endif |
c5413fbe | 958 | |
d2cbcc49 RR |
959 | /* |
960 | * cpu_init() initializes state that is per-CPU. Some data is already | |
961 | * initialized (naturally) in the bootstrap process, such as the GDT | |
962 | * and IDT. We reload them nevertheless, this function acts as a | |
963 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 964 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 965 | */ |
1ba76586 YL |
966 | #ifdef CONFIG_X86_64 |
967 | void __cpuinit cpu_init(void) | |
968 | { | |
969 | int cpu = stack_smp_processor_id(); | |
970 | struct tss_struct *t = &per_cpu(init_tss, cpu); | |
971 | struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu); | |
972 | unsigned long v; | |
1ba76586 YL |
973 | struct task_struct *me; |
974 | int i; | |
975 | ||
e7a22c1e BG |
976 | #ifdef CONFIG_NUMA |
977 | if (cpu != 0 && percpu_read(node_number) == 0 && | |
978 | cpu_to_node(cpu) != NUMA_NO_NODE) | |
979 | percpu_write(node_number, cpu_to_node(cpu)); | |
980 | #endif | |
981 | ||
1ba76586 YL |
982 | me = current; |
983 | ||
c2d1cec1 | 984 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) |
1ba76586 YL |
985 | panic("CPU#%d already initialized!\n", cpu); |
986 | ||
987 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
988 | ||
989 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
990 | ||
991 | /* | |
992 | * Initialize the per-CPU GDT with the boot GDT, | |
993 | * and set up the GDT descriptor: | |
994 | */ | |
995 | ||
996 | switch_to_new_gdt(); | |
2697fbd5 BG |
997 | loadsegment(fs, 0); |
998 | ||
1ba76586 YL |
999 | load_idt((const struct desc_ptr *)&idt_descr); |
1000 | ||
1001 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1002 | syscall_init(); | |
1003 | ||
1004 | wrmsrl(MSR_FS_BASE, 0); | |
1005 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1006 | barrier(); | |
1007 | ||
1008 | check_efer(); | |
1009 | if (cpu != 0 && x2apic) | |
1010 | enable_x2apic(); | |
1011 | ||
1012 | /* | |
1013 | * set up and load the per-CPU TSS | |
1014 | */ | |
1015 | if (!orig_ist->ist[0]) { | |
92d65b23 BG |
1016 | static const unsigned int sizes[N_EXCEPTION_STACKS] = { |
1017 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
1018 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
1ba76586 | 1019 | }; |
92d65b23 | 1020 | char *estacks = per_cpu(exception_stacks, cpu); |
1ba76586 | 1021 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
92d65b23 | 1022 | estacks += sizes[v]; |
1ba76586 YL |
1023 | orig_ist->ist[v] = t->x86_tss.ist[v] = |
1024 | (unsigned long)estacks; | |
1025 | } | |
1026 | } | |
1027 | ||
1028 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
1029 | /* | |
1030 | * <= is required because the CPU will access up to | |
1031 | * 8 bits beyond the end of the IO permission bitmap. | |
1032 | */ | |
1033 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1034 | t->io_bitmap[i] = ~0UL; | |
1035 | ||
1036 | atomic_inc(&init_mm.mm_count); | |
1037 | me->active_mm = &init_mm; | |
1038 | if (me->mm) | |
1039 | BUG(); | |
1040 | enter_lazy_tlb(&init_mm, me); | |
1041 | ||
1042 | load_sp0(t, ¤t->thread); | |
1043 | set_tss_desc(cpu, t); | |
1044 | load_TR_desc(); | |
1045 | load_LDT(&init_mm.context); | |
1046 | ||
1047 | #ifdef CONFIG_KGDB | |
1048 | /* | |
1049 | * If the kgdb is connected no debug regs should be altered. This | |
1050 | * is only applicable when KGDB and a KGDB I/O module are built | |
1051 | * into the kernel and you are using early debugging with | |
1052 | * kgdbwait. KGDB will control the kernel HW breakpoint registers. | |
1053 | */ | |
1054 | if (kgdb_connected && arch_kgdb_ops.correct_hw_break) | |
1055 | arch_kgdb_ops.correct_hw_break(); | |
1056 | else { | |
1057 | #endif | |
1058 | /* | |
1059 | * Clear all 6 debug registers: | |
1060 | */ | |
1061 | ||
1062 | set_debugreg(0UL, 0); | |
1063 | set_debugreg(0UL, 1); | |
1064 | set_debugreg(0UL, 2); | |
1065 | set_debugreg(0UL, 3); | |
1066 | set_debugreg(0UL, 6); | |
1067 | set_debugreg(0UL, 7); | |
1068 | #ifdef CONFIG_KGDB | |
1069 | /* If the kgdb is connected no debug regs should be altered. */ | |
1070 | } | |
1071 | #endif | |
1072 | ||
1073 | fpu_init(); | |
1074 | ||
1075 | raw_local_save_flags(kernel_eflags); | |
1076 | ||
1077 | if (is_uv_system()) | |
1078 | uv_cpu_init(); | |
1079 | } | |
1080 | ||
1081 | #else | |
1082 | ||
d2cbcc49 | 1083 | void __cpuinit cpu_init(void) |
9ee79a3d | 1084 | { |
d2cbcc49 RR |
1085 | int cpu = smp_processor_id(); |
1086 | struct task_struct *curr = current; | |
34048c9e | 1087 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 1088 | struct thread_struct *thread = &curr->thread; |
62111195 | 1089 | |
c2d1cec1 | 1090 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { |
62111195 JF |
1091 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); |
1092 | for (;;) local_irq_enable(); | |
1093 | } | |
1094 | ||
1095 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1096 | ||
1097 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
1098 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 1099 | |
4d37e7e3 | 1100 | load_idt(&idt_descr); |
c5413fbe | 1101 | switch_to_new_gdt(); |
1da177e4 | 1102 | |
1da177e4 LT |
1103 | /* |
1104 | * Set up and load the per-CPU TSS and LDT | |
1105 | */ | |
1106 | atomic_inc(&init_mm.mm_count); | |
62111195 JF |
1107 | curr->active_mm = &init_mm; |
1108 | if (curr->mm) | |
1109 | BUG(); | |
1110 | enter_lazy_tlb(&init_mm, curr); | |
1da177e4 | 1111 | |
faca6227 | 1112 | load_sp0(t, thread); |
34048c9e | 1113 | set_tss_desc(cpu, t); |
1da177e4 LT |
1114 | load_TR_desc(); |
1115 | load_LDT(&init_mm.context); | |
1116 | ||
22c4e308 | 1117 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1118 | /* Set up doublefault TSS pointer in the GDT */ |
1119 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1120 | #endif |
1da177e4 | 1121 | |
464d1a78 JF |
1122 | /* Clear %gs. */ |
1123 | asm volatile ("mov %0, %%gs" : : "r" (0)); | |
1da177e4 LT |
1124 | |
1125 | /* Clear all 6 debug registers: */ | |
4bb0d3ec ZA |
1126 | set_debugreg(0, 0); |
1127 | set_debugreg(0, 1); | |
1128 | set_debugreg(0, 2); | |
1129 | set_debugreg(0, 3); | |
1130 | set_debugreg(0, 6); | |
1131 | set_debugreg(0, 7); | |
1da177e4 LT |
1132 | |
1133 | /* | |
1134 | * Force FPU initialization: | |
1135 | */ | |
b359e8a4 SS |
1136 | if (cpu_has_xsave) |
1137 | current_thread_info()->status = TS_XSAVE; | |
1138 | else | |
1139 | current_thread_info()->status = 0; | |
1da177e4 LT |
1140 | clear_used_math(); |
1141 | mxcsr_feature_mask_init(); | |
dc1e35c6 SS |
1142 | |
1143 | /* | |
1144 | * Boot processor to setup the FP and extended state context info. | |
1145 | */ | |
b3572e36 | 1146 | if (smp_processor_id() == boot_cpu_id) |
dc1e35c6 SS |
1147 | init_thread_xstate(); |
1148 | ||
1149 | xsave_init(); | |
1da177e4 | 1150 | } |
e1367daf | 1151 | |
1ba76586 YL |
1152 | |
1153 | #endif |