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Commit | Line | Data |
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f0fc4aff | 1 | #include <linux/bootmem.h> |
9766cdbc | 2 | #include <linux/linkage.h> |
f0fc4aff | 3 | #include <linux/bitops.h> |
9766cdbc | 4 | #include <linux/kernel.h> |
f0fc4aff | 5 | #include <linux/module.h> |
9766cdbc JSR |
6 | #include <linux/percpu.h> |
7 | #include <linux/string.h> | |
ee098e1a | 8 | #include <linux/ctype.h> |
1da177e4 | 9 | #include <linux/delay.h> |
9766cdbc JSR |
10 | #include <linux/sched.h> |
11 | #include <linux/init.h> | |
0f46efeb | 12 | #include <linux/kprobes.h> |
9766cdbc | 13 | #include <linux/kgdb.h> |
1da177e4 | 14 | #include <linux/smp.h> |
9766cdbc | 15 | #include <linux/io.h> |
b51ef52d | 16 | #include <linux/syscore_ops.h> |
9766cdbc JSR |
17 | |
18 | #include <asm/stackprotector.h> | |
cdd6c482 | 19 | #include <asm/perf_event.h> |
1da177e4 | 20 | #include <asm/mmu_context.h> |
49d859d7 | 21 | #include <asm/archrandom.h> |
9766cdbc JSR |
22 | #include <asm/hypervisor.h> |
23 | #include <asm/processor.h> | |
1e02ce4c | 24 | #include <asm/tlbflush.h> |
f649e938 | 25 | #include <asm/debugreg.h> |
9766cdbc | 26 | #include <asm/sections.h> |
f40c3300 | 27 | #include <asm/vsyscall.h> |
8bdbd962 AC |
28 | #include <linux/topology.h> |
29 | #include <linux/cpumask.h> | |
9766cdbc | 30 | #include <asm/pgtable.h> |
60063497 | 31 | #include <linux/atomic.h> |
9766cdbc JSR |
32 | #include <asm/proto.h> |
33 | #include <asm/setup.h> | |
34 | #include <asm/apic.h> | |
35 | #include <asm/desc.h> | |
78f7f1e5 | 36 | #include <asm/fpu/internal.h> |
27b07da7 | 37 | #include <asm/mtrr.h> |
8bdbd962 | 38 | #include <linux/numa.h> |
9766cdbc JSR |
39 | #include <asm/asm.h> |
40 | #include <asm/cpu.h> | |
a03a3e28 | 41 | #include <asm/mce.h> |
9766cdbc | 42 | #include <asm/msr.h> |
8d4a4300 | 43 | #include <asm/pat.h> |
d288e1cf FY |
44 | #include <asm/microcode.h> |
45 | #include <asm/microcode_intel.h> | |
e641f5f5 IM |
46 | |
47 | #ifdef CONFIG_X86_LOCAL_APIC | |
bdbcdd48 | 48 | #include <asm/uv/uv.h> |
1da177e4 LT |
49 | #endif |
50 | ||
51 | #include "cpu.h" | |
52 | ||
c2d1cec1 | 53 | /* all of these masks are initialized in setup_cpu_local_masks() */ |
c2d1cec1 | 54 | cpumask_var_t cpu_initialized_mask; |
9766cdbc JSR |
55 | cpumask_var_t cpu_callout_mask; |
56 | cpumask_var_t cpu_callin_mask; | |
c2d1cec1 MT |
57 | |
58 | /* representing cpus for which sibling maps can be computed */ | |
59 | cpumask_var_t cpu_sibling_setup_mask; | |
60 | ||
2f2f52ba | 61 | /* correctly size the local cpu masks */ |
4369f1fb | 62 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
63 | { |
64 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
65 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
66 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
67 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
68 | } | |
69 | ||
148f9bb8 | 70 | static void default_init(struct cpuinfo_x86 *c) |
e8055139 OZ |
71 | { |
72 | #ifdef CONFIG_X86_64 | |
27c13ece | 73 | cpu_detect_cache_sizes(c); |
e8055139 OZ |
74 | #else |
75 | /* Not much we can do here... */ | |
76 | /* Check if at least it has cpuid */ | |
77 | if (c->cpuid_level == -1) { | |
78 | /* No cpuid. It must be an ancient CPU */ | |
79 | if (c->x86 == 4) | |
80 | strcpy(c->x86_model_id, "486"); | |
81 | else if (c->x86 == 3) | |
82 | strcpy(c->x86_model_id, "386"); | |
83 | } | |
84 | #endif | |
85 | } | |
86 | ||
148f9bb8 | 87 | static const struct cpu_dev default_cpu = { |
e8055139 OZ |
88 | .c_init = default_init, |
89 | .c_vendor = "Unknown", | |
90 | .c_x86_vendor = X86_VENDOR_UNKNOWN, | |
91 | }; | |
92 | ||
148f9bb8 | 93 | static const struct cpu_dev *this_cpu = &default_cpu; |
0a488a53 | 94 | |
06deef89 | 95 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 96 | #ifdef CONFIG_X86_64 |
06deef89 BG |
97 | /* |
98 | * We need valid kernel segments for data and code in long mode too | |
99 | * IRET will check the segment types kkeil 2000/10/28 | |
100 | * Also sysret mandates a special GDT layout | |
101 | * | |
9766cdbc | 102 | * TLS descriptors are currently at a different place compared to i386. |
06deef89 BG |
103 | * Hopefully nobody expects them at a fixed place (Wine?) |
104 | */ | |
1e5de182 AM |
105 | [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), |
106 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), | |
107 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), | |
108 | [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), | |
109 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), | |
110 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), | |
950ad7ff | 111 | #else |
1e5de182 AM |
112 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), |
113 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
114 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), | |
115 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), | |
bf504672 RR |
116 | /* |
117 | * Segments used for calling PnP BIOS have byte granularity. | |
118 | * They code segments and data segments have fixed 64k limits, | |
119 | * the transfer segment sizes are set at run time. | |
120 | */ | |
6842ef0e | 121 | /* 32-bit code */ |
1e5de182 | 122 | [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
6842ef0e | 123 | /* 16-bit code */ |
1e5de182 | 124 | [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 125 | /* 16-bit data */ |
1e5de182 | 126 | [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), |
6842ef0e | 127 | /* 16-bit data */ |
1e5de182 | 128 | [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), |
6842ef0e | 129 | /* 16-bit data */ |
1e5de182 | 130 | [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), |
bf504672 RR |
131 | /* |
132 | * The APM segments have byte granularity and their bases | |
133 | * are set at run time. All have 64k limits. | |
134 | */ | |
6842ef0e | 135 | /* 32-bit code */ |
1e5de182 | 136 | [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
bf504672 | 137 | /* 16-bit code */ |
1e5de182 | 138 | [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 139 | /* data */ |
72c4d853 | 140 | [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), |
bf504672 | 141 | |
1e5de182 AM |
142 | [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), |
143 | [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
60a5317f | 144 | GDT_STACK_CANARY_INIT |
950ad7ff | 145 | #endif |
06deef89 | 146 | } }; |
7a61d35d | 147 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 148 | |
8c3641e9 | 149 | static int __init x86_mpx_setup(char *s) |
0c752a93 | 150 | { |
8c3641e9 | 151 | /* require an exact match without trailing characters */ |
2cd3949f DH |
152 | if (strlen(s)) |
153 | return 0; | |
0c752a93 | 154 | |
8c3641e9 DH |
155 | /* do not emit a message if the feature is not present */ |
156 | if (!boot_cpu_has(X86_FEATURE_MPX)) | |
157 | return 1; | |
6bad06b7 | 158 | |
8c3641e9 DH |
159 | setup_clear_cpu_cap(X86_FEATURE_MPX); |
160 | pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); | |
b6f42a4a FY |
161 | return 1; |
162 | } | |
8c3641e9 | 163 | __setup("nompx", x86_mpx_setup); |
b6f42a4a | 164 | |
ba51dced | 165 | #ifdef CONFIG_X86_32 |
148f9bb8 PG |
166 | static int cachesize_override = -1; |
167 | static int disable_x86_serial_nr = 1; | |
1da177e4 | 168 | |
0a488a53 YL |
169 | static int __init cachesize_setup(char *str) |
170 | { | |
171 | get_option(&str, &cachesize_override); | |
172 | return 1; | |
173 | } | |
174 | __setup("cachesize=", cachesize_setup); | |
175 | ||
0a488a53 YL |
176 | static int __init x86_sep_setup(char *s) |
177 | { | |
178 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
179 | return 1; | |
180 | } | |
181 | __setup("nosep", x86_sep_setup); | |
182 | ||
183 | /* Standard macro to see if a specific flag is changeable */ | |
184 | static inline int flag_is_changeable_p(u32 flag) | |
185 | { | |
186 | u32 f1, f2; | |
187 | ||
94f6bac1 KH |
188 | /* |
189 | * Cyrix and IDT cpus allow disabling of CPUID | |
190 | * so the code below may return different results | |
191 | * when it is executed before and after enabling | |
192 | * the CPUID. Add "volatile" to not allow gcc to | |
193 | * optimize the subsequent calls to this function. | |
194 | */ | |
0f3fa48a IM |
195 | asm volatile ("pushfl \n\t" |
196 | "pushfl \n\t" | |
197 | "popl %0 \n\t" | |
198 | "movl %0, %1 \n\t" | |
199 | "xorl %2, %0 \n\t" | |
200 | "pushl %0 \n\t" | |
201 | "popfl \n\t" | |
202 | "pushfl \n\t" | |
203 | "popl %0 \n\t" | |
204 | "popfl \n\t" | |
205 | ||
94f6bac1 KH |
206 | : "=&r" (f1), "=&r" (f2) |
207 | : "ir" (flag)); | |
0a488a53 YL |
208 | |
209 | return ((f1^f2) & flag) != 0; | |
210 | } | |
211 | ||
212 | /* Probe for the CPUID instruction */ | |
148f9bb8 | 213 | int have_cpuid_p(void) |
0a488a53 YL |
214 | { |
215 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
216 | } | |
217 | ||
148f9bb8 | 218 | static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
0a488a53 | 219 | { |
0f3fa48a IM |
220 | unsigned long lo, hi; |
221 | ||
222 | if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) | |
223 | return; | |
224 | ||
225 | /* Disable processor serial number: */ | |
226 | ||
227 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
228 | lo |= 0x200000; | |
229 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
230 | ||
231 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
232 | clear_cpu_cap(c, X86_FEATURE_PN); | |
233 | ||
234 | /* Disabling the serial number may affect the cpuid level */ | |
235 | c->cpuid_level = cpuid_eax(0); | |
0a488a53 YL |
236 | } |
237 | ||
238 | static int __init x86_serial_nr_setup(char *s) | |
239 | { | |
240 | disable_x86_serial_nr = 0; | |
241 | return 1; | |
242 | } | |
243 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 244 | #else |
102bbe3a YL |
245 | static inline int flag_is_changeable_p(u32 flag) |
246 | { | |
247 | return 1; | |
248 | } | |
102bbe3a YL |
249 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
250 | { | |
251 | } | |
ba51dced | 252 | #endif |
0a488a53 | 253 | |
de5397ad FY |
254 | static __init int setup_disable_smep(char *arg) |
255 | { | |
b2cc2a07 | 256 | setup_clear_cpu_cap(X86_FEATURE_SMEP); |
de5397ad FY |
257 | return 1; |
258 | } | |
259 | __setup("nosmep", setup_disable_smep); | |
260 | ||
b2cc2a07 | 261 | static __always_inline void setup_smep(struct cpuinfo_x86 *c) |
de5397ad | 262 | { |
b2cc2a07 | 263 | if (cpu_has(c, X86_FEATURE_SMEP)) |
375074cc | 264 | cr4_set_bits(X86_CR4_SMEP); |
de5397ad FY |
265 | } |
266 | ||
52b6179a PA |
267 | static __init int setup_disable_smap(char *arg) |
268 | { | |
b2cc2a07 | 269 | setup_clear_cpu_cap(X86_FEATURE_SMAP); |
52b6179a PA |
270 | return 1; |
271 | } | |
272 | __setup("nosmap", setup_disable_smap); | |
273 | ||
b2cc2a07 PA |
274 | static __always_inline void setup_smap(struct cpuinfo_x86 *c) |
275 | { | |
581b7f15 | 276 | unsigned long eflags = native_save_fl(); |
b2cc2a07 PA |
277 | |
278 | /* This should have been cleared long ago */ | |
b2cc2a07 PA |
279 | BUG_ON(eflags & X86_EFLAGS_AC); |
280 | ||
03bbd596 PA |
281 | if (cpu_has(c, X86_FEATURE_SMAP)) { |
282 | #ifdef CONFIG_X86_SMAP | |
375074cc | 283 | cr4_set_bits(X86_CR4_SMAP); |
03bbd596 | 284 | #else |
375074cc | 285 | cr4_clear_bits(X86_CR4_SMAP); |
03bbd596 PA |
286 | #endif |
287 | } | |
de5397ad FY |
288 | } |
289 | ||
b38b0665 PA |
290 | /* |
291 | * Some CPU features depend on higher CPUID levels, which may not always | |
292 | * be available due to CPUID level capping or broken virtualization | |
293 | * software. Add those features to this table to auto-disable them. | |
294 | */ | |
295 | struct cpuid_dependent_feature { | |
296 | u32 feature; | |
297 | u32 level; | |
298 | }; | |
0f3fa48a | 299 | |
148f9bb8 | 300 | static const struct cpuid_dependent_feature |
b38b0665 PA |
301 | cpuid_dependent_features[] = { |
302 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
303 | { X86_FEATURE_DCA, 0x00000009 }, | |
304 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
305 | { 0, 0 } | |
306 | }; | |
307 | ||
148f9bb8 | 308 | static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) |
b38b0665 PA |
309 | { |
310 | const struct cpuid_dependent_feature *df; | |
9766cdbc | 311 | |
b38b0665 | 312 | for (df = cpuid_dependent_features; df->feature; df++) { |
0f3fa48a IM |
313 | |
314 | if (!cpu_has(c, df->feature)) | |
315 | continue; | |
b38b0665 PA |
316 | /* |
317 | * Note: cpuid_level is set to -1 if unavailable, but | |
318 | * extended_extended_level is set to 0 if unavailable | |
319 | * and the legitimate extended levels are all negative | |
320 | * when signed; hence the weird messing around with | |
321 | * signs here... | |
322 | */ | |
0f3fa48a | 323 | if (!((s32)df->level < 0 ? |
f6db44df | 324 | (u32)df->level > (u32)c->extended_cpuid_level : |
0f3fa48a IM |
325 | (s32)df->level > (s32)c->cpuid_level)) |
326 | continue; | |
327 | ||
328 | clear_cpu_cap(c, df->feature); | |
329 | if (!warn) | |
330 | continue; | |
331 | ||
332 | printk(KERN_WARNING | |
9def39be JT |
333 | "CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", |
334 | x86_cap_flag(df->feature), df->level); | |
b38b0665 | 335 | } |
f6db44df | 336 | } |
b38b0665 | 337 | |
102bbe3a YL |
338 | /* |
339 | * Naming convention should be: <Name> [(<Codename>)] | |
340 | * This table only is used unless init_<vendor>() below doesn't set it; | |
0f3fa48a IM |
341 | * in particular, if CPUID levels 0x80000002..4 are supported, this |
342 | * isn't used | |
102bbe3a YL |
343 | */ |
344 | ||
345 | /* Look up CPU names by table lookup. */ | |
148f9bb8 | 346 | static const char *table_lookup_model(struct cpuinfo_x86 *c) |
102bbe3a | 347 | { |
09dc68d9 JB |
348 | #ifdef CONFIG_X86_32 |
349 | const struct legacy_cpu_model_info *info; | |
102bbe3a YL |
350 | |
351 | if (c->x86_model >= 16) | |
352 | return NULL; /* Range check */ | |
353 | ||
354 | if (!this_cpu) | |
355 | return NULL; | |
356 | ||
09dc68d9 | 357 | info = this_cpu->legacy_models; |
102bbe3a | 358 | |
09dc68d9 | 359 | while (info->family) { |
102bbe3a YL |
360 | if (info->family == c->x86) |
361 | return info->model_names[c->x86_model]; | |
362 | info++; | |
363 | } | |
09dc68d9 | 364 | #endif |
102bbe3a YL |
365 | return NULL; /* Not found */ |
366 | } | |
367 | ||
148f9bb8 PG |
368 | __u32 cpu_caps_cleared[NCAPINTS]; |
369 | __u32 cpu_caps_set[NCAPINTS]; | |
7d851c8d | 370 | |
11e3a840 JF |
371 | void load_percpu_segment(int cpu) |
372 | { | |
373 | #ifdef CONFIG_X86_32 | |
374 | loadsegment(fs, __KERNEL_PERCPU); | |
375 | #else | |
376 | loadsegment(gs, 0); | |
377 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); | |
378 | #endif | |
60a5317f | 379 | load_stack_canary_segment(); |
11e3a840 JF |
380 | } |
381 | ||
0f3fa48a IM |
382 | /* |
383 | * Current gdt points %fs at the "master" per-cpu area: after this, | |
384 | * it's on the real one. | |
385 | */ | |
552be871 | 386 | void switch_to_new_gdt(int cpu) |
9d31d35b YL |
387 | { |
388 | struct desc_ptr gdt_descr; | |
389 | ||
2697fbd5 | 390 | gdt_descr.address = (long)get_cpu_gdt_table(cpu); |
9d31d35b YL |
391 | gdt_descr.size = GDT_SIZE - 1; |
392 | load_gdt(&gdt_descr); | |
2697fbd5 | 393 | /* Reload the per-cpu base */ |
11e3a840 JF |
394 | |
395 | load_percpu_segment(cpu); | |
9d31d35b YL |
396 | } |
397 | ||
148f9bb8 | 398 | static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 399 | |
148f9bb8 | 400 | static void get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
401 | { |
402 | unsigned int *v; | |
ee098e1a | 403 | char *p, *q, *s; |
1da177e4 | 404 | |
3da99c97 | 405 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 406 | return; |
1da177e4 | 407 | |
0f3fa48a | 408 | v = (unsigned int *)c->x86_model_id; |
1da177e4 LT |
409 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); |
410 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
411 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
412 | c->x86_model_id[48] = 0; | |
413 | ||
ee098e1a BP |
414 | /* Trim whitespace */ |
415 | p = q = s = &c->x86_model_id[0]; | |
416 | ||
417 | while (*p == ' ') | |
418 | p++; | |
419 | ||
420 | while (*p) { | |
421 | /* Note the last non-whitespace index */ | |
422 | if (!isspace(*p)) | |
423 | s = q; | |
424 | ||
425 | *q++ = *p++; | |
426 | } | |
427 | ||
428 | *(s + 1) = '\0'; | |
1da177e4 LT |
429 | } |
430 | ||
148f9bb8 | 431 | void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) |
1da177e4 | 432 | { |
9d31d35b | 433 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 434 | |
3da99c97 | 435 | n = c->extended_cpuid_level; |
1da177e4 LT |
436 | |
437 | if (n >= 0x80000005) { | |
9d31d35b | 438 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
9d31d35b | 439 | c->x86_cache_size = (ecx>>24) + (edx>>24); |
140fc727 YL |
440 | #ifdef CONFIG_X86_64 |
441 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
442 | c->x86_tlbsize = 0; | |
443 | #endif | |
1da177e4 LT |
444 | } |
445 | ||
446 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
447 | return; | |
448 | ||
0a488a53 | 449 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 450 | l2size = ecx >> 16; |
34048c9e | 451 | |
140fc727 YL |
452 | #ifdef CONFIG_X86_64 |
453 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
454 | #else | |
1da177e4 | 455 | /* do processor-specific cache resizing */ |
09dc68d9 JB |
456 | if (this_cpu->legacy_cache_size) |
457 | l2size = this_cpu->legacy_cache_size(c, l2size); | |
1da177e4 LT |
458 | |
459 | /* Allow user to override all this if necessary. */ | |
460 | if (cachesize_override != -1) | |
461 | l2size = cachesize_override; | |
462 | ||
34048c9e | 463 | if (l2size == 0) |
1da177e4 | 464 | return; /* Again, no L2 cache is possible */ |
140fc727 | 465 | #endif |
1da177e4 LT |
466 | |
467 | c->x86_cache_size = l2size; | |
1da177e4 LT |
468 | } |
469 | ||
e0ba94f1 AS |
470 | u16 __read_mostly tlb_lli_4k[NR_INFO]; |
471 | u16 __read_mostly tlb_lli_2m[NR_INFO]; | |
472 | u16 __read_mostly tlb_lli_4m[NR_INFO]; | |
473 | u16 __read_mostly tlb_lld_4k[NR_INFO]; | |
474 | u16 __read_mostly tlb_lld_2m[NR_INFO]; | |
475 | u16 __read_mostly tlb_lld_4m[NR_INFO]; | |
dd360393 | 476 | u16 __read_mostly tlb_lld_1g[NR_INFO]; |
e0ba94f1 | 477 | |
f94fe119 | 478 | static void cpu_detect_tlb(struct cpuinfo_x86 *c) |
e0ba94f1 AS |
479 | { |
480 | if (this_cpu->c_detect_tlb) | |
481 | this_cpu->c_detect_tlb(c); | |
482 | ||
f94fe119 | 483 | pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", |
e0ba94f1 | 484 | tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], |
f94fe119 SH |
485 | tlb_lli_4m[ENTRIES]); |
486 | ||
487 | pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", | |
488 | tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], | |
489 | tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); | |
e0ba94f1 AS |
490 | } |
491 | ||
148f9bb8 | 492 | void detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 493 | { |
c8e56d20 | 494 | #ifdef CONFIG_SMP |
0a488a53 YL |
495 | u32 eax, ebx, ecx, edx; |
496 | int index_msb, core_bits; | |
2eaad1fd | 497 | static bool printed; |
1da177e4 | 498 | |
0a488a53 | 499 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 500 | return; |
1da177e4 | 501 | |
0a488a53 YL |
502 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
503 | goto out; | |
1da177e4 | 504 | |
1cd78776 YL |
505 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
506 | return; | |
1da177e4 | 507 | |
0a488a53 | 508 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 509 | |
9d31d35b YL |
510 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
511 | ||
512 | if (smp_num_siblings == 1) { | |
2eaad1fd | 513 | printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n"); |
0f3fa48a IM |
514 | goto out; |
515 | } | |
9d31d35b | 516 | |
0f3fa48a IM |
517 | if (smp_num_siblings <= 1) |
518 | goto out; | |
9d31d35b | 519 | |
0f3fa48a IM |
520 | index_msb = get_count_order(smp_num_siblings); |
521 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); | |
9d31d35b | 522 | |
0f3fa48a | 523 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
9d31d35b | 524 | |
0f3fa48a | 525 | index_msb = get_count_order(smp_num_siblings); |
9d31d35b | 526 | |
0f3fa48a | 527 | core_bits = get_count_order(c->x86_max_cores); |
9d31d35b | 528 | |
0f3fa48a IM |
529 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & |
530 | ((1 << core_bits) - 1); | |
1da177e4 | 531 | |
0a488a53 | 532 | out: |
2eaad1fd | 533 | if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { |
0a488a53 YL |
534 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", |
535 | c->phys_proc_id); | |
536 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
537 | c->cpu_core_id); | |
2eaad1fd | 538 | printed = 1; |
9d31d35b | 539 | } |
9d31d35b | 540 | #endif |
97e4db7c | 541 | } |
1da177e4 | 542 | |
148f9bb8 | 543 | static void get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
544 | { |
545 | char *v = c->x86_vendor_id; | |
0f3fa48a | 546 | int i; |
1da177e4 LT |
547 | |
548 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
549 | if (!cpu_devs[i]) |
550 | break; | |
551 | ||
552 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
553 | (cpu_devs[i]->c_ident[1] && | |
554 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
0f3fa48a | 555 | |
10a434fc YL |
556 | this_cpu = cpu_devs[i]; |
557 | c->x86_vendor = this_cpu->c_x86_vendor; | |
558 | return; | |
1da177e4 LT |
559 | } |
560 | } | |
10a434fc | 561 | |
a9c56953 MK |
562 | printk_once(KERN_ERR |
563 | "CPU: vendor_id '%s' unknown, using generic init.\n" \ | |
564 | "CPU: Your system may be unstable.\n", v); | |
10a434fc | 565 | |
fe38d855 CE |
566 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
567 | this_cpu = &default_cpu; | |
1da177e4 LT |
568 | } |
569 | ||
148f9bb8 | 570 | void cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 571 | { |
1da177e4 | 572 | /* Get vendor name */ |
4a148513 HH |
573 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
574 | (unsigned int *)&c->x86_vendor_id[0], | |
575 | (unsigned int *)&c->x86_vendor_id[8], | |
576 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 577 | |
1da177e4 | 578 | c->x86 = 4; |
9d31d35b | 579 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
580 | if (c->cpuid_level >= 0x00000001) { |
581 | u32 junk, tfms, cap0, misc; | |
0f3fa48a | 582 | |
1da177e4 | 583 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
9d31d35b YL |
584 | c->x86 = (tfms >> 8) & 0xf; |
585 | c->x86_model = (tfms >> 4) & 0xf; | |
586 | c->x86_mask = tfms & 0xf; | |
0f3fa48a | 587 | |
f5f786d0 | 588 | if (c->x86 == 0xf) |
1da177e4 | 589 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 590 | if (c->x86 >= 0x6) |
9d31d35b | 591 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
0f3fa48a | 592 | |
d4387bd3 | 593 | if (cap0 & (1<<19)) { |
d4387bd3 | 594 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 595 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 596 | } |
1da177e4 | 597 | } |
1da177e4 | 598 | } |
3da99c97 | 599 | |
148f9bb8 | 600 | void get_cpu_cap(struct cpuinfo_x86 *c) |
093af8d7 YL |
601 | { |
602 | u32 tfms, xlvl; | |
3da99c97 | 603 | u32 ebx; |
093af8d7 | 604 | |
3da99c97 YL |
605 | /* Intel-defined flags: level 0x00000001 */ |
606 | if (c->cpuid_level >= 0x00000001) { | |
607 | u32 capability, excap; | |
0f3fa48a | 608 | |
3da99c97 YL |
609 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); |
610 | c->x86_capability[0] = capability; | |
611 | c->x86_capability[4] = excap; | |
612 | } | |
093af8d7 | 613 | |
bdc802dc PA |
614 | /* Additional Intel-defined flags: level 0x00000007 */ |
615 | if (c->cpuid_level >= 0x00000007) { | |
616 | u32 eax, ebx, ecx, edx; | |
617 | ||
618 | cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); | |
619 | ||
2494b030 | 620 | c->x86_capability[9] = ebx; |
bdc802dc PA |
621 | } |
622 | ||
6229ad27 FY |
623 | /* Extended state features: level 0x0000000d */ |
624 | if (c->cpuid_level >= 0x0000000d) { | |
625 | u32 eax, ebx, ecx, edx; | |
626 | ||
627 | cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); | |
628 | ||
629 | c->x86_capability[10] = eax; | |
630 | } | |
631 | ||
cbc82b17 PWJ |
632 | /* Additional Intel-defined flags: level 0x0000000F */ |
633 | if (c->cpuid_level >= 0x0000000F) { | |
634 | u32 eax, ebx, ecx, edx; | |
635 | ||
636 | /* QoS sub-leaf, EAX=0Fh, ECX=0 */ | |
637 | cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx); | |
638 | c->x86_capability[11] = edx; | |
639 | if (cpu_has(c, X86_FEATURE_CQM_LLC)) { | |
640 | /* will be overridden if occupancy monitoring exists */ | |
641 | c->x86_cache_max_rmid = ebx; | |
642 | ||
643 | /* QoS sub-leaf, EAX=0Fh, ECX=1 */ | |
644 | cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx); | |
645 | c->x86_capability[12] = edx; | |
646 | if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) { | |
647 | c->x86_cache_max_rmid = ecx; | |
648 | c->x86_cache_occ_scale = ebx; | |
649 | } | |
650 | } else { | |
651 | c->x86_cache_max_rmid = -1; | |
652 | c->x86_cache_occ_scale = -1; | |
653 | } | |
654 | } | |
655 | ||
3da99c97 YL |
656 | /* AMD-defined flags: level 0x80000001 */ |
657 | xlvl = cpuid_eax(0x80000000); | |
658 | c->extended_cpuid_level = xlvl; | |
0f3fa48a | 659 | |
3da99c97 YL |
660 | if ((xlvl & 0xffff0000) == 0x80000000) { |
661 | if (xlvl >= 0x80000001) { | |
662 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
663 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 664 | } |
093af8d7 | 665 | } |
093af8d7 | 666 | |
5122c890 YL |
667 | if (c->extended_cpuid_level >= 0x80000008) { |
668 | u32 eax = cpuid_eax(0x80000008); | |
669 | ||
670 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
671 | c->x86_phys_bits = eax & 0xff; | |
2167ceab | 672 | c->x86_capability[13] = cpuid_ebx(0x80000008); |
093af8d7 | 673 | } |
13c6c532 JB |
674 | #ifdef CONFIG_X86_32 |
675 | else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) | |
676 | c->x86_phys_bits = 36; | |
5122c890 | 677 | #endif |
e3224234 YL |
678 | |
679 | if (c->extended_cpuid_level >= 0x80000007) | |
680 | c->x86_power = cpuid_edx(0x80000007); | |
093af8d7 | 681 | |
1dedefd1 | 682 | init_scattered_cpuid_features(c); |
093af8d7 | 683 | } |
1da177e4 | 684 | |
148f9bb8 | 685 | static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
aef93c8b YL |
686 | { |
687 | #ifdef CONFIG_X86_32 | |
688 | int i; | |
689 | ||
690 | /* | |
691 | * First of all, decide if this is a 486 or higher | |
692 | * It's a 486 if we can modify the AC flag | |
693 | */ | |
694 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
695 | c->x86 = 4; | |
696 | else | |
697 | c->x86 = 3; | |
698 | ||
699 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
700 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
701 | c->x86_vendor_id[0] = 0; | |
702 | cpu_devs[i]->c_identify(c); | |
703 | if (c->x86_vendor_id[0]) { | |
704 | get_cpu_vendor(c); | |
705 | break; | |
706 | } | |
707 | } | |
708 | #endif | |
709 | } | |
710 | ||
34048c9e PC |
711 | /* |
712 | * Do minimum CPU detection early. | |
713 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
714 | * cache alignment. | |
715 | * The others are not touched to avoid unwanted side effects. | |
716 | * | |
717 | * WARNING: this function is only called on the BP. Don't add code here | |
718 | * that is supposed to run on all CPUs. | |
719 | */ | |
3da99c97 | 720 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 721 | { |
6627d242 YL |
722 | #ifdef CONFIG_X86_64 |
723 | c->x86_clflush_size = 64; | |
13c6c532 JB |
724 | c->x86_phys_bits = 36; |
725 | c->x86_virt_bits = 48; | |
6627d242 | 726 | #else |
d4387bd3 | 727 | c->x86_clflush_size = 32; |
13c6c532 JB |
728 | c->x86_phys_bits = 32; |
729 | c->x86_virt_bits = 32; | |
6627d242 | 730 | #endif |
0a488a53 | 731 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 732 | |
3da99c97 | 733 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 734 | c->extended_cpuid_level = 0; |
d7cd5611 | 735 | |
aef93c8b YL |
736 | if (!have_cpuid_p()) |
737 | identify_cpu_without_cpuid(c); | |
738 | ||
739 | /* cyrix could have cpuid enabled via c_identify()*/ | |
d7cd5611 RR |
740 | if (!have_cpuid_p()) |
741 | return; | |
742 | ||
743 | cpu_detect(c); | |
3da99c97 | 744 | get_cpu_vendor(c); |
3da99c97 | 745 | get_cpu_cap(c); |
12cf105c | 746 | |
10a434fc YL |
747 | if (this_cpu->c_early_init) |
748 | this_cpu->c_early_init(c); | |
093af8d7 | 749 | |
f6e9456c | 750 | c->cpu_index = 0; |
b38b0665 | 751 | filter_cpuid_features(c, false); |
de5397ad | 752 | |
a110b5ec BP |
753 | if (this_cpu->c_bsp_init) |
754 | this_cpu->c_bsp_init(c); | |
c3b83598 BP |
755 | |
756 | setup_force_cpu_cap(X86_FEATURE_ALWAYS); | |
db52ef74 | 757 | fpu__init_system(c); |
d7cd5611 RR |
758 | } |
759 | ||
9d31d35b YL |
760 | void __init early_cpu_init(void) |
761 | { | |
02dde8b4 | 762 | const struct cpu_dev *const *cdev; |
10a434fc YL |
763 | int count = 0; |
764 | ||
ac23f253 | 765 | #ifdef CONFIG_PROCESSOR_SELECT |
9766cdbc | 766 | printk(KERN_INFO "KERNEL supported cpus:\n"); |
31c997ca IM |
767 | #endif |
768 | ||
10a434fc | 769 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { |
02dde8b4 | 770 | const struct cpu_dev *cpudev = *cdev; |
9d31d35b | 771 | |
10a434fc YL |
772 | if (count >= X86_VENDOR_NUM) |
773 | break; | |
774 | cpu_devs[count] = cpudev; | |
775 | count++; | |
776 | ||
ac23f253 | 777 | #ifdef CONFIG_PROCESSOR_SELECT |
31c997ca IM |
778 | { |
779 | unsigned int j; | |
780 | ||
781 | for (j = 0; j < 2; j++) { | |
782 | if (!cpudev->c_ident[j]) | |
783 | continue; | |
784 | printk(KERN_INFO " %s %s\n", cpudev->c_vendor, | |
785 | cpudev->c_ident[j]); | |
786 | } | |
10a434fc | 787 | } |
0388423d | 788 | #endif |
10a434fc | 789 | } |
9d31d35b | 790 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 791 | } |
093af8d7 | 792 | |
b6734c35 | 793 | /* |
366d4a43 BP |
794 | * The NOPL instruction is supposed to exist on all CPUs of family >= 6; |
795 | * unfortunately, that's not true in practice because of early VIA | |
796 | * chips and (more importantly) broken virtualizers that are not easy | |
797 | * to detect. In the latter case it doesn't even *fail* reliably, so | |
798 | * probing for it doesn't even work. Disable it completely on 32-bit | |
ba0593bf | 799 | * unless we can find a reliable way to detect all the broken cases. |
366d4a43 | 800 | * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). |
b6734c35 | 801 | */ |
148f9bb8 | 802 | static void detect_nopl(struct cpuinfo_x86 *c) |
b6734c35 | 803 | { |
366d4a43 | 804 | #ifdef CONFIG_X86_32 |
b6734c35 | 805 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
366d4a43 BP |
806 | #else |
807 | set_cpu_cap(c, X86_FEATURE_NOPL); | |
808 | #endif | |
d7cd5611 RR |
809 | } |
810 | ||
148f9bb8 | 811 | static void generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 812 | { |
aef93c8b | 813 | c->extended_cpuid_level = 0; |
1da177e4 | 814 | |
3da99c97 | 815 | if (!have_cpuid_p()) |
aef93c8b | 816 | identify_cpu_without_cpuid(c); |
1d67953f | 817 | |
aef93c8b | 818 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 819 | if (!have_cpuid_p()) |
aef93c8b | 820 | return; |
1da177e4 | 821 | |
3da99c97 | 822 | cpu_detect(c); |
1da177e4 | 823 | |
3da99c97 | 824 | get_cpu_vendor(c); |
1da177e4 | 825 | |
3da99c97 | 826 | get_cpu_cap(c); |
1da177e4 | 827 | |
3da99c97 YL |
828 | if (c->cpuid_level >= 0x00000001) { |
829 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e | 830 | #ifdef CONFIG_X86_32 |
c8e56d20 | 831 | # ifdef CONFIG_SMP |
cb8cc442 | 832 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 833 | # else |
3da99c97 | 834 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
835 | # endif |
836 | #endif | |
b89d3b3e | 837 | c->phys_proc_id = c->initial_apicid; |
3da99c97 | 838 | } |
1da177e4 | 839 | |
1b05d60d | 840 | get_model_name(c); /* Default name */ |
1da177e4 | 841 | |
3da99c97 | 842 | detect_nopl(c); |
1da177e4 | 843 | } |
1da177e4 | 844 | |
cbc82b17 PWJ |
845 | static void x86_init_cache_qos(struct cpuinfo_x86 *c) |
846 | { | |
847 | /* | |
848 | * The heavy lifting of max_rmid and cache_occ_scale are handled | |
849 | * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu | |
850 | * in case CQM bits really aren't there in this CPU. | |
851 | */ | |
852 | if (c != &boot_cpu_data) { | |
853 | boot_cpu_data.x86_cache_max_rmid = | |
854 | min(boot_cpu_data.x86_cache_max_rmid, | |
855 | c->x86_cache_max_rmid); | |
856 | } | |
857 | } | |
858 | ||
1da177e4 LT |
859 | /* |
860 | * This does the hard work of actually picking apart the CPU stuff... | |
861 | */ | |
148f9bb8 | 862 | static void identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
863 | { |
864 | int i; | |
865 | ||
866 | c->loops_per_jiffy = loops_per_jiffy; | |
867 | c->x86_cache_size = -1; | |
868 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
869 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
870 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
871 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 872 | c->x86_max_cores = 1; |
102bbe3a | 873 | c->x86_coreid_bits = 0; |
11fdd252 | 874 | #ifdef CONFIG_X86_64 |
102bbe3a | 875 | c->x86_clflush_size = 64; |
13c6c532 JB |
876 | c->x86_phys_bits = 36; |
877 | c->x86_virt_bits = 48; | |
102bbe3a YL |
878 | #else |
879 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 880 | c->x86_clflush_size = 32; |
13c6c532 JB |
881 | c->x86_phys_bits = 32; |
882 | c->x86_virt_bits = 32; | |
102bbe3a YL |
883 | #endif |
884 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
885 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
886 | ||
1da177e4 LT |
887 | generic_identify(c); |
888 | ||
3898534d | 889 | if (this_cpu->c_identify) |
1da177e4 LT |
890 | this_cpu->c_identify(c); |
891 | ||
2759c328 YL |
892 | /* Clear/Set all flags overriden by options, after probe */ |
893 | for (i = 0; i < NCAPINTS; i++) { | |
894 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
895 | c->x86_capability[i] |= cpu_caps_set[i]; | |
896 | } | |
897 | ||
102bbe3a | 898 | #ifdef CONFIG_X86_64 |
cb8cc442 | 899 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
900 | #endif |
901 | ||
1da177e4 LT |
902 | /* |
903 | * Vendor-specific initialization. In this section we | |
904 | * canonicalize the feature flags, meaning if there are | |
905 | * features a certain CPU supports which CPUID doesn't | |
906 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
907 | * we handle them here. | |
908 | * | |
909 | * At the end of this section, c->x86_capability better | |
910 | * indicate the features this CPU genuinely supports! | |
911 | */ | |
912 | if (this_cpu->c_init) | |
913 | this_cpu->c_init(c); | |
914 | ||
915 | /* Disable the PN if appropriate */ | |
916 | squash_the_stupid_serial_number(c); | |
917 | ||
b2cc2a07 PA |
918 | /* Set up SMEP/SMAP */ |
919 | setup_smep(c); | |
920 | setup_smap(c); | |
921 | ||
1da177e4 | 922 | /* |
0f3fa48a IM |
923 | * The vendor-specific functions might have changed features. |
924 | * Now we do "generic changes." | |
1da177e4 LT |
925 | */ |
926 | ||
b38b0665 PA |
927 | /* Filter out anything that depends on CPUID levels we don't have */ |
928 | filter_cpuid_features(c, true); | |
929 | ||
1da177e4 | 930 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 931 | if (!c->x86_model_id[0]) { |
02dde8b4 | 932 | const char *p; |
1da177e4 | 933 | p = table_lookup_model(c); |
34048c9e | 934 | if (p) |
1da177e4 LT |
935 | strcpy(c->x86_model_id, p); |
936 | else | |
937 | /* Last resort... */ | |
938 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 939 | c->x86, c->x86_model); |
1da177e4 LT |
940 | } |
941 | ||
102bbe3a YL |
942 | #ifdef CONFIG_X86_64 |
943 | detect_ht(c); | |
944 | #endif | |
945 | ||
88b094fb | 946 | init_hypervisor(c); |
49d859d7 | 947 | x86_init_rdrand(c); |
cbc82b17 | 948 | x86_init_cache_qos(c); |
3e0c3737 YL |
949 | |
950 | /* | |
951 | * Clear/Set all flags overriden by options, need do it | |
952 | * before following smp all cpus cap AND. | |
953 | */ | |
954 | for (i = 0; i < NCAPINTS; i++) { | |
955 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
956 | c->x86_capability[i] |= cpu_caps_set[i]; | |
957 | } | |
958 | ||
1da177e4 LT |
959 | /* |
960 | * On SMP, boot_cpu_data holds the common feature set between | |
961 | * all CPUs; so make sure that we indicate which features are | |
962 | * common between the CPUs. The first time this routine gets | |
963 | * executed, c == &boot_cpu_data. | |
964 | */ | |
34048c9e | 965 | if (c != &boot_cpu_data) { |
1da177e4 | 966 | /* AND the already accumulated flags with these */ |
9d31d35b | 967 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 | 968 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
65fc985b BP |
969 | |
970 | /* OR, i.e. replicate the bug flags */ | |
971 | for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) | |
972 | c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; | |
1da177e4 LT |
973 | } |
974 | ||
975 | /* Init Machine Check Exception if available. */ | |
5e09954a | 976 | mcheck_cpu_init(c); |
30d432df AK |
977 | |
978 | select_idle_routine(c); | |
102bbe3a | 979 | |
de2d9445 | 980 | #ifdef CONFIG_NUMA |
102bbe3a YL |
981 | numa_add_cpu(smp_processor_id()); |
982 | #endif | |
31c2013e TG |
983 | /* The boot/hotplug time assigment got cleared, restore it */ |
984 | c->logical_proc_id = topology_phys_to_logical_pkg(c->phys_proc_id); | |
a6c4e076 | 985 | } |
31ab269a | 986 | |
8b6c0ab1 IM |
987 | /* |
988 | * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions | |
989 | * on 32-bit kernels: | |
990 | */ | |
cfda7bb9 AL |
991 | #ifdef CONFIG_X86_32 |
992 | void enable_sep_cpu(void) | |
993 | { | |
8b6c0ab1 IM |
994 | struct tss_struct *tss; |
995 | int cpu; | |
cfda7bb9 | 996 | |
8b6c0ab1 IM |
997 | cpu = get_cpu(); |
998 | tss = &per_cpu(cpu_tss, cpu); | |
999 | ||
1000 | if (!boot_cpu_has(X86_FEATURE_SEP)) | |
1001 | goto out; | |
1002 | ||
1003 | /* | |
cf9328cc AL |
1004 | * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- |
1005 | * see the big comment in struct x86_hw_tss's definition. | |
8b6c0ab1 | 1006 | */ |
cfda7bb9 AL |
1007 | |
1008 | tss->x86_tss.ss1 = __KERNEL_CS; | |
8b6c0ab1 IM |
1009 | wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); |
1010 | ||
cf9328cc AL |
1011 | wrmsr(MSR_IA32_SYSENTER_ESP, |
1012 | (unsigned long)tss + offsetofend(struct tss_struct, SYSENTER_stack), | |
1013 | 0); | |
8b6c0ab1 | 1014 | |
4c8cd0c5 | 1015 | wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); |
8b6c0ab1 IM |
1016 | |
1017 | out: | |
cfda7bb9 AL |
1018 | put_cpu(); |
1019 | } | |
e04d645f GC |
1020 | #endif |
1021 | ||
a6c4e076 JF |
1022 | void __init identify_boot_cpu(void) |
1023 | { | |
1024 | identify_cpu(&boot_cpu_data); | |
02c68a02 | 1025 | init_amd_e400_c1e_mask(); |
102bbe3a | 1026 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1027 | sysenter_setup(); |
6fe940d6 | 1028 | enable_sep_cpu(); |
102bbe3a | 1029 | #endif |
5b556332 | 1030 | cpu_detect_tlb(&boot_cpu_data); |
a6c4e076 | 1031 | } |
3b520b23 | 1032 | |
148f9bb8 | 1033 | void identify_secondary_cpu(struct cpuinfo_x86 *c) |
a6c4e076 JF |
1034 | { |
1035 | BUG_ON(c == &boot_cpu_data); | |
1036 | identify_cpu(c); | |
102bbe3a | 1037 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1038 | enable_sep_cpu(); |
102bbe3a | 1039 | #endif |
a6c4e076 | 1040 | mtrr_ap_init(); |
1da177e4 LT |
1041 | } |
1042 | ||
a0854a46 | 1043 | struct msr_range { |
0f3fa48a IM |
1044 | unsigned min; |
1045 | unsigned max; | |
a0854a46 | 1046 | }; |
1da177e4 | 1047 | |
148f9bb8 | 1048 | static const struct msr_range msr_range_array[] = { |
a0854a46 YL |
1049 | { 0x00000000, 0x00000418}, |
1050 | { 0xc0000000, 0xc000040b}, | |
1051 | { 0xc0010000, 0xc0010142}, | |
1052 | { 0xc0011000, 0xc001103b}, | |
1053 | }; | |
1da177e4 | 1054 | |
148f9bb8 | 1055 | static void __print_cpu_msr(void) |
a0854a46 | 1056 | { |
0f3fa48a | 1057 | unsigned index_min, index_max; |
a0854a46 YL |
1058 | unsigned index; |
1059 | u64 val; | |
1060 | int i; | |
a0854a46 YL |
1061 | |
1062 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
1063 | index_min = msr_range_array[i].min; | |
1064 | index_max = msr_range_array[i].max; | |
0f3fa48a | 1065 | |
a0854a46 | 1066 | for (index = index_min; index < index_max; index++) { |
ecd431d9 | 1067 | if (rdmsrl_safe(index, &val)) |
a0854a46 YL |
1068 | continue; |
1069 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1da177e4 | 1070 | } |
a0854a46 YL |
1071 | } |
1072 | } | |
94605eff | 1073 | |
148f9bb8 | 1074 | static int show_msr; |
0f3fa48a | 1075 | |
a0854a46 YL |
1076 | static __init int setup_show_msr(char *arg) |
1077 | { | |
1078 | int num; | |
3dd9d514 | 1079 | |
a0854a46 | 1080 | get_option(&arg, &num); |
3dd9d514 | 1081 | |
a0854a46 YL |
1082 | if (num > 0) |
1083 | show_msr = num; | |
1084 | return 1; | |
1da177e4 | 1085 | } |
a0854a46 | 1086 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 1087 | |
191679fd AK |
1088 | static __init int setup_noclflush(char *arg) |
1089 | { | |
840d2830 | 1090 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); |
da4aaa7d | 1091 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); |
191679fd AK |
1092 | return 1; |
1093 | } | |
1094 | __setup("noclflush", setup_noclflush); | |
1095 | ||
148f9bb8 | 1096 | void print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 | 1097 | { |
02dde8b4 | 1098 | const char *vendor = NULL; |
1da177e4 | 1099 | |
0f3fa48a | 1100 | if (c->x86_vendor < X86_VENDOR_NUM) { |
1da177e4 | 1101 | vendor = this_cpu->c_vendor; |
0f3fa48a IM |
1102 | } else { |
1103 | if (c->cpuid_level >= 0) | |
1104 | vendor = c->x86_vendor_id; | |
1105 | } | |
1da177e4 | 1106 | |
bd32a8cf | 1107 | if (vendor && !strstr(c->x86_model_id, vendor)) |
9d31d35b | 1108 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 1109 | |
9d31d35b | 1110 | if (c->x86_model_id[0]) |
adafb98d | 1111 | printk(KERN_CONT "%s", c->x86_model_id); |
1da177e4 | 1112 | else |
9d31d35b | 1113 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 1114 | |
7c5b190e | 1115 | printk(KERN_CONT " (family: 0x%x, model: 0x%x", c->x86, c->x86_model); |
924e101a | 1116 | |
34048c9e | 1117 | if (c->x86_mask || c->cpuid_level >= 0) |
7c5b190e | 1118 | printk(KERN_CONT ", stepping: 0x%x)\n", c->x86_mask); |
1da177e4 | 1119 | else |
924e101a | 1120 | printk(KERN_CONT ")\n"); |
a0854a46 | 1121 | |
0b8b8078 | 1122 | print_cpu_msr(c); |
21c3fcf3 YL |
1123 | } |
1124 | ||
148f9bb8 | 1125 | void print_cpu_msr(struct cpuinfo_x86 *c) |
21c3fcf3 | 1126 | { |
a0854a46 | 1127 | if (c->cpu_index < show_msr) |
21c3fcf3 | 1128 | __print_cpu_msr(); |
1da177e4 LT |
1129 | } |
1130 | ||
ac72e788 AK |
1131 | static __init int setup_disablecpuid(char *arg) |
1132 | { | |
1133 | int bit; | |
0f3fa48a | 1134 | |
ac72e788 AK |
1135 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) |
1136 | setup_clear_cpu_cap(bit); | |
1137 | else | |
1138 | return 0; | |
0f3fa48a | 1139 | |
ac72e788 AK |
1140 | return 1; |
1141 | } | |
1142 | __setup("clearcpuid=", setup_disablecpuid); | |
1143 | ||
d5494d4f | 1144 | #ifdef CONFIG_X86_64 |
9ff80942 | 1145 | struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table }; |
629f4f9d SA |
1146 | struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1, |
1147 | (unsigned long) debug_idt_table }; | |
d5494d4f | 1148 | |
947e76cd | 1149 | DEFINE_PER_CPU_FIRST(union irq_stack_union, |
277d5b40 | 1150 | irq_stack_union) __aligned(PAGE_SIZE) __visible; |
0f3fa48a | 1151 | |
bdf977b3 | 1152 | /* |
a7fcf28d AL |
1153 | * The following percpu variables are hot. Align current_task to |
1154 | * cacheline size such that they fall in the same cacheline. | |
bdf977b3 TH |
1155 | */ |
1156 | DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = | |
1157 | &init_task; | |
1158 | EXPORT_PER_CPU_SYMBOL(current_task); | |
d5494d4f | 1159 | |
bdf977b3 TH |
1160 | DEFINE_PER_CPU(char *, irq_stack_ptr) = |
1161 | init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; | |
1162 | ||
277d5b40 | 1163 | DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; |
d5494d4f | 1164 | |
c2daa3be PZ |
1165 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1166 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
1167 | ||
0f3fa48a IM |
1168 | /* |
1169 | * Special IST stacks which the CPU switches to when it calls | |
1170 | * an IST-marked descriptor entry. Up to 7 stacks (hardware | |
1171 | * limit), all of them are 4K, except the debug stack which | |
1172 | * is 8K. | |
1173 | */ | |
1174 | static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { | |
1175 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
1176 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
1177 | }; | |
1178 | ||
92d65b23 | 1179 | static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks |
3e352aa8 | 1180 | [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); |
d5494d4f | 1181 | |
d5494d4f YL |
1182 | /* May not be marked __init: used by software suspend */ |
1183 | void syscall_init(void) | |
1da177e4 | 1184 | { |
d5494d4f YL |
1185 | /* |
1186 | * LSTAR and STAR live in a bit strange symbiosis. | |
1187 | * They both write to the same internal register. STAR allows to | |
1188 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
1189 | */ | |
1190 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
47edb651 | 1191 | wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); |
d56fe4bf IM |
1192 | |
1193 | #ifdef CONFIG_IA32_EMULATION | |
47edb651 | 1194 | wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); |
a76c7f46 | 1195 | /* |
487d1edb DV |
1196 | * This only works on Intel CPUs. |
1197 | * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. | |
1198 | * This does not cause SYSENTER to jump to the wrong location, because | |
1199 | * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). | |
a76c7f46 DV |
1200 | */ |
1201 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); | |
1202 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); | |
4c8cd0c5 | 1203 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); |
d56fe4bf | 1204 | #else |
47edb651 | 1205 | wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); |
6b51311c | 1206 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); |
d56fe4bf IM |
1207 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); |
1208 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); | |
d5494d4f | 1209 | #endif |
03ae5768 | 1210 | |
d5494d4f YL |
1211 | /* Flags to clear on syscall */ |
1212 | wrmsrl(MSR_SYSCALL_MASK, | |
63bcff2a | 1213 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| |
8c7aa698 | 1214 | X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); |
1da177e4 | 1215 | } |
62111195 | 1216 | |
d5494d4f YL |
1217 | /* |
1218 | * Copies of the original ist values from the tss are only accessed during | |
1219 | * debugging, no special alignment required. | |
1220 | */ | |
1221 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
1222 | ||
228bdaa9 | 1223 | static DEFINE_PER_CPU(unsigned long, debug_stack_addr); |
42181186 | 1224 | DEFINE_PER_CPU(int, debug_stack_usage); |
228bdaa9 SR |
1225 | |
1226 | int is_debug_stack(unsigned long addr) | |
1227 | { | |
89cbc767 CL |
1228 | return __this_cpu_read(debug_stack_usage) || |
1229 | (addr <= __this_cpu_read(debug_stack_addr) && | |
1230 | addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ)); | |
228bdaa9 | 1231 | } |
0f46efeb | 1232 | NOKPROBE_SYMBOL(is_debug_stack); |
228bdaa9 | 1233 | |
629f4f9d | 1234 | DEFINE_PER_CPU(u32, debug_idt_ctr); |
f8988175 | 1235 | |
228bdaa9 SR |
1236 | void debug_stack_set_zero(void) |
1237 | { | |
629f4f9d SA |
1238 | this_cpu_inc(debug_idt_ctr); |
1239 | load_current_idt(); | |
228bdaa9 | 1240 | } |
0f46efeb | 1241 | NOKPROBE_SYMBOL(debug_stack_set_zero); |
228bdaa9 SR |
1242 | |
1243 | void debug_stack_reset(void) | |
1244 | { | |
629f4f9d | 1245 | if (WARN_ON(!this_cpu_read(debug_idt_ctr))) |
f8988175 | 1246 | return; |
629f4f9d SA |
1247 | if (this_cpu_dec_return(debug_idt_ctr) == 0) |
1248 | load_current_idt(); | |
228bdaa9 | 1249 | } |
0f46efeb | 1250 | NOKPROBE_SYMBOL(debug_stack_reset); |
228bdaa9 | 1251 | |
0f3fa48a | 1252 | #else /* CONFIG_X86_64 */ |
d5494d4f | 1253 | |
bdf977b3 TH |
1254 | DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; |
1255 | EXPORT_PER_CPU_SYMBOL(current_task); | |
c2daa3be PZ |
1256 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1257 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
bdf977b3 | 1258 | |
a7fcf28d AL |
1259 | /* |
1260 | * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find | |
1261 | * the top of the kernel stack. Use an extra percpu variable to track the | |
1262 | * top of the kernel stack directly. | |
1263 | */ | |
1264 | DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = | |
1265 | (unsigned long)&init_thread_union + THREAD_SIZE; | |
1266 | EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); | |
1267 | ||
60a5317f | 1268 | #ifdef CONFIG_CC_STACKPROTECTOR |
53f82452 | 1269 | DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); |
60a5317f | 1270 | #endif |
d5494d4f | 1271 | |
0f3fa48a | 1272 | #endif /* CONFIG_X86_64 */ |
c5413fbe | 1273 | |
9766cdbc JSR |
1274 | /* |
1275 | * Clear all 6 debug registers: | |
1276 | */ | |
1277 | static void clear_all_debug_regs(void) | |
1278 | { | |
1279 | int i; | |
1280 | ||
1281 | for (i = 0; i < 8; i++) { | |
1282 | /* Ignore db4, db5 */ | |
1283 | if ((i == 4) || (i == 5)) | |
1284 | continue; | |
1285 | ||
1286 | set_debugreg(0, i); | |
1287 | } | |
1288 | } | |
c5413fbe | 1289 | |
0bb9fef9 JW |
1290 | #ifdef CONFIG_KGDB |
1291 | /* | |
1292 | * Restore debug regs if using kgdbwait and you have a kernel debugger | |
1293 | * connection established. | |
1294 | */ | |
1295 | static void dbg_restore_debug_regs(void) | |
1296 | { | |
1297 | if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) | |
1298 | arch_kgdb_ops.correct_hw_break(); | |
1299 | } | |
1300 | #else /* ! CONFIG_KGDB */ | |
1301 | #define dbg_restore_debug_regs() | |
1302 | #endif /* ! CONFIG_KGDB */ | |
1303 | ||
ce4b1b16 IM |
1304 | static void wait_for_master_cpu(int cpu) |
1305 | { | |
1306 | #ifdef CONFIG_SMP | |
1307 | /* | |
1308 | * wait for ACK from master CPU before continuing | |
1309 | * with AP initialization | |
1310 | */ | |
1311 | WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); | |
1312 | while (!cpumask_test_cpu(cpu, cpu_callout_mask)) | |
1313 | cpu_relax(); | |
1314 | #endif | |
1315 | } | |
1316 | ||
d2cbcc49 RR |
1317 | /* |
1318 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1319 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1320 | * and IDT. We reload them nevertheless, this function acts as a | |
1321 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 1322 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 1323 | */ |
1ba76586 | 1324 | #ifdef CONFIG_X86_64 |
0f3fa48a | 1325 | |
148f9bb8 | 1326 | void cpu_init(void) |
1ba76586 | 1327 | { |
0fe1e009 | 1328 | struct orig_ist *oist; |
1ba76586 | 1329 | struct task_struct *me; |
0f3fa48a IM |
1330 | struct tss_struct *t; |
1331 | unsigned long v; | |
ce4b1b16 | 1332 | int cpu = stack_smp_processor_id(); |
1ba76586 YL |
1333 | int i; |
1334 | ||
ce4b1b16 IM |
1335 | wait_for_master_cpu(cpu); |
1336 | ||
1e02ce4c AL |
1337 | /* |
1338 | * Initialize the CR4 shadow before doing anything that could | |
1339 | * try to read it. | |
1340 | */ | |
1341 | cr4_init_shadow(); | |
1342 | ||
e6ebf5de FY |
1343 | /* |
1344 | * Load microcode on this cpu if a valid microcode is available. | |
1345 | * This is early microcode loading procedure. | |
1346 | */ | |
1347 | load_ucode_ap(); | |
1348 | ||
24933b82 | 1349 | t = &per_cpu(cpu_tss, cpu); |
0fe1e009 | 1350 | oist = &per_cpu(orig_ist, cpu); |
0f3fa48a | 1351 | |
e7a22c1e | 1352 | #ifdef CONFIG_NUMA |
27fd185f | 1353 | if (this_cpu_read(numa_node) == 0 && |
e534c7c5 LS |
1354 | early_cpu_to_node(cpu) != NUMA_NO_NODE) |
1355 | set_numa_node(early_cpu_to_node(cpu)); | |
e7a22c1e | 1356 | #endif |
1ba76586 YL |
1357 | |
1358 | me = current; | |
1359 | ||
2eaad1fd | 1360 | pr_debug("Initializing CPU#%d\n", cpu); |
1ba76586 | 1361 | |
375074cc | 1362 | cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); |
1ba76586 YL |
1363 | |
1364 | /* | |
1365 | * Initialize the per-CPU GDT with the boot GDT, | |
1366 | * and set up the GDT descriptor: | |
1367 | */ | |
1368 | ||
552be871 | 1369 | switch_to_new_gdt(cpu); |
2697fbd5 BG |
1370 | loadsegment(fs, 0); |
1371 | ||
cf910e83 | 1372 | load_current_idt(); |
1ba76586 YL |
1373 | |
1374 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1375 | syscall_init(); | |
1376 | ||
1377 | wrmsrl(MSR_FS_BASE, 0); | |
1378 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1379 | barrier(); | |
1380 | ||
4763ed4d | 1381 | x86_configure_nx(); |
659006bf | 1382 | x2apic_setup(); |
1ba76586 YL |
1383 | |
1384 | /* | |
1385 | * set up and load the per-CPU TSS | |
1386 | */ | |
0fe1e009 | 1387 | if (!oist->ist[0]) { |
92d65b23 | 1388 | char *estacks = per_cpu(exception_stacks, cpu); |
0f3fa48a | 1389 | |
1ba76586 | 1390 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
0f3fa48a | 1391 | estacks += exception_stack_sizes[v]; |
0fe1e009 | 1392 | oist->ist[v] = t->x86_tss.ist[v] = |
1ba76586 | 1393 | (unsigned long)estacks; |
228bdaa9 SR |
1394 | if (v == DEBUG_STACK-1) |
1395 | per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; | |
1ba76586 YL |
1396 | } |
1397 | } | |
1398 | ||
1399 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
0f3fa48a | 1400 | |
1ba76586 YL |
1401 | /* |
1402 | * <= is required because the CPU will access up to | |
1403 | * 8 bits beyond the end of the IO permission bitmap. | |
1404 | */ | |
1405 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1406 | t->io_bitmap[i] = ~0UL; | |
1407 | ||
1408 | atomic_inc(&init_mm.mm_count); | |
1409 | me->active_mm = &init_mm; | |
8c5dfd25 | 1410 | BUG_ON(me->mm); |
1ba76586 YL |
1411 | enter_lazy_tlb(&init_mm, me); |
1412 | ||
1413 | load_sp0(t, ¤t->thread); | |
1414 | set_tss_desc(cpu, t); | |
1415 | load_TR_desc(); | |
37868fe1 | 1416 | load_mm_ldt(&init_mm); |
1ba76586 | 1417 | |
0bb9fef9 JW |
1418 | clear_all_debug_regs(); |
1419 | dbg_restore_debug_regs(); | |
1ba76586 | 1420 | |
21c4cd10 | 1421 | fpu__init_cpu(); |
1ba76586 | 1422 | |
1ba76586 YL |
1423 | if (is_uv_system()) |
1424 | uv_cpu_init(); | |
1425 | } | |
1426 | ||
1427 | #else | |
1428 | ||
148f9bb8 | 1429 | void cpu_init(void) |
9ee79a3d | 1430 | { |
d2cbcc49 RR |
1431 | int cpu = smp_processor_id(); |
1432 | struct task_struct *curr = current; | |
24933b82 | 1433 | struct tss_struct *t = &per_cpu(cpu_tss, cpu); |
9ee79a3d | 1434 | struct thread_struct *thread = &curr->thread; |
62111195 | 1435 | |
ce4b1b16 | 1436 | wait_for_master_cpu(cpu); |
e6ebf5de | 1437 | |
5b2bdbc8 SR |
1438 | /* |
1439 | * Initialize the CR4 shadow before doing anything that could | |
1440 | * try to read it. | |
1441 | */ | |
1442 | cr4_init_shadow(); | |
1443 | ||
ce4b1b16 | 1444 | show_ucode_info_early(); |
62111195 JF |
1445 | |
1446 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1447 | ||
9298b815 | 1448 | if (cpu_feature_enabled(X86_FEATURE_VME) || cpu_has_tsc || cpu_has_de) |
375074cc | 1449 | cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); |
62111195 | 1450 | |
cf910e83 | 1451 | load_current_idt(); |
552be871 | 1452 | switch_to_new_gdt(cpu); |
1da177e4 | 1453 | |
1da177e4 LT |
1454 | /* |
1455 | * Set up and load the per-CPU TSS and LDT | |
1456 | */ | |
1457 | atomic_inc(&init_mm.mm_count); | |
62111195 | 1458 | curr->active_mm = &init_mm; |
8c5dfd25 | 1459 | BUG_ON(curr->mm); |
62111195 | 1460 | enter_lazy_tlb(&init_mm, curr); |
1da177e4 | 1461 | |
faca6227 | 1462 | load_sp0(t, thread); |
34048c9e | 1463 | set_tss_desc(cpu, t); |
1da177e4 | 1464 | load_TR_desc(); |
37868fe1 | 1465 | load_mm_ldt(&init_mm); |
1da177e4 | 1466 | |
f9a196b8 TG |
1467 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); |
1468 | ||
22c4e308 | 1469 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1470 | /* Set up doublefault TSS pointer in the GDT */ |
1471 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1472 | #endif |
1da177e4 | 1473 | |
9766cdbc | 1474 | clear_all_debug_regs(); |
0bb9fef9 | 1475 | dbg_restore_debug_regs(); |
1da177e4 | 1476 | |
21c4cd10 | 1477 | fpu__init_cpu(); |
1da177e4 | 1478 | } |
1ba76586 | 1479 | #endif |
5700f743 BP |
1480 | |
1481 | #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS | |
1482 | void warn_pre_alternatives(void) | |
1483 | { | |
1484 | WARN(1, "You're using static_cpu_has before alternatives have run!\n"); | |
1485 | } | |
1486 | EXPORT_SYMBOL_GPL(warn_pre_alternatives); | |
1487 | #endif | |
4a90a99c BP |
1488 | |
1489 | inline bool __static_cpu_has_safe(u16 bit) | |
1490 | { | |
1491 | return boot_cpu_has(bit); | |
1492 | } | |
1493 | EXPORT_SYMBOL_GPL(__static_cpu_has_safe); | |
b51ef52d LA |
1494 | |
1495 | static void bsp_resume(void) | |
1496 | { | |
1497 | if (this_cpu->c_bsp_resume) | |
1498 | this_cpu->c_bsp_resume(&boot_cpu_data); | |
1499 | } | |
1500 | ||
1501 | static struct syscore_ops cpu_syscore_ops = { | |
1502 | .resume = bsp_resume, | |
1503 | }; | |
1504 | ||
1505 | static int __init init_cpu_syscore(void) | |
1506 | { | |
1507 | register_syscore_ops(&cpu_syscore_ops); | |
1508 | return 0; | |
1509 | } | |
1510 | core_initcall(init_cpu_syscore); |