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1da177e4 LT |
1 | #include <linux/init.h> |
2 | #include <linux/string.h> | |
3 | #include <linux/delay.h> | |
4 | #include <linux/smp.h> | |
5 | #include <linux/module.h> | |
6 | #include <linux/percpu.h> | |
2b932f6c | 7 | #include <linux/bootmem.h> |
1da177e4 LT |
8 | #include <asm/processor.h> |
9 | #include <asm/i387.h> | |
10 | #include <asm/msr.h> | |
11 | #include <asm/io.h> | |
12 | #include <asm/mmu_context.h> | |
27b07da7 | 13 | #include <asm/mtrr.h> |
a03a3e28 | 14 | #include <asm/mce.h> |
8d4a4300 | 15 | #include <asm/pat.h> |
b6734c35 | 16 | #include <asm/asm.h> |
1da177e4 LT |
17 | #ifdef CONFIG_X86_LOCAL_APIC |
18 | #include <asm/mpspec.h> | |
19 | #include <asm/apic.h> | |
20 | #include <mach_apic.h> | |
21 | #endif | |
22 | ||
23 | #include "cpu.h" | |
24 | ||
7a61d35d | 25 | DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = { |
6842ef0e GOC |
26 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, |
27 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, | |
28 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, | |
29 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, | |
bf504672 RR |
30 | /* |
31 | * Segments used for calling PnP BIOS have byte granularity. | |
32 | * They code segments and data segments have fixed 64k limits, | |
33 | * the transfer segment sizes are set at run time. | |
34 | */ | |
6842ef0e GOC |
35 | /* 32-bit code */ |
36 | [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, | |
37 | /* 16-bit code */ | |
38 | [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, | |
39 | /* 16-bit data */ | |
40 | [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, | |
41 | /* 16-bit data */ | |
42 | [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, | |
43 | /* 16-bit data */ | |
44 | [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, | |
bf504672 RR |
45 | /* |
46 | * The APM segments have byte granularity and their bases | |
47 | * are set at run time. All have 64k limits. | |
48 | */ | |
6842ef0e GOC |
49 | /* 32-bit code */ |
50 | [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, | |
bf504672 | 51 | /* 16-bit code */ |
6842ef0e GOC |
52 | [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, |
53 | /* data */ | |
54 | [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, | |
bf504672 | 55 | |
6842ef0e GOC |
56 | [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, |
57 | [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } }, | |
7a61d35d JF |
58 | } }; |
59 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); | |
ae1ee11b | 60 | |
7d851c8d AK |
61 | __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; |
62 | ||
3bc9b76b | 63 | static int cachesize_override __cpuinitdata = -1; |
3bc9b76b | 64 | static int disable_x86_serial_nr __cpuinitdata = 1; |
1da177e4 | 65 | |
34048c9e | 66 | struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 67 | |
34048c9e | 68 | static void __cpuinit default_init(struct cpuinfo_x86 *c) |
1da177e4 LT |
69 | { |
70 | /* Not much we can do here... */ | |
71 | /* Check if at least it has cpuid */ | |
72 | if (c->cpuid_level == -1) { | |
73 | /* No cpuid. It must be an ancient CPU */ | |
74 | if (c->x86 == 4) | |
75 | strcpy(c->x86_model_id, "486"); | |
76 | else if (c->x86 == 3) | |
77 | strcpy(c->x86_model_id, "386"); | |
78 | } | |
79 | } | |
80 | ||
95414930 | 81 | static struct cpu_dev __cpuinitdata default_cpu = { |
1da177e4 | 82 | .c_init = default_init, |
fe38d855 | 83 | .c_vendor = "Unknown", |
1da177e4 | 84 | }; |
34048c9e | 85 | static struct cpu_dev *this_cpu __cpuinitdata = &default_cpu; |
1da177e4 LT |
86 | |
87 | static int __init cachesize_setup(char *str) | |
88 | { | |
34048c9e | 89 | get_option(&str, &cachesize_override); |
1da177e4 LT |
90 | return 1; |
91 | } | |
92 | __setup("cachesize=", cachesize_setup); | |
93 | ||
3bc9b76b | 94 | int __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
95 | { |
96 | unsigned int *v; | |
97 | char *p, *q; | |
98 | ||
99 | if (cpuid_eax(0x80000000) < 0x80000004) | |
100 | return 0; | |
101 | ||
102 | v = (unsigned int *) c->x86_model_id; | |
103 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
104 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
105 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
106 | c->x86_model_id[48] = 0; | |
107 | ||
108 | /* Intel chips right-justify this string for some dumb reason; | |
109 | undo that brain damage */ | |
110 | p = q = &c->x86_model_id[0]; | |
34048c9e | 111 | while (*p == ' ') |
1da177e4 | 112 | p++; |
34048c9e PC |
113 | if (p != q) { |
114 | while (*p) | |
1da177e4 | 115 | *q++ = *p++; |
34048c9e | 116 | while (q <= &c->x86_model_id[48]) |
1da177e4 LT |
117 | *q++ = '\0'; /* Zero-pad the rest */ |
118 | } | |
119 | ||
120 | return 1; | |
121 | } | |
122 | ||
123 | ||
3bc9b76b | 124 | void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) |
1da177e4 LT |
125 | { |
126 | unsigned int n, dummy, ecx, edx, l2size; | |
127 | ||
128 | n = cpuid_eax(0x80000000); | |
129 | ||
130 | if (n >= 0x80000005) { | |
131 | cpuid(0x80000005, &dummy, &dummy, &ecx, &edx); | |
132 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", | |
133 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); | |
34048c9e | 134 | c->x86_cache_size = (ecx>>24)+(edx>>24); |
1da177e4 LT |
135 | } |
136 | ||
137 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
138 | return; | |
139 | ||
140 | ecx = cpuid_ecx(0x80000006); | |
141 | l2size = ecx >> 16; | |
34048c9e | 142 | |
1da177e4 LT |
143 | /* do processor-specific cache resizing */ |
144 | if (this_cpu->c_size_cache) | |
34048c9e | 145 | l2size = this_cpu->c_size_cache(c, l2size); |
1da177e4 LT |
146 | |
147 | /* Allow user to override all this if necessary. */ | |
148 | if (cachesize_override != -1) | |
149 | l2size = cachesize_override; | |
150 | ||
34048c9e | 151 | if (l2size == 0) |
1da177e4 LT |
152 | return; /* Again, no L2 cache is possible */ |
153 | ||
154 | c->x86_cache_size = l2size; | |
155 | ||
156 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
157 | l2size, ecx & 0xFF); | |
158 | } | |
159 | ||
34048c9e PC |
160 | /* |
161 | * Naming convention should be: <Name> [(<Codename>)] | |
162 | * This table only is used unless init_<vendor>() below doesn't set it; | |
163 | * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used | |
164 | * | |
165 | */ | |
1da177e4 LT |
166 | |
167 | /* Look up CPU names by table lookup. */ | |
3bc9b76b | 168 | static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c) |
1da177e4 LT |
169 | { |
170 | struct cpu_model_info *info; | |
171 | ||
34048c9e | 172 | if (c->x86_model >= 16) |
1da177e4 LT |
173 | return NULL; /* Range check */ |
174 | ||
175 | if (!this_cpu) | |
176 | return NULL; | |
177 | ||
178 | info = this_cpu->c_models; | |
179 | ||
180 | while (info && info->family) { | |
181 | if (info->family == c->x86) | |
182 | return info->model_names[c->x86_model]; | |
183 | info++; | |
184 | } | |
185 | return NULL; /* Not found */ | |
186 | } | |
187 | ||
188 | ||
3bc9b76b | 189 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c, int early) |
1da177e4 LT |
190 | { |
191 | char *v = c->x86_vendor_id; | |
192 | int i; | |
fe38d855 | 193 | static int printed; |
1da177e4 LT |
194 | |
195 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
196 | if (cpu_devs[i]) { | |
34048c9e PC |
197 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || |
198 | (cpu_devs[i]->c_ident[1] && | |
199 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
1da177e4 LT |
200 | c->x86_vendor = i; |
201 | if (!early) | |
202 | this_cpu = cpu_devs[i]; | |
fe38d855 | 203 | return; |
1da177e4 LT |
204 | } |
205 | } | |
206 | } | |
fe38d855 CE |
207 | if (!printed) { |
208 | printed++; | |
209 | printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n"); | |
210 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); | |
211 | } | |
212 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
213 | this_cpu = &default_cpu; | |
1da177e4 LT |
214 | } |
215 | ||
216 | ||
34048c9e | 217 | static int __init x86_fxsr_setup(char *s) |
1da177e4 | 218 | { |
13530257 AK |
219 | setup_clear_cpu_cap(X86_FEATURE_FXSR); |
220 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
1da177e4 LT |
221 | return 1; |
222 | } | |
223 | __setup("nofxsr", x86_fxsr_setup); | |
224 | ||
225 | ||
34048c9e | 226 | static int __init x86_sep_setup(char *s) |
4f886511 | 227 | { |
13530257 | 228 | setup_clear_cpu_cap(X86_FEATURE_SEP); |
4f886511 CE |
229 | return 1; |
230 | } | |
231 | __setup("nosep", x86_sep_setup); | |
232 | ||
233 | ||
1da177e4 LT |
234 | /* Standard macro to see if a specific flag is changeable */ |
235 | static inline int flag_is_changeable_p(u32 flag) | |
236 | { | |
237 | u32 f1, f2; | |
238 | ||
239 | asm("pushfl\n\t" | |
240 | "pushfl\n\t" | |
241 | "popl %0\n\t" | |
242 | "movl %0,%1\n\t" | |
243 | "xorl %2,%0\n\t" | |
244 | "pushl %0\n\t" | |
245 | "popfl\n\t" | |
246 | "pushfl\n\t" | |
247 | "popl %0\n\t" | |
248 | "popfl\n\t" | |
249 | : "=&r" (f1), "=&r" (f2) | |
250 | : "ir" (flag)); | |
251 | ||
252 | return ((f1^f2) & flag) != 0; | |
253 | } | |
254 | ||
255 | ||
256 | /* Probe for the CPUID instruction */ | |
3bc9b76b | 257 | static int __cpuinit have_cpuid_p(void) |
1da177e4 LT |
258 | { |
259 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
260 | } | |
261 | ||
d7cd5611 | 262 | void __init cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 263 | { |
1da177e4 | 264 | /* Get vendor name */ |
4a148513 HH |
265 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
266 | (unsigned int *)&c->x86_vendor_id[0], | |
267 | (unsigned int *)&c->x86_vendor_id[8], | |
268 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 269 | |
1da177e4 LT |
270 | c->x86 = 4; |
271 | if (c->cpuid_level >= 0x00000001) { | |
272 | u32 junk, tfms, cap0, misc; | |
273 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
274 | c->x86 = (tfms >> 8) & 15; | |
275 | c->x86_model = (tfms >> 4) & 15; | |
f5f786d0 | 276 | if (c->x86 == 0xf) |
1da177e4 | 277 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 278 | if (c->x86 >= 0x6) |
1da177e4 | 279 | c->x86_model += ((tfms >> 16) & 0xF) << 4; |
1da177e4 | 280 | c->x86_mask = tfms & 15; |
d4387bd3 | 281 | if (cap0 & (1<<19)) { |
1da177e4 | 282 | c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8; |
d4387bd3 HY |
283 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
284 | } | |
1da177e4 | 285 | } |
1da177e4 | 286 | } |
093af8d7 YL |
287 | static void __cpuinit early_get_cap(struct cpuinfo_x86 *c) |
288 | { | |
289 | u32 tfms, xlvl; | |
4a148513 | 290 | unsigned int ebx; |
093af8d7 YL |
291 | |
292 | memset(&c->x86_capability, 0, sizeof c->x86_capability); | |
293 | if (have_cpuid_p()) { | |
294 | /* Intel-defined flags: level 0x00000001 */ | |
295 | if (c->cpuid_level >= 0x00000001) { | |
296 | u32 capability, excap; | |
297 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); | |
298 | c->x86_capability[0] = capability; | |
299 | c->x86_capability[4] = excap; | |
300 | } | |
301 | ||
302 | /* AMD-defined flags: level 0x80000001 */ | |
303 | xlvl = cpuid_eax(0x80000000); | |
304 | if ((xlvl & 0xffff0000) == 0x80000000) { | |
305 | if (xlvl >= 0x80000001) { | |
306 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
307 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
308 | } | |
309 | } | |
310 | ||
311 | } | |
312 | ||
313 | } | |
1da177e4 | 314 | |
34048c9e PC |
315 | /* |
316 | * Do minimum CPU detection early. | |
317 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
318 | * cache alignment. | |
319 | * The others are not touched to avoid unwanted side effects. | |
320 | * | |
321 | * WARNING: this function is only called on the BP. Don't add code here | |
322 | * that is supposed to run on all CPUs. | |
323 | */ | |
d7cd5611 RR |
324 | static void __init early_cpu_detect(void) |
325 | { | |
326 | struct cpuinfo_x86 *c = &boot_cpu_data; | |
327 | ||
328 | c->x86_cache_alignment = 32; | |
d4387bd3 | 329 | c->x86_clflush_size = 32; |
d7cd5611 RR |
330 | |
331 | if (!have_cpuid_p()) | |
332 | return; | |
333 | ||
334 | cpu_detect(c); | |
335 | ||
336 | get_cpu_vendor(c, 1); | |
2b16a235 | 337 | |
12cf105c KH |
338 | early_get_cap(c); |
339 | ||
03ae5768 TP |
340 | if (c->x86_vendor != X86_VENDOR_UNKNOWN && |
341 | cpu_devs[c->x86_vendor]->c_early_init) | |
342 | cpu_devs[c->x86_vendor]->c_early_init(c); | |
d7cd5611 RR |
343 | } |
344 | ||
b6734c35 PA |
345 | /* |
346 | * The NOPL instruction is supposed to exist on all CPUs with | |
347 | * family >= 6, unfortunately, that's not true in practice because | |
348 | * of early VIA chips and (more importantly) broken virtualizers that | |
349 | * are not easy to detect. Hence, probe for it based on first | |
350 | * principles. | |
351 | */ | |
352 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
353 | { | |
354 | const u32 nopl_signature = 0x888c53b1; /* Random number */ | |
355 | u32 has_nopl = nopl_signature; | |
356 | ||
357 | clear_cpu_cap(c, X86_FEATURE_NOPL); | |
358 | if (c->x86 >= 6) { | |
359 | asm volatile("\n" | |
360 | "1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */ | |
361 | "2:\n" | |
362 | " .section .fixup,\"ax\"\n" | |
363 | "3: xor %0,%0\n" | |
364 | " jmp 2b\n" | |
365 | " .previous\n" | |
366 | _ASM_EXTABLE(1b,3b) | |
367 | : "+a" (has_nopl)); | |
368 | ||
369 | if (has_nopl == nopl_signature) | |
370 | set_cpu_cap(c, X86_FEATURE_NOPL); | |
371 | } | |
372 | } | |
373 | ||
34048c9e | 374 | static void __cpuinit generic_identify(struct cpuinfo_x86 *c) |
1da177e4 LT |
375 | { |
376 | u32 tfms, xlvl; | |
4a148513 | 377 | unsigned int ebx; |
1da177e4 LT |
378 | |
379 | if (have_cpuid_p()) { | |
380 | /* Get vendor name */ | |
4a148513 HH |
381 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
382 | (unsigned int *)&c->x86_vendor_id[0], | |
383 | (unsigned int *)&c->x86_vendor_id[8], | |
384 | (unsigned int *)&c->x86_vendor_id[4]); | |
34048c9e | 385 | |
1da177e4 LT |
386 | get_cpu_vendor(c, 0); |
387 | /* Initialize the standard set of capabilities */ | |
388 | /* Note that the vendor-specific code below might override */ | |
1da177e4 | 389 | /* Intel-defined flags: level 0x00000001 */ |
34048c9e | 390 | if (c->cpuid_level >= 0x00000001) { |
1da177e4 | 391 | u32 capability, excap; |
1e9f28fa | 392 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); |
1da177e4 LT |
393 | c->x86_capability[0] = capability; |
394 | c->x86_capability[4] = excap; | |
395 | c->x86 = (tfms >> 8) & 15; | |
396 | c->x86_model = (tfms >> 4) & 15; | |
ed2da193 | 397 | if (c->x86 == 0xf) |
1da177e4 | 398 | c->x86 += (tfms >> 20) & 0xff; |
ed2da193 | 399 | if (c->x86 >= 0x6) |
1da177e4 | 400 | c->x86_model += ((tfms >> 16) & 0xF) << 4; |
1da177e4 | 401 | c->x86_mask = tfms & 15; |
01aaea1a | 402 | c->initial_apicid = (ebx >> 24) & 0xFF; |
96c52749 | 403 | #ifdef CONFIG_X86_HT |
01aaea1a YL |
404 | c->apicid = phys_pkg_id(c->initial_apicid, 0); |
405 | c->phys_proc_id = c->initial_apicid; | |
1e9f28fa | 406 | #else |
01aaea1a | 407 | c->apicid = c->initial_apicid; |
1e9f28fa | 408 | #endif |
9716951e | 409 | if (test_cpu_cap(c, X86_FEATURE_CLFLSH)) |
770d132f | 410 | c->x86_clflush_size = ((ebx >> 8) & 0xff) * 8; |
1da177e4 LT |
411 | } else { |
412 | /* Have CPUID level 0 only - unheard of */ | |
413 | c->x86 = 4; | |
414 | } | |
415 | ||
416 | /* AMD-defined flags: level 0x80000001 */ | |
417 | xlvl = cpuid_eax(0x80000000); | |
34048c9e PC |
418 | if ((xlvl & 0xffff0000) == 0x80000000) { |
419 | if (xlvl >= 0x80000001) { | |
1da177e4 LT |
420 | c->x86_capability[1] = cpuid_edx(0x80000001); |
421 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
422 | } | |
34048c9e | 423 | if (xlvl >= 0x80000004) |
1da177e4 LT |
424 | get_model_name(c); /* Default name */ |
425 | } | |
1d67953f VP |
426 | |
427 | init_scattered_cpuid_features(c); | |
b6734c35 | 428 | detect_nopl(c); |
1da177e4 LT |
429 | } |
430 | } | |
431 | ||
3bc9b76b | 432 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
1da177e4 | 433 | { |
34048c9e | 434 | if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) { |
1da177e4 | 435 | /* Disable processor serial number */ |
34048c9e PC |
436 | unsigned long lo, hi; |
437 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
1da177e4 | 438 | lo |= 0x200000; |
34048c9e | 439 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); |
1da177e4 | 440 | printk(KERN_NOTICE "CPU serial number disabled.\n"); |
4cbe668a | 441 | clear_cpu_cap(c, X86_FEATURE_PN); |
1da177e4 LT |
442 | |
443 | /* Disabling the serial number may affect the cpuid level */ | |
444 | c->cpuid_level = cpuid_eax(0); | |
445 | } | |
446 | } | |
447 | ||
448 | static int __init x86_serial_nr_setup(char *s) | |
449 | { | |
450 | disable_x86_serial_nr = 0; | |
451 | return 1; | |
452 | } | |
453 | __setup("serialnumber", x86_serial_nr_setup); | |
454 | ||
455 | ||
456 | ||
457 | /* | |
458 | * This does the hard work of actually picking apart the CPU stuff... | |
459 | */ | |
9a250347 | 460 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
461 | { |
462 | int i; | |
463 | ||
464 | c->loops_per_jiffy = loops_per_jiffy; | |
465 | c->x86_cache_size = -1; | |
466 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
467 | c->cpuid_level = -1; /* CPUID not detected */ | |
468 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ | |
469 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
470 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 471 | c->x86_max_cores = 1; |
770d132f | 472 | c->x86_clflush_size = 32; |
1da177e4 LT |
473 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
474 | ||
475 | if (!have_cpuid_p()) { | |
34048c9e PC |
476 | /* |
477 | * First of all, decide if this is a 486 or higher | |
478 | * It's a 486 if we can modify the AC flag | |
479 | */ | |
480 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
1da177e4 LT |
481 | c->x86 = 4; |
482 | else | |
483 | c->x86 = 3; | |
484 | } | |
485 | ||
486 | generic_identify(c); | |
487 | ||
3898534d | 488 | if (this_cpu->c_identify) |
1da177e4 LT |
489 | this_cpu->c_identify(c); |
490 | ||
1da177e4 LT |
491 | /* |
492 | * Vendor-specific initialization. In this section we | |
493 | * canonicalize the feature flags, meaning if there are | |
494 | * features a certain CPU supports which CPUID doesn't | |
495 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
496 | * we handle them here. | |
497 | * | |
498 | * At the end of this section, c->x86_capability better | |
499 | * indicate the features this CPU genuinely supports! | |
500 | */ | |
501 | if (this_cpu->c_init) | |
502 | this_cpu->c_init(c); | |
503 | ||
504 | /* Disable the PN if appropriate */ | |
505 | squash_the_stupid_serial_number(c); | |
506 | ||
507 | /* | |
508 | * The vendor-specific functions might have changed features. Now | |
509 | * we do "generic changes." | |
510 | */ | |
511 | ||
1da177e4 | 512 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 513 | if (!c->x86_model_id[0]) { |
1da177e4 LT |
514 | char *p; |
515 | p = table_lookup_model(c); | |
34048c9e | 516 | if (p) |
1da177e4 LT |
517 | strcpy(c->x86_model_id, p); |
518 | else | |
519 | /* Last resort... */ | |
520 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 521 | c->x86, c->x86_model); |
1da177e4 LT |
522 | } |
523 | ||
1da177e4 LT |
524 | /* |
525 | * On SMP, boot_cpu_data holds the common feature set between | |
526 | * all CPUs; so make sure that we indicate which features are | |
527 | * common between the CPUs. The first time this routine gets | |
528 | * executed, c == &boot_cpu_data. | |
529 | */ | |
34048c9e | 530 | if (c != &boot_cpu_data) { |
1da177e4 | 531 | /* AND the already accumulated flags with these */ |
34048c9e | 532 | for (i = 0 ; i < NCAPINTS ; i++) |
1da177e4 LT |
533 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
534 | } | |
535 | ||
7d851c8d AK |
536 | /* Clear all flags overriden by options */ |
537 | for (i = 0; i < NCAPINTS; i++) | |
12c247a6 | 538 | c->x86_capability[i] &= ~cleared_cpu_caps[i]; |
7d851c8d | 539 | |
1da177e4 | 540 | /* Init Machine Check Exception if available. */ |
1da177e4 | 541 | mcheck_init(c); |
30d432df AK |
542 | |
543 | select_idle_routine(c); | |
a6c4e076 | 544 | } |
31ab269a | 545 | |
a6c4e076 JF |
546 | void __init identify_boot_cpu(void) |
547 | { | |
548 | identify_cpu(&boot_cpu_data); | |
549 | sysenter_setup(); | |
6fe940d6 | 550 | enable_sep_cpu(); |
a6c4e076 | 551 | } |
3b520b23 | 552 | |
a6c4e076 JF |
553 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) |
554 | { | |
555 | BUG_ON(c == &boot_cpu_data); | |
556 | identify_cpu(c); | |
557 | enable_sep_cpu(); | |
558 | mtrr_ap_init(); | |
1da177e4 LT |
559 | } |
560 | ||
561 | #ifdef CONFIG_X86_HT | |
3bc9b76b | 562 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 LT |
563 | { |
564 | u32 eax, ebx, ecx, edx; | |
94605eff | 565 | int index_msb, core_bits; |
1da177e4 | 566 | |
94605eff SS |
567 | cpuid(1, &eax, &ebx, &ecx, &edx); |
568 | ||
63518644 | 569 | if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
1da177e4 LT |
570 | return; |
571 | ||
1da177e4 LT |
572 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
573 | ||
574 | if (smp_num_siblings == 1) { | |
575 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
34048c9e | 576 | } else if (smp_num_siblings > 1) { |
1da177e4 LT |
577 | |
578 | if (smp_num_siblings > NR_CPUS) { | |
4b89aff9 RS |
579 | printk(KERN_WARNING "CPU: Unsupported number of the " |
580 | "siblings %d", smp_num_siblings); | |
1da177e4 LT |
581 | smp_num_siblings = 1; |
582 | return; | |
583 | } | |
94605eff SS |
584 | |
585 | index_msb = get_count_order(smp_num_siblings); | |
01aaea1a | 586 | c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb); |
1da177e4 LT |
587 | |
588 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
4b89aff9 | 589 | c->phys_proc_id); |
3dd9d514 | 590 | |
94605eff | 591 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
3dd9d514 | 592 | |
94605eff | 593 | index_msb = get_count_order(smp_num_siblings) ; |
3dd9d514 | 594 | |
94605eff | 595 | core_bits = get_count_order(c->x86_max_cores); |
3dd9d514 | 596 | |
01aaea1a | 597 | c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) & |
94605eff | 598 | ((1 << core_bits) - 1); |
3dd9d514 | 599 | |
94605eff | 600 | if (c->x86_max_cores > 1) |
3dd9d514 | 601 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", |
4b89aff9 | 602 | c->cpu_core_id); |
1da177e4 LT |
603 | } |
604 | } | |
605 | #endif | |
606 | ||
191679fd AK |
607 | static __init int setup_noclflush(char *arg) |
608 | { | |
609 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
610 | return 1; | |
611 | } | |
612 | __setup("noclflush", setup_noclflush); | |
613 | ||
3bc9b76b | 614 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 LT |
615 | { |
616 | char *vendor = NULL; | |
617 | ||
618 | if (c->x86_vendor < X86_VENDOR_NUM) | |
619 | vendor = this_cpu->c_vendor; | |
620 | else if (c->cpuid_level >= 0) | |
621 | vendor = c->x86_vendor_id; | |
622 | ||
623 | if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor))) | |
624 | printk("%s ", vendor); | |
625 | ||
626 | if (!c->x86_model_id[0]) | |
627 | printk("%d86", c->x86); | |
628 | else | |
629 | printk("%s", c->x86_model_id); | |
630 | ||
34048c9e | 631 | if (c->x86_mask || c->cpuid_level >= 0) |
1da177e4 LT |
632 | printk(" stepping %02x\n", c->x86_mask); |
633 | else | |
634 | printk("\n"); | |
635 | } | |
636 | ||
ac72e788 AK |
637 | static __init int setup_disablecpuid(char *arg) |
638 | { | |
639 | int bit; | |
640 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) | |
641 | setup_clear_cpu_cap(bit); | |
642 | else | |
643 | return 0; | |
644 | return 1; | |
645 | } | |
646 | __setup("clearcpuid=", setup_disablecpuid); | |
647 | ||
3bc9b76b | 648 | cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE; |
1da177e4 | 649 | |
1da177e4 LT |
650 | void __init early_cpu_init(void) |
651 | { | |
03ae5768 TP |
652 | struct cpu_vendor_dev *cvdev; |
653 | ||
654 | for (cvdev = __x86cpuvendor_start ; | |
655 | cvdev < __x86cpuvendor_end ; | |
656 | cvdev++) | |
657 | cpu_devs[cvdev->vendor] = cvdev->cpu_dev; | |
658 | ||
1da177e4 | 659 | early_cpu_detect(); |
8d4a4300 | 660 | validate_pat_support(&boot_cpu_data); |
1da177e4 | 661 | } |
62111195 | 662 | |
7c3576d2 | 663 | /* Make sure %fs is initialized properly in idle threads */ |
6b2fb3c6 | 664 | struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) |
f95d47ca JF |
665 | { |
666 | memset(regs, 0, sizeof(struct pt_regs)); | |
65ea5b03 | 667 | regs->fs = __KERNEL_PERCPU; |
f95d47ca JF |
668 | return regs; |
669 | } | |
670 | ||
c5413fbe JF |
671 | /* Current gdt points %fs at the "master" per-cpu area: after this, |
672 | * it's on the real one. */ | |
673 | void switch_to_new_gdt(void) | |
674 | { | |
6b68f01b | 675 | struct desc_ptr gdt_descr; |
c5413fbe JF |
676 | |
677 | gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id()); | |
678 | gdt_descr.size = GDT_SIZE - 1; | |
679 | load_gdt(&gdt_descr); | |
680 | asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory"); | |
681 | } | |
682 | ||
d2cbcc49 RR |
683 | /* |
684 | * cpu_init() initializes state that is per-CPU. Some data is already | |
685 | * initialized (naturally) in the bootstrap process, such as the GDT | |
686 | * and IDT. We reload them nevertheless, this function acts as a | |
687 | * 'CPU state barrier', nothing should get across. | |
688 | */ | |
689 | void __cpuinit cpu_init(void) | |
9ee79a3d | 690 | { |
d2cbcc49 RR |
691 | int cpu = smp_processor_id(); |
692 | struct task_struct *curr = current; | |
34048c9e | 693 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 694 | struct thread_struct *thread = &curr->thread; |
62111195 JF |
695 | |
696 | if (cpu_test_and_set(cpu, cpu_initialized)) { | |
697 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); | |
698 | for (;;) local_irq_enable(); | |
699 | } | |
700 | ||
701 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
702 | ||
703 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
704 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 705 | |
4d37e7e3 | 706 | load_idt(&idt_descr); |
c5413fbe | 707 | switch_to_new_gdt(); |
1da177e4 | 708 | |
1da177e4 LT |
709 | /* |
710 | * Set up and load the per-CPU TSS and LDT | |
711 | */ | |
712 | atomic_inc(&init_mm.mm_count); | |
62111195 JF |
713 | curr->active_mm = &init_mm; |
714 | if (curr->mm) | |
715 | BUG(); | |
716 | enter_lazy_tlb(&init_mm, curr); | |
1da177e4 | 717 | |
faca6227 | 718 | load_sp0(t, thread); |
34048c9e | 719 | set_tss_desc(cpu, t); |
1da177e4 LT |
720 | load_TR_desc(); |
721 | load_LDT(&init_mm.context); | |
722 | ||
22c4e308 | 723 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
724 | /* Set up doublefault TSS pointer in the GDT */ |
725 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 726 | #endif |
1da177e4 | 727 | |
464d1a78 JF |
728 | /* Clear %gs. */ |
729 | asm volatile ("mov %0, %%gs" : : "r" (0)); | |
1da177e4 LT |
730 | |
731 | /* Clear all 6 debug registers: */ | |
4bb0d3ec ZA |
732 | set_debugreg(0, 0); |
733 | set_debugreg(0, 1); | |
734 | set_debugreg(0, 2); | |
735 | set_debugreg(0, 3); | |
736 | set_debugreg(0, 6); | |
737 | set_debugreg(0, 7); | |
1da177e4 LT |
738 | |
739 | /* | |
740 | * Force FPU initialization: | |
741 | */ | |
742 | current_thread_info()->status = 0; | |
743 | clear_used_math(); | |
744 | mxcsr_feature_mask_init(); | |
745 | } | |
e1367daf LS |
746 | |
747 | #ifdef CONFIG_HOTPLUG_CPU | |
3bc9b76b | 748 | void __cpuinit cpu_uninit(void) |
e1367daf LS |
749 | { |
750 | int cpu = raw_smp_processor_id(); | |
751 | cpu_clear(cpu, cpu_initialized); | |
752 | ||
753 | /* lazy TLB state */ | |
754 | per_cpu(cpu_tlbstate, cpu).state = 0; | |
755 | per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm; | |
756 | } | |
757 | #endif |