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Commit | Line | Data |
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9766cdbc | 1 | #include <linux/topology.h> |
f0fc4aff | 2 | #include <linux/bootmem.h> |
9766cdbc | 3 | #include <linux/linkage.h> |
f0fc4aff | 4 | #include <linux/bitops.h> |
9766cdbc | 5 | #include <linux/kernel.h> |
f0fc4aff | 6 | #include <linux/module.h> |
9766cdbc JSR |
7 | #include <linux/percpu.h> |
8 | #include <linux/string.h> | |
1da177e4 | 9 | #include <linux/delay.h> |
9766cdbc JSR |
10 | #include <linux/sched.h> |
11 | #include <linux/init.h> | |
12 | #include <linux/kgdb.h> | |
1da177e4 | 13 | #include <linux/smp.h> |
9766cdbc JSR |
14 | #include <linux/io.h> |
15 | ||
16 | #include <asm/stackprotector.h> | |
1da177e4 | 17 | #include <asm/mmu_context.h> |
9766cdbc JSR |
18 | #include <asm/hypervisor.h> |
19 | #include <asm/processor.h> | |
20 | #include <asm/sections.h> | |
21 | #include <asm/cpumask.h> | |
22 | #include <asm/pgtable.h> | |
23 | #include <asm/atomic.h> | |
24 | #include <asm/proto.h> | |
25 | #include <asm/setup.h> | |
26 | #include <asm/apic.h> | |
27 | #include <asm/desc.h> | |
28 | #include <asm/i387.h> | |
27b07da7 | 29 | #include <asm/mtrr.h> |
9766cdbc JSR |
30 | #include <asm/numa.h> |
31 | #include <asm/asm.h> | |
32 | #include <asm/cpu.h> | |
a03a3e28 | 33 | #include <asm/mce.h> |
9766cdbc | 34 | #include <asm/msr.h> |
8d4a4300 | 35 | #include <asm/pat.h> |
b342797c | 36 | #include <asm/smp.h> |
e641f5f5 IM |
37 | |
38 | #ifdef CONFIG_X86_LOCAL_APIC | |
bdbcdd48 | 39 | #include <asm/uv/uv.h> |
1da177e4 LT |
40 | #endif |
41 | ||
42 | #include "cpu.h" | |
43 | ||
c2d1cec1 MT |
44 | #ifdef CONFIG_X86_64 |
45 | ||
46 | /* all of these masks are initialized in setup_cpu_local_masks() */ | |
c2d1cec1 | 47 | cpumask_var_t cpu_initialized_mask; |
9766cdbc JSR |
48 | cpumask_var_t cpu_callout_mask; |
49 | cpumask_var_t cpu_callin_mask; | |
c2d1cec1 MT |
50 | |
51 | /* representing cpus for which sibling maps can be computed */ | |
52 | cpumask_var_t cpu_sibling_setup_mask; | |
53 | ||
2f2f52ba | 54 | /* correctly size the local cpu masks */ |
4369f1fb | 55 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
56 | { |
57 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
58 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
59 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
60 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
61 | } | |
62 | ||
c2d1cec1 MT |
63 | #else /* CONFIG_X86_32 */ |
64 | ||
9766cdbc | 65 | cpumask_t cpu_sibling_setup_map; |
c2d1cec1 MT |
66 | cpumask_t cpu_callout_map; |
67 | cpumask_t cpu_initialized; | |
9766cdbc | 68 | cpumask_t cpu_callin_map; |
c2d1cec1 MT |
69 | |
70 | #endif /* CONFIG_X86_32 */ | |
71 | ||
72 | ||
0a488a53 YL |
73 | static struct cpu_dev *this_cpu __cpuinitdata; |
74 | ||
06deef89 | 75 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 76 | #ifdef CONFIG_X86_64 |
06deef89 BG |
77 | /* |
78 | * We need valid kernel segments for data and code in long mode too | |
79 | * IRET will check the segment types kkeil 2000/10/28 | |
80 | * Also sysret mandates a special GDT layout | |
81 | * | |
9766cdbc | 82 | * TLS descriptors are currently at a different place compared to i386. |
06deef89 BG |
83 | * Hopefully nobody expects them at a fixed place (Wine?) |
84 | */ | |
950ad7ff YL |
85 | [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } }, |
86 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } }, | |
87 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } }, | |
88 | [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } }, | |
89 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } }, | |
90 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } }, | |
950ad7ff | 91 | #else |
6842ef0e GOC |
92 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, |
93 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, | |
94 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, | |
95 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, | |
bf504672 RR |
96 | /* |
97 | * Segments used for calling PnP BIOS have byte granularity. | |
98 | * They code segments and data segments have fixed 64k limits, | |
99 | * the transfer segment sizes are set at run time. | |
100 | */ | |
6842ef0e GOC |
101 | /* 32-bit code */ |
102 | [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, | |
103 | /* 16-bit code */ | |
104 | [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, | |
105 | /* 16-bit data */ | |
106 | [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, | |
107 | /* 16-bit data */ | |
108 | [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, | |
109 | /* 16-bit data */ | |
110 | [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, | |
bf504672 RR |
111 | /* |
112 | * The APM segments have byte granularity and their bases | |
113 | * are set at run time. All have 64k limits. | |
114 | */ | |
6842ef0e GOC |
115 | /* 32-bit code */ |
116 | [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, | |
bf504672 | 117 | /* 16-bit code */ |
6842ef0e GOC |
118 | [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, |
119 | /* data */ | |
120 | [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, | |
bf504672 | 121 | |
6842ef0e | 122 | [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, |
0dd76d73 | 123 | [GDT_ENTRY_PERCPU] = { { { 0x0000ffff, 0x00cf9200 } } }, |
60a5317f | 124 | GDT_STACK_CANARY_INIT |
950ad7ff | 125 | #endif |
06deef89 | 126 | } }; |
7a61d35d | 127 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 128 | |
ba51dced | 129 | #ifdef CONFIG_X86_32 |
3bc9b76b | 130 | static int cachesize_override __cpuinitdata = -1; |
3bc9b76b | 131 | static int disable_x86_serial_nr __cpuinitdata = 1; |
1da177e4 | 132 | |
0a488a53 YL |
133 | static int __init cachesize_setup(char *str) |
134 | { | |
135 | get_option(&str, &cachesize_override); | |
136 | return 1; | |
137 | } | |
138 | __setup("cachesize=", cachesize_setup); | |
139 | ||
0a488a53 YL |
140 | static int __init x86_fxsr_setup(char *s) |
141 | { | |
142 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
143 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
144 | return 1; | |
145 | } | |
146 | __setup("nofxsr", x86_fxsr_setup); | |
147 | ||
148 | static int __init x86_sep_setup(char *s) | |
149 | { | |
150 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
151 | return 1; | |
152 | } | |
153 | __setup("nosep", x86_sep_setup); | |
154 | ||
155 | /* Standard macro to see if a specific flag is changeable */ | |
156 | static inline int flag_is_changeable_p(u32 flag) | |
157 | { | |
158 | u32 f1, f2; | |
159 | ||
94f6bac1 KH |
160 | /* |
161 | * Cyrix and IDT cpus allow disabling of CPUID | |
162 | * so the code below may return different results | |
163 | * when it is executed before and after enabling | |
164 | * the CPUID. Add "volatile" to not allow gcc to | |
165 | * optimize the subsequent calls to this function. | |
166 | */ | |
167 | asm volatile ("pushfl\n\t" | |
168 | "pushfl\n\t" | |
169 | "popl %0\n\t" | |
170 | "movl %0,%1\n\t" | |
171 | "xorl %2,%0\n\t" | |
172 | "pushl %0\n\t" | |
173 | "popfl\n\t" | |
174 | "pushfl\n\t" | |
175 | "popl %0\n\t" | |
176 | "popfl\n\t" | |
177 | : "=&r" (f1), "=&r" (f2) | |
178 | : "ir" (flag)); | |
0a488a53 YL |
179 | |
180 | return ((f1^f2) & flag) != 0; | |
181 | } | |
182 | ||
183 | /* Probe for the CPUID instruction */ | |
184 | static int __cpuinit have_cpuid_p(void) | |
185 | { | |
186 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
187 | } | |
188 | ||
189 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
190 | { | |
191 | if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) { | |
192 | /* Disable processor serial number */ | |
193 | unsigned long lo, hi; | |
194 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
195 | lo |= 0x200000; | |
196 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
197 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
198 | clear_cpu_cap(c, X86_FEATURE_PN); | |
199 | ||
200 | /* Disabling the serial number may affect the cpuid level */ | |
201 | c->cpuid_level = cpuid_eax(0); | |
202 | } | |
203 | } | |
204 | ||
205 | static int __init x86_serial_nr_setup(char *s) | |
206 | { | |
207 | disable_x86_serial_nr = 0; | |
208 | return 1; | |
209 | } | |
210 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 211 | #else |
102bbe3a YL |
212 | static inline int flag_is_changeable_p(u32 flag) |
213 | { | |
214 | return 1; | |
215 | } | |
ba51dced YL |
216 | /* Probe for the CPUID instruction */ |
217 | static inline int have_cpuid_p(void) | |
218 | { | |
219 | return 1; | |
220 | } | |
102bbe3a YL |
221 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
222 | { | |
223 | } | |
ba51dced | 224 | #endif |
0a488a53 | 225 | |
b38b0665 PA |
226 | /* |
227 | * Some CPU features depend on higher CPUID levels, which may not always | |
228 | * be available due to CPUID level capping or broken virtualization | |
229 | * software. Add those features to this table to auto-disable them. | |
230 | */ | |
231 | struct cpuid_dependent_feature { | |
232 | u32 feature; | |
233 | u32 level; | |
234 | }; | |
235 | static const struct cpuid_dependent_feature __cpuinitconst | |
236 | cpuid_dependent_features[] = { | |
237 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
238 | { X86_FEATURE_DCA, 0x00000009 }, | |
239 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
240 | { 0, 0 } | |
241 | }; | |
242 | ||
243 | static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) | |
244 | { | |
245 | const struct cpuid_dependent_feature *df; | |
9766cdbc | 246 | |
b38b0665 PA |
247 | for (df = cpuid_dependent_features; df->feature; df++) { |
248 | /* | |
249 | * Note: cpuid_level is set to -1 if unavailable, but | |
250 | * extended_extended_level is set to 0 if unavailable | |
251 | * and the legitimate extended levels are all negative | |
252 | * when signed; hence the weird messing around with | |
253 | * signs here... | |
254 | */ | |
255 | if (cpu_has(c, df->feature) && | |
f6db44df YL |
256 | ((s32)df->level < 0 ? |
257 | (u32)df->level > (u32)c->extended_cpuid_level : | |
258 | (s32)df->level > (s32)c->cpuid_level)) { | |
b38b0665 PA |
259 | clear_cpu_cap(c, df->feature); |
260 | if (warn) | |
261 | printk(KERN_WARNING | |
262 | "CPU: CPU feature %s disabled " | |
263 | "due to lack of CPUID level 0x%x\n", | |
264 | x86_cap_flags[df->feature], | |
265 | df->level); | |
266 | } | |
267 | } | |
f6db44df | 268 | } |
b38b0665 | 269 | |
102bbe3a YL |
270 | /* |
271 | * Naming convention should be: <Name> [(<Codename>)] | |
272 | * This table only is used unless init_<vendor>() below doesn't set it; | |
273 | * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used | |
274 | * | |
275 | */ | |
276 | ||
277 | /* Look up CPU names by table lookup. */ | |
278 | static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c) | |
279 | { | |
280 | struct cpu_model_info *info; | |
281 | ||
282 | if (c->x86_model >= 16) | |
283 | return NULL; /* Range check */ | |
284 | ||
285 | if (!this_cpu) | |
286 | return NULL; | |
287 | ||
288 | info = this_cpu->c_models; | |
289 | ||
290 | while (info && info->family) { | |
291 | if (info->family == c->x86) | |
292 | return info->model_names[c->x86_model]; | |
293 | info++; | |
294 | } | |
295 | return NULL; /* Not found */ | |
296 | } | |
297 | ||
7d851c8d AK |
298 | __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; |
299 | ||
11e3a840 JF |
300 | void load_percpu_segment(int cpu) |
301 | { | |
302 | #ifdef CONFIG_X86_32 | |
303 | loadsegment(fs, __KERNEL_PERCPU); | |
304 | #else | |
305 | loadsegment(gs, 0); | |
306 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); | |
307 | #endif | |
60a5317f | 308 | load_stack_canary_segment(); |
11e3a840 JF |
309 | } |
310 | ||
9d31d35b YL |
311 | /* Current gdt points %fs at the "master" per-cpu area: after this, |
312 | * it's on the real one. */ | |
552be871 | 313 | void switch_to_new_gdt(int cpu) |
9d31d35b YL |
314 | { |
315 | struct desc_ptr gdt_descr; | |
316 | ||
2697fbd5 | 317 | gdt_descr.address = (long)get_cpu_gdt_table(cpu); |
9d31d35b YL |
318 | gdt_descr.size = GDT_SIZE - 1; |
319 | load_gdt(&gdt_descr); | |
2697fbd5 | 320 | /* Reload the per-cpu base */ |
11e3a840 JF |
321 | |
322 | load_percpu_segment(cpu); | |
9d31d35b YL |
323 | } |
324 | ||
10a434fc | 325 | static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 326 | |
34048c9e | 327 | static void __cpuinit default_init(struct cpuinfo_x86 *c) |
1da177e4 | 328 | { |
b9e67f00 YL |
329 | #ifdef CONFIG_X86_64 |
330 | display_cacheinfo(c); | |
331 | #else | |
1da177e4 LT |
332 | /* Not much we can do here... */ |
333 | /* Check if at least it has cpuid */ | |
334 | if (c->cpuid_level == -1) { | |
335 | /* No cpuid. It must be an ancient CPU */ | |
336 | if (c->x86 == 4) | |
337 | strcpy(c->x86_model_id, "486"); | |
338 | else if (c->x86 == 3) | |
339 | strcpy(c->x86_model_id, "386"); | |
340 | } | |
b9e67f00 | 341 | #endif |
1da177e4 LT |
342 | } |
343 | ||
95414930 | 344 | static struct cpu_dev __cpuinitdata default_cpu = { |
1da177e4 | 345 | .c_init = default_init, |
fe38d855 | 346 | .c_vendor = "Unknown", |
10a434fc | 347 | .c_x86_vendor = X86_VENDOR_UNKNOWN, |
1da177e4 | 348 | }; |
1da177e4 | 349 | |
1b05d60d | 350 | static void __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
351 | { |
352 | unsigned int *v; | |
353 | char *p, *q; | |
354 | ||
3da99c97 | 355 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 356 | return; |
1da177e4 LT |
357 | |
358 | v = (unsigned int *) c->x86_model_id; | |
359 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
360 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
361 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
362 | c->x86_model_id[48] = 0; | |
363 | ||
364 | /* Intel chips right-justify this string for some dumb reason; | |
365 | undo that brain damage */ | |
366 | p = q = &c->x86_model_id[0]; | |
34048c9e | 367 | while (*p == ' ') |
9766cdbc | 368 | p++; |
34048c9e | 369 | if (p != q) { |
9766cdbc JSR |
370 | while (*p) |
371 | *q++ = *p++; | |
372 | while (q <= &c->x86_model_id[48]) | |
373 | *q++ = '\0'; /* Zero-pad the rest */ | |
1da177e4 | 374 | } |
1da177e4 LT |
375 | } |
376 | ||
3bc9b76b | 377 | void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) |
1da177e4 | 378 | { |
9d31d35b | 379 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 380 | |
3da99c97 | 381 | n = c->extended_cpuid_level; |
1da177e4 LT |
382 | |
383 | if (n >= 0x80000005) { | |
9d31d35b | 384 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 385 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", |
9d31d35b YL |
386 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); |
387 | c->x86_cache_size = (ecx>>24) + (edx>>24); | |
140fc727 YL |
388 | #ifdef CONFIG_X86_64 |
389 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
390 | c->x86_tlbsize = 0; | |
391 | #endif | |
1da177e4 LT |
392 | } |
393 | ||
394 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
395 | return; | |
396 | ||
0a488a53 | 397 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 398 | l2size = ecx >> 16; |
34048c9e | 399 | |
140fc727 YL |
400 | #ifdef CONFIG_X86_64 |
401 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
402 | #else | |
1da177e4 LT |
403 | /* do processor-specific cache resizing */ |
404 | if (this_cpu->c_size_cache) | |
34048c9e | 405 | l2size = this_cpu->c_size_cache(c, l2size); |
1da177e4 LT |
406 | |
407 | /* Allow user to override all this if necessary. */ | |
408 | if (cachesize_override != -1) | |
409 | l2size = cachesize_override; | |
410 | ||
34048c9e | 411 | if (l2size == 0) |
1da177e4 | 412 | return; /* Again, no L2 cache is possible */ |
140fc727 | 413 | #endif |
1da177e4 LT |
414 | |
415 | c->x86_cache_size = l2size; | |
416 | ||
417 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
0a488a53 | 418 | l2size, ecx & 0xFF); |
1da177e4 LT |
419 | } |
420 | ||
9d31d35b | 421 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 422 | { |
97e4db7c | 423 | #ifdef CONFIG_X86_HT |
0a488a53 YL |
424 | u32 eax, ebx, ecx, edx; |
425 | int index_msb, core_bits; | |
1da177e4 | 426 | |
0a488a53 | 427 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 428 | return; |
1da177e4 | 429 | |
0a488a53 YL |
430 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
431 | goto out; | |
1da177e4 | 432 | |
1cd78776 YL |
433 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
434 | return; | |
1da177e4 | 435 | |
0a488a53 | 436 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 437 | |
9d31d35b YL |
438 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
439 | ||
440 | if (smp_num_siblings == 1) { | |
441 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
442 | } else if (smp_num_siblings > 1) { | |
443 | ||
9628937d | 444 | if (smp_num_siblings > nr_cpu_ids) { |
9766cdbc JSR |
445 | pr_warning("CPU: Unsupported number of siblings %d", |
446 | smp_num_siblings); | |
9d31d35b YL |
447 | smp_num_siblings = 1; |
448 | return; | |
449 | } | |
450 | ||
451 | index_msb = get_count_order(smp_num_siblings); | |
9766cdbc JSR |
452 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, |
453 | index_msb); | |
9d31d35b YL |
454 | |
455 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; | |
456 | ||
457 | index_msb = get_count_order(smp_num_siblings); | |
458 | ||
459 | core_bits = get_count_order(c->x86_max_cores); | |
460 | ||
cb8cc442 | 461 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & |
1cd78776 | 462 | ((1 << core_bits) - 1); |
1da177e4 | 463 | } |
1da177e4 | 464 | |
0a488a53 YL |
465 | out: |
466 | if ((c->x86_max_cores * smp_num_siblings) > 1) { | |
467 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
468 | c->phys_proc_id); | |
469 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
470 | c->cpu_core_id); | |
9d31d35b | 471 | } |
9d31d35b | 472 | #endif |
97e4db7c | 473 | } |
1da177e4 | 474 | |
3da99c97 | 475 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
476 | { |
477 | char *v = c->x86_vendor_id; | |
478 | int i; | |
fe38d855 | 479 | static int printed; |
1da177e4 LT |
480 | |
481 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
482 | if (!cpu_devs[i]) |
483 | break; | |
484 | ||
485 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
486 | (cpu_devs[i]->c_ident[1] && | |
487 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
488 | this_cpu = cpu_devs[i]; | |
489 | c->x86_vendor = this_cpu->c_x86_vendor; | |
490 | return; | |
1da177e4 LT |
491 | } |
492 | } | |
10a434fc | 493 | |
fe38d855 CE |
494 | if (!printed) { |
495 | printed++; | |
9766cdbc JSR |
496 | printk(KERN_ERR "CPU: vendor_id '%s'" |
497 | "unknown, using generic init.\n", v); | |
fe38d855 CE |
498 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); |
499 | } | |
10a434fc | 500 | |
fe38d855 CE |
501 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
502 | this_cpu = &default_cpu; | |
1da177e4 LT |
503 | } |
504 | ||
9d31d35b | 505 | void __cpuinit cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 506 | { |
1da177e4 | 507 | /* Get vendor name */ |
4a148513 HH |
508 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
509 | (unsigned int *)&c->x86_vendor_id[0], | |
510 | (unsigned int *)&c->x86_vendor_id[8], | |
511 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 512 | |
1da177e4 | 513 | c->x86 = 4; |
9d31d35b | 514 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
515 | if (c->cpuid_level >= 0x00000001) { |
516 | u32 junk, tfms, cap0, misc; | |
517 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
9d31d35b YL |
518 | c->x86 = (tfms >> 8) & 0xf; |
519 | c->x86_model = (tfms >> 4) & 0xf; | |
520 | c->x86_mask = tfms & 0xf; | |
f5f786d0 | 521 | if (c->x86 == 0xf) |
1da177e4 | 522 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 523 | if (c->x86 >= 0x6) |
9d31d35b | 524 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
d4387bd3 | 525 | if (cap0 & (1<<19)) { |
d4387bd3 | 526 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 527 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 528 | } |
1da177e4 | 529 | } |
1da177e4 | 530 | } |
3da99c97 YL |
531 | |
532 | static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) | |
093af8d7 YL |
533 | { |
534 | u32 tfms, xlvl; | |
3da99c97 | 535 | u32 ebx; |
093af8d7 | 536 | |
3da99c97 YL |
537 | /* Intel-defined flags: level 0x00000001 */ |
538 | if (c->cpuid_level >= 0x00000001) { | |
539 | u32 capability, excap; | |
540 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); | |
541 | c->x86_capability[0] = capability; | |
542 | c->x86_capability[4] = excap; | |
543 | } | |
093af8d7 | 544 | |
3da99c97 YL |
545 | /* AMD-defined flags: level 0x80000001 */ |
546 | xlvl = cpuid_eax(0x80000000); | |
547 | c->extended_cpuid_level = xlvl; | |
548 | if ((xlvl & 0xffff0000) == 0x80000000) { | |
549 | if (xlvl >= 0x80000001) { | |
550 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
551 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 552 | } |
093af8d7 | 553 | } |
093af8d7 | 554 | |
5122c890 | 555 | #ifdef CONFIG_X86_64 |
5122c890 YL |
556 | if (c->extended_cpuid_level >= 0x80000008) { |
557 | u32 eax = cpuid_eax(0x80000008); | |
558 | ||
559 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
560 | c->x86_phys_bits = eax & 0xff; | |
093af8d7 | 561 | } |
5122c890 | 562 | #endif |
e3224234 YL |
563 | |
564 | if (c->extended_cpuid_level >= 0x80000007) | |
565 | c->x86_power = cpuid_edx(0x80000007); | |
093af8d7 YL |
566 | |
567 | } | |
1da177e4 | 568 | |
aef93c8b YL |
569 | static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
570 | { | |
571 | #ifdef CONFIG_X86_32 | |
572 | int i; | |
573 | ||
574 | /* | |
575 | * First of all, decide if this is a 486 or higher | |
576 | * It's a 486 if we can modify the AC flag | |
577 | */ | |
578 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
579 | c->x86 = 4; | |
580 | else | |
581 | c->x86 = 3; | |
582 | ||
583 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
584 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
585 | c->x86_vendor_id[0] = 0; | |
586 | cpu_devs[i]->c_identify(c); | |
587 | if (c->x86_vendor_id[0]) { | |
588 | get_cpu_vendor(c); | |
589 | break; | |
590 | } | |
591 | } | |
592 | #endif | |
593 | } | |
594 | ||
34048c9e PC |
595 | /* |
596 | * Do minimum CPU detection early. | |
597 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
598 | * cache alignment. | |
599 | * The others are not touched to avoid unwanted side effects. | |
600 | * | |
601 | * WARNING: this function is only called on the BP. Don't add code here | |
602 | * that is supposed to run on all CPUs. | |
603 | */ | |
3da99c97 | 604 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 605 | { |
6627d242 YL |
606 | #ifdef CONFIG_X86_64 |
607 | c->x86_clflush_size = 64; | |
608 | #else | |
d4387bd3 | 609 | c->x86_clflush_size = 32; |
6627d242 | 610 | #endif |
0a488a53 | 611 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 612 | |
3da99c97 | 613 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 614 | c->extended_cpuid_level = 0; |
d7cd5611 | 615 | |
aef93c8b YL |
616 | if (!have_cpuid_p()) |
617 | identify_cpu_without_cpuid(c); | |
618 | ||
619 | /* cyrix could have cpuid enabled via c_identify()*/ | |
d7cd5611 RR |
620 | if (!have_cpuid_p()) |
621 | return; | |
622 | ||
623 | cpu_detect(c); | |
624 | ||
3da99c97 | 625 | get_cpu_vendor(c); |
2b16a235 | 626 | |
3da99c97 | 627 | get_cpu_cap(c); |
12cf105c | 628 | |
10a434fc YL |
629 | if (this_cpu->c_early_init) |
630 | this_cpu->c_early_init(c); | |
093af8d7 | 631 | |
1c4acdb4 | 632 | #ifdef CONFIG_SMP |
bfcb4c1b | 633 | c->cpu_index = boot_cpu_id; |
1c4acdb4 | 634 | #endif |
b38b0665 | 635 | filter_cpuid_features(c, false); |
d7cd5611 RR |
636 | } |
637 | ||
9d31d35b YL |
638 | void __init early_cpu_init(void) |
639 | { | |
10a434fc YL |
640 | struct cpu_dev **cdev; |
641 | int count = 0; | |
642 | ||
9766cdbc | 643 | printk(KERN_INFO "KERNEL supported cpus:\n"); |
10a434fc YL |
644 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { |
645 | struct cpu_dev *cpudev = *cdev; | |
646 | unsigned int j; | |
9d31d35b | 647 | |
10a434fc YL |
648 | if (count >= X86_VENDOR_NUM) |
649 | break; | |
650 | cpu_devs[count] = cpudev; | |
651 | count++; | |
652 | ||
653 | for (j = 0; j < 2; j++) { | |
654 | if (!cpudev->c_ident[j]) | |
655 | continue; | |
9766cdbc | 656 | printk(KERN_INFO " %s %s\n", cpudev->c_vendor, |
10a434fc YL |
657 | cpudev->c_ident[j]); |
658 | } | |
659 | } | |
9d31d35b | 660 | |
9d31d35b | 661 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 662 | } |
093af8d7 | 663 | |
b6734c35 PA |
664 | /* |
665 | * The NOPL instruction is supposed to exist on all CPUs with | |
ba0593bf | 666 | * family >= 6; unfortunately, that's not true in practice because |
b6734c35 | 667 | * of early VIA chips and (more importantly) broken virtualizers that |
ba0593bf PA |
668 | * are not easy to detect. In the latter case it doesn't even *fail* |
669 | * reliably, so probing for it doesn't even work. Disable it completely | |
670 | * unless we can find a reliable way to detect all the broken cases. | |
b6734c35 PA |
671 | */ |
672 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
673 | { | |
b6734c35 | 674 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
d7cd5611 RR |
675 | } |
676 | ||
34048c9e | 677 | static void __cpuinit generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 678 | { |
aef93c8b | 679 | c->extended_cpuid_level = 0; |
1da177e4 | 680 | |
3da99c97 | 681 | if (!have_cpuid_p()) |
aef93c8b | 682 | identify_cpu_without_cpuid(c); |
1d67953f | 683 | |
aef93c8b | 684 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 685 | if (!have_cpuid_p()) |
aef93c8b | 686 | return; |
1da177e4 | 687 | |
3da99c97 | 688 | cpu_detect(c); |
1da177e4 | 689 | |
3da99c97 | 690 | get_cpu_vendor(c); |
1da177e4 | 691 | |
3da99c97 | 692 | get_cpu_cap(c); |
1da177e4 | 693 | |
3da99c97 YL |
694 | if (c->cpuid_level >= 0x00000001) { |
695 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e YL |
696 | #ifdef CONFIG_X86_32 |
697 | # ifdef CONFIG_X86_HT | |
cb8cc442 | 698 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 699 | # else |
3da99c97 | 700 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
701 | # endif |
702 | #endif | |
1da177e4 | 703 | |
b89d3b3e YL |
704 | #ifdef CONFIG_X86_HT |
705 | c->phys_proc_id = c->initial_apicid; | |
1e9f28fa | 706 | #endif |
3da99c97 | 707 | } |
1da177e4 | 708 | |
1b05d60d | 709 | get_model_name(c); /* Default name */ |
1da177e4 | 710 | |
3da99c97 YL |
711 | init_scattered_cpuid_features(c); |
712 | detect_nopl(c); | |
1da177e4 | 713 | } |
1da177e4 LT |
714 | |
715 | /* | |
716 | * This does the hard work of actually picking apart the CPU stuff... | |
717 | */ | |
9a250347 | 718 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
719 | { |
720 | int i; | |
721 | ||
722 | c->loops_per_jiffy = loops_per_jiffy; | |
723 | c->x86_cache_size = -1; | |
724 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
725 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
726 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
727 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 728 | c->x86_max_cores = 1; |
102bbe3a | 729 | c->x86_coreid_bits = 0; |
11fdd252 | 730 | #ifdef CONFIG_X86_64 |
102bbe3a YL |
731 | c->x86_clflush_size = 64; |
732 | #else | |
733 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 734 | c->x86_clflush_size = 32; |
102bbe3a YL |
735 | #endif |
736 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
737 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
738 | ||
1da177e4 LT |
739 | generic_identify(c); |
740 | ||
3898534d | 741 | if (this_cpu->c_identify) |
1da177e4 LT |
742 | this_cpu->c_identify(c); |
743 | ||
102bbe3a | 744 | #ifdef CONFIG_X86_64 |
cb8cc442 | 745 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
746 | #endif |
747 | ||
1da177e4 LT |
748 | /* |
749 | * Vendor-specific initialization. In this section we | |
750 | * canonicalize the feature flags, meaning if there are | |
751 | * features a certain CPU supports which CPUID doesn't | |
752 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
753 | * we handle them here. | |
754 | * | |
755 | * At the end of this section, c->x86_capability better | |
756 | * indicate the features this CPU genuinely supports! | |
757 | */ | |
758 | if (this_cpu->c_init) | |
759 | this_cpu->c_init(c); | |
760 | ||
761 | /* Disable the PN if appropriate */ | |
762 | squash_the_stupid_serial_number(c); | |
763 | ||
764 | /* | |
765 | * The vendor-specific functions might have changed features. Now | |
766 | * we do "generic changes." | |
767 | */ | |
768 | ||
b38b0665 PA |
769 | /* Filter out anything that depends on CPUID levels we don't have */ |
770 | filter_cpuid_features(c, true); | |
771 | ||
1da177e4 | 772 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 773 | if (!c->x86_model_id[0]) { |
1da177e4 LT |
774 | char *p; |
775 | p = table_lookup_model(c); | |
34048c9e | 776 | if (p) |
1da177e4 LT |
777 | strcpy(c->x86_model_id, p); |
778 | else | |
779 | /* Last resort... */ | |
780 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 781 | c->x86, c->x86_model); |
1da177e4 LT |
782 | } |
783 | ||
102bbe3a YL |
784 | #ifdef CONFIG_X86_64 |
785 | detect_ht(c); | |
786 | #endif | |
787 | ||
88b094fb | 788 | init_hypervisor(c); |
1da177e4 LT |
789 | /* |
790 | * On SMP, boot_cpu_data holds the common feature set between | |
791 | * all CPUs; so make sure that we indicate which features are | |
792 | * common between the CPUs. The first time this routine gets | |
793 | * executed, c == &boot_cpu_data. | |
794 | */ | |
34048c9e | 795 | if (c != &boot_cpu_data) { |
1da177e4 | 796 | /* AND the already accumulated flags with these */ |
9d31d35b | 797 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 LT |
798 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
799 | } | |
800 | ||
7d851c8d AK |
801 | /* Clear all flags overriden by options */ |
802 | for (i = 0; i < NCAPINTS; i++) | |
12c247a6 | 803 | c->x86_capability[i] &= ~cleared_cpu_caps[i]; |
7d851c8d | 804 | |
102bbe3a | 805 | #ifdef CONFIG_X86_MCE |
1da177e4 | 806 | /* Init Machine Check Exception if available. */ |
1da177e4 | 807 | mcheck_init(c); |
102bbe3a | 808 | #endif |
30d432df AK |
809 | |
810 | select_idle_routine(c); | |
102bbe3a YL |
811 | |
812 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) | |
813 | numa_add_cpu(smp_processor_id()); | |
814 | #endif | |
a6c4e076 | 815 | } |
31ab269a | 816 | |
e04d645f GC |
817 | #ifdef CONFIG_X86_64 |
818 | static void vgetcpu_set_mode(void) | |
819 | { | |
820 | if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) | |
821 | vgetcpu_mode = VGETCPU_RDTSCP; | |
822 | else | |
823 | vgetcpu_mode = VGETCPU_LSL; | |
824 | } | |
825 | #endif | |
826 | ||
a6c4e076 JF |
827 | void __init identify_boot_cpu(void) |
828 | { | |
829 | identify_cpu(&boot_cpu_data); | |
102bbe3a | 830 | #ifdef CONFIG_X86_32 |
a6c4e076 | 831 | sysenter_setup(); |
6fe940d6 | 832 | enable_sep_cpu(); |
e04d645f GC |
833 | #else |
834 | vgetcpu_set_mode(); | |
102bbe3a | 835 | #endif |
a6c4e076 | 836 | } |
3b520b23 | 837 | |
a6c4e076 JF |
838 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) |
839 | { | |
840 | BUG_ON(c == &boot_cpu_data); | |
841 | identify_cpu(c); | |
102bbe3a | 842 | #ifdef CONFIG_X86_32 |
a6c4e076 | 843 | enable_sep_cpu(); |
102bbe3a | 844 | #endif |
a6c4e076 | 845 | mtrr_ap_init(); |
1da177e4 LT |
846 | } |
847 | ||
a0854a46 YL |
848 | struct msr_range { |
849 | unsigned min; | |
850 | unsigned max; | |
851 | }; | |
1da177e4 | 852 | |
a0854a46 YL |
853 | static struct msr_range msr_range_array[] __cpuinitdata = { |
854 | { 0x00000000, 0x00000418}, | |
855 | { 0xc0000000, 0xc000040b}, | |
856 | { 0xc0010000, 0xc0010142}, | |
857 | { 0xc0011000, 0xc001103b}, | |
858 | }; | |
1da177e4 | 859 | |
a0854a46 YL |
860 | static void __cpuinit print_cpu_msr(void) |
861 | { | |
862 | unsigned index; | |
863 | u64 val; | |
864 | int i; | |
865 | unsigned index_min, index_max; | |
866 | ||
867 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
868 | index_min = msr_range_array[i].min; | |
869 | index_max = msr_range_array[i].max; | |
870 | for (index = index_min; index < index_max; index++) { | |
871 | if (rdmsrl_amd_safe(index, &val)) | |
872 | continue; | |
873 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1da177e4 | 874 | } |
a0854a46 YL |
875 | } |
876 | } | |
94605eff | 877 | |
a0854a46 YL |
878 | static int show_msr __cpuinitdata; |
879 | static __init int setup_show_msr(char *arg) | |
880 | { | |
881 | int num; | |
3dd9d514 | 882 | |
a0854a46 | 883 | get_option(&arg, &num); |
3dd9d514 | 884 | |
a0854a46 YL |
885 | if (num > 0) |
886 | show_msr = num; | |
887 | return 1; | |
1da177e4 | 888 | } |
a0854a46 | 889 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 890 | |
191679fd AK |
891 | static __init int setup_noclflush(char *arg) |
892 | { | |
893 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
894 | return 1; | |
895 | } | |
896 | __setup("noclflush", setup_noclflush); | |
897 | ||
3bc9b76b | 898 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 LT |
899 | { |
900 | char *vendor = NULL; | |
901 | ||
902 | if (c->x86_vendor < X86_VENDOR_NUM) | |
903 | vendor = this_cpu->c_vendor; | |
904 | else if (c->cpuid_level >= 0) | |
905 | vendor = c->x86_vendor_id; | |
906 | ||
bd32a8cf | 907 | if (vendor && !strstr(c->x86_model_id, vendor)) |
9d31d35b | 908 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 909 | |
9d31d35b YL |
910 | if (c->x86_model_id[0]) |
911 | printk(KERN_CONT "%s", c->x86_model_id); | |
1da177e4 | 912 | else |
9d31d35b | 913 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 914 | |
34048c9e | 915 | if (c->x86_mask || c->cpuid_level >= 0) |
9d31d35b | 916 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); |
1da177e4 | 917 | else |
9d31d35b | 918 | printk(KERN_CONT "\n"); |
a0854a46 YL |
919 | |
920 | #ifdef CONFIG_SMP | |
921 | if (c->cpu_index < show_msr) | |
922 | print_cpu_msr(); | |
923 | #else | |
924 | if (show_msr) | |
925 | print_cpu_msr(); | |
926 | #endif | |
1da177e4 LT |
927 | } |
928 | ||
ac72e788 AK |
929 | static __init int setup_disablecpuid(char *arg) |
930 | { | |
931 | int bit; | |
932 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) | |
933 | setup_clear_cpu_cap(bit); | |
934 | else | |
935 | return 0; | |
936 | return 1; | |
937 | } | |
938 | __setup("clearcpuid=", setup_disablecpuid); | |
939 | ||
d5494d4f | 940 | #ifdef CONFIG_X86_64 |
d5494d4f YL |
941 | struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; |
942 | ||
947e76cd BG |
943 | DEFINE_PER_CPU_FIRST(union irq_stack_union, |
944 | irq_stack_union) __aligned(PAGE_SIZE); | |
26f80bd6 | 945 | DEFINE_PER_CPU(char *, irq_stack_ptr) = |
2add8e23 | 946 | init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; |
d5494d4f | 947 | |
9af45651 BG |
948 | DEFINE_PER_CPU(unsigned long, kernel_stack) = |
949 | (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; | |
950 | EXPORT_PER_CPU_SYMBOL(kernel_stack); | |
d5494d4f | 951 | |
56895530 | 952 | DEFINE_PER_CPU(unsigned int, irq_count) = -1; |
d5494d4f | 953 | |
92d65b23 BG |
954 | static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks |
955 | [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]) | |
956 | __aligned(PAGE_SIZE); | |
d5494d4f | 957 | |
d5494d4f YL |
958 | /* May not be marked __init: used by software suspend */ |
959 | void syscall_init(void) | |
1da177e4 | 960 | { |
d5494d4f YL |
961 | /* |
962 | * LSTAR and STAR live in a bit strange symbiosis. | |
963 | * They both write to the same internal register. STAR allows to | |
964 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
965 | */ | |
966 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
967 | wrmsrl(MSR_LSTAR, system_call); | |
968 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
03ae5768 | 969 | |
d5494d4f YL |
970 | #ifdef CONFIG_IA32_EMULATION |
971 | syscall32_cpu_init(); | |
972 | #endif | |
03ae5768 | 973 | |
d5494d4f YL |
974 | /* Flags to clear on syscall */ |
975 | wrmsrl(MSR_SYSCALL_MASK, | |
976 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); | |
1da177e4 | 977 | } |
62111195 | 978 | |
d5494d4f YL |
979 | unsigned long kernel_eflags; |
980 | ||
981 | /* | |
982 | * Copies of the original ist values from the tss are only accessed during | |
983 | * debugging, no special alignment required. | |
984 | */ | |
985 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
986 | ||
60a5317f | 987 | #else /* x86_64 */ |
d5494d4f | 988 | |
60a5317f TH |
989 | #ifdef CONFIG_CC_STACKPROTECTOR |
990 | DEFINE_PER_CPU(unsigned long, stack_canary); | |
991 | #endif | |
d5494d4f | 992 | |
60a5317f | 993 | /* Make sure %fs and %gs are initialized properly in idle threads */ |
6b2fb3c6 | 994 | struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) |
f95d47ca JF |
995 | { |
996 | memset(regs, 0, sizeof(struct pt_regs)); | |
65ea5b03 | 997 | regs->fs = __KERNEL_PERCPU; |
60a5317f | 998 | regs->gs = __KERNEL_STACK_CANARY; |
f95d47ca JF |
999 | return regs; |
1000 | } | |
60a5317f | 1001 | #endif /* x86_64 */ |
c5413fbe | 1002 | |
9766cdbc JSR |
1003 | /* |
1004 | * Clear all 6 debug registers: | |
1005 | */ | |
1006 | static void clear_all_debug_regs(void) | |
1007 | { | |
1008 | int i; | |
1009 | ||
1010 | for (i = 0; i < 8; i++) { | |
1011 | /* Ignore db4, db5 */ | |
1012 | if ((i == 4) || (i == 5)) | |
1013 | continue; | |
1014 | ||
1015 | set_debugreg(0, i); | |
1016 | } | |
1017 | } | |
1018 | ||
d2cbcc49 RR |
1019 | /* |
1020 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1021 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1022 | * and IDT. We reload them nevertheless, this function acts as a | |
1023 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 1024 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 1025 | */ |
1ba76586 YL |
1026 | #ifdef CONFIG_X86_64 |
1027 | void __cpuinit cpu_init(void) | |
1028 | { | |
1029 | int cpu = stack_smp_processor_id(); | |
1030 | struct tss_struct *t = &per_cpu(init_tss, cpu); | |
1031 | struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu); | |
1032 | unsigned long v; | |
1ba76586 YL |
1033 | struct task_struct *me; |
1034 | int i; | |
1035 | ||
e7a22c1e BG |
1036 | #ifdef CONFIG_NUMA |
1037 | if (cpu != 0 && percpu_read(node_number) == 0 && | |
1038 | cpu_to_node(cpu) != NUMA_NO_NODE) | |
1039 | percpu_write(node_number, cpu_to_node(cpu)); | |
1040 | #endif | |
1ba76586 YL |
1041 | |
1042 | me = current; | |
1043 | ||
c2d1cec1 | 1044 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) |
1ba76586 YL |
1045 | panic("CPU#%d already initialized!\n", cpu); |
1046 | ||
1047 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1048 | ||
1049 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
1050 | ||
1051 | /* | |
1052 | * Initialize the per-CPU GDT with the boot GDT, | |
1053 | * and set up the GDT descriptor: | |
1054 | */ | |
1055 | ||
552be871 | 1056 | switch_to_new_gdt(cpu); |
2697fbd5 BG |
1057 | loadsegment(fs, 0); |
1058 | ||
1ba76586 YL |
1059 | load_idt((const struct desc_ptr *)&idt_descr); |
1060 | ||
1061 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1062 | syscall_init(); | |
1063 | ||
1064 | wrmsrl(MSR_FS_BASE, 0); | |
1065 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1066 | barrier(); | |
1067 | ||
1068 | check_efer(); | |
06cd9a7d | 1069 | if (cpu != 0) |
1ba76586 YL |
1070 | enable_x2apic(); |
1071 | ||
1072 | /* | |
1073 | * set up and load the per-CPU TSS | |
1074 | */ | |
1075 | if (!orig_ist->ist[0]) { | |
92d65b23 BG |
1076 | static const unsigned int sizes[N_EXCEPTION_STACKS] = { |
1077 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
1078 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
1ba76586 | 1079 | }; |
92d65b23 | 1080 | char *estacks = per_cpu(exception_stacks, cpu); |
1ba76586 | 1081 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
92d65b23 | 1082 | estacks += sizes[v]; |
1ba76586 YL |
1083 | orig_ist->ist[v] = t->x86_tss.ist[v] = |
1084 | (unsigned long)estacks; | |
1085 | } | |
1086 | } | |
1087 | ||
1088 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
1089 | /* | |
1090 | * <= is required because the CPU will access up to | |
1091 | * 8 bits beyond the end of the IO permission bitmap. | |
1092 | */ | |
1093 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1094 | t->io_bitmap[i] = ~0UL; | |
1095 | ||
1096 | atomic_inc(&init_mm.mm_count); | |
1097 | me->active_mm = &init_mm; | |
1098 | if (me->mm) | |
1099 | BUG(); | |
1100 | enter_lazy_tlb(&init_mm, me); | |
1101 | ||
1102 | load_sp0(t, ¤t->thread); | |
1103 | set_tss_desc(cpu, t); | |
1104 | load_TR_desc(); | |
1105 | load_LDT(&init_mm.context); | |
1106 | ||
1107 | #ifdef CONFIG_KGDB | |
1108 | /* | |
1109 | * If the kgdb is connected no debug regs should be altered. This | |
1110 | * is only applicable when KGDB and a KGDB I/O module are built | |
1111 | * into the kernel and you are using early debugging with | |
1112 | * kgdbwait. KGDB will control the kernel HW breakpoint registers. | |
1113 | */ | |
1114 | if (kgdb_connected && arch_kgdb_ops.correct_hw_break) | |
1115 | arch_kgdb_ops.correct_hw_break(); | |
8f6d86dc | 1116 | else |
1ba76586 | 1117 | #endif |
9766cdbc | 1118 | clear_all_debug_regs(); |
1ba76586 YL |
1119 | |
1120 | fpu_init(); | |
1121 | ||
1122 | raw_local_save_flags(kernel_eflags); | |
1123 | ||
1124 | if (is_uv_system()) | |
1125 | uv_cpu_init(); | |
1126 | } | |
1127 | ||
1128 | #else | |
1129 | ||
d2cbcc49 | 1130 | void __cpuinit cpu_init(void) |
9ee79a3d | 1131 | { |
d2cbcc49 RR |
1132 | int cpu = smp_processor_id(); |
1133 | struct task_struct *curr = current; | |
34048c9e | 1134 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 1135 | struct thread_struct *thread = &curr->thread; |
62111195 | 1136 | |
c2d1cec1 | 1137 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { |
62111195 | 1138 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); |
9766cdbc JSR |
1139 | for (;;) |
1140 | local_irq_enable(); | |
62111195 JF |
1141 | } |
1142 | ||
1143 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1144 | ||
1145 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
1146 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 1147 | |
4d37e7e3 | 1148 | load_idt(&idt_descr); |
552be871 | 1149 | switch_to_new_gdt(cpu); |
1da177e4 | 1150 | |
1da177e4 LT |
1151 | /* |
1152 | * Set up and load the per-CPU TSS and LDT | |
1153 | */ | |
1154 | atomic_inc(&init_mm.mm_count); | |
62111195 JF |
1155 | curr->active_mm = &init_mm; |
1156 | if (curr->mm) | |
1157 | BUG(); | |
1158 | enter_lazy_tlb(&init_mm, curr); | |
1da177e4 | 1159 | |
faca6227 | 1160 | load_sp0(t, thread); |
34048c9e | 1161 | set_tss_desc(cpu, t); |
1da177e4 LT |
1162 | load_TR_desc(); |
1163 | load_LDT(&init_mm.context); | |
1164 | ||
22c4e308 | 1165 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1166 | /* Set up doublefault TSS pointer in the GDT */ |
1167 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1168 | #endif |
1da177e4 | 1169 | |
9766cdbc | 1170 | clear_all_debug_regs(); |
1da177e4 LT |
1171 | |
1172 | /* | |
1173 | * Force FPU initialization: | |
1174 | */ | |
b359e8a4 SS |
1175 | if (cpu_has_xsave) |
1176 | current_thread_info()->status = TS_XSAVE; | |
1177 | else | |
1178 | current_thread_info()->status = 0; | |
1da177e4 LT |
1179 | clear_used_math(); |
1180 | mxcsr_feature_mask_init(); | |
dc1e35c6 SS |
1181 | |
1182 | /* | |
1183 | * Boot processor to setup the FP and extended state context info. | |
1184 | */ | |
b3572e36 | 1185 | if (smp_processor_id() == boot_cpu_id) |
dc1e35c6 SS |
1186 | init_thread_xstate(); |
1187 | ||
1188 | xsave_init(); | |
1da177e4 | 1189 | } |
e1367daf | 1190 | |
1ba76586 | 1191 | #endif |