]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | #include <linux/init.h> |
2 | #include <linux/string.h> | |
3 | #include <linux/delay.h> | |
4 | #include <linux/smp.h> | |
5 | #include <linux/module.h> | |
6 | #include <linux/percpu.h> | |
2b932f6c | 7 | #include <linux/bootmem.h> |
1da177e4 LT |
8 | #include <asm/processor.h> |
9 | #include <asm/i387.h> | |
10 | #include <asm/msr.h> | |
11 | #include <asm/io.h> | |
12 | #include <asm/mmu_context.h> | |
27b07da7 | 13 | #include <asm/mtrr.h> |
a03a3e28 | 14 | #include <asm/mce.h> |
8d4a4300 | 15 | #include <asm/pat.h> |
7e00df58 | 16 | #include <asm/asm.h> |
1da177e4 LT |
17 | #ifdef CONFIG_X86_LOCAL_APIC |
18 | #include <asm/mpspec.h> | |
19 | #include <asm/apic.h> | |
20 | #include <mach_apic.h> | |
21 | #endif | |
22 | ||
23 | #include "cpu.h" | |
24 | ||
7a61d35d | 25 | DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = { |
6842ef0e GOC |
26 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, |
27 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, | |
28 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, | |
29 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, | |
bf504672 RR |
30 | /* |
31 | * Segments used for calling PnP BIOS have byte granularity. | |
32 | * They code segments and data segments have fixed 64k limits, | |
33 | * the transfer segment sizes are set at run time. | |
34 | */ | |
6842ef0e GOC |
35 | /* 32-bit code */ |
36 | [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, | |
37 | /* 16-bit code */ | |
38 | [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, | |
39 | /* 16-bit data */ | |
40 | [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, | |
41 | /* 16-bit data */ | |
42 | [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, | |
43 | /* 16-bit data */ | |
44 | [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, | |
bf504672 RR |
45 | /* |
46 | * The APM segments have byte granularity and their bases | |
47 | * are set at run time. All have 64k limits. | |
48 | */ | |
6842ef0e GOC |
49 | /* 32-bit code */ |
50 | [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, | |
bf504672 | 51 | /* 16-bit code */ |
6842ef0e GOC |
52 | [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, |
53 | /* data */ | |
54 | [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, | |
bf504672 | 55 | |
6842ef0e GOC |
56 | [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, |
57 | [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } }, | |
7a61d35d JF |
58 | } }; |
59 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); | |
ae1ee11b | 60 | |
7d851c8d AK |
61 | __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; |
62 | ||
9d31d35b YL |
63 | /* Current gdt points %fs at the "master" per-cpu area: after this, |
64 | * it's on the real one. */ | |
65 | void switch_to_new_gdt(void) | |
66 | { | |
67 | struct desc_ptr gdt_descr; | |
68 | ||
69 | gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id()); | |
70 | gdt_descr.size = GDT_SIZE - 1; | |
71 | load_gdt(&gdt_descr); | |
72 | asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory"); | |
73 | } | |
74 | ||
3bc9b76b | 75 | static int cachesize_override __cpuinitdata = -1; |
3bc9b76b | 76 | static int disable_x86_serial_nr __cpuinitdata = 1; |
1da177e4 | 77 | |
34048c9e | 78 | struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 79 | |
34048c9e | 80 | static void __cpuinit default_init(struct cpuinfo_x86 *c) |
1da177e4 LT |
81 | { |
82 | /* Not much we can do here... */ | |
83 | /* Check if at least it has cpuid */ | |
84 | if (c->cpuid_level == -1) { | |
85 | /* No cpuid. It must be an ancient CPU */ | |
86 | if (c->x86 == 4) | |
87 | strcpy(c->x86_model_id, "486"); | |
88 | else if (c->x86 == 3) | |
89 | strcpy(c->x86_model_id, "386"); | |
90 | } | |
91 | } | |
92 | ||
95414930 | 93 | static struct cpu_dev __cpuinitdata default_cpu = { |
1da177e4 | 94 | .c_init = default_init, |
fe38d855 | 95 | .c_vendor = "Unknown", |
1da177e4 | 96 | }; |
34048c9e | 97 | static struct cpu_dev *this_cpu __cpuinitdata = &default_cpu; |
1da177e4 LT |
98 | |
99 | static int __init cachesize_setup(char *str) | |
100 | { | |
34048c9e | 101 | get_option(&str, &cachesize_override); |
1da177e4 LT |
102 | return 1; |
103 | } | |
104 | __setup("cachesize=", cachesize_setup); | |
105 | ||
3bc9b76b | 106 | int __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
107 | { |
108 | unsigned int *v; | |
109 | char *p, *q; | |
110 | ||
3da99c97 | 111 | if (c->extended_cpuid_level < 0x80000004) |
1da177e4 LT |
112 | return 0; |
113 | ||
114 | v = (unsigned int *) c->x86_model_id; | |
115 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
116 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
117 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
118 | c->x86_model_id[48] = 0; | |
119 | ||
120 | /* Intel chips right-justify this string for some dumb reason; | |
121 | undo that brain damage */ | |
122 | p = q = &c->x86_model_id[0]; | |
34048c9e | 123 | while (*p == ' ') |
1da177e4 | 124 | p++; |
34048c9e PC |
125 | if (p != q) { |
126 | while (*p) | |
1da177e4 | 127 | *q++ = *p++; |
34048c9e | 128 | while (q <= &c->x86_model_id[48]) |
1da177e4 LT |
129 | *q++ = '\0'; /* Zero-pad the rest */ |
130 | } | |
131 | ||
132 | return 1; | |
133 | } | |
134 | ||
135 | ||
3bc9b76b | 136 | void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) |
1da177e4 | 137 | { |
9d31d35b | 138 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 139 | |
3da99c97 | 140 | n = c->extended_cpuid_level; |
1da177e4 LT |
141 | |
142 | if (n >= 0x80000005) { | |
9d31d35b | 143 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 144 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", |
9d31d35b YL |
145 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); |
146 | c->x86_cache_size = (ecx>>24) + (edx>>24); | |
1da177e4 LT |
147 | } |
148 | ||
149 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
150 | return; | |
151 | ||
152 | ecx = cpuid_ecx(0x80000006); | |
153 | l2size = ecx >> 16; | |
34048c9e | 154 | |
1da177e4 LT |
155 | /* do processor-specific cache resizing */ |
156 | if (this_cpu->c_size_cache) | |
34048c9e | 157 | l2size = this_cpu->c_size_cache(c, l2size); |
1da177e4 LT |
158 | |
159 | /* Allow user to override all this if necessary. */ | |
160 | if (cachesize_override != -1) | |
161 | l2size = cachesize_override; | |
162 | ||
34048c9e | 163 | if (l2size == 0) |
1da177e4 LT |
164 | return; /* Again, no L2 cache is possible */ |
165 | ||
166 | c->x86_cache_size = l2size; | |
167 | ||
168 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
169 | l2size, ecx & 0xFF); | |
170 | } | |
171 | ||
34048c9e PC |
172 | /* |
173 | * Naming convention should be: <Name> [(<Codename>)] | |
174 | * This table only is used unless init_<vendor>() below doesn't set it; | |
175 | * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used | |
176 | * | |
177 | */ | |
1da177e4 LT |
178 | |
179 | /* Look up CPU names by table lookup. */ | |
3bc9b76b | 180 | static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c) |
1da177e4 LT |
181 | { |
182 | struct cpu_model_info *info; | |
183 | ||
34048c9e | 184 | if (c->x86_model >= 16) |
1da177e4 LT |
185 | return NULL; /* Range check */ |
186 | ||
187 | if (!this_cpu) | |
188 | return NULL; | |
189 | ||
190 | info = this_cpu->c_models; | |
191 | ||
192 | while (info && info->family) { | |
193 | if (info->family == c->x86) | |
194 | return info->model_names[c->x86_model]; | |
195 | info++; | |
196 | } | |
197 | return NULL; /* Not found */ | |
198 | } | |
199 | ||
9d31d35b YL |
200 | #ifdef CONFIG_X86_HT |
201 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) | |
202 | { | |
203 | u32 eax, ebx, ecx, edx; | |
204 | int index_msb, core_bits; | |
205 | ||
206 | cpuid(1, &eax, &ebx, &ecx, &edx); | |
207 | ||
208 | if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY)) | |
209 | return; | |
210 | ||
211 | smp_num_siblings = (ebx & 0xff0000) >> 16; | |
212 | ||
213 | if (smp_num_siblings == 1) { | |
214 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
215 | } else if (smp_num_siblings > 1) { | |
216 | ||
217 | if (smp_num_siblings > NR_CPUS) { | |
218 | printk(KERN_WARNING "CPU: Unsupported number of siblings %d", | |
219 | smp_num_siblings); | |
220 | smp_num_siblings = 1; | |
221 | return; | |
222 | } | |
223 | ||
224 | index_msb = get_count_order(smp_num_siblings); | |
225 | c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb); | |
226 | ||
227 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
228 | c->phys_proc_id); | |
229 | ||
230 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; | |
231 | ||
232 | index_msb = get_count_order(smp_num_siblings); | |
233 | ||
234 | core_bits = get_count_order(c->x86_max_cores); | |
235 | ||
236 | c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) & | |
237 | ((1 << core_bits) - 1); | |
238 | ||
239 | if (c->x86_max_cores > 1) | |
240 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
241 | c->cpu_core_id); | |
242 | } | |
243 | } | |
244 | #endif | |
1da177e4 | 245 | |
3da99c97 | 246 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
247 | { |
248 | char *v = c->x86_vendor_id; | |
249 | int i; | |
fe38d855 | 250 | static int printed; |
1da177e4 LT |
251 | |
252 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
253 | if (cpu_devs[i]) { | |
34048c9e PC |
254 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || |
255 | (cpu_devs[i]->c_ident[1] && | |
256 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
1da177e4 | 257 | c->x86_vendor = i; |
3da99c97 | 258 | this_cpu = cpu_devs[i]; |
fe38d855 | 259 | return; |
1da177e4 LT |
260 | } |
261 | } | |
262 | } | |
fe38d855 CE |
263 | if (!printed) { |
264 | printed++; | |
265 | printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n"); | |
266 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); | |
267 | } | |
268 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
269 | this_cpu = &default_cpu; | |
1da177e4 LT |
270 | } |
271 | ||
272 | ||
34048c9e | 273 | static int __init x86_fxsr_setup(char *s) |
1da177e4 | 274 | { |
13530257 AK |
275 | setup_clear_cpu_cap(X86_FEATURE_FXSR); |
276 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
1da177e4 LT |
277 | return 1; |
278 | } | |
279 | __setup("nofxsr", x86_fxsr_setup); | |
280 | ||
281 | ||
34048c9e | 282 | static int __init x86_sep_setup(char *s) |
4f886511 | 283 | { |
13530257 | 284 | setup_clear_cpu_cap(X86_FEATURE_SEP); |
4f886511 CE |
285 | return 1; |
286 | } | |
287 | __setup("nosep", x86_sep_setup); | |
288 | ||
289 | ||
1da177e4 LT |
290 | /* Standard macro to see if a specific flag is changeable */ |
291 | static inline int flag_is_changeable_p(u32 flag) | |
292 | { | |
293 | u32 f1, f2; | |
294 | ||
295 | asm("pushfl\n\t" | |
296 | "pushfl\n\t" | |
297 | "popl %0\n\t" | |
298 | "movl %0,%1\n\t" | |
299 | "xorl %2,%0\n\t" | |
300 | "pushl %0\n\t" | |
301 | "popfl\n\t" | |
302 | "pushfl\n\t" | |
303 | "popl %0\n\t" | |
304 | "popfl\n\t" | |
305 | : "=&r" (f1), "=&r" (f2) | |
306 | : "ir" (flag)); | |
307 | ||
308 | return ((f1^f2) & flag) != 0; | |
309 | } | |
310 | ||
311 | ||
312 | /* Probe for the CPUID instruction */ | |
3bc9b76b | 313 | static int __cpuinit have_cpuid_p(void) |
1da177e4 LT |
314 | { |
315 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
316 | } | |
317 | ||
9d31d35b YL |
318 | static void __init early_cpu_support_print(void) |
319 | { | |
320 | int i,j; | |
321 | struct cpu_dev *cpu_devx; | |
322 | ||
323 | printk("KERNEL supported cpus:\n"); | |
324 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
325 | cpu_devx = cpu_devs[i]; | |
326 | if (!cpu_devx) | |
327 | continue; | |
328 | for (j = 0; j < 2; j++) { | |
329 | if (!cpu_devx->c_ident[j]) | |
330 | continue; | |
331 | printk(" %s %s\n", cpu_devx->c_vendor, | |
332 | cpu_devx->c_ident[j]); | |
333 | } | |
334 | } | |
335 | } | |
336 | ||
337 | void __cpuinit cpu_detect(struct cpuinfo_x86 *c) | |
1da177e4 | 338 | { |
1da177e4 | 339 | /* Get vendor name */ |
4a148513 HH |
340 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
341 | (unsigned int *)&c->x86_vendor_id[0], | |
342 | (unsigned int *)&c->x86_vendor_id[8], | |
343 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 344 | |
1da177e4 | 345 | c->x86 = 4; |
9d31d35b | 346 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
347 | if (c->cpuid_level >= 0x00000001) { |
348 | u32 junk, tfms, cap0, misc; | |
349 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
9d31d35b YL |
350 | c->x86 = (tfms >> 8) & 0xf; |
351 | c->x86_model = (tfms >> 4) & 0xf; | |
352 | c->x86_mask = tfms & 0xf; | |
f5f786d0 | 353 | if (c->x86 == 0xf) |
1da177e4 | 354 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 355 | if (c->x86 >= 0x6) |
9d31d35b | 356 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
d4387bd3 | 357 | if (cap0 & (1<<19)) { |
d4387bd3 | 358 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 359 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 360 | } |
1da177e4 | 361 | } |
1da177e4 | 362 | } |
3da99c97 YL |
363 | |
364 | static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) | |
093af8d7 YL |
365 | { |
366 | u32 tfms, xlvl; | |
3da99c97 | 367 | u32 ebx; |
093af8d7 | 368 | |
3da99c97 YL |
369 | /* Intel-defined flags: level 0x00000001 */ |
370 | if (c->cpuid_level >= 0x00000001) { | |
371 | u32 capability, excap; | |
372 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); | |
373 | c->x86_capability[0] = capability; | |
374 | c->x86_capability[4] = excap; | |
375 | } | |
093af8d7 | 376 | |
3da99c97 YL |
377 | /* AMD-defined flags: level 0x80000001 */ |
378 | xlvl = cpuid_eax(0x80000000); | |
379 | c->extended_cpuid_level = xlvl; | |
380 | if ((xlvl & 0xffff0000) == 0x80000000) { | |
381 | if (xlvl >= 0x80000001) { | |
382 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
383 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 384 | } |
093af8d7 | 385 | } |
093af8d7 | 386 | } |
34048c9e PC |
387 | /* |
388 | * Do minimum CPU detection early. | |
389 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
390 | * cache alignment. | |
391 | * The others are not touched to avoid unwanted side effects. | |
392 | * | |
393 | * WARNING: this function is only called on the BP. Don't add code here | |
394 | * that is supposed to run on all CPUs. | |
395 | */ | |
3da99c97 | 396 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 397 | { |
d7cd5611 | 398 | c->x86_cache_alignment = 32; |
d4387bd3 | 399 | c->x86_clflush_size = 32; |
d7cd5611 RR |
400 | |
401 | if (!have_cpuid_p()) | |
402 | return; | |
403 | ||
3da99c97 YL |
404 | c->extended_cpuid_level = 0; |
405 | ||
406 | memset(&c->x86_capability, 0, sizeof c->x86_capability); | |
407 | ||
d7cd5611 RR |
408 | cpu_detect(c); |
409 | ||
3da99c97 | 410 | get_cpu_vendor(c); |
2b16a235 | 411 | |
3da99c97 | 412 | get_cpu_cap(c); |
5031088d | 413 | |
03ae5768 TP |
414 | if (c->x86_vendor != X86_VENDOR_UNKNOWN && |
415 | cpu_devs[c->x86_vendor]->c_early_init) | |
416 | cpu_devs[c->x86_vendor]->c_early_init(c); | |
3da99c97 YL |
417 | |
418 | validate_pat_support(c); | |
d7cd5611 RR |
419 | } |
420 | ||
9d31d35b YL |
421 | void __init early_cpu_init(void) |
422 | { | |
423 | struct cpu_vendor_dev *cvdev; | |
424 | ||
425 | for (cvdev = __x86cpuvendor_start; cvdev < __x86cpuvendor_end; cvdev++) | |
426 | cpu_devs[cvdev->vendor] = cvdev->cpu_dev; | |
427 | ||
428 | early_cpu_support_print(); | |
429 | early_identify_cpu(&boot_cpu_data); | |
430 | } | |
431 | ||
7e00df58 PA |
432 | /* |
433 | * The NOPL instruction is supposed to exist on all CPUs with | |
434 | * family >= 6, unfortunately, that's not true in practice because | |
435 | * of early VIA chips and (more importantly) broken virtualizers that | |
436 | * are not easy to detect. Hence, probe for it based on first | |
437 | * principles. | |
438 | */ | |
439 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
440 | { | |
441 | const u32 nopl_signature = 0x888c53b1; /* Random number */ | |
442 | u32 has_nopl = nopl_signature; | |
443 | ||
444 | clear_cpu_cap(c, X86_FEATURE_NOPL); | |
445 | if (c->x86 >= 6) { | |
446 | asm volatile("\n" | |
447 | "1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */ | |
448 | "2:\n" | |
449 | " .section .fixup,\"ax\"\n" | |
450 | "3: xor %0,%0\n" | |
451 | " jmp 2b\n" | |
452 | " .previous\n" | |
453 | _ASM_EXTABLE(1b,3b) | |
454 | : "+a" (has_nopl)); | |
455 | ||
456 | if (has_nopl == nopl_signature) | |
457 | set_cpu_cap(c, X86_FEATURE_NOPL); | |
458 | } | |
459 | } | |
460 | ||
34048c9e | 461 | static void __cpuinit generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 462 | { |
3da99c97 YL |
463 | if (!have_cpuid_p()) |
464 | return; | |
465 | ||
466 | c->extended_cpuid_level = 0; | |
467 | ||
468 | cpu_detect(c); | |
469 | ||
470 | get_cpu_vendor(c); | |
471 | ||
472 | get_cpu_cap(c); | |
473 | ||
474 | if (c->cpuid_level >= 0x00000001) { | |
475 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
96c52749 | 476 | #ifdef CONFIG_X86_HT |
3da99c97 YL |
477 | c->apicid = phys_pkg_id(c->initial_apicid, 0); |
478 | c->phys_proc_id = c->initial_apicid; | |
1e9f28fa | 479 | #else |
3da99c97 | 480 | c->apicid = c->initial_apicid; |
1e9f28fa | 481 | #endif |
3da99c97 | 482 | } |
1da177e4 | 483 | |
3da99c97 YL |
484 | if (c->extended_cpuid_level >= 0x80000004) |
485 | get_model_name(c); /* Default name */ | |
1d67953f | 486 | |
3da99c97 YL |
487 | init_scattered_cpuid_features(c); |
488 | detect_nopl(c); | |
1da177e4 LT |
489 | } |
490 | ||
3bc9b76b | 491 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
1da177e4 | 492 | { |
34048c9e | 493 | if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) { |
1da177e4 | 494 | /* Disable processor serial number */ |
34048c9e PC |
495 | unsigned long lo, hi; |
496 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
1da177e4 | 497 | lo |= 0x200000; |
34048c9e | 498 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); |
1da177e4 | 499 | printk(KERN_NOTICE "CPU serial number disabled.\n"); |
4cbe668a | 500 | clear_cpu_cap(c, X86_FEATURE_PN); |
1da177e4 LT |
501 | |
502 | /* Disabling the serial number may affect the cpuid level */ | |
503 | c->cpuid_level = cpuid_eax(0); | |
504 | } | |
505 | } | |
506 | ||
507 | static int __init x86_serial_nr_setup(char *s) | |
508 | { | |
509 | disable_x86_serial_nr = 0; | |
510 | return 1; | |
511 | } | |
512 | __setup("serialnumber", x86_serial_nr_setup); | |
513 | ||
514 | ||
515 | ||
516 | /* | |
517 | * This does the hard work of actually picking apart the CPU stuff... | |
518 | */ | |
9a250347 | 519 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
520 | { |
521 | int i; | |
522 | ||
523 | c->loops_per_jiffy = loops_per_jiffy; | |
524 | c->x86_cache_size = -1; | |
525 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
526 | c->cpuid_level = -1; /* CPUID not detected */ | |
527 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ | |
528 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
529 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 530 | c->x86_max_cores = 1; |
770d132f | 531 | c->x86_clflush_size = 32; |
1da177e4 LT |
532 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
533 | ||
534 | if (!have_cpuid_p()) { | |
34048c9e PC |
535 | /* |
536 | * First of all, decide if this is a 486 or higher | |
537 | * It's a 486 if we can modify the AC flag | |
538 | */ | |
539 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
1da177e4 LT |
540 | c->x86 = 4; |
541 | else | |
542 | c->x86 = 3; | |
543 | } | |
544 | ||
545 | generic_identify(c); | |
546 | ||
3898534d | 547 | if (this_cpu->c_identify) |
1da177e4 LT |
548 | this_cpu->c_identify(c); |
549 | ||
1da177e4 LT |
550 | /* |
551 | * Vendor-specific initialization. In this section we | |
552 | * canonicalize the feature flags, meaning if there are | |
553 | * features a certain CPU supports which CPUID doesn't | |
554 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
555 | * we handle them here. | |
556 | * | |
557 | * At the end of this section, c->x86_capability better | |
558 | * indicate the features this CPU genuinely supports! | |
559 | */ | |
560 | if (this_cpu->c_init) | |
561 | this_cpu->c_init(c); | |
562 | ||
563 | /* Disable the PN if appropriate */ | |
564 | squash_the_stupid_serial_number(c); | |
565 | ||
566 | /* | |
567 | * The vendor-specific functions might have changed features. Now | |
568 | * we do "generic changes." | |
569 | */ | |
570 | ||
1da177e4 | 571 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 572 | if (!c->x86_model_id[0]) { |
1da177e4 LT |
573 | char *p; |
574 | p = table_lookup_model(c); | |
34048c9e | 575 | if (p) |
1da177e4 LT |
576 | strcpy(c->x86_model_id, p); |
577 | else | |
578 | /* Last resort... */ | |
579 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 580 | c->x86, c->x86_model); |
1da177e4 LT |
581 | } |
582 | ||
1da177e4 LT |
583 | /* |
584 | * On SMP, boot_cpu_data holds the common feature set between | |
585 | * all CPUs; so make sure that we indicate which features are | |
586 | * common between the CPUs. The first time this routine gets | |
587 | * executed, c == &boot_cpu_data. | |
588 | */ | |
34048c9e | 589 | if (c != &boot_cpu_data) { |
1da177e4 | 590 | /* AND the already accumulated flags with these */ |
9d31d35b | 591 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 LT |
592 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
593 | } | |
594 | ||
7d851c8d AK |
595 | /* Clear all flags overriden by options */ |
596 | for (i = 0; i < NCAPINTS; i++) | |
12c247a6 | 597 | c->x86_capability[i] &= ~cleared_cpu_caps[i]; |
7d851c8d | 598 | |
1da177e4 | 599 | /* Init Machine Check Exception if available. */ |
1da177e4 | 600 | mcheck_init(c); |
30d432df AK |
601 | |
602 | select_idle_routine(c); | |
a6c4e076 | 603 | } |
31ab269a | 604 | |
a6c4e076 JF |
605 | void __init identify_boot_cpu(void) |
606 | { | |
607 | identify_cpu(&boot_cpu_data); | |
608 | sysenter_setup(); | |
6fe940d6 | 609 | enable_sep_cpu(); |
a6c4e076 | 610 | } |
3b520b23 | 611 | |
a6c4e076 JF |
612 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) |
613 | { | |
614 | BUG_ON(c == &boot_cpu_data); | |
615 | identify_cpu(c); | |
616 | enable_sep_cpu(); | |
617 | mtrr_ap_init(); | |
1da177e4 LT |
618 | } |
619 | ||
191679fd AK |
620 | static __init int setup_noclflush(char *arg) |
621 | { | |
622 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
623 | return 1; | |
624 | } | |
625 | __setup("noclflush", setup_noclflush); | |
626 | ||
3bc9b76b | 627 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 LT |
628 | { |
629 | char *vendor = NULL; | |
630 | ||
631 | if (c->x86_vendor < X86_VENDOR_NUM) | |
632 | vendor = this_cpu->c_vendor; | |
633 | else if (c->cpuid_level >= 0) | |
634 | vendor = c->x86_vendor_id; | |
635 | ||
636 | if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor))) | |
9d31d35b | 637 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 638 | |
9d31d35b YL |
639 | if (c->x86_model_id[0]) |
640 | printk(KERN_CONT "%s", c->x86_model_id); | |
1da177e4 | 641 | else |
9d31d35b | 642 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 643 | |
34048c9e | 644 | if (c->x86_mask || c->cpuid_level >= 0) |
9d31d35b | 645 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); |
1da177e4 | 646 | else |
9d31d35b | 647 | printk(KERN_CONT "\n"); |
1da177e4 LT |
648 | } |
649 | ||
ac72e788 AK |
650 | static __init int setup_disablecpuid(char *arg) |
651 | { | |
652 | int bit; | |
653 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) | |
654 | setup_clear_cpu_cap(bit); | |
655 | else | |
656 | return 0; | |
657 | return 1; | |
658 | } | |
659 | __setup("clearcpuid=", setup_disablecpuid); | |
660 | ||
3bc9b76b | 661 | cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE; |
1da177e4 | 662 | |
7c3576d2 | 663 | /* Make sure %fs is initialized properly in idle threads */ |
6b2fb3c6 | 664 | struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) |
f95d47ca JF |
665 | { |
666 | memset(regs, 0, sizeof(struct pt_regs)); | |
65ea5b03 | 667 | regs->fs = __KERNEL_PERCPU; |
f95d47ca JF |
668 | return regs; |
669 | } | |
670 | ||
d2cbcc49 RR |
671 | /* |
672 | * cpu_init() initializes state that is per-CPU. Some data is already | |
673 | * initialized (naturally) in the bootstrap process, such as the GDT | |
674 | * and IDT. We reload them nevertheless, this function acts as a | |
675 | * 'CPU state barrier', nothing should get across. | |
676 | */ | |
677 | void __cpuinit cpu_init(void) | |
9ee79a3d | 678 | { |
d2cbcc49 RR |
679 | int cpu = smp_processor_id(); |
680 | struct task_struct *curr = current; | |
34048c9e | 681 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 682 | struct thread_struct *thread = &curr->thread; |
62111195 JF |
683 | |
684 | if (cpu_test_and_set(cpu, cpu_initialized)) { | |
685 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); | |
686 | for (;;) local_irq_enable(); | |
687 | } | |
688 | ||
689 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
690 | ||
691 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
692 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 693 | |
4d37e7e3 | 694 | load_idt(&idt_descr); |
c5413fbe | 695 | switch_to_new_gdt(); |
1da177e4 | 696 | |
1da177e4 LT |
697 | /* |
698 | * Set up and load the per-CPU TSS and LDT | |
699 | */ | |
700 | atomic_inc(&init_mm.mm_count); | |
62111195 JF |
701 | curr->active_mm = &init_mm; |
702 | if (curr->mm) | |
703 | BUG(); | |
704 | enter_lazy_tlb(&init_mm, curr); | |
1da177e4 | 705 | |
faca6227 | 706 | load_sp0(t, thread); |
34048c9e | 707 | set_tss_desc(cpu, t); |
1da177e4 LT |
708 | load_TR_desc(); |
709 | load_LDT(&init_mm.context); | |
710 | ||
22c4e308 | 711 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
712 | /* Set up doublefault TSS pointer in the GDT */ |
713 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 714 | #endif |
1da177e4 | 715 | |
464d1a78 JF |
716 | /* Clear %gs. */ |
717 | asm volatile ("mov %0, %%gs" : : "r" (0)); | |
1da177e4 LT |
718 | |
719 | /* Clear all 6 debug registers: */ | |
4bb0d3ec ZA |
720 | set_debugreg(0, 0); |
721 | set_debugreg(0, 1); | |
722 | set_debugreg(0, 2); | |
723 | set_debugreg(0, 3); | |
724 | set_debugreg(0, 6); | |
725 | set_debugreg(0, 7); | |
1da177e4 LT |
726 | |
727 | /* | |
728 | * Force FPU initialization: | |
729 | */ | |
730 | current_thread_info()->status = 0; | |
731 | clear_used_math(); | |
732 | mxcsr_feature_mask_init(); | |
733 | } | |
e1367daf LS |
734 | |
735 | #ifdef CONFIG_HOTPLUG_CPU | |
3bc9b76b | 736 | void __cpuinit cpu_uninit(void) |
e1367daf LS |
737 | { |
738 | int cpu = raw_smp_processor_id(); | |
739 | cpu_clear(cpu, cpu_initialized); | |
740 | ||
741 | /* lazy TLB state */ | |
742 | per_cpu(cpu_tlbstate, cpu).state = 0; | |
743 | per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm; | |
744 | } | |
745 | #endif |