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1da177e4 | 1 | #include <linux/init.h> |
f0fc4aff YL |
2 | #include <linux/kernel.h> |
3 | #include <linux/sched.h> | |
1da177e4 | 4 | #include <linux/string.h> |
f0fc4aff YL |
5 | #include <linux/bootmem.h> |
6 | #include <linux/bitops.h> | |
7 | #include <linux/module.h> | |
8 | #include <linux/kgdb.h> | |
9 | #include <linux/topology.h> | |
1da177e4 LT |
10 | #include <linux/delay.h> |
11 | #include <linux/smp.h> | |
1da177e4 | 12 | #include <linux/percpu.h> |
1da177e4 LT |
13 | #include <asm/i387.h> |
14 | #include <asm/msr.h> | |
15 | #include <asm/io.h> | |
f0fc4aff | 16 | #include <asm/linkage.h> |
1da177e4 | 17 | #include <asm/mmu_context.h> |
27b07da7 | 18 | #include <asm/mtrr.h> |
a03a3e28 | 19 | #include <asm/mce.h> |
8d4a4300 | 20 | #include <asm/pat.h> |
b6734c35 | 21 | #include <asm/asm.h> |
f0fc4aff | 22 | #include <asm/numa.h> |
b342797c | 23 | #include <asm/smp.h> |
f472cdba | 24 | #include <asm/cpu.h> |
06879033 | 25 | #include <asm/cpumask.h> |
1da177e4 LT |
26 | #ifdef CONFIG_X86_LOCAL_APIC |
27 | #include <asm/mpspec.h> | |
28 | #include <asm/apic.h> | |
f0fc4aff | 29 | #include <asm/genapic.h> |
f0fc4aff | 30 | #include <asm/genapic.h> |
bdbcdd48 | 31 | #include <asm/uv/uv.h> |
1da177e4 LT |
32 | #endif |
33 | ||
f0fc4aff YL |
34 | #include <asm/pgtable.h> |
35 | #include <asm/processor.h> | |
36 | #include <asm/desc.h> | |
37 | #include <asm/atomic.h> | |
38 | #include <asm/proto.h> | |
39 | #include <asm/sections.h> | |
40 | #include <asm/setup.h> | |
88b094fb | 41 | #include <asm/hypervisor.h> |
60a5317f | 42 | #include <asm/stackprotector.h> |
f0fc4aff | 43 | |
1da177e4 LT |
44 | #include "cpu.h" |
45 | ||
c2d1cec1 MT |
46 | #ifdef CONFIG_X86_64 |
47 | ||
48 | /* all of these masks are initialized in setup_cpu_local_masks() */ | |
49 | cpumask_var_t cpu_callin_mask; | |
50 | cpumask_var_t cpu_callout_mask; | |
51 | cpumask_var_t cpu_initialized_mask; | |
52 | ||
53 | /* representing cpus for which sibling maps can be computed */ | |
54 | cpumask_var_t cpu_sibling_setup_mask; | |
55 | ||
2f2f52ba | 56 | /* correctly size the local cpu masks */ |
4369f1fb | 57 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
58 | { |
59 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
60 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
61 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
62 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
63 | } | |
64 | ||
c2d1cec1 MT |
65 | #else /* CONFIG_X86_32 */ |
66 | ||
67 | cpumask_t cpu_callin_map; | |
68 | cpumask_t cpu_callout_map; | |
69 | cpumask_t cpu_initialized; | |
70 | cpumask_t cpu_sibling_setup_map; | |
71 | ||
72 | #endif /* CONFIG_X86_32 */ | |
73 | ||
74 | ||
0a488a53 YL |
75 | static struct cpu_dev *this_cpu __cpuinitdata; |
76 | ||
06deef89 | 77 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 78 | #ifdef CONFIG_X86_64 |
06deef89 BG |
79 | /* |
80 | * We need valid kernel segments for data and code in long mode too | |
81 | * IRET will check the segment types kkeil 2000/10/28 | |
82 | * Also sysret mandates a special GDT layout | |
83 | * | |
84 | * The TLS descriptors are currently at a different place compared to i386. | |
85 | * Hopefully nobody expects them at a fixed place (Wine?) | |
86 | */ | |
950ad7ff YL |
87 | [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } }, |
88 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } }, | |
89 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } }, | |
90 | [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } }, | |
91 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } }, | |
92 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } }, | |
950ad7ff | 93 | #else |
6842ef0e GOC |
94 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, |
95 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, | |
96 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, | |
97 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, | |
bf504672 RR |
98 | /* |
99 | * Segments used for calling PnP BIOS have byte granularity. | |
100 | * They code segments and data segments have fixed 64k limits, | |
101 | * the transfer segment sizes are set at run time. | |
102 | */ | |
6842ef0e GOC |
103 | /* 32-bit code */ |
104 | [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, | |
105 | /* 16-bit code */ | |
106 | [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, | |
107 | /* 16-bit data */ | |
108 | [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, | |
109 | /* 16-bit data */ | |
110 | [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, | |
111 | /* 16-bit data */ | |
112 | [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, | |
bf504672 RR |
113 | /* |
114 | * The APM segments have byte granularity and their bases | |
115 | * are set at run time. All have 64k limits. | |
116 | */ | |
6842ef0e GOC |
117 | /* 32-bit code */ |
118 | [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, | |
bf504672 | 119 | /* 16-bit code */ |
6842ef0e GOC |
120 | [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, |
121 | /* data */ | |
122 | [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, | |
bf504672 | 123 | |
6842ef0e | 124 | [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, |
0dd76d73 | 125 | [GDT_ENTRY_PERCPU] = { { { 0x0000ffff, 0x00cf9200 } } }, |
60a5317f | 126 | GDT_STACK_CANARY_INIT |
950ad7ff | 127 | #endif |
06deef89 | 128 | } }; |
7a61d35d | 129 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 130 | |
ba51dced | 131 | #ifdef CONFIG_X86_32 |
3bc9b76b | 132 | static int cachesize_override __cpuinitdata = -1; |
3bc9b76b | 133 | static int disable_x86_serial_nr __cpuinitdata = 1; |
1da177e4 | 134 | |
0a488a53 YL |
135 | static int __init cachesize_setup(char *str) |
136 | { | |
137 | get_option(&str, &cachesize_override); | |
138 | return 1; | |
139 | } | |
140 | __setup("cachesize=", cachesize_setup); | |
141 | ||
0a488a53 YL |
142 | static int __init x86_fxsr_setup(char *s) |
143 | { | |
144 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
145 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
146 | return 1; | |
147 | } | |
148 | __setup("nofxsr", x86_fxsr_setup); | |
149 | ||
150 | static int __init x86_sep_setup(char *s) | |
151 | { | |
152 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
153 | return 1; | |
154 | } | |
155 | __setup("nosep", x86_sep_setup); | |
156 | ||
157 | /* Standard macro to see if a specific flag is changeable */ | |
158 | static inline int flag_is_changeable_p(u32 flag) | |
159 | { | |
160 | u32 f1, f2; | |
161 | ||
94f6bac1 KH |
162 | /* |
163 | * Cyrix and IDT cpus allow disabling of CPUID | |
164 | * so the code below may return different results | |
165 | * when it is executed before and after enabling | |
166 | * the CPUID. Add "volatile" to not allow gcc to | |
167 | * optimize the subsequent calls to this function. | |
168 | */ | |
169 | asm volatile ("pushfl\n\t" | |
170 | "pushfl\n\t" | |
171 | "popl %0\n\t" | |
172 | "movl %0,%1\n\t" | |
173 | "xorl %2,%0\n\t" | |
174 | "pushl %0\n\t" | |
175 | "popfl\n\t" | |
176 | "pushfl\n\t" | |
177 | "popl %0\n\t" | |
178 | "popfl\n\t" | |
179 | : "=&r" (f1), "=&r" (f2) | |
180 | : "ir" (flag)); | |
0a488a53 YL |
181 | |
182 | return ((f1^f2) & flag) != 0; | |
183 | } | |
184 | ||
185 | /* Probe for the CPUID instruction */ | |
186 | static int __cpuinit have_cpuid_p(void) | |
187 | { | |
188 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
189 | } | |
190 | ||
191 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
192 | { | |
193 | if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) { | |
194 | /* Disable processor serial number */ | |
195 | unsigned long lo, hi; | |
196 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
197 | lo |= 0x200000; | |
198 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
199 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
200 | clear_cpu_cap(c, X86_FEATURE_PN); | |
201 | ||
202 | /* Disabling the serial number may affect the cpuid level */ | |
203 | c->cpuid_level = cpuid_eax(0); | |
204 | } | |
205 | } | |
206 | ||
207 | static int __init x86_serial_nr_setup(char *s) | |
208 | { | |
209 | disable_x86_serial_nr = 0; | |
210 | return 1; | |
211 | } | |
212 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 213 | #else |
102bbe3a YL |
214 | static inline int flag_is_changeable_p(u32 flag) |
215 | { | |
216 | return 1; | |
217 | } | |
ba51dced YL |
218 | /* Probe for the CPUID instruction */ |
219 | static inline int have_cpuid_p(void) | |
220 | { | |
221 | return 1; | |
222 | } | |
102bbe3a YL |
223 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
224 | { | |
225 | } | |
ba51dced | 226 | #endif |
0a488a53 | 227 | |
b38b0665 PA |
228 | /* |
229 | * Some CPU features depend on higher CPUID levels, which may not always | |
230 | * be available due to CPUID level capping or broken virtualization | |
231 | * software. Add those features to this table to auto-disable them. | |
232 | */ | |
233 | struct cpuid_dependent_feature { | |
234 | u32 feature; | |
235 | u32 level; | |
236 | }; | |
237 | static const struct cpuid_dependent_feature __cpuinitconst | |
238 | cpuid_dependent_features[] = { | |
239 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
240 | { X86_FEATURE_DCA, 0x00000009 }, | |
241 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
242 | { 0, 0 } | |
243 | }; | |
244 | ||
245 | static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) | |
246 | { | |
247 | const struct cpuid_dependent_feature *df; | |
248 | for (df = cpuid_dependent_features; df->feature; df++) { | |
249 | /* | |
250 | * Note: cpuid_level is set to -1 if unavailable, but | |
251 | * extended_extended_level is set to 0 if unavailable | |
252 | * and the legitimate extended levels are all negative | |
253 | * when signed; hence the weird messing around with | |
254 | * signs here... | |
255 | */ | |
256 | if (cpu_has(c, df->feature) && | |
f6db44df YL |
257 | ((s32)df->level < 0 ? |
258 | (u32)df->level > (u32)c->extended_cpuid_level : | |
259 | (s32)df->level > (s32)c->cpuid_level)) { | |
b38b0665 PA |
260 | clear_cpu_cap(c, df->feature); |
261 | if (warn) | |
262 | printk(KERN_WARNING | |
263 | "CPU: CPU feature %s disabled " | |
264 | "due to lack of CPUID level 0x%x\n", | |
265 | x86_cap_flags[df->feature], | |
266 | df->level); | |
267 | } | |
268 | } | |
f6db44df | 269 | } |
b38b0665 | 270 | |
102bbe3a YL |
271 | /* |
272 | * Naming convention should be: <Name> [(<Codename>)] | |
273 | * This table only is used unless init_<vendor>() below doesn't set it; | |
274 | * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used | |
275 | * | |
276 | */ | |
277 | ||
278 | /* Look up CPU names by table lookup. */ | |
279 | static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c) | |
280 | { | |
281 | struct cpu_model_info *info; | |
282 | ||
283 | if (c->x86_model >= 16) | |
284 | return NULL; /* Range check */ | |
285 | ||
286 | if (!this_cpu) | |
287 | return NULL; | |
288 | ||
289 | info = this_cpu->c_models; | |
290 | ||
291 | while (info && info->family) { | |
292 | if (info->family == c->x86) | |
293 | return info->model_names[c->x86_model]; | |
294 | info++; | |
295 | } | |
296 | return NULL; /* Not found */ | |
297 | } | |
298 | ||
7d851c8d AK |
299 | __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; |
300 | ||
11e3a840 JF |
301 | void load_percpu_segment(int cpu) |
302 | { | |
303 | #ifdef CONFIG_X86_32 | |
304 | loadsegment(fs, __KERNEL_PERCPU); | |
305 | #else | |
306 | loadsegment(gs, 0); | |
307 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); | |
308 | #endif | |
60a5317f | 309 | load_stack_canary_segment(); |
11e3a840 JF |
310 | } |
311 | ||
9d31d35b YL |
312 | /* Current gdt points %fs at the "master" per-cpu area: after this, |
313 | * it's on the real one. */ | |
552be871 | 314 | void switch_to_new_gdt(int cpu) |
9d31d35b YL |
315 | { |
316 | struct desc_ptr gdt_descr; | |
317 | ||
2697fbd5 | 318 | gdt_descr.address = (long)get_cpu_gdt_table(cpu); |
9d31d35b YL |
319 | gdt_descr.size = GDT_SIZE - 1; |
320 | load_gdt(&gdt_descr); | |
2697fbd5 | 321 | /* Reload the per-cpu base */ |
11e3a840 JF |
322 | |
323 | load_percpu_segment(cpu); | |
9d31d35b YL |
324 | } |
325 | ||
10a434fc | 326 | static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 327 | |
34048c9e | 328 | static void __cpuinit default_init(struct cpuinfo_x86 *c) |
1da177e4 | 329 | { |
b9e67f00 YL |
330 | #ifdef CONFIG_X86_64 |
331 | display_cacheinfo(c); | |
332 | #else | |
1da177e4 LT |
333 | /* Not much we can do here... */ |
334 | /* Check if at least it has cpuid */ | |
335 | if (c->cpuid_level == -1) { | |
336 | /* No cpuid. It must be an ancient CPU */ | |
337 | if (c->x86 == 4) | |
338 | strcpy(c->x86_model_id, "486"); | |
339 | else if (c->x86 == 3) | |
340 | strcpy(c->x86_model_id, "386"); | |
341 | } | |
b9e67f00 | 342 | #endif |
1da177e4 LT |
343 | } |
344 | ||
95414930 | 345 | static struct cpu_dev __cpuinitdata default_cpu = { |
1da177e4 | 346 | .c_init = default_init, |
fe38d855 | 347 | .c_vendor = "Unknown", |
10a434fc | 348 | .c_x86_vendor = X86_VENDOR_UNKNOWN, |
1da177e4 | 349 | }; |
1da177e4 | 350 | |
1b05d60d | 351 | static void __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
352 | { |
353 | unsigned int *v; | |
354 | char *p, *q; | |
355 | ||
3da99c97 | 356 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 357 | return; |
1da177e4 LT |
358 | |
359 | v = (unsigned int *) c->x86_model_id; | |
360 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
361 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
362 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
363 | c->x86_model_id[48] = 0; | |
364 | ||
365 | /* Intel chips right-justify this string for some dumb reason; | |
366 | undo that brain damage */ | |
367 | p = q = &c->x86_model_id[0]; | |
34048c9e | 368 | while (*p == ' ') |
1da177e4 | 369 | p++; |
34048c9e PC |
370 | if (p != q) { |
371 | while (*p) | |
1da177e4 | 372 | *q++ = *p++; |
34048c9e | 373 | while (q <= &c->x86_model_id[48]) |
1da177e4 LT |
374 | *q++ = '\0'; /* Zero-pad the rest */ |
375 | } | |
1da177e4 LT |
376 | } |
377 | ||
3bc9b76b | 378 | void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) |
1da177e4 | 379 | { |
9d31d35b | 380 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 381 | |
3da99c97 | 382 | n = c->extended_cpuid_level; |
1da177e4 LT |
383 | |
384 | if (n >= 0x80000005) { | |
9d31d35b | 385 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 386 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", |
9d31d35b YL |
387 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); |
388 | c->x86_cache_size = (ecx>>24) + (edx>>24); | |
140fc727 YL |
389 | #ifdef CONFIG_X86_64 |
390 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
391 | c->x86_tlbsize = 0; | |
392 | #endif | |
1da177e4 LT |
393 | } |
394 | ||
395 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
396 | return; | |
397 | ||
0a488a53 | 398 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 399 | l2size = ecx >> 16; |
34048c9e | 400 | |
140fc727 YL |
401 | #ifdef CONFIG_X86_64 |
402 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
403 | #else | |
1da177e4 LT |
404 | /* do processor-specific cache resizing */ |
405 | if (this_cpu->c_size_cache) | |
34048c9e | 406 | l2size = this_cpu->c_size_cache(c, l2size); |
1da177e4 LT |
407 | |
408 | /* Allow user to override all this if necessary. */ | |
409 | if (cachesize_override != -1) | |
410 | l2size = cachesize_override; | |
411 | ||
34048c9e | 412 | if (l2size == 0) |
1da177e4 | 413 | return; /* Again, no L2 cache is possible */ |
140fc727 | 414 | #endif |
1da177e4 LT |
415 | |
416 | c->x86_cache_size = l2size; | |
417 | ||
418 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
0a488a53 | 419 | l2size, ecx & 0xFF); |
1da177e4 LT |
420 | } |
421 | ||
9d31d35b | 422 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 423 | { |
97e4db7c | 424 | #ifdef CONFIG_X86_HT |
0a488a53 YL |
425 | u32 eax, ebx, ecx, edx; |
426 | int index_msb, core_bits; | |
1da177e4 | 427 | |
0a488a53 | 428 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 429 | return; |
1da177e4 | 430 | |
0a488a53 YL |
431 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
432 | goto out; | |
1da177e4 | 433 | |
1cd78776 YL |
434 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
435 | return; | |
1da177e4 | 436 | |
0a488a53 | 437 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 438 | |
9d31d35b YL |
439 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
440 | ||
441 | if (smp_num_siblings == 1) { | |
442 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
443 | } else if (smp_num_siblings > 1) { | |
444 | ||
9628937d | 445 | if (smp_num_siblings > nr_cpu_ids) { |
9d31d35b YL |
446 | printk(KERN_WARNING "CPU: Unsupported number of siblings %d", |
447 | smp_num_siblings); | |
448 | smp_num_siblings = 1; | |
449 | return; | |
450 | } | |
451 | ||
452 | index_msb = get_count_order(smp_num_siblings); | |
cb8cc442 | 453 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); |
9d31d35b YL |
454 | |
455 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; | |
456 | ||
457 | index_msb = get_count_order(smp_num_siblings); | |
458 | ||
459 | core_bits = get_count_order(c->x86_max_cores); | |
460 | ||
cb8cc442 | 461 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & |
1cd78776 | 462 | ((1 << core_bits) - 1); |
1da177e4 | 463 | } |
1da177e4 | 464 | |
0a488a53 YL |
465 | out: |
466 | if ((c->x86_max_cores * smp_num_siblings) > 1) { | |
467 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
468 | c->phys_proc_id); | |
469 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
470 | c->cpu_core_id); | |
9d31d35b | 471 | } |
9d31d35b | 472 | #endif |
97e4db7c | 473 | } |
1da177e4 | 474 | |
3da99c97 | 475 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
476 | { |
477 | char *v = c->x86_vendor_id; | |
478 | int i; | |
fe38d855 | 479 | static int printed; |
1da177e4 LT |
480 | |
481 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
482 | if (!cpu_devs[i]) |
483 | break; | |
484 | ||
485 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
486 | (cpu_devs[i]->c_ident[1] && | |
487 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
488 | this_cpu = cpu_devs[i]; | |
489 | c->x86_vendor = this_cpu->c_x86_vendor; | |
490 | return; | |
1da177e4 LT |
491 | } |
492 | } | |
10a434fc | 493 | |
fe38d855 CE |
494 | if (!printed) { |
495 | printed++; | |
43603c8d | 496 | printk(KERN_ERR "CPU: vendor_id '%s' unknown, using generic init.\n", v); |
fe38d855 CE |
497 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); |
498 | } | |
10a434fc | 499 | |
fe38d855 CE |
500 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
501 | this_cpu = &default_cpu; | |
1da177e4 LT |
502 | } |
503 | ||
9d31d35b | 504 | void __cpuinit cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 505 | { |
1da177e4 | 506 | /* Get vendor name */ |
4a148513 HH |
507 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
508 | (unsigned int *)&c->x86_vendor_id[0], | |
509 | (unsigned int *)&c->x86_vendor_id[8], | |
510 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 511 | |
1da177e4 | 512 | c->x86 = 4; |
9d31d35b | 513 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
514 | if (c->cpuid_level >= 0x00000001) { |
515 | u32 junk, tfms, cap0, misc; | |
516 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
9d31d35b YL |
517 | c->x86 = (tfms >> 8) & 0xf; |
518 | c->x86_model = (tfms >> 4) & 0xf; | |
519 | c->x86_mask = tfms & 0xf; | |
f5f786d0 | 520 | if (c->x86 == 0xf) |
1da177e4 | 521 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 522 | if (c->x86 >= 0x6) |
9d31d35b | 523 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
d4387bd3 | 524 | if (cap0 & (1<<19)) { |
d4387bd3 | 525 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 526 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 527 | } |
1da177e4 | 528 | } |
1da177e4 | 529 | } |
3da99c97 YL |
530 | |
531 | static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) | |
093af8d7 YL |
532 | { |
533 | u32 tfms, xlvl; | |
3da99c97 | 534 | u32 ebx; |
093af8d7 | 535 | |
3da99c97 YL |
536 | /* Intel-defined flags: level 0x00000001 */ |
537 | if (c->cpuid_level >= 0x00000001) { | |
538 | u32 capability, excap; | |
539 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); | |
540 | c->x86_capability[0] = capability; | |
541 | c->x86_capability[4] = excap; | |
542 | } | |
093af8d7 | 543 | |
3da99c97 YL |
544 | /* AMD-defined flags: level 0x80000001 */ |
545 | xlvl = cpuid_eax(0x80000000); | |
546 | c->extended_cpuid_level = xlvl; | |
547 | if ((xlvl & 0xffff0000) == 0x80000000) { | |
548 | if (xlvl >= 0x80000001) { | |
549 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
550 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 551 | } |
093af8d7 | 552 | } |
093af8d7 | 553 | |
5122c890 | 554 | #ifdef CONFIG_X86_64 |
5122c890 YL |
555 | if (c->extended_cpuid_level >= 0x80000008) { |
556 | u32 eax = cpuid_eax(0x80000008); | |
557 | ||
558 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
559 | c->x86_phys_bits = eax & 0xff; | |
093af8d7 | 560 | } |
5122c890 | 561 | #endif |
e3224234 YL |
562 | |
563 | if (c->extended_cpuid_level >= 0x80000007) | |
564 | c->x86_power = cpuid_edx(0x80000007); | |
093af8d7 YL |
565 | |
566 | } | |
1da177e4 | 567 | |
aef93c8b YL |
568 | static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
569 | { | |
570 | #ifdef CONFIG_X86_32 | |
571 | int i; | |
572 | ||
573 | /* | |
574 | * First of all, decide if this is a 486 or higher | |
575 | * It's a 486 if we can modify the AC flag | |
576 | */ | |
577 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
578 | c->x86 = 4; | |
579 | else | |
580 | c->x86 = 3; | |
581 | ||
582 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
583 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
584 | c->x86_vendor_id[0] = 0; | |
585 | cpu_devs[i]->c_identify(c); | |
586 | if (c->x86_vendor_id[0]) { | |
587 | get_cpu_vendor(c); | |
588 | break; | |
589 | } | |
590 | } | |
591 | #endif | |
592 | } | |
593 | ||
34048c9e PC |
594 | /* |
595 | * Do minimum CPU detection early. | |
596 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
597 | * cache alignment. | |
598 | * The others are not touched to avoid unwanted side effects. | |
599 | * | |
600 | * WARNING: this function is only called on the BP. Don't add code here | |
601 | * that is supposed to run on all CPUs. | |
602 | */ | |
3da99c97 | 603 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 604 | { |
6627d242 YL |
605 | #ifdef CONFIG_X86_64 |
606 | c->x86_clflush_size = 64; | |
607 | #else | |
d4387bd3 | 608 | c->x86_clflush_size = 32; |
6627d242 | 609 | #endif |
0a488a53 | 610 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 611 | |
3da99c97 | 612 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 613 | c->extended_cpuid_level = 0; |
d7cd5611 | 614 | |
aef93c8b YL |
615 | if (!have_cpuid_p()) |
616 | identify_cpu_without_cpuid(c); | |
617 | ||
618 | /* cyrix could have cpuid enabled via c_identify()*/ | |
d7cd5611 RR |
619 | if (!have_cpuid_p()) |
620 | return; | |
621 | ||
622 | cpu_detect(c); | |
623 | ||
3da99c97 | 624 | get_cpu_vendor(c); |
2b16a235 | 625 | |
3da99c97 | 626 | get_cpu_cap(c); |
12cf105c | 627 | |
10a434fc YL |
628 | if (this_cpu->c_early_init) |
629 | this_cpu->c_early_init(c); | |
093af8d7 | 630 | |
1c4acdb4 | 631 | #ifdef CONFIG_SMP |
bfcb4c1b | 632 | c->cpu_index = boot_cpu_id; |
1c4acdb4 | 633 | #endif |
b38b0665 | 634 | filter_cpuid_features(c, false); |
d7cd5611 RR |
635 | } |
636 | ||
9d31d35b YL |
637 | void __init early_cpu_init(void) |
638 | { | |
10a434fc YL |
639 | struct cpu_dev **cdev; |
640 | int count = 0; | |
641 | ||
642 | printk("KERNEL supported cpus:\n"); | |
643 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { | |
644 | struct cpu_dev *cpudev = *cdev; | |
645 | unsigned int j; | |
9d31d35b | 646 | |
10a434fc YL |
647 | if (count >= X86_VENDOR_NUM) |
648 | break; | |
649 | cpu_devs[count] = cpudev; | |
650 | count++; | |
651 | ||
652 | for (j = 0; j < 2; j++) { | |
653 | if (!cpudev->c_ident[j]) | |
654 | continue; | |
655 | printk(" %s %s\n", cpudev->c_vendor, | |
656 | cpudev->c_ident[j]); | |
657 | } | |
658 | } | |
9d31d35b | 659 | |
9d31d35b | 660 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 661 | } |
093af8d7 | 662 | |
b6734c35 PA |
663 | /* |
664 | * The NOPL instruction is supposed to exist on all CPUs with | |
ba0593bf | 665 | * family >= 6; unfortunately, that's not true in practice because |
b6734c35 | 666 | * of early VIA chips and (more importantly) broken virtualizers that |
ba0593bf PA |
667 | * are not easy to detect. In the latter case it doesn't even *fail* |
668 | * reliably, so probing for it doesn't even work. Disable it completely | |
669 | * unless we can find a reliable way to detect all the broken cases. | |
b6734c35 PA |
670 | */ |
671 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
672 | { | |
b6734c35 | 673 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
d7cd5611 RR |
674 | } |
675 | ||
34048c9e | 676 | static void __cpuinit generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 677 | { |
aef93c8b | 678 | c->extended_cpuid_level = 0; |
1da177e4 | 679 | |
3da99c97 | 680 | if (!have_cpuid_p()) |
aef93c8b | 681 | identify_cpu_without_cpuid(c); |
1d67953f | 682 | |
aef93c8b | 683 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 684 | if (!have_cpuid_p()) |
aef93c8b | 685 | return; |
1da177e4 | 686 | |
3da99c97 | 687 | cpu_detect(c); |
1da177e4 | 688 | |
3da99c97 | 689 | get_cpu_vendor(c); |
1da177e4 | 690 | |
3da99c97 | 691 | get_cpu_cap(c); |
1da177e4 | 692 | |
3da99c97 YL |
693 | if (c->cpuid_level >= 0x00000001) { |
694 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e YL |
695 | #ifdef CONFIG_X86_32 |
696 | # ifdef CONFIG_X86_HT | |
cb8cc442 | 697 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 698 | # else |
3da99c97 | 699 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
700 | # endif |
701 | #endif | |
1da177e4 | 702 | |
b89d3b3e YL |
703 | #ifdef CONFIG_X86_HT |
704 | c->phys_proc_id = c->initial_apicid; | |
1e9f28fa | 705 | #endif |
3da99c97 | 706 | } |
1da177e4 | 707 | |
1b05d60d | 708 | get_model_name(c); /* Default name */ |
1da177e4 | 709 | |
3da99c97 YL |
710 | init_scattered_cpuid_features(c); |
711 | detect_nopl(c); | |
1da177e4 | 712 | } |
1da177e4 LT |
713 | |
714 | /* | |
715 | * This does the hard work of actually picking apart the CPU stuff... | |
716 | */ | |
9a250347 | 717 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
718 | { |
719 | int i; | |
720 | ||
721 | c->loops_per_jiffy = loops_per_jiffy; | |
722 | c->x86_cache_size = -1; | |
723 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
724 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
725 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
726 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 727 | c->x86_max_cores = 1; |
102bbe3a | 728 | c->x86_coreid_bits = 0; |
11fdd252 | 729 | #ifdef CONFIG_X86_64 |
102bbe3a YL |
730 | c->x86_clflush_size = 64; |
731 | #else | |
732 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 733 | c->x86_clflush_size = 32; |
102bbe3a YL |
734 | #endif |
735 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
736 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
737 | ||
1da177e4 LT |
738 | generic_identify(c); |
739 | ||
3898534d | 740 | if (this_cpu->c_identify) |
1da177e4 LT |
741 | this_cpu->c_identify(c); |
742 | ||
102bbe3a | 743 | #ifdef CONFIG_X86_64 |
cb8cc442 | 744 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
745 | #endif |
746 | ||
1da177e4 LT |
747 | /* |
748 | * Vendor-specific initialization. In this section we | |
749 | * canonicalize the feature flags, meaning if there are | |
750 | * features a certain CPU supports which CPUID doesn't | |
751 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
752 | * we handle them here. | |
753 | * | |
754 | * At the end of this section, c->x86_capability better | |
755 | * indicate the features this CPU genuinely supports! | |
756 | */ | |
757 | if (this_cpu->c_init) | |
758 | this_cpu->c_init(c); | |
759 | ||
760 | /* Disable the PN if appropriate */ | |
761 | squash_the_stupid_serial_number(c); | |
762 | ||
763 | /* | |
764 | * The vendor-specific functions might have changed features. Now | |
765 | * we do "generic changes." | |
766 | */ | |
767 | ||
b38b0665 PA |
768 | /* Filter out anything that depends on CPUID levels we don't have */ |
769 | filter_cpuid_features(c, true); | |
770 | ||
1da177e4 | 771 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 772 | if (!c->x86_model_id[0]) { |
1da177e4 LT |
773 | char *p; |
774 | p = table_lookup_model(c); | |
34048c9e | 775 | if (p) |
1da177e4 LT |
776 | strcpy(c->x86_model_id, p); |
777 | else | |
778 | /* Last resort... */ | |
779 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 780 | c->x86, c->x86_model); |
1da177e4 LT |
781 | } |
782 | ||
102bbe3a YL |
783 | #ifdef CONFIG_X86_64 |
784 | detect_ht(c); | |
785 | #endif | |
786 | ||
88b094fb | 787 | init_hypervisor(c); |
1da177e4 LT |
788 | /* |
789 | * On SMP, boot_cpu_data holds the common feature set between | |
790 | * all CPUs; so make sure that we indicate which features are | |
791 | * common between the CPUs. The first time this routine gets | |
792 | * executed, c == &boot_cpu_data. | |
793 | */ | |
34048c9e | 794 | if (c != &boot_cpu_data) { |
1da177e4 | 795 | /* AND the already accumulated flags with these */ |
9d31d35b | 796 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 LT |
797 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
798 | } | |
799 | ||
7d851c8d AK |
800 | /* Clear all flags overriden by options */ |
801 | for (i = 0; i < NCAPINTS; i++) | |
12c247a6 | 802 | c->x86_capability[i] &= ~cleared_cpu_caps[i]; |
7d851c8d | 803 | |
102bbe3a | 804 | #ifdef CONFIG_X86_MCE |
1da177e4 | 805 | /* Init Machine Check Exception if available. */ |
1da177e4 | 806 | mcheck_init(c); |
102bbe3a | 807 | #endif |
30d432df AK |
808 | |
809 | select_idle_routine(c); | |
102bbe3a YL |
810 | |
811 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) | |
812 | numa_add_cpu(smp_processor_id()); | |
813 | #endif | |
a6c4e076 | 814 | } |
31ab269a | 815 | |
e04d645f GC |
816 | #ifdef CONFIG_X86_64 |
817 | static void vgetcpu_set_mode(void) | |
818 | { | |
819 | if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) | |
820 | vgetcpu_mode = VGETCPU_RDTSCP; | |
821 | else | |
822 | vgetcpu_mode = VGETCPU_LSL; | |
823 | } | |
824 | #endif | |
825 | ||
a6c4e076 JF |
826 | void __init identify_boot_cpu(void) |
827 | { | |
828 | identify_cpu(&boot_cpu_data); | |
102bbe3a | 829 | #ifdef CONFIG_X86_32 |
a6c4e076 | 830 | sysenter_setup(); |
6fe940d6 | 831 | enable_sep_cpu(); |
e04d645f GC |
832 | #else |
833 | vgetcpu_set_mode(); | |
102bbe3a | 834 | #endif |
a6c4e076 | 835 | } |
3b520b23 | 836 | |
a6c4e076 JF |
837 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) |
838 | { | |
839 | BUG_ON(c == &boot_cpu_data); | |
840 | identify_cpu(c); | |
102bbe3a | 841 | #ifdef CONFIG_X86_32 |
a6c4e076 | 842 | enable_sep_cpu(); |
102bbe3a | 843 | #endif |
a6c4e076 | 844 | mtrr_ap_init(); |
1da177e4 LT |
845 | } |
846 | ||
a0854a46 YL |
847 | struct msr_range { |
848 | unsigned min; | |
849 | unsigned max; | |
850 | }; | |
1da177e4 | 851 | |
a0854a46 YL |
852 | static struct msr_range msr_range_array[] __cpuinitdata = { |
853 | { 0x00000000, 0x00000418}, | |
854 | { 0xc0000000, 0xc000040b}, | |
855 | { 0xc0010000, 0xc0010142}, | |
856 | { 0xc0011000, 0xc001103b}, | |
857 | }; | |
1da177e4 | 858 | |
a0854a46 YL |
859 | static void __cpuinit print_cpu_msr(void) |
860 | { | |
861 | unsigned index; | |
862 | u64 val; | |
863 | int i; | |
864 | unsigned index_min, index_max; | |
865 | ||
866 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
867 | index_min = msr_range_array[i].min; | |
868 | index_max = msr_range_array[i].max; | |
869 | for (index = index_min; index < index_max; index++) { | |
870 | if (rdmsrl_amd_safe(index, &val)) | |
871 | continue; | |
872 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1da177e4 | 873 | } |
a0854a46 YL |
874 | } |
875 | } | |
94605eff | 876 | |
a0854a46 YL |
877 | static int show_msr __cpuinitdata; |
878 | static __init int setup_show_msr(char *arg) | |
879 | { | |
880 | int num; | |
3dd9d514 | 881 | |
a0854a46 | 882 | get_option(&arg, &num); |
3dd9d514 | 883 | |
a0854a46 YL |
884 | if (num > 0) |
885 | show_msr = num; | |
886 | return 1; | |
1da177e4 | 887 | } |
a0854a46 | 888 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 889 | |
191679fd AK |
890 | static __init int setup_noclflush(char *arg) |
891 | { | |
892 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
893 | return 1; | |
894 | } | |
895 | __setup("noclflush", setup_noclflush); | |
896 | ||
3bc9b76b | 897 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 LT |
898 | { |
899 | char *vendor = NULL; | |
900 | ||
901 | if (c->x86_vendor < X86_VENDOR_NUM) | |
902 | vendor = this_cpu->c_vendor; | |
903 | else if (c->cpuid_level >= 0) | |
904 | vendor = c->x86_vendor_id; | |
905 | ||
bd32a8cf | 906 | if (vendor && !strstr(c->x86_model_id, vendor)) |
9d31d35b | 907 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 908 | |
9d31d35b YL |
909 | if (c->x86_model_id[0]) |
910 | printk(KERN_CONT "%s", c->x86_model_id); | |
1da177e4 | 911 | else |
9d31d35b | 912 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 913 | |
34048c9e | 914 | if (c->x86_mask || c->cpuid_level >= 0) |
9d31d35b | 915 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); |
1da177e4 | 916 | else |
9d31d35b | 917 | printk(KERN_CONT "\n"); |
a0854a46 YL |
918 | |
919 | #ifdef CONFIG_SMP | |
920 | if (c->cpu_index < show_msr) | |
921 | print_cpu_msr(); | |
922 | #else | |
923 | if (show_msr) | |
924 | print_cpu_msr(); | |
925 | #endif | |
1da177e4 LT |
926 | } |
927 | ||
ac72e788 AK |
928 | static __init int setup_disablecpuid(char *arg) |
929 | { | |
930 | int bit; | |
931 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) | |
932 | setup_clear_cpu_cap(bit); | |
933 | else | |
934 | return 0; | |
935 | return 1; | |
936 | } | |
937 | __setup("clearcpuid=", setup_disablecpuid); | |
938 | ||
d5494d4f | 939 | #ifdef CONFIG_X86_64 |
d5494d4f YL |
940 | struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; |
941 | ||
947e76cd BG |
942 | DEFINE_PER_CPU_FIRST(union irq_stack_union, |
943 | irq_stack_union) __aligned(PAGE_SIZE); | |
26f80bd6 | 944 | DEFINE_PER_CPU(char *, irq_stack_ptr) = |
2add8e23 | 945 | init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; |
d5494d4f | 946 | |
9af45651 BG |
947 | DEFINE_PER_CPU(unsigned long, kernel_stack) = |
948 | (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; | |
949 | EXPORT_PER_CPU_SYMBOL(kernel_stack); | |
d5494d4f | 950 | |
56895530 | 951 | DEFINE_PER_CPU(unsigned int, irq_count) = -1; |
d5494d4f | 952 | |
92d65b23 BG |
953 | static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks |
954 | [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]) | |
955 | __aligned(PAGE_SIZE); | |
d5494d4f YL |
956 | |
957 | extern asmlinkage void ignore_sysret(void); | |
958 | ||
959 | /* May not be marked __init: used by software suspend */ | |
960 | void syscall_init(void) | |
1da177e4 | 961 | { |
d5494d4f YL |
962 | /* |
963 | * LSTAR and STAR live in a bit strange symbiosis. | |
964 | * They both write to the same internal register. STAR allows to | |
965 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
966 | */ | |
967 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
968 | wrmsrl(MSR_LSTAR, system_call); | |
969 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
03ae5768 | 970 | |
d5494d4f YL |
971 | #ifdef CONFIG_IA32_EMULATION |
972 | syscall32_cpu_init(); | |
973 | #endif | |
03ae5768 | 974 | |
d5494d4f YL |
975 | /* Flags to clear on syscall */ |
976 | wrmsrl(MSR_SYSCALL_MASK, | |
977 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); | |
1da177e4 | 978 | } |
62111195 | 979 | |
d5494d4f YL |
980 | unsigned long kernel_eflags; |
981 | ||
982 | /* | |
983 | * Copies of the original ist values from the tss are only accessed during | |
984 | * debugging, no special alignment required. | |
985 | */ | |
986 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
987 | ||
60a5317f | 988 | #else /* x86_64 */ |
d5494d4f | 989 | |
60a5317f TH |
990 | #ifdef CONFIG_CC_STACKPROTECTOR |
991 | DEFINE_PER_CPU(unsigned long, stack_canary); | |
992 | #endif | |
d5494d4f | 993 | |
60a5317f | 994 | /* Make sure %fs and %gs are initialized properly in idle threads */ |
6b2fb3c6 | 995 | struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) |
f95d47ca JF |
996 | { |
997 | memset(regs, 0, sizeof(struct pt_regs)); | |
65ea5b03 | 998 | regs->fs = __KERNEL_PERCPU; |
60a5317f | 999 | regs->gs = __KERNEL_STACK_CANARY; |
f95d47ca JF |
1000 | return regs; |
1001 | } | |
60a5317f | 1002 | #endif /* x86_64 */ |
c5413fbe | 1003 | |
d2cbcc49 RR |
1004 | /* |
1005 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1006 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1007 | * and IDT. We reload them nevertheless, this function acts as a | |
1008 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 1009 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 1010 | */ |
1ba76586 YL |
1011 | #ifdef CONFIG_X86_64 |
1012 | void __cpuinit cpu_init(void) | |
1013 | { | |
1014 | int cpu = stack_smp_processor_id(); | |
1015 | struct tss_struct *t = &per_cpu(init_tss, cpu); | |
1016 | struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu); | |
1017 | unsigned long v; | |
1ba76586 YL |
1018 | struct task_struct *me; |
1019 | int i; | |
1020 | ||
e7a22c1e BG |
1021 | #ifdef CONFIG_NUMA |
1022 | if (cpu != 0 && percpu_read(node_number) == 0 && | |
1023 | cpu_to_node(cpu) != NUMA_NO_NODE) | |
1024 | percpu_write(node_number, cpu_to_node(cpu)); | |
1025 | #endif | |
1ba76586 YL |
1026 | |
1027 | me = current; | |
1028 | ||
c2d1cec1 | 1029 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) |
1ba76586 YL |
1030 | panic("CPU#%d already initialized!\n", cpu); |
1031 | ||
1032 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1033 | ||
1034 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
1035 | ||
1036 | /* | |
1037 | * Initialize the per-CPU GDT with the boot GDT, | |
1038 | * and set up the GDT descriptor: | |
1039 | */ | |
1040 | ||
552be871 | 1041 | switch_to_new_gdt(cpu); |
2697fbd5 BG |
1042 | loadsegment(fs, 0); |
1043 | ||
1ba76586 YL |
1044 | load_idt((const struct desc_ptr *)&idt_descr); |
1045 | ||
1046 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1047 | syscall_init(); | |
1048 | ||
1049 | wrmsrl(MSR_FS_BASE, 0); | |
1050 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1051 | barrier(); | |
1052 | ||
1053 | check_efer(); | |
1054 | if (cpu != 0 && x2apic) | |
1055 | enable_x2apic(); | |
1056 | ||
1057 | /* | |
1058 | * set up and load the per-CPU TSS | |
1059 | */ | |
1060 | if (!orig_ist->ist[0]) { | |
92d65b23 BG |
1061 | static const unsigned int sizes[N_EXCEPTION_STACKS] = { |
1062 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
1063 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
1ba76586 | 1064 | }; |
92d65b23 | 1065 | char *estacks = per_cpu(exception_stacks, cpu); |
1ba76586 | 1066 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
92d65b23 | 1067 | estacks += sizes[v]; |
1ba76586 YL |
1068 | orig_ist->ist[v] = t->x86_tss.ist[v] = |
1069 | (unsigned long)estacks; | |
1070 | } | |
1071 | } | |
1072 | ||
1073 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
1074 | /* | |
1075 | * <= is required because the CPU will access up to | |
1076 | * 8 bits beyond the end of the IO permission bitmap. | |
1077 | */ | |
1078 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1079 | t->io_bitmap[i] = ~0UL; | |
1080 | ||
1081 | atomic_inc(&init_mm.mm_count); | |
1082 | me->active_mm = &init_mm; | |
1083 | if (me->mm) | |
1084 | BUG(); | |
1085 | enter_lazy_tlb(&init_mm, me); | |
1086 | ||
1087 | load_sp0(t, ¤t->thread); | |
1088 | set_tss_desc(cpu, t); | |
1089 | load_TR_desc(); | |
1090 | load_LDT(&init_mm.context); | |
1091 | ||
1092 | #ifdef CONFIG_KGDB | |
1093 | /* | |
1094 | * If the kgdb is connected no debug regs should be altered. This | |
1095 | * is only applicable when KGDB and a KGDB I/O module are built | |
1096 | * into the kernel and you are using early debugging with | |
1097 | * kgdbwait. KGDB will control the kernel HW breakpoint registers. | |
1098 | */ | |
1099 | if (kgdb_connected && arch_kgdb_ops.correct_hw_break) | |
1100 | arch_kgdb_ops.correct_hw_break(); | |
8f6d86dc | 1101 | else |
1ba76586 | 1102 | #endif |
8f6d86dc PZ |
1103 | { |
1104 | /* | |
1105 | * Clear all 6 debug registers: | |
1106 | */ | |
1107 | set_debugreg(0UL, 0); | |
1108 | set_debugreg(0UL, 1); | |
1109 | set_debugreg(0UL, 2); | |
1110 | set_debugreg(0UL, 3); | |
1111 | set_debugreg(0UL, 6); | |
1112 | set_debugreg(0UL, 7); | |
1ba76586 | 1113 | } |
1ba76586 YL |
1114 | |
1115 | fpu_init(); | |
1116 | ||
1117 | raw_local_save_flags(kernel_eflags); | |
1118 | ||
1119 | if (is_uv_system()) | |
1120 | uv_cpu_init(); | |
1121 | } | |
1122 | ||
1123 | #else | |
1124 | ||
d2cbcc49 | 1125 | void __cpuinit cpu_init(void) |
9ee79a3d | 1126 | { |
d2cbcc49 RR |
1127 | int cpu = smp_processor_id(); |
1128 | struct task_struct *curr = current; | |
34048c9e | 1129 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 1130 | struct thread_struct *thread = &curr->thread; |
62111195 | 1131 | |
c2d1cec1 | 1132 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { |
62111195 JF |
1133 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); |
1134 | for (;;) local_irq_enable(); | |
1135 | } | |
1136 | ||
1137 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1138 | ||
1139 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
1140 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 1141 | |
4d37e7e3 | 1142 | load_idt(&idt_descr); |
552be871 | 1143 | switch_to_new_gdt(cpu); |
1da177e4 | 1144 | |
1da177e4 LT |
1145 | /* |
1146 | * Set up and load the per-CPU TSS and LDT | |
1147 | */ | |
1148 | atomic_inc(&init_mm.mm_count); | |
62111195 JF |
1149 | curr->active_mm = &init_mm; |
1150 | if (curr->mm) | |
1151 | BUG(); | |
1152 | enter_lazy_tlb(&init_mm, curr); | |
1da177e4 | 1153 | |
faca6227 | 1154 | load_sp0(t, thread); |
34048c9e | 1155 | set_tss_desc(cpu, t); |
1da177e4 LT |
1156 | load_TR_desc(); |
1157 | load_LDT(&init_mm.context); | |
1158 | ||
22c4e308 | 1159 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1160 | /* Set up doublefault TSS pointer in the GDT */ |
1161 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1162 | #endif |
1da177e4 | 1163 | |
1da177e4 | 1164 | /* Clear all 6 debug registers: */ |
4bb0d3ec ZA |
1165 | set_debugreg(0, 0); |
1166 | set_debugreg(0, 1); | |
1167 | set_debugreg(0, 2); | |
1168 | set_debugreg(0, 3); | |
1169 | set_debugreg(0, 6); | |
1170 | set_debugreg(0, 7); | |
1da177e4 LT |
1171 | |
1172 | /* | |
1173 | * Force FPU initialization: | |
1174 | */ | |
b359e8a4 SS |
1175 | if (cpu_has_xsave) |
1176 | current_thread_info()->status = TS_XSAVE; | |
1177 | else | |
1178 | current_thread_info()->status = 0; | |
1da177e4 LT |
1179 | clear_used_math(); |
1180 | mxcsr_feature_mask_init(); | |
dc1e35c6 SS |
1181 | |
1182 | /* | |
1183 | * Boot processor to setup the FP and extended state context info. | |
1184 | */ | |
b3572e36 | 1185 | if (smp_processor_id() == boot_cpu_id) |
dc1e35c6 SS |
1186 | init_thread_xstate(); |
1187 | ||
1188 | xsave_init(); | |
1da177e4 | 1189 | } |
e1367daf | 1190 | |
1ba76586 YL |
1191 | |
1192 | #endif |