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Commit | Line | Data |
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f0fc4aff | 1 | #include <linux/bootmem.h> |
9766cdbc | 2 | #include <linux/linkage.h> |
f0fc4aff | 3 | #include <linux/bitops.h> |
9766cdbc | 4 | #include <linux/kernel.h> |
f0fc4aff | 5 | #include <linux/module.h> |
9766cdbc JSR |
6 | #include <linux/percpu.h> |
7 | #include <linux/string.h> | |
1da177e4 | 8 | #include <linux/delay.h> |
9766cdbc JSR |
9 | #include <linux/sched.h> |
10 | #include <linux/init.h> | |
11 | #include <linux/kgdb.h> | |
1da177e4 | 12 | #include <linux/smp.h> |
9766cdbc JSR |
13 | #include <linux/io.h> |
14 | ||
15 | #include <asm/stackprotector.h> | |
cdd6c482 | 16 | #include <asm/perf_event.h> |
1da177e4 | 17 | #include <asm/mmu_context.h> |
49d859d7 | 18 | #include <asm/archrandom.h> |
9766cdbc JSR |
19 | #include <asm/hypervisor.h> |
20 | #include <asm/processor.h> | |
f649e938 | 21 | #include <asm/debugreg.h> |
9766cdbc | 22 | #include <asm/sections.h> |
8bdbd962 AC |
23 | #include <linux/topology.h> |
24 | #include <linux/cpumask.h> | |
9766cdbc | 25 | #include <asm/pgtable.h> |
60063497 | 26 | #include <linux/atomic.h> |
9766cdbc JSR |
27 | #include <asm/proto.h> |
28 | #include <asm/setup.h> | |
29 | #include <asm/apic.h> | |
30 | #include <asm/desc.h> | |
31 | #include <asm/i387.h> | |
1361b83a | 32 | #include <asm/fpu-internal.h> |
27b07da7 | 33 | #include <asm/mtrr.h> |
8bdbd962 | 34 | #include <linux/numa.h> |
9766cdbc JSR |
35 | #include <asm/asm.h> |
36 | #include <asm/cpu.h> | |
a03a3e28 | 37 | #include <asm/mce.h> |
9766cdbc | 38 | #include <asm/msr.h> |
8d4a4300 | 39 | #include <asm/pat.h> |
e641f5f5 IM |
40 | |
41 | #ifdef CONFIG_X86_LOCAL_APIC | |
bdbcdd48 | 42 | #include <asm/uv/uv.h> |
1da177e4 LT |
43 | #endif |
44 | ||
45 | #include "cpu.h" | |
46 | ||
c2d1cec1 | 47 | /* all of these masks are initialized in setup_cpu_local_masks() */ |
c2d1cec1 | 48 | cpumask_var_t cpu_initialized_mask; |
9766cdbc JSR |
49 | cpumask_var_t cpu_callout_mask; |
50 | cpumask_var_t cpu_callin_mask; | |
c2d1cec1 MT |
51 | |
52 | /* representing cpus for which sibling maps can be computed */ | |
53 | cpumask_var_t cpu_sibling_setup_mask; | |
54 | ||
2f2f52ba | 55 | /* correctly size the local cpu masks */ |
4369f1fb | 56 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
57 | { |
58 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
59 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
60 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
61 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
62 | } | |
63 | ||
e8055139 OZ |
64 | static void __cpuinit default_init(struct cpuinfo_x86 *c) |
65 | { | |
66 | #ifdef CONFIG_X86_64 | |
27c13ece | 67 | cpu_detect_cache_sizes(c); |
e8055139 OZ |
68 | #else |
69 | /* Not much we can do here... */ | |
70 | /* Check if at least it has cpuid */ | |
71 | if (c->cpuid_level == -1) { | |
72 | /* No cpuid. It must be an ancient CPU */ | |
73 | if (c->x86 == 4) | |
74 | strcpy(c->x86_model_id, "486"); | |
75 | else if (c->x86 == 3) | |
76 | strcpy(c->x86_model_id, "386"); | |
77 | } | |
78 | #endif | |
79 | } | |
80 | ||
81 | static const struct cpu_dev __cpuinitconst default_cpu = { | |
82 | .c_init = default_init, | |
83 | .c_vendor = "Unknown", | |
84 | .c_x86_vendor = X86_VENDOR_UNKNOWN, | |
85 | }; | |
86 | ||
87 | static const struct cpu_dev *this_cpu __cpuinitdata = &default_cpu; | |
0a488a53 | 88 | |
06deef89 | 89 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 90 | #ifdef CONFIG_X86_64 |
06deef89 BG |
91 | /* |
92 | * We need valid kernel segments for data and code in long mode too | |
93 | * IRET will check the segment types kkeil 2000/10/28 | |
94 | * Also sysret mandates a special GDT layout | |
95 | * | |
9766cdbc | 96 | * TLS descriptors are currently at a different place compared to i386. |
06deef89 BG |
97 | * Hopefully nobody expects them at a fixed place (Wine?) |
98 | */ | |
1e5de182 AM |
99 | [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), |
100 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), | |
101 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), | |
102 | [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), | |
103 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), | |
104 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), | |
950ad7ff | 105 | #else |
1e5de182 AM |
106 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), |
107 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
108 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), | |
109 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), | |
bf504672 RR |
110 | /* |
111 | * Segments used for calling PnP BIOS have byte granularity. | |
112 | * They code segments and data segments have fixed 64k limits, | |
113 | * the transfer segment sizes are set at run time. | |
114 | */ | |
6842ef0e | 115 | /* 32-bit code */ |
1e5de182 | 116 | [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
6842ef0e | 117 | /* 16-bit code */ |
1e5de182 | 118 | [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 119 | /* 16-bit data */ |
1e5de182 | 120 | [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), |
6842ef0e | 121 | /* 16-bit data */ |
1e5de182 | 122 | [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), |
6842ef0e | 123 | /* 16-bit data */ |
1e5de182 | 124 | [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), |
bf504672 RR |
125 | /* |
126 | * The APM segments have byte granularity and their bases | |
127 | * are set at run time. All have 64k limits. | |
128 | */ | |
6842ef0e | 129 | /* 32-bit code */ |
1e5de182 | 130 | [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
bf504672 | 131 | /* 16-bit code */ |
1e5de182 | 132 | [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 133 | /* data */ |
72c4d853 | 134 | [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), |
bf504672 | 135 | |
1e5de182 AM |
136 | [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), |
137 | [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
60a5317f | 138 | GDT_STACK_CANARY_INIT |
950ad7ff | 139 | #endif |
06deef89 | 140 | } }; |
7a61d35d | 141 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 142 | |
0c752a93 SS |
143 | static int __init x86_xsave_setup(char *s) |
144 | { | |
145 | setup_clear_cpu_cap(X86_FEATURE_XSAVE); | |
6bad06b7 | 146 | setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); |
c6fd893d SS |
147 | setup_clear_cpu_cap(X86_FEATURE_AVX); |
148 | setup_clear_cpu_cap(X86_FEATURE_AVX2); | |
0c752a93 SS |
149 | return 1; |
150 | } | |
151 | __setup("noxsave", x86_xsave_setup); | |
152 | ||
6bad06b7 SS |
153 | static int __init x86_xsaveopt_setup(char *s) |
154 | { | |
155 | setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); | |
156 | return 1; | |
157 | } | |
158 | __setup("noxsaveopt", x86_xsaveopt_setup); | |
159 | ||
ba51dced | 160 | #ifdef CONFIG_X86_32 |
3bc9b76b | 161 | static int cachesize_override __cpuinitdata = -1; |
3bc9b76b | 162 | static int disable_x86_serial_nr __cpuinitdata = 1; |
1da177e4 | 163 | |
0a488a53 YL |
164 | static int __init cachesize_setup(char *str) |
165 | { | |
166 | get_option(&str, &cachesize_override); | |
167 | return 1; | |
168 | } | |
169 | __setup("cachesize=", cachesize_setup); | |
170 | ||
0a488a53 YL |
171 | static int __init x86_fxsr_setup(char *s) |
172 | { | |
173 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
174 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
175 | return 1; | |
176 | } | |
177 | __setup("nofxsr", x86_fxsr_setup); | |
178 | ||
179 | static int __init x86_sep_setup(char *s) | |
180 | { | |
181 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
182 | return 1; | |
183 | } | |
184 | __setup("nosep", x86_sep_setup); | |
185 | ||
186 | /* Standard macro to see if a specific flag is changeable */ | |
187 | static inline int flag_is_changeable_p(u32 flag) | |
188 | { | |
189 | u32 f1, f2; | |
190 | ||
94f6bac1 KH |
191 | /* |
192 | * Cyrix and IDT cpus allow disabling of CPUID | |
193 | * so the code below may return different results | |
194 | * when it is executed before and after enabling | |
195 | * the CPUID. Add "volatile" to not allow gcc to | |
196 | * optimize the subsequent calls to this function. | |
197 | */ | |
0f3fa48a IM |
198 | asm volatile ("pushfl \n\t" |
199 | "pushfl \n\t" | |
200 | "popl %0 \n\t" | |
201 | "movl %0, %1 \n\t" | |
202 | "xorl %2, %0 \n\t" | |
203 | "pushl %0 \n\t" | |
204 | "popfl \n\t" | |
205 | "pushfl \n\t" | |
206 | "popl %0 \n\t" | |
207 | "popfl \n\t" | |
208 | ||
94f6bac1 KH |
209 | : "=&r" (f1), "=&r" (f2) |
210 | : "ir" (flag)); | |
0a488a53 YL |
211 | |
212 | return ((f1^f2) & flag) != 0; | |
213 | } | |
214 | ||
215 | /* Probe for the CPUID instruction */ | |
216 | static int __cpuinit have_cpuid_p(void) | |
217 | { | |
218 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
219 | } | |
220 | ||
221 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
222 | { | |
0f3fa48a IM |
223 | unsigned long lo, hi; |
224 | ||
225 | if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) | |
226 | return; | |
227 | ||
228 | /* Disable processor serial number: */ | |
229 | ||
230 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
231 | lo |= 0x200000; | |
232 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
233 | ||
234 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
235 | clear_cpu_cap(c, X86_FEATURE_PN); | |
236 | ||
237 | /* Disabling the serial number may affect the cpuid level */ | |
238 | c->cpuid_level = cpuid_eax(0); | |
0a488a53 YL |
239 | } |
240 | ||
241 | static int __init x86_serial_nr_setup(char *s) | |
242 | { | |
243 | disable_x86_serial_nr = 0; | |
244 | return 1; | |
245 | } | |
246 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 247 | #else |
102bbe3a YL |
248 | static inline int flag_is_changeable_p(u32 flag) |
249 | { | |
250 | return 1; | |
251 | } | |
ba51dced YL |
252 | /* Probe for the CPUID instruction */ |
253 | static inline int have_cpuid_p(void) | |
254 | { | |
255 | return 1; | |
256 | } | |
102bbe3a YL |
257 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
258 | { | |
259 | } | |
ba51dced | 260 | #endif |
0a488a53 | 261 | |
82da65da | 262 | static int disable_smep __cpuinitdata; |
de5397ad FY |
263 | static __init int setup_disable_smep(char *arg) |
264 | { | |
265 | disable_smep = 1; | |
266 | return 1; | |
267 | } | |
268 | __setup("nosmep", setup_disable_smep); | |
269 | ||
82da65da | 270 | static __cpuinit void setup_smep(struct cpuinfo_x86 *c) |
de5397ad FY |
271 | { |
272 | if (cpu_has(c, X86_FEATURE_SMEP)) { | |
273 | if (unlikely(disable_smep)) { | |
274 | setup_clear_cpu_cap(X86_FEATURE_SMEP); | |
275 | clear_in_cr4(X86_CR4_SMEP); | |
276 | } else | |
277 | set_in_cr4(X86_CR4_SMEP); | |
278 | } | |
279 | } | |
280 | ||
b38b0665 PA |
281 | /* |
282 | * Some CPU features depend on higher CPUID levels, which may not always | |
283 | * be available due to CPUID level capping or broken virtualization | |
284 | * software. Add those features to this table to auto-disable them. | |
285 | */ | |
286 | struct cpuid_dependent_feature { | |
287 | u32 feature; | |
288 | u32 level; | |
289 | }; | |
0f3fa48a | 290 | |
b38b0665 PA |
291 | static const struct cpuid_dependent_feature __cpuinitconst |
292 | cpuid_dependent_features[] = { | |
293 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
294 | { X86_FEATURE_DCA, 0x00000009 }, | |
295 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
296 | { 0, 0 } | |
297 | }; | |
298 | ||
299 | static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) | |
300 | { | |
301 | const struct cpuid_dependent_feature *df; | |
9766cdbc | 302 | |
b38b0665 | 303 | for (df = cpuid_dependent_features; df->feature; df++) { |
0f3fa48a IM |
304 | |
305 | if (!cpu_has(c, df->feature)) | |
306 | continue; | |
b38b0665 PA |
307 | /* |
308 | * Note: cpuid_level is set to -1 if unavailable, but | |
309 | * extended_extended_level is set to 0 if unavailable | |
310 | * and the legitimate extended levels are all negative | |
311 | * when signed; hence the weird messing around with | |
312 | * signs here... | |
313 | */ | |
0f3fa48a | 314 | if (!((s32)df->level < 0 ? |
f6db44df | 315 | (u32)df->level > (u32)c->extended_cpuid_level : |
0f3fa48a IM |
316 | (s32)df->level > (s32)c->cpuid_level)) |
317 | continue; | |
318 | ||
319 | clear_cpu_cap(c, df->feature); | |
320 | if (!warn) | |
321 | continue; | |
322 | ||
323 | printk(KERN_WARNING | |
324 | "CPU: CPU feature %s disabled, no CPUID level 0x%x\n", | |
325 | x86_cap_flags[df->feature], df->level); | |
b38b0665 | 326 | } |
f6db44df | 327 | } |
b38b0665 | 328 | |
102bbe3a YL |
329 | /* |
330 | * Naming convention should be: <Name> [(<Codename>)] | |
331 | * This table only is used unless init_<vendor>() below doesn't set it; | |
0f3fa48a IM |
332 | * in particular, if CPUID levels 0x80000002..4 are supported, this |
333 | * isn't used | |
102bbe3a YL |
334 | */ |
335 | ||
336 | /* Look up CPU names by table lookup. */ | |
02dde8b4 | 337 | static const char *__cpuinit table_lookup_model(struct cpuinfo_x86 *c) |
102bbe3a | 338 | { |
02dde8b4 | 339 | const struct cpu_model_info *info; |
102bbe3a YL |
340 | |
341 | if (c->x86_model >= 16) | |
342 | return NULL; /* Range check */ | |
343 | ||
344 | if (!this_cpu) | |
345 | return NULL; | |
346 | ||
347 | info = this_cpu->c_models; | |
348 | ||
349 | while (info && info->family) { | |
350 | if (info->family == c->x86) | |
351 | return info->model_names[c->x86_model]; | |
352 | info++; | |
353 | } | |
354 | return NULL; /* Not found */ | |
355 | } | |
356 | ||
3e0c3737 YL |
357 | __u32 cpu_caps_cleared[NCAPINTS] __cpuinitdata; |
358 | __u32 cpu_caps_set[NCAPINTS] __cpuinitdata; | |
7d851c8d | 359 | |
11e3a840 JF |
360 | void load_percpu_segment(int cpu) |
361 | { | |
362 | #ifdef CONFIG_X86_32 | |
363 | loadsegment(fs, __KERNEL_PERCPU); | |
364 | #else | |
365 | loadsegment(gs, 0); | |
366 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); | |
367 | #endif | |
60a5317f | 368 | load_stack_canary_segment(); |
11e3a840 JF |
369 | } |
370 | ||
0f3fa48a IM |
371 | /* |
372 | * Current gdt points %fs at the "master" per-cpu area: after this, | |
373 | * it's on the real one. | |
374 | */ | |
552be871 | 375 | void switch_to_new_gdt(int cpu) |
9d31d35b YL |
376 | { |
377 | struct desc_ptr gdt_descr; | |
378 | ||
2697fbd5 | 379 | gdt_descr.address = (long)get_cpu_gdt_table(cpu); |
9d31d35b YL |
380 | gdt_descr.size = GDT_SIZE - 1; |
381 | load_gdt(&gdt_descr); | |
2697fbd5 | 382 | /* Reload the per-cpu base */ |
11e3a840 JF |
383 | |
384 | load_percpu_segment(cpu); | |
9d31d35b YL |
385 | } |
386 | ||
02dde8b4 | 387 | static const struct cpu_dev *__cpuinitdata cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 388 | |
1b05d60d | 389 | static void __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
390 | { |
391 | unsigned int *v; | |
392 | char *p, *q; | |
393 | ||
3da99c97 | 394 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 395 | return; |
1da177e4 | 396 | |
0f3fa48a | 397 | v = (unsigned int *)c->x86_model_id; |
1da177e4 LT |
398 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); |
399 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
400 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
401 | c->x86_model_id[48] = 0; | |
402 | ||
0f3fa48a IM |
403 | /* |
404 | * Intel chips right-justify this string for some dumb reason; | |
405 | * undo that brain damage: | |
406 | */ | |
1da177e4 | 407 | p = q = &c->x86_model_id[0]; |
34048c9e | 408 | while (*p == ' ') |
9766cdbc | 409 | p++; |
34048c9e | 410 | if (p != q) { |
9766cdbc JSR |
411 | while (*p) |
412 | *q++ = *p++; | |
413 | while (q <= &c->x86_model_id[48]) | |
414 | *q++ = '\0'; /* Zero-pad the rest */ | |
1da177e4 | 415 | } |
1da177e4 LT |
416 | } |
417 | ||
27c13ece | 418 | void __cpuinit cpu_detect_cache_sizes(struct cpuinfo_x86 *c) |
1da177e4 | 419 | { |
9d31d35b | 420 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 421 | |
3da99c97 | 422 | n = c->extended_cpuid_level; |
1da177e4 LT |
423 | |
424 | if (n >= 0x80000005) { | |
9d31d35b | 425 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
9d31d35b | 426 | c->x86_cache_size = (ecx>>24) + (edx>>24); |
140fc727 YL |
427 | #ifdef CONFIG_X86_64 |
428 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
429 | c->x86_tlbsize = 0; | |
430 | #endif | |
1da177e4 LT |
431 | } |
432 | ||
433 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
434 | return; | |
435 | ||
0a488a53 | 436 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 437 | l2size = ecx >> 16; |
34048c9e | 438 | |
140fc727 YL |
439 | #ifdef CONFIG_X86_64 |
440 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
441 | #else | |
1da177e4 LT |
442 | /* do processor-specific cache resizing */ |
443 | if (this_cpu->c_size_cache) | |
34048c9e | 444 | l2size = this_cpu->c_size_cache(c, l2size); |
1da177e4 LT |
445 | |
446 | /* Allow user to override all this if necessary. */ | |
447 | if (cachesize_override != -1) | |
448 | l2size = cachesize_override; | |
449 | ||
34048c9e | 450 | if (l2size == 0) |
1da177e4 | 451 | return; /* Again, no L2 cache is possible */ |
140fc727 | 452 | #endif |
1da177e4 LT |
453 | |
454 | c->x86_cache_size = l2size; | |
1da177e4 LT |
455 | } |
456 | ||
e0ba94f1 AS |
457 | u16 __read_mostly tlb_lli_4k[NR_INFO]; |
458 | u16 __read_mostly tlb_lli_2m[NR_INFO]; | |
459 | u16 __read_mostly tlb_lli_4m[NR_INFO]; | |
460 | u16 __read_mostly tlb_lld_4k[NR_INFO]; | |
461 | u16 __read_mostly tlb_lld_2m[NR_INFO]; | |
462 | u16 __read_mostly tlb_lld_4m[NR_INFO]; | |
463 | ||
c4211f42 AS |
464 | /* |
465 | * tlb_flushall_shift shows the balance point in replacing cr3 write | |
466 | * with multiple 'invlpg'. It will do this replacement when | |
467 | * flush_tlb_lines <= active_lines/2^tlb_flushall_shift. | |
468 | * If tlb_flushall_shift is -1, means the replacement will be disabled. | |
469 | */ | |
470 | s8 __read_mostly tlb_flushall_shift = -1; | |
471 | ||
e0ba94f1 AS |
472 | void __cpuinit cpu_detect_tlb(struct cpuinfo_x86 *c) |
473 | { | |
474 | if (this_cpu->c_detect_tlb) | |
475 | this_cpu->c_detect_tlb(c); | |
476 | ||
477 | printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \ | |
c4211f42 AS |
478 | "Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \ |
479 | "tlb_flushall_shift is 0x%x\n", | |
e0ba94f1 AS |
480 | tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], |
481 | tlb_lli_4m[ENTRIES], tlb_lld_4k[ENTRIES], | |
c4211f42 AS |
482 | tlb_lld_2m[ENTRIES], tlb_lld_4m[ENTRIES], |
483 | tlb_flushall_shift); | |
e0ba94f1 AS |
484 | } |
485 | ||
9d31d35b | 486 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 487 | { |
97e4db7c | 488 | #ifdef CONFIG_X86_HT |
0a488a53 YL |
489 | u32 eax, ebx, ecx, edx; |
490 | int index_msb, core_bits; | |
2eaad1fd | 491 | static bool printed; |
1da177e4 | 492 | |
0a488a53 | 493 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 494 | return; |
1da177e4 | 495 | |
0a488a53 YL |
496 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
497 | goto out; | |
1da177e4 | 498 | |
1cd78776 YL |
499 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
500 | return; | |
1da177e4 | 501 | |
0a488a53 | 502 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 503 | |
9d31d35b YL |
504 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
505 | ||
506 | if (smp_num_siblings == 1) { | |
2eaad1fd | 507 | printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n"); |
0f3fa48a IM |
508 | goto out; |
509 | } | |
9d31d35b | 510 | |
0f3fa48a IM |
511 | if (smp_num_siblings <= 1) |
512 | goto out; | |
9d31d35b | 513 | |
0f3fa48a IM |
514 | index_msb = get_count_order(smp_num_siblings); |
515 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); | |
9d31d35b | 516 | |
0f3fa48a | 517 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
9d31d35b | 518 | |
0f3fa48a | 519 | index_msb = get_count_order(smp_num_siblings); |
9d31d35b | 520 | |
0f3fa48a | 521 | core_bits = get_count_order(c->x86_max_cores); |
9d31d35b | 522 | |
0f3fa48a IM |
523 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & |
524 | ((1 << core_bits) - 1); | |
1da177e4 | 525 | |
0a488a53 | 526 | out: |
2eaad1fd | 527 | if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { |
0a488a53 YL |
528 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", |
529 | c->phys_proc_id); | |
530 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
531 | c->cpu_core_id); | |
2eaad1fd | 532 | printed = 1; |
9d31d35b | 533 | } |
9d31d35b | 534 | #endif |
97e4db7c | 535 | } |
1da177e4 | 536 | |
3da99c97 | 537 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
538 | { |
539 | char *v = c->x86_vendor_id; | |
0f3fa48a | 540 | int i; |
1da177e4 LT |
541 | |
542 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
543 | if (!cpu_devs[i]) |
544 | break; | |
545 | ||
546 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
547 | (cpu_devs[i]->c_ident[1] && | |
548 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
0f3fa48a | 549 | |
10a434fc YL |
550 | this_cpu = cpu_devs[i]; |
551 | c->x86_vendor = this_cpu->c_x86_vendor; | |
552 | return; | |
1da177e4 LT |
553 | } |
554 | } | |
10a434fc | 555 | |
a9c56953 MK |
556 | printk_once(KERN_ERR |
557 | "CPU: vendor_id '%s' unknown, using generic init.\n" \ | |
558 | "CPU: Your system may be unstable.\n", v); | |
10a434fc | 559 | |
fe38d855 CE |
560 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
561 | this_cpu = &default_cpu; | |
1da177e4 LT |
562 | } |
563 | ||
9d31d35b | 564 | void __cpuinit cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 565 | { |
1da177e4 | 566 | /* Get vendor name */ |
4a148513 HH |
567 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
568 | (unsigned int *)&c->x86_vendor_id[0], | |
569 | (unsigned int *)&c->x86_vendor_id[8], | |
570 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 571 | |
1da177e4 | 572 | c->x86 = 4; |
9d31d35b | 573 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
574 | if (c->cpuid_level >= 0x00000001) { |
575 | u32 junk, tfms, cap0, misc; | |
0f3fa48a | 576 | |
1da177e4 | 577 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
9d31d35b YL |
578 | c->x86 = (tfms >> 8) & 0xf; |
579 | c->x86_model = (tfms >> 4) & 0xf; | |
580 | c->x86_mask = tfms & 0xf; | |
0f3fa48a | 581 | |
f5f786d0 | 582 | if (c->x86 == 0xf) |
1da177e4 | 583 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 584 | if (c->x86 >= 0x6) |
9d31d35b | 585 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
0f3fa48a | 586 | |
d4387bd3 | 587 | if (cap0 & (1<<19)) { |
d4387bd3 | 588 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 589 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 590 | } |
1da177e4 | 591 | } |
1da177e4 | 592 | } |
3da99c97 | 593 | |
d900329e | 594 | void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) |
093af8d7 YL |
595 | { |
596 | u32 tfms, xlvl; | |
3da99c97 | 597 | u32 ebx; |
093af8d7 | 598 | |
3da99c97 YL |
599 | /* Intel-defined flags: level 0x00000001 */ |
600 | if (c->cpuid_level >= 0x00000001) { | |
601 | u32 capability, excap; | |
0f3fa48a | 602 | |
3da99c97 YL |
603 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); |
604 | c->x86_capability[0] = capability; | |
605 | c->x86_capability[4] = excap; | |
606 | } | |
093af8d7 | 607 | |
bdc802dc PA |
608 | /* Additional Intel-defined flags: level 0x00000007 */ |
609 | if (c->cpuid_level >= 0x00000007) { | |
610 | u32 eax, ebx, ecx, edx; | |
611 | ||
612 | cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); | |
613 | ||
2494b030 | 614 | c->x86_capability[9] = ebx; |
bdc802dc PA |
615 | } |
616 | ||
3da99c97 YL |
617 | /* AMD-defined flags: level 0x80000001 */ |
618 | xlvl = cpuid_eax(0x80000000); | |
619 | c->extended_cpuid_level = xlvl; | |
0f3fa48a | 620 | |
3da99c97 YL |
621 | if ((xlvl & 0xffff0000) == 0x80000000) { |
622 | if (xlvl >= 0x80000001) { | |
623 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
624 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 625 | } |
093af8d7 | 626 | } |
093af8d7 | 627 | |
5122c890 YL |
628 | if (c->extended_cpuid_level >= 0x80000008) { |
629 | u32 eax = cpuid_eax(0x80000008); | |
630 | ||
631 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
632 | c->x86_phys_bits = eax & 0xff; | |
093af8d7 | 633 | } |
13c6c532 JB |
634 | #ifdef CONFIG_X86_32 |
635 | else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) | |
636 | c->x86_phys_bits = 36; | |
5122c890 | 637 | #endif |
e3224234 YL |
638 | |
639 | if (c->extended_cpuid_level >= 0x80000007) | |
640 | c->x86_power = cpuid_edx(0x80000007); | |
093af8d7 | 641 | |
1dedefd1 | 642 | init_scattered_cpuid_features(c); |
093af8d7 | 643 | } |
1da177e4 | 644 | |
aef93c8b YL |
645 | static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
646 | { | |
647 | #ifdef CONFIG_X86_32 | |
648 | int i; | |
649 | ||
650 | /* | |
651 | * First of all, decide if this is a 486 or higher | |
652 | * It's a 486 if we can modify the AC flag | |
653 | */ | |
654 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
655 | c->x86 = 4; | |
656 | else | |
657 | c->x86 = 3; | |
658 | ||
659 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
660 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
661 | c->x86_vendor_id[0] = 0; | |
662 | cpu_devs[i]->c_identify(c); | |
663 | if (c->x86_vendor_id[0]) { | |
664 | get_cpu_vendor(c); | |
665 | break; | |
666 | } | |
667 | } | |
668 | #endif | |
669 | } | |
670 | ||
34048c9e PC |
671 | /* |
672 | * Do minimum CPU detection early. | |
673 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
674 | * cache alignment. | |
675 | * The others are not touched to avoid unwanted side effects. | |
676 | * | |
677 | * WARNING: this function is only called on the BP. Don't add code here | |
678 | * that is supposed to run on all CPUs. | |
679 | */ | |
3da99c97 | 680 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 681 | { |
6627d242 YL |
682 | #ifdef CONFIG_X86_64 |
683 | c->x86_clflush_size = 64; | |
13c6c532 JB |
684 | c->x86_phys_bits = 36; |
685 | c->x86_virt_bits = 48; | |
6627d242 | 686 | #else |
d4387bd3 | 687 | c->x86_clflush_size = 32; |
13c6c532 JB |
688 | c->x86_phys_bits = 32; |
689 | c->x86_virt_bits = 32; | |
6627d242 | 690 | #endif |
0a488a53 | 691 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 692 | |
3da99c97 | 693 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 694 | c->extended_cpuid_level = 0; |
d7cd5611 | 695 | |
aef93c8b YL |
696 | if (!have_cpuid_p()) |
697 | identify_cpu_without_cpuid(c); | |
698 | ||
699 | /* cyrix could have cpuid enabled via c_identify()*/ | |
d7cd5611 RR |
700 | if (!have_cpuid_p()) |
701 | return; | |
702 | ||
703 | cpu_detect(c); | |
704 | ||
3da99c97 | 705 | get_cpu_vendor(c); |
2b16a235 | 706 | |
3da99c97 | 707 | get_cpu_cap(c); |
12cf105c | 708 | |
10a434fc YL |
709 | if (this_cpu->c_early_init) |
710 | this_cpu->c_early_init(c); | |
093af8d7 | 711 | |
f6e9456c | 712 | c->cpu_index = 0; |
b38b0665 | 713 | filter_cpuid_features(c, false); |
de5397ad FY |
714 | |
715 | setup_smep(c); | |
a110b5ec BP |
716 | |
717 | if (this_cpu->c_bsp_init) | |
718 | this_cpu->c_bsp_init(c); | |
d7cd5611 RR |
719 | } |
720 | ||
9d31d35b YL |
721 | void __init early_cpu_init(void) |
722 | { | |
02dde8b4 | 723 | const struct cpu_dev *const *cdev; |
10a434fc YL |
724 | int count = 0; |
725 | ||
ac23f253 | 726 | #ifdef CONFIG_PROCESSOR_SELECT |
9766cdbc | 727 | printk(KERN_INFO "KERNEL supported cpus:\n"); |
31c997ca IM |
728 | #endif |
729 | ||
10a434fc | 730 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { |
02dde8b4 | 731 | const struct cpu_dev *cpudev = *cdev; |
9d31d35b | 732 | |
10a434fc YL |
733 | if (count >= X86_VENDOR_NUM) |
734 | break; | |
735 | cpu_devs[count] = cpudev; | |
736 | count++; | |
737 | ||
ac23f253 | 738 | #ifdef CONFIG_PROCESSOR_SELECT |
31c997ca IM |
739 | { |
740 | unsigned int j; | |
741 | ||
742 | for (j = 0; j < 2; j++) { | |
743 | if (!cpudev->c_ident[j]) | |
744 | continue; | |
745 | printk(KERN_INFO " %s %s\n", cpudev->c_vendor, | |
746 | cpudev->c_ident[j]); | |
747 | } | |
10a434fc | 748 | } |
0388423d | 749 | #endif |
10a434fc | 750 | } |
9d31d35b | 751 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 752 | } |
093af8d7 | 753 | |
b6734c35 | 754 | /* |
366d4a43 BP |
755 | * The NOPL instruction is supposed to exist on all CPUs of family >= 6; |
756 | * unfortunately, that's not true in practice because of early VIA | |
757 | * chips and (more importantly) broken virtualizers that are not easy | |
758 | * to detect. In the latter case it doesn't even *fail* reliably, so | |
759 | * probing for it doesn't even work. Disable it completely on 32-bit | |
ba0593bf | 760 | * unless we can find a reliable way to detect all the broken cases. |
366d4a43 | 761 | * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). |
b6734c35 PA |
762 | */ |
763 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
764 | { | |
366d4a43 | 765 | #ifdef CONFIG_X86_32 |
b6734c35 | 766 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
366d4a43 BP |
767 | #else |
768 | set_cpu_cap(c, X86_FEATURE_NOPL); | |
769 | #endif | |
d7cd5611 RR |
770 | } |
771 | ||
34048c9e | 772 | static void __cpuinit generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 773 | { |
aef93c8b | 774 | c->extended_cpuid_level = 0; |
1da177e4 | 775 | |
3da99c97 | 776 | if (!have_cpuid_p()) |
aef93c8b | 777 | identify_cpu_without_cpuid(c); |
1d67953f | 778 | |
aef93c8b | 779 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 780 | if (!have_cpuid_p()) |
aef93c8b | 781 | return; |
1da177e4 | 782 | |
3da99c97 | 783 | cpu_detect(c); |
1da177e4 | 784 | |
3da99c97 | 785 | get_cpu_vendor(c); |
1da177e4 | 786 | |
3da99c97 | 787 | get_cpu_cap(c); |
1da177e4 | 788 | |
3da99c97 YL |
789 | if (c->cpuid_level >= 0x00000001) { |
790 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e YL |
791 | #ifdef CONFIG_X86_32 |
792 | # ifdef CONFIG_X86_HT | |
cb8cc442 | 793 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 794 | # else |
3da99c97 | 795 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
796 | # endif |
797 | #endif | |
b89d3b3e | 798 | c->phys_proc_id = c->initial_apicid; |
3da99c97 | 799 | } |
1da177e4 | 800 | |
de5397ad FY |
801 | setup_smep(c); |
802 | ||
1b05d60d | 803 | get_model_name(c); /* Default name */ |
1da177e4 | 804 | |
3da99c97 | 805 | detect_nopl(c); |
1da177e4 | 806 | } |
1da177e4 LT |
807 | |
808 | /* | |
809 | * This does the hard work of actually picking apart the CPU stuff... | |
810 | */ | |
9a250347 | 811 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
812 | { |
813 | int i; | |
814 | ||
815 | c->loops_per_jiffy = loops_per_jiffy; | |
816 | c->x86_cache_size = -1; | |
817 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
818 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
819 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
820 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 821 | c->x86_max_cores = 1; |
102bbe3a | 822 | c->x86_coreid_bits = 0; |
11fdd252 | 823 | #ifdef CONFIG_X86_64 |
102bbe3a | 824 | c->x86_clflush_size = 64; |
13c6c532 JB |
825 | c->x86_phys_bits = 36; |
826 | c->x86_virt_bits = 48; | |
102bbe3a YL |
827 | #else |
828 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 829 | c->x86_clflush_size = 32; |
13c6c532 JB |
830 | c->x86_phys_bits = 32; |
831 | c->x86_virt_bits = 32; | |
102bbe3a YL |
832 | #endif |
833 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
834 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
835 | ||
1da177e4 LT |
836 | generic_identify(c); |
837 | ||
3898534d | 838 | if (this_cpu->c_identify) |
1da177e4 LT |
839 | this_cpu->c_identify(c); |
840 | ||
2759c328 YL |
841 | /* Clear/Set all flags overriden by options, after probe */ |
842 | for (i = 0; i < NCAPINTS; i++) { | |
843 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
844 | c->x86_capability[i] |= cpu_caps_set[i]; | |
845 | } | |
846 | ||
102bbe3a | 847 | #ifdef CONFIG_X86_64 |
cb8cc442 | 848 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
849 | #endif |
850 | ||
1da177e4 LT |
851 | /* |
852 | * Vendor-specific initialization. In this section we | |
853 | * canonicalize the feature flags, meaning if there are | |
854 | * features a certain CPU supports which CPUID doesn't | |
855 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
856 | * we handle them here. | |
857 | * | |
858 | * At the end of this section, c->x86_capability better | |
859 | * indicate the features this CPU genuinely supports! | |
860 | */ | |
861 | if (this_cpu->c_init) | |
862 | this_cpu->c_init(c); | |
863 | ||
864 | /* Disable the PN if appropriate */ | |
865 | squash_the_stupid_serial_number(c); | |
866 | ||
867 | /* | |
0f3fa48a IM |
868 | * The vendor-specific functions might have changed features. |
869 | * Now we do "generic changes." | |
1da177e4 LT |
870 | */ |
871 | ||
b38b0665 PA |
872 | /* Filter out anything that depends on CPUID levels we don't have */ |
873 | filter_cpuid_features(c, true); | |
874 | ||
1da177e4 | 875 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 876 | if (!c->x86_model_id[0]) { |
02dde8b4 | 877 | const char *p; |
1da177e4 | 878 | p = table_lookup_model(c); |
34048c9e | 879 | if (p) |
1da177e4 LT |
880 | strcpy(c->x86_model_id, p); |
881 | else | |
882 | /* Last resort... */ | |
883 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 884 | c->x86, c->x86_model); |
1da177e4 LT |
885 | } |
886 | ||
102bbe3a YL |
887 | #ifdef CONFIG_X86_64 |
888 | detect_ht(c); | |
889 | #endif | |
890 | ||
88b094fb | 891 | init_hypervisor(c); |
49d859d7 | 892 | x86_init_rdrand(c); |
3e0c3737 YL |
893 | |
894 | /* | |
895 | * Clear/Set all flags overriden by options, need do it | |
896 | * before following smp all cpus cap AND. | |
897 | */ | |
898 | for (i = 0; i < NCAPINTS; i++) { | |
899 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
900 | c->x86_capability[i] |= cpu_caps_set[i]; | |
901 | } | |
902 | ||
1da177e4 LT |
903 | /* |
904 | * On SMP, boot_cpu_data holds the common feature set between | |
905 | * all CPUs; so make sure that we indicate which features are | |
906 | * common between the CPUs. The first time this routine gets | |
907 | * executed, c == &boot_cpu_data. | |
908 | */ | |
34048c9e | 909 | if (c != &boot_cpu_data) { |
1da177e4 | 910 | /* AND the already accumulated flags with these */ |
9d31d35b | 911 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 LT |
912 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
913 | } | |
914 | ||
915 | /* Init Machine Check Exception if available. */ | |
5e09954a | 916 | mcheck_cpu_init(c); |
30d432df AK |
917 | |
918 | select_idle_routine(c); | |
102bbe3a | 919 | |
de2d9445 | 920 | #ifdef CONFIG_NUMA |
102bbe3a YL |
921 | numa_add_cpu(smp_processor_id()); |
922 | #endif | |
a6c4e076 | 923 | } |
31ab269a | 924 | |
e04d645f GC |
925 | #ifdef CONFIG_X86_64 |
926 | static void vgetcpu_set_mode(void) | |
927 | { | |
928 | if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) | |
929 | vgetcpu_mode = VGETCPU_RDTSCP; | |
930 | else | |
931 | vgetcpu_mode = VGETCPU_LSL; | |
932 | } | |
933 | #endif | |
934 | ||
a6c4e076 JF |
935 | void __init identify_boot_cpu(void) |
936 | { | |
937 | identify_cpu(&boot_cpu_data); | |
02c68a02 | 938 | init_amd_e400_c1e_mask(); |
102bbe3a | 939 | #ifdef CONFIG_X86_32 |
a6c4e076 | 940 | sysenter_setup(); |
6fe940d6 | 941 | enable_sep_cpu(); |
e04d645f GC |
942 | #else |
943 | vgetcpu_set_mode(); | |
102bbe3a | 944 | #endif |
e0ba94f1 AS |
945 | if (boot_cpu_data.cpuid_level >= 2) |
946 | cpu_detect_tlb(&boot_cpu_data); | |
a6c4e076 | 947 | } |
3b520b23 | 948 | |
a6c4e076 JF |
949 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) |
950 | { | |
951 | BUG_ON(c == &boot_cpu_data); | |
952 | identify_cpu(c); | |
102bbe3a | 953 | #ifdef CONFIG_X86_32 |
a6c4e076 | 954 | enable_sep_cpu(); |
102bbe3a | 955 | #endif |
a6c4e076 | 956 | mtrr_ap_init(); |
1da177e4 LT |
957 | } |
958 | ||
a0854a46 | 959 | struct msr_range { |
0f3fa48a IM |
960 | unsigned min; |
961 | unsigned max; | |
a0854a46 | 962 | }; |
1da177e4 | 963 | |
02dde8b4 | 964 | static const struct msr_range msr_range_array[] __cpuinitconst = { |
a0854a46 YL |
965 | { 0x00000000, 0x00000418}, |
966 | { 0xc0000000, 0xc000040b}, | |
967 | { 0xc0010000, 0xc0010142}, | |
968 | { 0xc0011000, 0xc001103b}, | |
969 | }; | |
1da177e4 | 970 | |
21c3fcf3 | 971 | static void __cpuinit __print_cpu_msr(void) |
a0854a46 | 972 | { |
0f3fa48a | 973 | unsigned index_min, index_max; |
a0854a46 YL |
974 | unsigned index; |
975 | u64 val; | |
976 | int i; | |
a0854a46 YL |
977 | |
978 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
979 | index_min = msr_range_array[i].min; | |
980 | index_max = msr_range_array[i].max; | |
0f3fa48a | 981 | |
a0854a46 | 982 | for (index = index_min; index < index_max; index++) { |
ecd431d9 | 983 | if (rdmsrl_safe(index, &val)) |
a0854a46 YL |
984 | continue; |
985 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1da177e4 | 986 | } |
a0854a46 YL |
987 | } |
988 | } | |
94605eff | 989 | |
a0854a46 | 990 | static int show_msr __cpuinitdata; |
0f3fa48a | 991 | |
a0854a46 YL |
992 | static __init int setup_show_msr(char *arg) |
993 | { | |
994 | int num; | |
3dd9d514 | 995 | |
a0854a46 | 996 | get_option(&arg, &num); |
3dd9d514 | 997 | |
a0854a46 YL |
998 | if (num > 0) |
999 | show_msr = num; | |
1000 | return 1; | |
1da177e4 | 1001 | } |
a0854a46 | 1002 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 1003 | |
191679fd AK |
1004 | static __init int setup_noclflush(char *arg) |
1005 | { | |
1006 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
1007 | return 1; | |
1008 | } | |
1009 | __setup("noclflush", setup_noclflush); | |
1010 | ||
3bc9b76b | 1011 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 | 1012 | { |
02dde8b4 | 1013 | const char *vendor = NULL; |
1da177e4 | 1014 | |
0f3fa48a | 1015 | if (c->x86_vendor < X86_VENDOR_NUM) { |
1da177e4 | 1016 | vendor = this_cpu->c_vendor; |
0f3fa48a IM |
1017 | } else { |
1018 | if (c->cpuid_level >= 0) | |
1019 | vendor = c->x86_vendor_id; | |
1020 | } | |
1da177e4 | 1021 | |
bd32a8cf | 1022 | if (vendor && !strstr(c->x86_model_id, vendor)) |
9d31d35b | 1023 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 1024 | |
9d31d35b YL |
1025 | if (c->x86_model_id[0]) |
1026 | printk(KERN_CONT "%s", c->x86_model_id); | |
1da177e4 | 1027 | else |
9d31d35b | 1028 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 1029 | |
34048c9e | 1030 | if (c->x86_mask || c->cpuid_level >= 0) |
9d31d35b | 1031 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); |
1da177e4 | 1032 | else |
9d31d35b | 1033 | printk(KERN_CONT "\n"); |
a0854a46 | 1034 | |
0b8b8078 | 1035 | print_cpu_msr(c); |
21c3fcf3 YL |
1036 | } |
1037 | ||
1038 | void __cpuinit print_cpu_msr(struct cpuinfo_x86 *c) | |
1039 | { | |
a0854a46 | 1040 | if (c->cpu_index < show_msr) |
21c3fcf3 | 1041 | __print_cpu_msr(); |
1da177e4 LT |
1042 | } |
1043 | ||
ac72e788 AK |
1044 | static __init int setup_disablecpuid(char *arg) |
1045 | { | |
1046 | int bit; | |
0f3fa48a | 1047 | |
ac72e788 AK |
1048 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) |
1049 | setup_clear_cpu_cap(bit); | |
1050 | else | |
1051 | return 0; | |
0f3fa48a | 1052 | |
ac72e788 AK |
1053 | return 1; |
1054 | } | |
1055 | __setup("clearcpuid=", setup_disablecpuid); | |
1056 | ||
d5494d4f | 1057 | #ifdef CONFIG_X86_64 |
9ff80942 | 1058 | struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table }; |
228bdaa9 SR |
1059 | struct desc_ptr nmi_idt_descr = { NR_VECTORS * 16 - 1, |
1060 | (unsigned long) nmi_idt_table }; | |
d5494d4f | 1061 | |
947e76cd BG |
1062 | DEFINE_PER_CPU_FIRST(union irq_stack_union, |
1063 | irq_stack_union) __aligned(PAGE_SIZE); | |
0f3fa48a | 1064 | |
bdf977b3 TH |
1065 | /* |
1066 | * The following four percpu variables are hot. Align current_task to | |
1067 | * cacheline size such that all four fall in the same cacheline. | |
1068 | */ | |
1069 | DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = | |
1070 | &init_task; | |
1071 | EXPORT_PER_CPU_SYMBOL(current_task); | |
d5494d4f | 1072 | |
9af45651 BG |
1073 | DEFINE_PER_CPU(unsigned long, kernel_stack) = |
1074 | (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; | |
1075 | EXPORT_PER_CPU_SYMBOL(kernel_stack); | |
1076 | ||
bdf977b3 TH |
1077 | DEFINE_PER_CPU(char *, irq_stack_ptr) = |
1078 | init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; | |
1079 | ||
56895530 | 1080 | DEFINE_PER_CPU(unsigned int, irq_count) = -1; |
d5494d4f | 1081 | |
7e16838d LT |
1082 | DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); |
1083 | ||
0f3fa48a IM |
1084 | /* |
1085 | * Special IST stacks which the CPU switches to when it calls | |
1086 | * an IST-marked descriptor entry. Up to 7 stacks (hardware | |
1087 | * limit), all of them are 4K, except the debug stack which | |
1088 | * is 8K. | |
1089 | */ | |
1090 | static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { | |
1091 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
1092 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
1093 | }; | |
1094 | ||
92d65b23 | 1095 | static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks |
3e352aa8 | 1096 | [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); |
d5494d4f | 1097 | |
d5494d4f YL |
1098 | /* May not be marked __init: used by software suspend */ |
1099 | void syscall_init(void) | |
1da177e4 | 1100 | { |
d5494d4f YL |
1101 | /* |
1102 | * LSTAR and STAR live in a bit strange symbiosis. | |
1103 | * They both write to the same internal register. STAR allows to | |
1104 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
1105 | */ | |
1106 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
1107 | wrmsrl(MSR_LSTAR, system_call); | |
1108 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
03ae5768 | 1109 | |
d5494d4f YL |
1110 | #ifdef CONFIG_IA32_EMULATION |
1111 | syscall32_cpu_init(); | |
1112 | #endif | |
03ae5768 | 1113 | |
d5494d4f YL |
1114 | /* Flags to clear on syscall */ |
1115 | wrmsrl(MSR_SYSCALL_MASK, | |
1116 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); | |
1da177e4 | 1117 | } |
62111195 | 1118 | |
d5494d4f YL |
1119 | unsigned long kernel_eflags; |
1120 | ||
1121 | /* | |
1122 | * Copies of the original ist values from the tss are only accessed during | |
1123 | * debugging, no special alignment required. | |
1124 | */ | |
1125 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
1126 | ||
228bdaa9 | 1127 | static DEFINE_PER_CPU(unsigned long, debug_stack_addr); |
42181186 | 1128 | DEFINE_PER_CPU(int, debug_stack_usage); |
228bdaa9 SR |
1129 | |
1130 | int is_debug_stack(unsigned long addr) | |
1131 | { | |
42181186 SR |
1132 | return __get_cpu_var(debug_stack_usage) || |
1133 | (addr <= __get_cpu_var(debug_stack_addr) && | |
1134 | addr > (__get_cpu_var(debug_stack_addr) - DEBUG_STKSZ)); | |
228bdaa9 SR |
1135 | } |
1136 | ||
f8988175 SR |
1137 | static DEFINE_PER_CPU(u32, debug_stack_use_ctr); |
1138 | ||
228bdaa9 SR |
1139 | void debug_stack_set_zero(void) |
1140 | { | |
f8988175 | 1141 | this_cpu_inc(debug_stack_use_ctr); |
228bdaa9 SR |
1142 | load_idt((const struct desc_ptr *)&nmi_idt_descr); |
1143 | } | |
1144 | ||
1145 | void debug_stack_reset(void) | |
1146 | { | |
f8988175 SR |
1147 | if (WARN_ON(!this_cpu_read(debug_stack_use_ctr))) |
1148 | return; | |
1149 | if (this_cpu_dec_return(debug_stack_use_ctr) == 0) | |
1150 | load_idt((const struct desc_ptr *)&idt_descr); | |
228bdaa9 SR |
1151 | } |
1152 | ||
0f3fa48a | 1153 | #else /* CONFIG_X86_64 */ |
d5494d4f | 1154 | |
bdf977b3 TH |
1155 | DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; |
1156 | EXPORT_PER_CPU_SYMBOL(current_task); | |
27e74da9 | 1157 | DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); |
bdf977b3 | 1158 | |
60a5317f | 1159 | #ifdef CONFIG_CC_STACKPROTECTOR |
53f82452 | 1160 | DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); |
60a5317f | 1161 | #endif |
d5494d4f | 1162 | |
60a5317f | 1163 | /* Make sure %fs and %gs are initialized properly in idle threads */ |
6b2fb3c6 | 1164 | struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) |
f95d47ca JF |
1165 | { |
1166 | memset(regs, 0, sizeof(struct pt_regs)); | |
65ea5b03 | 1167 | regs->fs = __KERNEL_PERCPU; |
60a5317f | 1168 | regs->gs = __KERNEL_STACK_CANARY; |
0f3fa48a | 1169 | |
f95d47ca JF |
1170 | return regs; |
1171 | } | |
0f3fa48a | 1172 | #endif /* CONFIG_X86_64 */ |
c5413fbe | 1173 | |
9766cdbc JSR |
1174 | /* |
1175 | * Clear all 6 debug registers: | |
1176 | */ | |
1177 | static void clear_all_debug_regs(void) | |
1178 | { | |
1179 | int i; | |
1180 | ||
1181 | for (i = 0; i < 8; i++) { | |
1182 | /* Ignore db4, db5 */ | |
1183 | if ((i == 4) || (i == 5)) | |
1184 | continue; | |
1185 | ||
1186 | set_debugreg(0, i); | |
1187 | } | |
1188 | } | |
c5413fbe | 1189 | |
0bb9fef9 JW |
1190 | #ifdef CONFIG_KGDB |
1191 | /* | |
1192 | * Restore debug regs if using kgdbwait and you have a kernel debugger | |
1193 | * connection established. | |
1194 | */ | |
1195 | static void dbg_restore_debug_regs(void) | |
1196 | { | |
1197 | if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) | |
1198 | arch_kgdb_ops.correct_hw_break(); | |
1199 | } | |
1200 | #else /* ! CONFIG_KGDB */ | |
1201 | #define dbg_restore_debug_regs() | |
1202 | #endif /* ! CONFIG_KGDB */ | |
1203 | ||
d2cbcc49 RR |
1204 | /* |
1205 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1206 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1207 | * and IDT. We reload them nevertheless, this function acts as a | |
1208 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 1209 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 1210 | */ |
1ba76586 | 1211 | #ifdef CONFIG_X86_64 |
0f3fa48a | 1212 | |
1ba76586 YL |
1213 | void __cpuinit cpu_init(void) |
1214 | { | |
0fe1e009 | 1215 | struct orig_ist *oist; |
1ba76586 | 1216 | struct task_struct *me; |
0f3fa48a IM |
1217 | struct tss_struct *t; |
1218 | unsigned long v; | |
1219 | int cpu; | |
1ba76586 YL |
1220 | int i; |
1221 | ||
0f3fa48a IM |
1222 | cpu = stack_smp_processor_id(); |
1223 | t = &per_cpu(init_tss, cpu); | |
0fe1e009 | 1224 | oist = &per_cpu(orig_ist, cpu); |
0f3fa48a | 1225 | |
e7a22c1e | 1226 | #ifdef CONFIG_NUMA |
c6ae41e7 | 1227 | if (cpu != 0 && this_cpu_read(numa_node) == 0 && |
e534c7c5 LS |
1228 | early_cpu_to_node(cpu) != NUMA_NO_NODE) |
1229 | set_numa_node(early_cpu_to_node(cpu)); | |
e7a22c1e | 1230 | #endif |
1ba76586 YL |
1231 | |
1232 | me = current; | |
1233 | ||
c2d1cec1 | 1234 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) |
1ba76586 YL |
1235 | panic("CPU#%d already initialized!\n", cpu); |
1236 | ||
2eaad1fd | 1237 | pr_debug("Initializing CPU#%d\n", cpu); |
1ba76586 YL |
1238 | |
1239 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
1240 | ||
1241 | /* | |
1242 | * Initialize the per-CPU GDT with the boot GDT, | |
1243 | * and set up the GDT descriptor: | |
1244 | */ | |
1245 | ||
552be871 | 1246 | switch_to_new_gdt(cpu); |
2697fbd5 BG |
1247 | loadsegment(fs, 0); |
1248 | ||
1ba76586 YL |
1249 | load_idt((const struct desc_ptr *)&idt_descr); |
1250 | ||
1251 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1252 | syscall_init(); | |
1253 | ||
1254 | wrmsrl(MSR_FS_BASE, 0); | |
1255 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1256 | barrier(); | |
1257 | ||
4763ed4d | 1258 | x86_configure_nx(); |
06cd9a7d | 1259 | if (cpu != 0) |
1ba76586 YL |
1260 | enable_x2apic(); |
1261 | ||
1262 | /* | |
1263 | * set up and load the per-CPU TSS | |
1264 | */ | |
0fe1e009 | 1265 | if (!oist->ist[0]) { |
92d65b23 | 1266 | char *estacks = per_cpu(exception_stacks, cpu); |
0f3fa48a | 1267 | |
1ba76586 | 1268 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
0f3fa48a | 1269 | estacks += exception_stack_sizes[v]; |
0fe1e009 | 1270 | oist->ist[v] = t->x86_tss.ist[v] = |
1ba76586 | 1271 | (unsigned long)estacks; |
228bdaa9 SR |
1272 | if (v == DEBUG_STACK-1) |
1273 | per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; | |
1ba76586 YL |
1274 | } |
1275 | } | |
1276 | ||
1277 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
0f3fa48a | 1278 | |
1ba76586 YL |
1279 | /* |
1280 | * <= is required because the CPU will access up to | |
1281 | * 8 bits beyond the end of the IO permission bitmap. | |
1282 | */ | |
1283 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1284 | t->io_bitmap[i] = ~0UL; | |
1285 | ||
1286 | atomic_inc(&init_mm.mm_count); | |
1287 | me->active_mm = &init_mm; | |
8c5dfd25 | 1288 | BUG_ON(me->mm); |
1ba76586 YL |
1289 | enter_lazy_tlb(&init_mm, me); |
1290 | ||
1291 | load_sp0(t, ¤t->thread); | |
1292 | set_tss_desc(cpu, t); | |
1293 | load_TR_desc(); | |
1294 | load_LDT(&init_mm.context); | |
1295 | ||
0bb9fef9 JW |
1296 | clear_all_debug_regs(); |
1297 | dbg_restore_debug_regs(); | |
1ba76586 YL |
1298 | |
1299 | fpu_init(); | |
0e49bf66 | 1300 | xsave_init(); |
1ba76586 YL |
1301 | |
1302 | raw_local_save_flags(kernel_eflags); | |
1303 | ||
1304 | if (is_uv_system()) | |
1305 | uv_cpu_init(); | |
1306 | } | |
1307 | ||
1308 | #else | |
1309 | ||
d2cbcc49 | 1310 | void __cpuinit cpu_init(void) |
9ee79a3d | 1311 | { |
d2cbcc49 RR |
1312 | int cpu = smp_processor_id(); |
1313 | struct task_struct *curr = current; | |
34048c9e | 1314 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 1315 | struct thread_struct *thread = &curr->thread; |
62111195 | 1316 | |
c2d1cec1 | 1317 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { |
62111195 | 1318 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); |
9766cdbc JSR |
1319 | for (;;) |
1320 | local_irq_enable(); | |
62111195 JF |
1321 | } |
1322 | ||
1323 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1324 | ||
1325 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
1326 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 1327 | |
4d37e7e3 | 1328 | load_idt(&idt_descr); |
552be871 | 1329 | switch_to_new_gdt(cpu); |
1da177e4 | 1330 | |
1da177e4 LT |
1331 | /* |
1332 | * Set up and load the per-CPU TSS and LDT | |
1333 | */ | |
1334 | atomic_inc(&init_mm.mm_count); | |
62111195 | 1335 | curr->active_mm = &init_mm; |
8c5dfd25 | 1336 | BUG_ON(curr->mm); |
62111195 | 1337 | enter_lazy_tlb(&init_mm, curr); |
1da177e4 | 1338 | |
faca6227 | 1339 | load_sp0(t, thread); |
34048c9e | 1340 | set_tss_desc(cpu, t); |
1da177e4 LT |
1341 | load_TR_desc(); |
1342 | load_LDT(&init_mm.context); | |
1343 | ||
f9a196b8 TG |
1344 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); |
1345 | ||
22c4e308 | 1346 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1347 | /* Set up doublefault TSS pointer in the GDT */ |
1348 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1349 | #endif |
1da177e4 | 1350 | |
9766cdbc | 1351 | clear_all_debug_regs(); |
0bb9fef9 | 1352 | dbg_restore_debug_regs(); |
1da177e4 | 1353 | |
0e49bf66 | 1354 | fpu_init(); |
dc1e35c6 | 1355 | xsave_init(); |
1da177e4 | 1356 | } |
1ba76586 | 1357 | #endif |