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Commit | Line | Data |
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457c8996 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
2458e53f KS |
2 | /* cpu_feature_enabled() cannot be used this early */ |
3 | #define USE_EARLY_PGTABLE_L5 | |
4 | ||
57c8a661 | 5 | #include <linux/memblock.h> |
9766cdbc | 6 | #include <linux/linkage.h> |
f0fc4aff | 7 | #include <linux/bitops.h> |
9766cdbc | 8 | #include <linux/kernel.h> |
186f4360 | 9 | #include <linux/export.h> |
9766cdbc JSR |
10 | #include <linux/percpu.h> |
11 | #include <linux/string.h> | |
ee098e1a | 12 | #include <linux/ctype.h> |
1da177e4 | 13 | #include <linux/delay.h> |
68e21be2 | 14 | #include <linux/sched/mm.h> |
e6017571 | 15 | #include <linux/sched/clock.h> |
9164bb4a | 16 | #include <linux/sched/task.h> |
b47a3698 | 17 | #include <linux/sched/smt.h> |
9766cdbc | 18 | #include <linux/init.h> |
0f46efeb | 19 | #include <linux/kprobes.h> |
9766cdbc | 20 | #include <linux/kgdb.h> |
1da177e4 | 21 | #include <linux/smp.h> |
9766cdbc | 22 | #include <linux/io.h> |
b51ef52d | 23 | #include <linux/syscore_ops.h> |
65fddcfc | 24 | #include <linux/pgtable.h> |
9766cdbc JSR |
25 | |
26 | #include <asm/stackprotector.h> | |
cdd6c482 | 27 | #include <asm/perf_event.h> |
1da177e4 | 28 | #include <asm/mmu_context.h> |
dc4e0021 | 29 | #include <asm/doublefault.h> |
49d859d7 | 30 | #include <asm/archrandom.h> |
9766cdbc JSR |
31 | #include <asm/hypervisor.h> |
32 | #include <asm/processor.h> | |
1e02ce4c | 33 | #include <asm/tlbflush.h> |
f649e938 | 34 | #include <asm/debugreg.h> |
9766cdbc | 35 | #include <asm/sections.h> |
f40c3300 | 36 | #include <asm/vsyscall.h> |
8bdbd962 AC |
37 | #include <linux/topology.h> |
38 | #include <linux/cpumask.h> | |
60063497 | 39 | #include <linux/atomic.h> |
9766cdbc JSR |
40 | #include <asm/proto.h> |
41 | #include <asm/setup.h> | |
42 | #include <asm/apic.h> | |
43 | #include <asm/desc.h> | |
78f7f1e5 | 44 | #include <asm/fpu/internal.h> |
27b07da7 | 45 | #include <asm/mtrr.h> |
0274f955 | 46 | #include <asm/hwcap2.h> |
8bdbd962 | 47 | #include <linux/numa.h> |
9766cdbc | 48 | #include <asm/asm.h> |
0f6ff2bc | 49 | #include <asm/bugs.h> |
9766cdbc | 50 | #include <asm/cpu.h> |
a03a3e28 | 51 | #include <asm/mce.h> |
9766cdbc | 52 | #include <asm/msr.h> |
eb243d1d | 53 | #include <asm/memtype.h> |
d288e1cf FY |
54 | #include <asm/microcode.h> |
55 | #include <asm/microcode_intel.h> | |
fec9434a DW |
56 | #include <asm/intel-family.h> |
57 | #include <asm/cpu_device_id.h> | |
bdbcdd48 | 58 | #include <asm/uv/uv.h> |
1da177e4 LT |
59 | |
60 | #include "cpu.h" | |
61 | ||
0274f955 GA |
62 | u32 elf_hwcap2 __read_mostly; |
63 | ||
c2d1cec1 | 64 | /* all of these masks are initialized in setup_cpu_local_masks() */ |
c2d1cec1 | 65 | cpumask_var_t cpu_initialized_mask; |
9766cdbc JSR |
66 | cpumask_var_t cpu_callout_mask; |
67 | cpumask_var_t cpu_callin_mask; | |
c2d1cec1 MT |
68 | |
69 | /* representing cpus for which sibling maps can be computed */ | |
70 | cpumask_var_t cpu_sibling_setup_mask; | |
71 | ||
f8b64d08 BP |
72 | /* Number of siblings per CPU package */ |
73 | int smp_num_siblings = 1; | |
74 | EXPORT_SYMBOL(smp_num_siblings); | |
75 | ||
76 | /* Last level cache ID of each logical CPU */ | |
77 | DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; | |
78 | ||
2f2f52ba | 79 | /* correctly size the local cpu masks */ |
4369f1fb | 80 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
81 | { |
82 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
83 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
84 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
85 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
86 | } | |
87 | ||
148f9bb8 | 88 | static void default_init(struct cpuinfo_x86 *c) |
e8055139 OZ |
89 | { |
90 | #ifdef CONFIG_X86_64 | |
27c13ece | 91 | cpu_detect_cache_sizes(c); |
e8055139 OZ |
92 | #else |
93 | /* Not much we can do here... */ | |
94 | /* Check if at least it has cpuid */ | |
95 | if (c->cpuid_level == -1) { | |
96 | /* No cpuid. It must be an ancient CPU */ | |
97 | if (c->x86 == 4) | |
98 | strcpy(c->x86_model_id, "486"); | |
99 | else if (c->x86 == 3) | |
100 | strcpy(c->x86_model_id, "386"); | |
101 | } | |
102 | #endif | |
103 | } | |
104 | ||
148f9bb8 | 105 | static const struct cpu_dev default_cpu = { |
e8055139 OZ |
106 | .c_init = default_init, |
107 | .c_vendor = "Unknown", | |
108 | .c_x86_vendor = X86_VENDOR_UNKNOWN, | |
109 | }; | |
110 | ||
148f9bb8 | 111 | static const struct cpu_dev *this_cpu = &default_cpu; |
0a488a53 | 112 | |
06deef89 | 113 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 114 | #ifdef CONFIG_X86_64 |
06deef89 BG |
115 | /* |
116 | * We need valid kernel segments for data and code in long mode too | |
117 | * IRET will check the segment types kkeil 2000/10/28 | |
118 | * Also sysret mandates a special GDT layout | |
119 | * | |
9766cdbc | 120 | * TLS descriptors are currently at a different place compared to i386. |
06deef89 BG |
121 | * Hopefully nobody expects them at a fixed place (Wine?) |
122 | */ | |
1e5de182 AM |
123 | [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), |
124 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), | |
125 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), | |
126 | [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), | |
127 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), | |
128 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), | |
950ad7ff | 129 | #else |
1e5de182 AM |
130 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), |
131 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
132 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), | |
133 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), | |
bf504672 RR |
134 | /* |
135 | * Segments used for calling PnP BIOS have byte granularity. | |
136 | * They code segments and data segments have fixed 64k limits, | |
137 | * the transfer segment sizes are set at run time. | |
138 | */ | |
6842ef0e | 139 | /* 32-bit code */ |
1e5de182 | 140 | [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
6842ef0e | 141 | /* 16-bit code */ |
1e5de182 | 142 | [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 143 | /* 16-bit data */ |
1e5de182 | 144 | [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), |
6842ef0e | 145 | /* 16-bit data */ |
1e5de182 | 146 | [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), |
6842ef0e | 147 | /* 16-bit data */ |
1e5de182 | 148 | [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), |
bf504672 RR |
149 | /* |
150 | * The APM segments have byte granularity and their bases | |
151 | * are set at run time. All have 64k limits. | |
152 | */ | |
6842ef0e | 153 | /* 32-bit code */ |
1e5de182 | 154 | [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
bf504672 | 155 | /* 16-bit code */ |
1e5de182 | 156 | [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 157 | /* data */ |
72c4d853 | 158 | [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), |
bf504672 | 159 | |
1e5de182 AM |
160 | [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), |
161 | [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
60a5317f | 162 | GDT_STACK_CANARY_INIT |
950ad7ff | 163 | #endif |
06deef89 | 164 | } }; |
7a61d35d | 165 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 166 | |
0790c9aa | 167 | #ifdef CONFIG_X86_64 |
c7ad5ad2 | 168 | static int __init x86_nopcid_setup(char *s) |
0790c9aa | 169 | { |
c7ad5ad2 AL |
170 | /* nopcid doesn't accept parameters */ |
171 | if (s) | |
172 | return -EINVAL; | |
0790c9aa AL |
173 | |
174 | /* do not emit a message if the feature is not present */ | |
175 | if (!boot_cpu_has(X86_FEATURE_PCID)) | |
c7ad5ad2 | 176 | return 0; |
0790c9aa AL |
177 | |
178 | setup_clear_cpu_cap(X86_FEATURE_PCID); | |
179 | pr_info("nopcid: PCID feature disabled\n"); | |
c7ad5ad2 | 180 | return 0; |
0790c9aa | 181 | } |
c7ad5ad2 | 182 | early_param("nopcid", x86_nopcid_setup); |
0790c9aa AL |
183 | #endif |
184 | ||
d12a72b8 AL |
185 | static int __init x86_noinvpcid_setup(char *s) |
186 | { | |
187 | /* noinvpcid doesn't accept parameters */ | |
188 | if (s) | |
189 | return -EINVAL; | |
190 | ||
191 | /* do not emit a message if the feature is not present */ | |
192 | if (!boot_cpu_has(X86_FEATURE_INVPCID)) | |
193 | return 0; | |
194 | ||
195 | setup_clear_cpu_cap(X86_FEATURE_INVPCID); | |
196 | pr_info("noinvpcid: INVPCID feature disabled\n"); | |
197 | return 0; | |
198 | } | |
199 | early_param("noinvpcid", x86_noinvpcid_setup); | |
200 | ||
ba51dced | 201 | #ifdef CONFIG_X86_32 |
148f9bb8 PG |
202 | static int cachesize_override = -1; |
203 | static int disable_x86_serial_nr = 1; | |
1da177e4 | 204 | |
0a488a53 YL |
205 | static int __init cachesize_setup(char *str) |
206 | { | |
207 | get_option(&str, &cachesize_override); | |
208 | return 1; | |
209 | } | |
210 | __setup("cachesize=", cachesize_setup); | |
211 | ||
0a488a53 YL |
212 | static int __init x86_sep_setup(char *s) |
213 | { | |
214 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
215 | return 1; | |
216 | } | |
217 | __setup("nosep", x86_sep_setup); | |
218 | ||
219 | /* Standard macro to see if a specific flag is changeable */ | |
220 | static inline int flag_is_changeable_p(u32 flag) | |
221 | { | |
222 | u32 f1, f2; | |
223 | ||
94f6bac1 KH |
224 | /* |
225 | * Cyrix and IDT cpus allow disabling of CPUID | |
226 | * so the code below may return different results | |
227 | * when it is executed before and after enabling | |
228 | * the CPUID. Add "volatile" to not allow gcc to | |
229 | * optimize the subsequent calls to this function. | |
230 | */ | |
0f3fa48a IM |
231 | asm volatile ("pushfl \n\t" |
232 | "pushfl \n\t" | |
233 | "popl %0 \n\t" | |
234 | "movl %0, %1 \n\t" | |
235 | "xorl %2, %0 \n\t" | |
236 | "pushl %0 \n\t" | |
237 | "popfl \n\t" | |
238 | "pushfl \n\t" | |
239 | "popl %0 \n\t" | |
240 | "popfl \n\t" | |
241 | ||
94f6bac1 KH |
242 | : "=&r" (f1), "=&r" (f2) |
243 | : "ir" (flag)); | |
0a488a53 YL |
244 | |
245 | return ((f1^f2) & flag) != 0; | |
246 | } | |
247 | ||
248 | /* Probe for the CPUID instruction */ | |
148f9bb8 | 249 | int have_cpuid_p(void) |
0a488a53 YL |
250 | { |
251 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
252 | } | |
253 | ||
148f9bb8 | 254 | static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
0a488a53 | 255 | { |
0f3fa48a IM |
256 | unsigned long lo, hi; |
257 | ||
258 | if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) | |
259 | return; | |
260 | ||
261 | /* Disable processor serial number: */ | |
262 | ||
263 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
264 | lo |= 0x200000; | |
265 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
266 | ||
1b74dde7 | 267 | pr_notice("CPU serial number disabled.\n"); |
0f3fa48a IM |
268 | clear_cpu_cap(c, X86_FEATURE_PN); |
269 | ||
270 | /* Disabling the serial number may affect the cpuid level */ | |
271 | c->cpuid_level = cpuid_eax(0); | |
0a488a53 YL |
272 | } |
273 | ||
274 | static int __init x86_serial_nr_setup(char *s) | |
275 | { | |
276 | disable_x86_serial_nr = 0; | |
277 | return 1; | |
278 | } | |
279 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 280 | #else |
102bbe3a YL |
281 | static inline int flag_is_changeable_p(u32 flag) |
282 | { | |
283 | return 1; | |
284 | } | |
102bbe3a YL |
285 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
286 | { | |
287 | } | |
ba51dced | 288 | #endif |
0a488a53 | 289 | |
de5397ad FY |
290 | static __init int setup_disable_smep(char *arg) |
291 | { | |
b2cc2a07 | 292 | setup_clear_cpu_cap(X86_FEATURE_SMEP); |
de5397ad FY |
293 | return 1; |
294 | } | |
295 | __setup("nosmep", setup_disable_smep); | |
296 | ||
b2cc2a07 | 297 | static __always_inline void setup_smep(struct cpuinfo_x86 *c) |
de5397ad | 298 | { |
b2cc2a07 | 299 | if (cpu_has(c, X86_FEATURE_SMEP)) |
375074cc | 300 | cr4_set_bits(X86_CR4_SMEP); |
de5397ad FY |
301 | } |
302 | ||
52b6179a PA |
303 | static __init int setup_disable_smap(char *arg) |
304 | { | |
b2cc2a07 | 305 | setup_clear_cpu_cap(X86_FEATURE_SMAP); |
52b6179a PA |
306 | return 1; |
307 | } | |
308 | __setup("nosmap", setup_disable_smap); | |
309 | ||
b2cc2a07 PA |
310 | static __always_inline void setup_smap(struct cpuinfo_x86 *c) |
311 | { | |
581b7f15 | 312 | unsigned long eflags = native_save_fl(); |
b2cc2a07 PA |
313 | |
314 | /* This should have been cleared long ago */ | |
b2cc2a07 PA |
315 | BUG_ON(eflags & X86_EFLAGS_AC); |
316 | ||
03bbd596 PA |
317 | if (cpu_has(c, X86_FEATURE_SMAP)) { |
318 | #ifdef CONFIG_X86_SMAP | |
375074cc | 319 | cr4_set_bits(X86_CR4_SMAP); |
03bbd596 | 320 | #else |
375074cc | 321 | cr4_clear_bits(X86_CR4_SMAP); |
03bbd596 PA |
322 | #endif |
323 | } | |
de5397ad FY |
324 | } |
325 | ||
aa35f896 RN |
326 | static __always_inline void setup_umip(struct cpuinfo_x86 *c) |
327 | { | |
328 | /* Check the boot processor, plus build option for UMIP. */ | |
329 | if (!cpu_feature_enabled(X86_FEATURE_UMIP)) | |
330 | goto out; | |
331 | ||
332 | /* Check the current processor's cpuid bits. */ | |
333 | if (!cpu_has(c, X86_FEATURE_UMIP)) | |
334 | goto out; | |
335 | ||
336 | cr4_set_bits(X86_CR4_UMIP); | |
337 | ||
438cbf88 | 338 | pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n"); |
770c7755 | 339 | |
aa35f896 RN |
340 | return; |
341 | ||
342 | out: | |
343 | /* | |
344 | * Make sure UMIP is disabled in case it was enabled in a | |
345 | * previous boot (e.g., via kexec). | |
346 | */ | |
347 | cr4_clear_bits(X86_CR4_UMIP); | |
348 | } | |
349 | ||
7652ac92 TG |
350 | static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); |
351 | static unsigned long cr4_pinned_bits __ro_after_init; | |
352 | ||
353 | void native_write_cr0(unsigned long val) | |
354 | { | |
355 | unsigned long bits_missing = 0; | |
356 | ||
357 | set_register: | |
358 | asm volatile("mov %0,%%cr0": "+r" (val), "+m" (__force_order)); | |
359 | ||
360 | if (static_branch_likely(&cr_pinning)) { | |
361 | if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) { | |
362 | bits_missing = X86_CR0_WP; | |
363 | val |= bits_missing; | |
364 | goto set_register; | |
365 | } | |
366 | /* Warn after we've set the missing bits. */ | |
367 | WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n"); | |
368 | } | |
369 | } | |
370 | EXPORT_SYMBOL(native_write_cr0); | |
371 | ||
372 | void native_write_cr4(unsigned long val) | |
373 | { | |
374 | unsigned long bits_missing = 0; | |
375 | ||
376 | set_register: | |
377 | asm volatile("mov %0,%%cr4": "+r" (val), "+m" (cr4_pinned_bits)); | |
378 | ||
379 | if (static_branch_likely(&cr_pinning)) { | |
380 | if (unlikely((val & cr4_pinned_bits) != cr4_pinned_bits)) { | |
381 | bits_missing = ~val & cr4_pinned_bits; | |
382 | val |= bits_missing; | |
383 | goto set_register; | |
384 | } | |
385 | /* Warn after we've set the missing bits. */ | |
386 | WARN_ONCE(bits_missing, "CR4 bits went missing: %lx!?\n", | |
387 | bits_missing); | |
388 | } | |
389 | } | |
21953ee5 | 390 | #if IS_MODULE(CONFIG_LKDTM) |
d8f0b353 | 391 | EXPORT_SYMBOL_GPL(native_write_cr4); |
21953ee5 | 392 | #endif |
d8f0b353 TG |
393 | |
394 | void cr4_update_irqsoff(unsigned long set, unsigned long clear) | |
395 | { | |
396 | unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4); | |
397 | ||
398 | lockdep_assert_irqs_disabled(); | |
399 | ||
400 | newval = (cr4 & ~clear) | set; | |
401 | if (newval != cr4) { | |
402 | this_cpu_write(cpu_tlbstate.cr4, newval); | |
403 | __write_cr4(newval); | |
404 | } | |
405 | } | |
406 | EXPORT_SYMBOL(cr4_update_irqsoff); | |
407 | ||
408 | /* Read the CR4 shadow. */ | |
409 | unsigned long cr4_read_shadow(void) | |
410 | { | |
411 | return this_cpu_read(cpu_tlbstate.cr4); | |
412 | } | |
413 | EXPORT_SYMBOL_GPL(cr4_read_shadow); | |
7652ac92 TG |
414 | |
415 | void cr4_init(void) | |
416 | { | |
417 | unsigned long cr4 = __read_cr4(); | |
418 | ||
419 | if (boot_cpu_has(X86_FEATURE_PCID)) | |
420 | cr4 |= X86_CR4_PCIDE; | |
421 | if (static_branch_likely(&cr_pinning)) | |
422 | cr4 |= cr4_pinned_bits; | |
423 | ||
424 | __write_cr4(cr4); | |
425 | ||
426 | /* Initialize cr4 shadow for this CPU. */ | |
427 | this_cpu_write(cpu_tlbstate.cr4, cr4); | |
428 | } | |
873d50d5 KC |
429 | |
430 | /* | |
431 | * Once CPU feature detection is finished (and boot params have been | |
432 | * parsed), record any of the sensitive CR bits that are set, and | |
433 | * enable CR pinning. | |
434 | */ | |
435 | static void __init setup_cr_pinning(void) | |
436 | { | |
437 | unsigned long mask; | |
438 | ||
439 | mask = (X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP); | |
440 | cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & mask; | |
441 | static_key_enable(&cr_pinning.key); | |
442 | } | |
443 | ||
b745cfba | 444 | static __init int x86_nofsgsbase_setup(char *arg) |
dd649bd0 | 445 | { |
b745cfba AL |
446 | /* Require an exact match without trailing characters. */ |
447 | if (strlen(arg)) | |
448 | return 0; | |
449 | ||
450 | /* Do not emit a message if the feature is not present. */ | |
451 | if (!boot_cpu_has(X86_FEATURE_FSGSBASE)) | |
452 | return 1; | |
453 | ||
454 | setup_clear_cpu_cap(X86_FEATURE_FSGSBASE); | |
455 | pr_info("FSGSBASE disabled via kernel command line\n"); | |
dd649bd0 AL |
456 | return 1; |
457 | } | |
b745cfba | 458 | __setup("nofsgsbase", x86_nofsgsbase_setup); |
dd649bd0 | 459 | |
06976945 DH |
460 | /* |
461 | * Protection Keys are not available in 32-bit mode. | |
462 | */ | |
463 | static bool pku_disabled; | |
464 | ||
465 | static __always_inline void setup_pku(struct cpuinfo_x86 *c) | |
466 | { | |
a5eff725 SAS |
467 | struct pkru_state *pk; |
468 | ||
e8df1a95 DH |
469 | /* check the boot processor, plus compile options for PKU: */ |
470 | if (!cpu_feature_enabled(X86_FEATURE_PKU)) | |
471 | return; | |
472 | /* checks the actual processor's cpuid bits: */ | |
06976945 DH |
473 | if (!cpu_has(c, X86_FEATURE_PKU)) |
474 | return; | |
475 | if (pku_disabled) | |
476 | return; | |
477 | ||
478 | cr4_set_bits(X86_CR4_PKE); | |
a5eff725 SAS |
479 | pk = get_xsave_addr(&init_fpstate.xsave, XFEATURE_PKRU); |
480 | if (pk) | |
481 | pk->pkru = init_pkru_value; | |
06976945 DH |
482 | /* |
483 | * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE | |
484 | * cpuid bit to be set. We need to ensure that we | |
485 | * update that bit in this CPU's "cpu_info". | |
486 | */ | |
735a6dd0 | 487 | set_cpu_cap(c, X86_FEATURE_OSPKE); |
06976945 DH |
488 | } |
489 | ||
490 | #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS | |
491 | static __init int setup_disable_pku(char *arg) | |
492 | { | |
493 | /* | |
494 | * Do not clear the X86_FEATURE_PKU bit. All of the | |
495 | * runtime checks are against OSPKE so clearing the | |
496 | * bit does nothing. | |
497 | * | |
498 | * This way, we will see "pku" in cpuinfo, but not | |
499 | * "ospke", which is exactly what we want. It shows | |
500 | * that the CPU has PKU, but the OS has not enabled it. | |
501 | * This happens to be exactly how a system would look | |
502 | * if we disabled the config option. | |
503 | */ | |
504 | pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); | |
505 | pku_disabled = true; | |
506 | return 1; | |
507 | } | |
508 | __setup("nopku", setup_disable_pku); | |
509 | #endif /* CONFIG_X86_64 */ | |
510 | ||
b38b0665 PA |
511 | /* |
512 | * Some CPU features depend on higher CPUID levels, which may not always | |
513 | * be available due to CPUID level capping or broken virtualization | |
514 | * software. Add those features to this table to auto-disable them. | |
515 | */ | |
516 | struct cpuid_dependent_feature { | |
517 | u32 feature; | |
518 | u32 level; | |
519 | }; | |
0f3fa48a | 520 | |
148f9bb8 | 521 | static const struct cpuid_dependent_feature |
b38b0665 PA |
522 | cpuid_dependent_features[] = { |
523 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
524 | { X86_FEATURE_DCA, 0x00000009 }, | |
525 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
526 | { 0, 0 } | |
527 | }; | |
528 | ||
148f9bb8 | 529 | static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) |
b38b0665 PA |
530 | { |
531 | const struct cpuid_dependent_feature *df; | |
9766cdbc | 532 | |
b38b0665 | 533 | for (df = cpuid_dependent_features; df->feature; df++) { |
0f3fa48a IM |
534 | |
535 | if (!cpu_has(c, df->feature)) | |
536 | continue; | |
b38b0665 PA |
537 | /* |
538 | * Note: cpuid_level is set to -1 if unavailable, but | |
539 | * extended_extended_level is set to 0 if unavailable | |
540 | * and the legitimate extended levels are all negative | |
541 | * when signed; hence the weird messing around with | |
542 | * signs here... | |
543 | */ | |
0f3fa48a | 544 | if (!((s32)df->level < 0 ? |
f6db44df | 545 | (u32)df->level > (u32)c->extended_cpuid_level : |
0f3fa48a IM |
546 | (s32)df->level > (s32)c->cpuid_level)) |
547 | continue; | |
548 | ||
549 | clear_cpu_cap(c, df->feature); | |
550 | if (!warn) | |
551 | continue; | |
552 | ||
1b74dde7 CY |
553 | pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", |
554 | x86_cap_flag(df->feature), df->level); | |
b38b0665 | 555 | } |
f6db44df | 556 | } |
b38b0665 | 557 | |
102bbe3a YL |
558 | /* |
559 | * Naming convention should be: <Name> [(<Codename>)] | |
560 | * This table only is used unless init_<vendor>() below doesn't set it; | |
0f3fa48a IM |
561 | * in particular, if CPUID levels 0x80000002..4 are supported, this |
562 | * isn't used | |
102bbe3a YL |
563 | */ |
564 | ||
565 | /* Look up CPU names by table lookup. */ | |
148f9bb8 | 566 | static const char *table_lookup_model(struct cpuinfo_x86 *c) |
102bbe3a | 567 | { |
09dc68d9 JB |
568 | #ifdef CONFIG_X86_32 |
569 | const struct legacy_cpu_model_info *info; | |
102bbe3a YL |
570 | |
571 | if (c->x86_model >= 16) | |
572 | return NULL; /* Range check */ | |
573 | ||
574 | if (!this_cpu) | |
575 | return NULL; | |
576 | ||
09dc68d9 | 577 | info = this_cpu->legacy_models; |
102bbe3a | 578 | |
09dc68d9 | 579 | while (info->family) { |
102bbe3a YL |
580 | if (info->family == c->x86) |
581 | return info->model_names[c->x86_model]; | |
582 | info++; | |
583 | } | |
09dc68d9 | 584 | #endif |
102bbe3a YL |
585 | return NULL; /* Not found */ |
586 | } | |
587 | ||
f6a892dd FY |
588 | /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */ |
589 | __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); | |
590 | __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); | |
7d851c8d | 591 | |
11e3a840 JF |
592 | void load_percpu_segment(int cpu) |
593 | { | |
594 | #ifdef CONFIG_X86_32 | |
595 | loadsegment(fs, __KERNEL_PERCPU); | |
596 | #else | |
45e876f7 | 597 | __loadsegment_simple(gs, 0); |
35060ed6 | 598 | wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); |
11e3a840 | 599 | #endif |
60a5317f | 600 | load_stack_canary_segment(); |
11e3a840 JF |
601 | } |
602 | ||
72f5e08d AL |
603 | #ifdef CONFIG_X86_32 |
604 | /* The 32-bit entry code needs to find cpu_entry_area. */ | |
605 | DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); | |
606 | #endif | |
607 | ||
45fc8757 TG |
608 | /* Load the original GDT from the per-cpu structure */ |
609 | void load_direct_gdt(int cpu) | |
610 | { | |
611 | struct desc_ptr gdt_descr; | |
612 | ||
613 | gdt_descr.address = (long)get_cpu_gdt_rw(cpu); | |
614 | gdt_descr.size = GDT_SIZE - 1; | |
615 | load_gdt(&gdt_descr); | |
616 | } | |
617 | EXPORT_SYMBOL_GPL(load_direct_gdt); | |
618 | ||
69218e47 TG |
619 | /* Load a fixmap remapping of the per-cpu GDT */ |
620 | void load_fixmap_gdt(int cpu) | |
621 | { | |
622 | struct desc_ptr gdt_descr; | |
623 | ||
624 | gdt_descr.address = (long)get_cpu_gdt_ro(cpu); | |
625 | gdt_descr.size = GDT_SIZE - 1; | |
626 | load_gdt(&gdt_descr); | |
627 | } | |
45fc8757 | 628 | EXPORT_SYMBOL_GPL(load_fixmap_gdt); |
69218e47 | 629 | |
0f3fa48a IM |
630 | /* |
631 | * Current gdt points %fs at the "master" per-cpu area: after this, | |
632 | * it's on the real one. | |
633 | */ | |
552be871 | 634 | void switch_to_new_gdt(int cpu) |
9d31d35b | 635 | { |
45fc8757 TG |
636 | /* Load the original GDT */ |
637 | load_direct_gdt(cpu); | |
2697fbd5 | 638 | /* Reload the per-cpu base */ |
11e3a840 | 639 | load_percpu_segment(cpu); |
9d31d35b YL |
640 | } |
641 | ||
148f9bb8 | 642 | static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 643 | |
148f9bb8 | 644 | static void get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
645 | { |
646 | unsigned int *v; | |
ee098e1a | 647 | char *p, *q, *s; |
1da177e4 | 648 | |
3da99c97 | 649 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 650 | return; |
1da177e4 | 651 | |
0f3fa48a | 652 | v = (unsigned int *)c->x86_model_id; |
1da177e4 LT |
653 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); |
654 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
655 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
656 | c->x86_model_id[48] = 0; | |
657 | ||
ee098e1a BP |
658 | /* Trim whitespace */ |
659 | p = q = s = &c->x86_model_id[0]; | |
660 | ||
661 | while (*p == ' ') | |
662 | p++; | |
663 | ||
664 | while (*p) { | |
665 | /* Note the last non-whitespace index */ | |
666 | if (!isspace(*p)) | |
667 | s = q; | |
668 | ||
669 | *q++ = *p++; | |
670 | } | |
671 | ||
672 | *(s + 1) = '\0'; | |
1da177e4 LT |
673 | } |
674 | ||
9305bd6c | 675 | void detect_num_cpu_cores(struct cpuinfo_x86 *c) |
2cc61be6 DW |
676 | { |
677 | unsigned int eax, ebx, ecx, edx; | |
678 | ||
9305bd6c | 679 | c->x86_max_cores = 1; |
2cc61be6 | 680 | if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) |
9305bd6c | 681 | return; |
2cc61be6 DW |
682 | |
683 | cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); | |
684 | if (eax & 0x1f) | |
9305bd6c | 685 | c->x86_max_cores = (eax >> 26) + 1; |
2cc61be6 DW |
686 | } |
687 | ||
148f9bb8 | 688 | void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) |
1da177e4 | 689 | { |
9d31d35b | 690 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 691 | |
3da99c97 | 692 | n = c->extended_cpuid_level; |
1da177e4 LT |
693 | |
694 | if (n >= 0x80000005) { | |
9d31d35b | 695 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
9d31d35b | 696 | c->x86_cache_size = (ecx>>24) + (edx>>24); |
140fc727 YL |
697 | #ifdef CONFIG_X86_64 |
698 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
699 | c->x86_tlbsize = 0; | |
700 | #endif | |
1da177e4 LT |
701 | } |
702 | ||
703 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
704 | return; | |
705 | ||
0a488a53 | 706 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 707 | l2size = ecx >> 16; |
34048c9e | 708 | |
140fc727 YL |
709 | #ifdef CONFIG_X86_64 |
710 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
711 | #else | |
1da177e4 | 712 | /* do processor-specific cache resizing */ |
09dc68d9 JB |
713 | if (this_cpu->legacy_cache_size) |
714 | l2size = this_cpu->legacy_cache_size(c, l2size); | |
1da177e4 LT |
715 | |
716 | /* Allow user to override all this if necessary. */ | |
717 | if (cachesize_override != -1) | |
718 | l2size = cachesize_override; | |
719 | ||
34048c9e | 720 | if (l2size == 0) |
1da177e4 | 721 | return; /* Again, no L2 cache is possible */ |
140fc727 | 722 | #endif |
1da177e4 LT |
723 | |
724 | c->x86_cache_size = l2size; | |
1da177e4 LT |
725 | } |
726 | ||
e0ba94f1 AS |
727 | u16 __read_mostly tlb_lli_4k[NR_INFO]; |
728 | u16 __read_mostly tlb_lli_2m[NR_INFO]; | |
729 | u16 __read_mostly tlb_lli_4m[NR_INFO]; | |
730 | u16 __read_mostly tlb_lld_4k[NR_INFO]; | |
731 | u16 __read_mostly tlb_lld_2m[NR_INFO]; | |
732 | u16 __read_mostly tlb_lld_4m[NR_INFO]; | |
dd360393 | 733 | u16 __read_mostly tlb_lld_1g[NR_INFO]; |
e0ba94f1 | 734 | |
f94fe119 | 735 | static void cpu_detect_tlb(struct cpuinfo_x86 *c) |
e0ba94f1 AS |
736 | { |
737 | if (this_cpu->c_detect_tlb) | |
738 | this_cpu->c_detect_tlb(c); | |
739 | ||
f94fe119 | 740 | pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", |
e0ba94f1 | 741 | tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], |
f94fe119 SH |
742 | tlb_lli_4m[ENTRIES]); |
743 | ||
744 | pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", | |
745 | tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], | |
746 | tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); | |
e0ba94f1 AS |
747 | } |
748 | ||
545401f4 | 749 | int detect_ht_early(struct cpuinfo_x86 *c) |
1da177e4 | 750 | { |
c8e56d20 | 751 | #ifdef CONFIG_SMP |
0a488a53 | 752 | u32 eax, ebx, ecx, edx; |
1da177e4 | 753 | |
0a488a53 | 754 | if (!cpu_has(c, X86_FEATURE_HT)) |
545401f4 | 755 | return -1; |
1da177e4 | 756 | |
0a488a53 | 757 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
545401f4 | 758 | return -1; |
1da177e4 | 759 | |
1cd78776 | 760 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
545401f4 | 761 | return -1; |
1da177e4 | 762 | |
0a488a53 | 763 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 764 | |
9d31d35b | 765 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
545401f4 | 766 | if (smp_num_siblings == 1) |
1b74dde7 | 767 | pr_info_once("CPU0: Hyper-Threading is disabled\n"); |
545401f4 TG |
768 | #endif |
769 | return 0; | |
770 | } | |
9d31d35b | 771 | |
545401f4 TG |
772 | void detect_ht(struct cpuinfo_x86 *c) |
773 | { | |
774 | #ifdef CONFIG_SMP | |
775 | int index_msb, core_bits; | |
55e6d279 | 776 | |
545401f4 | 777 | if (detect_ht_early(c) < 0) |
55e6d279 | 778 | return; |
9d31d35b | 779 | |
0f3fa48a IM |
780 | index_msb = get_count_order(smp_num_siblings); |
781 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); | |
9d31d35b | 782 | |
0f3fa48a | 783 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
9d31d35b | 784 | |
0f3fa48a | 785 | index_msb = get_count_order(smp_num_siblings); |
9d31d35b | 786 | |
0f3fa48a | 787 | core_bits = get_count_order(c->x86_max_cores); |
9d31d35b | 788 | |
0f3fa48a IM |
789 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & |
790 | ((1 << core_bits) - 1); | |
9d31d35b | 791 | #endif |
97e4db7c | 792 | } |
1da177e4 | 793 | |
148f9bb8 | 794 | static void get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
795 | { |
796 | char *v = c->x86_vendor_id; | |
0f3fa48a | 797 | int i; |
1da177e4 LT |
798 | |
799 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
800 | if (!cpu_devs[i]) |
801 | break; | |
802 | ||
803 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
804 | (cpu_devs[i]->c_ident[1] && | |
805 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
0f3fa48a | 806 | |
10a434fc YL |
807 | this_cpu = cpu_devs[i]; |
808 | c->x86_vendor = this_cpu->c_x86_vendor; | |
809 | return; | |
1da177e4 LT |
810 | } |
811 | } | |
10a434fc | 812 | |
1b74dde7 CY |
813 | pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ |
814 | "CPU: Your system may be unstable.\n", v); | |
10a434fc | 815 | |
fe38d855 CE |
816 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
817 | this_cpu = &default_cpu; | |
1da177e4 LT |
818 | } |
819 | ||
148f9bb8 | 820 | void cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 821 | { |
1da177e4 | 822 | /* Get vendor name */ |
4a148513 HH |
823 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
824 | (unsigned int *)&c->x86_vendor_id[0], | |
825 | (unsigned int *)&c->x86_vendor_id[8], | |
826 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 827 | |
1da177e4 | 828 | c->x86 = 4; |
9d31d35b | 829 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
830 | if (c->cpuid_level >= 0x00000001) { |
831 | u32 junk, tfms, cap0, misc; | |
0f3fa48a | 832 | |
1da177e4 | 833 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
99f925ce BP |
834 | c->x86 = x86_family(tfms); |
835 | c->x86_model = x86_model(tfms); | |
b399151c | 836 | c->x86_stepping = x86_stepping(tfms); |
0f3fa48a | 837 | |
d4387bd3 | 838 | if (cap0 & (1<<19)) { |
d4387bd3 | 839 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 840 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 841 | } |
1da177e4 | 842 | } |
1da177e4 | 843 | } |
3da99c97 | 844 | |
8bf1ebca AL |
845 | static void apply_forced_caps(struct cpuinfo_x86 *c) |
846 | { | |
847 | int i; | |
848 | ||
6cbd2171 | 849 | for (i = 0; i < NCAPINTS + NBUGINTS; i++) { |
8bf1ebca AL |
850 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; |
851 | c->x86_capability[i] |= cpu_caps_set[i]; | |
852 | } | |
853 | } | |
854 | ||
7fcae111 DW |
855 | static void init_speculation_control(struct cpuinfo_x86 *c) |
856 | { | |
857 | /* | |
858 | * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, | |
859 | * and they also have a different bit for STIBP support. Also, | |
860 | * a hypervisor might have set the individual AMD bits even on | |
861 | * Intel CPUs, for finer-grained selection of what's available. | |
7fcae111 DW |
862 | */ |
863 | if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { | |
864 | set_cpu_cap(c, X86_FEATURE_IBRS); | |
865 | set_cpu_cap(c, X86_FEATURE_IBPB); | |
7eb8956a | 866 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); |
7fcae111 | 867 | } |
e7c587da | 868 | |
7fcae111 DW |
869 | if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) |
870 | set_cpu_cap(c, X86_FEATURE_STIBP); | |
e7c587da | 871 | |
bc226f07 TL |
872 | if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || |
873 | cpu_has(c, X86_FEATURE_VIRT_SSBD)) | |
52817587 TG |
874 | set_cpu_cap(c, X86_FEATURE_SSBD); |
875 | ||
7eb8956a | 876 | if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { |
e7c587da | 877 | set_cpu_cap(c, X86_FEATURE_IBRS); |
7eb8956a TG |
878 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); |
879 | } | |
e7c587da BP |
880 | |
881 | if (cpu_has(c, X86_FEATURE_AMD_IBPB)) | |
882 | set_cpu_cap(c, X86_FEATURE_IBPB); | |
883 | ||
7eb8956a | 884 | if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { |
e7c587da | 885 | set_cpu_cap(c, X86_FEATURE_STIBP); |
7eb8956a TG |
886 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); |
887 | } | |
6ac2f49e KRW |
888 | |
889 | if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { | |
890 | set_cpu_cap(c, X86_FEATURE_SSBD); | |
891 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); | |
892 | clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); | |
893 | } | |
7fcae111 DW |
894 | } |
895 | ||
148f9bb8 | 896 | void get_cpu_cap(struct cpuinfo_x86 *c) |
093af8d7 | 897 | { |
39c06df4 | 898 | u32 eax, ebx, ecx, edx; |
093af8d7 | 899 | |
3da99c97 YL |
900 | /* Intel-defined flags: level 0x00000001 */ |
901 | if (c->cpuid_level >= 0x00000001) { | |
39c06df4 | 902 | cpuid(0x00000001, &eax, &ebx, &ecx, &edx); |
0f3fa48a | 903 | |
39c06df4 BP |
904 | c->x86_capability[CPUID_1_ECX] = ecx; |
905 | c->x86_capability[CPUID_1_EDX] = edx; | |
3da99c97 | 906 | } |
093af8d7 | 907 | |
3df8d920 AL |
908 | /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ |
909 | if (c->cpuid_level >= 0x00000006) | |
910 | c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); | |
911 | ||
bdc802dc PA |
912 | /* Additional Intel-defined flags: level 0x00000007 */ |
913 | if (c->cpuid_level >= 0x00000007) { | |
bdc802dc | 914 | cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); |
39c06df4 | 915 | c->x86_capability[CPUID_7_0_EBX] = ebx; |
dfb4a70f | 916 | c->x86_capability[CPUID_7_ECX] = ecx; |
95ca0ee8 | 917 | c->x86_capability[CPUID_7_EDX] = edx; |
b302e4b1 FY |
918 | |
919 | /* Check valid sub-leaf index before accessing it */ | |
920 | if (eax >= 1) { | |
921 | cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx); | |
922 | c->x86_capability[CPUID_7_1_EAX] = eax; | |
923 | } | |
bdc802dc PA |
924 | } |
925 | ||
6229ad27 FY |
926 | /* Extended state features: level 0x0000000d */ |
927 | if (c->cpuid_level >= 0x0000000d) { | |
6229ad27 FY |
928 | cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); |
929 | ||
39c06df4 | 930 | c->x86_capability[CPUID_D_1_EAX] = eax; |
6229ad27 FY |
931 | } |
932 | ||
3da99c97 | 933 | /* AMD-defined flags: level 0x80000001 */ |
39c06df4 BP |
934 | eax = cpuid_eax(0x80000000); |
935 | c->extended_cpuid_level = eax; | |
936 | ||
937 | if ((eax & 0xffff0000) == 0x80000000) { | |
938 | if (eax >= 0x80000001) { | |
939 | cpuid(0x80000001, &eax, &ebx, &ecx, &edx); | |
0f3fa48a | 940 | |
39c06df4 BP |
941 | c->x86_capability[CPUID_8000_0001_ECX] = ecx; |
942 | c->x86_capability[CPUID_8000_0001_EDX] = edx; | |
093af8d7 | 943 | } |
093af8d7 | 944 | } |
093af8d7 | 945 | |
71faad43 YG |
946 | if (c->extended_cpuid_level >= 0x80000007) { |
947 | cpuid(0x80000007, &eax, &ebx, &ecx, &edx); | |
948 | ||
949 | c->x86_capability[CPUID_8000_0007_EBX] = ebx; | |
950 | c->x86_power = edx; | |
951 | } | |
952 | ||
c65732e4 TG |
953 | if (c->extended_cpuid_level >= 0x80000008) { |
954 | cpuid(0x80000008, &eax, &ebx, &ecx, &edx); | |
955 | c->x86_capability[CPUID_8000_0008_EBX] = ebx; | |
956 | } | |
957 | ||
2ccd71f1 | 958 | if (c->extended_cpuid_level >= 0x8000000a) |
39c06df4 | 959 | c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); |
093af8d7 | 960 | |
1dedefd1 | 961 | init_scattered_cpuid_features(c); |
7fcae111 | 962 | init_speculation_control(c); |
60d34501 AL |
963 | |
964 | /* | |
965 | * Clear/Set all flags overridden by options, after probe. | |
966 | * This needs to happen each time we re-probe, which may happen | |
967 | * several times during CPU initialization. | |
968 | */ | |
969 | apply_forced_caps(c); | |
093af8d7 | 970 | } |
1da177e4 | 971 | |
405c018a | 972 | void get_cpu_address_sizes(struct cpuinfo_x86 *c) |
d94a155c KS |
973 | { |
974 | u32 eax, ebx, ecx, edx; | |
975 | ||
976 | if (c->extended_cpuid_level >= 0x80000008) { | |
977 | cpuid(0x80000008, &eax, &ebx, &ecx, &edx); | |
978 | ||
979 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
980 | c->x86_phys_bits = eax & 0xff; | |
d94a155c KS |
981 | } |
982 | #ifdef CONFIG_X86_32 | |
983 | else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) | |
984 | c->x86_phys_bits = 36; | |
985 | #endif | |
cc51e542 | 986 | c->x86_cache_bits = c->x86_phys_bits; |
d94a155c KS |
987 | } |
988 | ||
148f9bb8 | 989 | static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
aef93c8b YL |
990 | { |
991 | #ifdef CONFIG_X86_32 | |
992 | int i; | |
993 | ||
994 | /* | |
995 | * First of all, decide if this is a 486 or higher | |
996 | * It's a 486 if we can modify the AC flag | |
997 | */ | |
998 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
999 | c->x86 = 4; | |
1000 | else | |
1001 | c->x86 = 3; | |
1002 | ||
1003 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
1004 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
1005 | c->x86_vendor_id[0] = 0; | |
1006 | cpu_devs[i]->c_identify(c); | |
1007 | if (c->x86_vendor_id[0]) { | |
1008 | get_cpu_vendor(c); | |
1009 | break; | |
1010 | } | |
1011 | } | |
1012 | #endif | |
1013 | } | |
1014 | ||
db4d30fb VT |
1015 | #define NO_SPECULATION BIT(0) |
1016 | #define NO_MELTDOWN BIT(1) | |
1017 | #define NO_SSB BIT(2) | |
1018 | #define NO_L1TF BIT(3) | |
1019 | #define NO_MDS BIT(4) | |
1020 | #define MSBDS_ONLY BIT(5) | |
1021 | #define NO_SWAPGS BIT(6) | |
1022 | #define NO_ITLB_MULTIHIT BIT(7) | |
1e41a766 | 1023 | #define NO_SPECTRE_V2 BIT(8) |
36ad3513 | 1024 | |
f6d502fc TG |
1025 | #define VULNWL(vendor, family, model, whitelist) \ |
1026 | X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist) | |
36ad3513 TG |
1027 | |
1028 | #define VULNWL_INTEL(model, whitelist) \ | |
1029 | VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist) | |
1030 | ||
1031 | #define VULNWL_AMD(family, whitelist) \ | |
1032 | VULNWL(AMD, family, X86_MODEL_ANY, whitelist) | |
1033 | ||
1034 | #define VULNWL_HYGON(family, whitelist) \ | |
1035 | VULNWL(HYGON, family, X86_MODEL_ANY, whitelist) | |
1036 | ||
1037 | static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { | |
1038 | VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), | |
1039 | VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), | |
1040 | VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), | |
1041 | VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), | |
1042 | ||
ed5194c2 | 1043 | /* Intel Family 6 */ |
db4d30fb VT |
1044 | VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), |
1045 | VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), | |
1046 | VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), | |
1047 | VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), | |
1048 | VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), | |
1049 | ||
1050 | VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
1051 | VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
1052 | VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
1053 | VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
1054 | VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
1055 | VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
36ad3513 TG |
1056 | |
1057 | VULNWL_INTEL(CORE_YONAH, NO_SSB), | |
1058 | ||
db4d30fb VT |
1059 | VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), |
1060 | VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
36ad3513 | 1061 | |
db4d30fb VT |
1062 | VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), |
1063 | VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
1064 | VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
f36cf386 TG |
1065 | |
1066 | /* | |
1067 | * Technically, swapgs isn't serializing on AMD (despite it previously | |
1068 | * being documented as such in the APM). But according to AMD, %gs is | |
1069 | * updated non-speculatively, and the issuing of %gs-relative memory | |
1070 | * operands will be blocked until the %gs update completes, which is | |
1071 | * good enough for our purposes. | |
1072 | */ | |
ed5194c2 | 1073 | |
cad14885 PG |
1074 | VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT), |
1075 | ||
ed5194c2 | 1076 | /* AMD Family 0xf - 0x12 */ |
db4d30fb VT |
1077 | VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), |
1078 | VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
1079 | VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
1080 | VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
36ad3513 TG |
1081 | |
1082 | /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ | |
db4d30fb VT |
1083 | VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), |
1084 | VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
1e41a766 TW |
1085 | |
1086 | /* Zhaoxin Family 7 */ | |
a84de2fa TW |
1087 | VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS), |
1088 | VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS), | |
fec9434a DW |
1089 | {} |
1090 | }; | |
1091 | ||
7e5b3c26 MG |
1092 | #define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \ |
1093 | X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \ | |
1094 | INTEL_FAM6_##model, steppings, \ | |
1095 | X86_FEATURE_ANY, issues) | |
1096 | ||
1097 | #define SRBDS BIT(0) | |
1098 | ||
1099 | static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = { | |
1100 | VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS), | |
1101 | VULNBL_INTEL_STEPPINGS(HASWELL, X86_STEPPING_ANY, SRBDS), | |
1102 | VULNBL_INTEL_STEPPINGS(HASWELL_L, X86_STEPPING_ANY, SRBDS), | |
1103 | VULNBL_INTEL_STEPPINGS(HASWELL_G, X86_STEPPING_ANY, SRBDS), | |
1104 | VULNBL_INTEL_STEPPINGS(BROADWELL_G, X86_STEPPING_ANY, SRBDS), | |
1105 | VULNBL_INTEL_STEPPINGS(BROADWELL, X86_STEPPING_ANY, SRBDS), | |
1106 | VULNBL_INTEL_STEPPINGS(SKYLAKE_L, X86_STEPPING_ANY, SRBDS), | |
1107 | VULNBL_INTEL_STEPPINGS(SKYLAKE, X86_STEPPING_ANY, SRBDS), | |
1108 | VULNBL_INTEL_STEPPINGS(KABYLAKE_L, X86_STEPPINGS(0x0, 0xC), SRBDS), | |
1109 | VULNBL_INTEL_STEPPINGS(KABYLAKE, X86_STEPPINGS(0x0, 0xD), SRBDS), | |
1110 | {} | |
1111 | }; | |
1112 | ||
93920f61 | 1113 | static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which) |
36ad3513 | 1114 | { |
93920f61 | 1115 | const struct x86_cpu_id *m = x86_match_cpu(table); |
c456442c | 1116 | |
36ad3513 TG |
1117 | return m && !!(m->driver_data & which); |
1118 | } | |
17dbca11 | 1119 | |
286836a7 | 1120 | u64 x86_read_arch_cap_msr(void) |
fec9434a DW |
1121 | { |
1122 | u64 ia32_cap = 0; | |
1123 | ||
286836a7 PG |
1124 | if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) |
1125 | rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); | |
1126 | ||
1127 | return ia32_cap; | |
1128 | } | |
1129 | ||
1130 | static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) | |
1131 | { | |
1132 | u64 ia32_cap = x86_read_arch_cap_msr(); | |
1133 | ||
db4d30fb | 1134 | /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */ |
93920f61 MG |
1135 | if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) && |
1136 | !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO)) | |
db4d30fb VT |
1137 | setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT); |
1138 | ||
93920f61 | 1139 | if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION)) |
8ecc4979 DB |
1140 | return; |
1141 | ||
1142 | setup_force_cpu_bug(X86_BUG_SPECTRE_V1); | |
1e41a766 | 1143 | |
93920f61 | 1144 | if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2)) |
1e41a766 | 1145 | setup_force_cpu_bug(X86_BUG_SPECTRE_V2); |
8ecc4979 | 1146 | |
93920f61 MG |
1147 | if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) && |
1148 | !(ia32_cap & ARCH_CAP_SSB_NO) && | |
24809860 | 1149 | !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) |
c456442c KRW |
1150 | setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); |
1151 | ||
706d5168 SP |
1152 | if (ia32_cap & ARCH_CAP_IBRS_ALL) |
1153 | setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); | |
1154 | ||
93920f61 MG |
1155 | if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) && |
1156 | !(ia32_cap & ARCH_CAP_MDS_NO)) { | |
ed5194c2 | 1157 | setup_force_cpu_bug(X86_BUG_MDS); |
93920f61 | 1158 | if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY)) |
e261f209 TG |
1159 | setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); |
1160 | } | |
ed5194c2 | 1161 | |
93920f61 | 1162 | if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS)) |
f36cf386 TG |
1163 | setup_force_cpu_bug(X86_BUG_SWAPGS); |
1164 | ||
1b42f017 PG |
1165 | /* |
1166 | * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when: | |
1167 | * - TSX is supported or | |
1168 | * - TSX_CTRL is present | |
1169 | * | |
1170 | * TSX_CTRL check is needed for cases when TSX could be disabled before | |
1171 | * the kernel boot e.g. kexec. | |
1172 | * TSX_CTRL check alone is not sufficient for cases when the microcode | |
1173 | * update is not present or running as guest that don't get TSX_CTRL. | |
1174 | */ | |
1175 | if (!(ia32_cap & ARCH_CAP_TAA_NO) && | |
1176 | (cpu_has(c, X86_FEATURE_RTM) || | |
1177 | (ia32_cap & ARCH_CAP_TSX_CTRL_MSR))) | |
1178 | setup_force_cpu_bug(X86_BUG_TAA); | |
1179 | ||
7e5b3c26 MG |
1180 | /* |
1181 | * SRBDS affects CPUs which support RDRAND or RDSEED and are listed | |
1182 | * in the vulnerability blacklist. | |
1183 | */ | |
1184 | if ((cpu_has(c, X86_FEATURE_RDRAND) || | |
1185 | cpu_has(c, X86_FEATURE_RDSEED)) && | |
1186 | cpu_matches(cpu_vuln_blacklist, SRBDS)) | |
1187 | setup_force_cpu_bug(X86_BUG_SRBDS); | |
1188 | ||
93920f61 | 1189 | if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN)) |
4a28bfe3 | 1190 | return; |
fec9434a | 1191 | |
fec9434a DW |
1192 | /* Rogue Data Cache Load? No! */ |
1193 | if (ia32_cap & ARCH_CAP_RDCL_NO) | |
4a28bfe3 | 1194 | return; |
fec9434a | 1195 | |
4a28bfe3 | 1196 | setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); |
17dbca11 | 1197 | |
93920f61 | 1198 | if (cpu_matches(cpu_vuln_whitelist, NO_L1TF)) |
17dbca11 AK |
1199 | return; |
1200 | ||
1201 | setup_force_cpu_bug(X86_BUG_L1TF); | |
fec9434a DW |
1202 | } |
1203 | ||
8990cac6 PT |
1204 | /* |
1205 | * The NOPL instruction is supposed to exist on all CPUs of family >= 6; | |
1206 | * unfortunately, that's not true in practice because of early VIA | |
1207 | * chips and (more importantly) broken virtualizers that are not easy | |
1208 | * to detect. In the latter case it doesn't even *fail* reliably, so | |
1209 | * probing for it doesn't even work. Disable it completely on 32-bit | |
1210 | * unless we can find a reliable way to detect all the broken cases. | |
1211 | * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). | |
1212 | */ | |
9b3661cd | 1213 | static void detect_nopl(void) |
8990cac6 PT |
1214 | { |
1215 | #ifdef CONFIG_X86_32 | |
9b3661cd | 1216 | setup_clear_cpu_cap(X86_FEATURE_NOPL); |
8990cac6 | 1217 | #else |
9b3661cd | 1218 | setup_force_cpu_cap(X86_FEATURE_NOPL); |
8990cac6 PT |
1219 | #endif |
1220 | } | |
1221 | ||
34048c9e PC |
1222 | /* |
1223 | * Do minimum CPU detection early. | |
1224 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
1225 | * cache alignment. | |
1226 | * The others are not touched to avoid unwanted side effects. | |
1227 | * | |
a1652bb8 JD |
1228 | * WARNING: this function is only called on the boot CPU. Don't add code |
1229 | * here that is supposed to run on all CPUs. | |
34048c9e | 1230 | */ |
3da99c97 | 1231 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 1232 | { |
6627d242 YL |
1233 | #ifdef CONFIG_X86_64 |
1234 | c->x86_clflush_size = 64; | |
13c6c532 JB |
1235 | c->x86_phys_bits = 36; |
1236 | c->x86_virt_bits = 48; | |
6627d242 | 1237 | #else |
d4387bd3 | 1238 | c->x86_clflush_size = 32; |
13c6c532 JB |
1239 | c->x86_phys_bits = 32; |
1240 | c->x86_virt_bits = 32; | |
6627d242 | 1241 | #endif |
0a488a53 | 1242 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 1243 | |
0e96f31e | 1244 | memset(&c->x86_capability, 0, sizeof(c->x86_capability)); |
0a488a53 | 1245 | c->extended_cpuid_level = 0; |
d7cd5611 | 1246 | |
2893cc8f MW |
1247 | if (!have_cpuid_p()) |
1248 | identify_cpu_without_cpuid(c); | |
1249 | ||
aef93c8b | 1250 | /* cyrix could have cpuid enabled via c_identify()*/ |
05fb3c19 AL |
1251 | if (have_cpuid_p()) { |
1252 | cpu_detect(c); | |
1253 | get_cpu_vendor(c); | |
1254 | get_cpu_cap(c); | |
d94a155c | 1255 | get_cpu_address_sizes(c); |
78d1b296 | 1256 | setup_force_cpu_cap(X86_FEATURE_CPUID); |
d7cd5611 | 1257 | |
05fb3c19 AL |
1258 | if (this_cpu->c_early_init) |
1259 | this_cpu->c_early_init(c); | |
12cf105c | 1260 | |
05fb3c19 AL |
1261 | c->cpu_index = 0; |
1262 | filter_cpuid_features(c, false); | |
093af8d7 | 1263 | |
05fb3c19 AL |
1264 | if (this_cpu->c_bsp_init) |
1265 | this_cpu->c_bsp_init(c); | |
78d1b296 | 1266 | } else { |
78d1b296 | 1267 | setup_clear_cpu_cap(X86_FEATURE_CPUID); |
05fb3c19 | 1268 | } |
c3b83598 BP |
1269 | |
1270 | setup_force_cpu_cap(X86_FEATURE_ALWAYS); | |
a89f040f | 1271 | |
4a28bfe3 | 1272 | cpu_set_bug_bits(c); |
99c6fa25 | 1273 | |
6650cdd9 PZI |
1274 | cpu_set_core_cap_bits(c); |
1275 | ||
db52ef74 | 1276 | fpu__init_system(c); |
b8b7abae AL |
1277 | |
1278 | #ifdef CONFIG_X86_32 | |
1279 | /* | |
1280 | * Regardless of whether PCID is enumerated, the SDM says | |
1281 | * that it can't be enabled in 32-bit mode. | |
1282 | */ | |
1283 | setup_clear_cpu_cap(X86_FEATURE_PCID); | |
1284 | #endif | |
372fddf7 KS |
1285 | |
1286 | /* | |
1287 | * Later in the boot process pgtable_l5_enabled() relies on | |
1288 | * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not | |
1289 | * enabled by this point we need to clear the feature bit to avoid | |
1290 | * false-positives at the later stage. | |
1291 | * | |
1292 | * pgtable_l5_enabled() can be false here for several reasons: | |
1293 | * - 5-level paging is disabled compile-time; | |
1294 | * - it's 32-bit kernel; | |
1295 | * - machine doesn't support 5-level paging; | |
1296 | * - user specified 'no5lvl' in kernel command line. | |
1297 | */ | |
1298 | if (!pgtable_l5_enabled()) | |
1299 | setup_clear_cpu_cap(X86_FEATURE_LA57); | |
8990cac6 | 1300 | |
9b3661cd | 1301 | detect_nopl(); |
d7cd5611 RR |
1302 | } |
1303 | ||
9d31d35b YL |
1304 | void __init early_cpu_init(void) |
1305 | { | |
02dde8b4 | 1306 | const struct cpu_dev *const *cdev; |
10a434fc YL |
1307 | int count = 0; |
1308 | ||
ac23f253 | 1309 | #ifdef CONFIG_PROCESSOR_SELECT |
1b74dde7 | 1310 | pr_info("KERNEL supported cpus:\n"); |
31c997ca IM |
1311 | #endif |
1312 | ||
10a434fc | 1313 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { |
02dde8b4 | 1314 | const struct cpu_dev *cpudev = *cdev; |
9d31d35b | 1315 | |
10a434fc YL |
1316 | if (count >= X86_VENDOR_NUM) |
1317 | break; | |
1318 | cpu_devs[count] = cpudev; | |
1319 | count++; | |
1320 | ||
ac23f253 | 1321 | #ifdef CONFIG_PROCESSOR_SELECT |
31c997ca IM |
1322 | { |
1323 | unsigned int j; | |
1324 | ||
1325 | for (j = 0; j < 2; j++) { | |
1326 | if (!cpudev->c_ident[j]) | |
1327 | continue; | |
1b74dde7 | 1328 | pr_info(" %s %s\n", cpudev->c_vendor, |
31c997ca IM |
1329 | cpudev->c_ident[j]); |
1330 | } | |
10a434fc | 1331 | } |
0388423d | 1332 | #endif |
10a434fc | 1333 | } |
9d31d35b | 1334 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 1335 | } |
093af8d7 | 1336 | |
7a5d6704 AL |
1337 | static void detect_null_seg_behavior(struct cpuinfo_x86 *c) |
1338 | { | |
1339 | #ifdef CONFIG_X86_64 | |
58a5aac5 | 1340 | /* |
7a5d6704 AL |
1341 | * Empirically, writing zero to a segment selector on AMD does |
1342 | * not clear the base, whereas writing zero to a segment | |
1343 | * selector on Intel does clear the base. Intel's behavior | |
1344 | * allows slightly faster context switches in the common case | |
1345 | * where GS is unused by the prev and next threads. | |
58a5aac5 | 1346 | * |
7a5d6704 AL |
1347 | * Since neither vendor documents this anywhere that I can see, |
1348 | * detect it directly instead of hardcoding the choice by | |
1349 | * vendor. | |
1350 | * | |
1351 | * I've designated AMD's behavior as the "bug" because it's | |
1352 | * counterintuitive and less friendly. | |
58a5aac5 | 1353 | */ |
7a5d6704 AL |
1354 | |
1355 | unsigned long old_base, tmp; | |
1356 | rdmsrl(MSR_FS_BASE, old_base); | |
1357 | wrmsrl(MSR_FS_BASE, 1); | |
1358 | loadsegment(fs, 0); | |
1359 | rdmsrl(MSR_FS_BASE, tmp); | |
1360 | if (tmp != 0) | |
1361 | set_cpu_bug(c, X86_BUG_NULL_SEG); | |
1362 | wrmsrl(MSR_FS_BASE, old_base); | |
366d4a43 | 1363 | #endif |
d7cd5611 RR |
1364 | } |
1365 | ||
148f9bb8 | 1366 | static void generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 1367 | { |
aef93c8b | 1368 | c->extended_cpuid_level = 0; |
1da177e4 | 1369 | |
3da99c97 | 1370 | if (!have_cpuid_p()) |
aef93c8b | 1371 | identify_cpu_without_cpuid(c); |
1d67953f | 1372 | |
aef93c8b | 1373 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 1374 | if (!have_cpuid_p()) |
aef93c8b | 1375 | return; |
1da177e4 | 1376 | |
3da99c97 | 1377 | cpu_detect(c); |
1da177e4 | 1378 | |
3da99c97 | 1379 | get_cpu_vendor(c); |
1da177e4 | 1380 | |
3da99c97 | 1381 | get_cpu_cap(c); |
1da177e4 | 1382 | |
d94a155c KS |
1383 | get_cpu_address_sizes(c); |
1384 | ||
3da99c97 YL |
1385 | if (c->cpuid_level >= 0x00000001) { |
1386 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e | 1387 | #ifdef CONFIG_X86_32 |
c8e56d20 | 1388 | # ifdef CONFIG_SMP |
cb8cc442 | 1389 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 1390 | # else |
3da99c97 | 1391 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
1392 | # endif |
1393 | #endif | |
b89d3b3e | 1394 | c->phys_proc_id = c->initial_apicid; |
3da99c97 | 1395 | } |
1da177e4 | 1396 | |
1b05d60d | 1397 | get_model_name(c); /* Default name */ |
1da177e4 | 1398 | |
7a5d6704 | 1399 | detect_null_seg_behavior(c); |
0230bb03 AL |
1400 | |
1401 | /* | |
1402 | * ESPFIX is a strange bug. All real CPUs have it. Paravirt | |
1403 | * systems that run Linux at CPL > 0 may or may not have the | |
1404 | * issue, but, even if they have the issue, there's absolutely | |
1405 | * nothing we can do about it because we can't use the real IRET | |
1406 | * instruction. | |
1407 | * | |
1408 | * NB: For the time being, only 32-bit kernels support | |
1409 | * X86_BUG_ESPFIX as such. 64-bit kernels directly choose | |
1410 | * whether to apply espfix using paravirt hooks. If any | |
1411 | * non-paravirt system ever shows up that does *not* have the | |
1412 | * ESPFIX issue, we can change this. | |
1413 | */ | |
1414 | #ifdef CONFIG_X86_32 | |
9bad5658 | 1415 | # ifdef CONFIG_PARAVIRT_XXL |
0230bb03 AL |
1416 | do { |
1417 | extern void native_iret(void); | |
5c83511b | 1418 | if (pv_ops.cpu.iret == native_iret) |
0230bb03 AL |
1419 | set_cpu_bug(c, X86_BUG_ESPFIX); |
1420 | } while (0); | |
1421 | # else | |
1422 | set_cpu_bug(c, X86_BUG_ESPFIX); | |
1423 | # endif | |
1424 | #endif | |
1da177e4 | 1425 | } |
1da177e4 | 1426 | |
d49597fd | 1427 | /* |
9d85eb91 TG |
1428 | * Validate that ACPI/mptables have the same information about the |
1429 | * effective APIC id and update the package map. | |
d49597fd | 1430 | */ |
9d85eb91 | 1431 | static void validate_apic_and_package_id(struct cpuinfo_x86 *c) |
d49597fd TG |
1432 | { |
1433 | #ifdef CONFIG_SMP | |
9d85eb91 | 1434 | unsigned int apicid, cpu = smp_processor_id(); |
d49597fd TG |
1435 | |
1436 | apicid = apic->cpu_present_to_apicid(cpu); | |
d49597fd | 1437 | |
9d85eb91 TG |
1438 | if (apicid != c->apicid) { |
1439 | pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", | |
d49597fd | 1440 | cpu, apicid, c->initial_apicid); |
d49597fd | 1441 | } |
9d85eb91 | 1442 | BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); |
212bf4fd | 1443 | BUG_ON(topology_update_die_map(c->cpu_die_id, cpu)); |
d49597fd TG |
1444 | #else |
1445 | c->logical_proc_id = 0; | |
1446 | #endif | |
1447 | } | |
1448 | ||
1da177e4 LT |
1449 | /* |
1450 | * This does the hard work of actually picking apart the CPU stuff... | |
1451 | */ | |
148f9bb8 | 1452 | static void identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
1453 | { |
1454 | int i; | |
1455 | ||
1456 | c->loops_per_jiffy = loops_per_jiffy; | |
24dbc600 | 1457 | c->x86_cache_size = 0; |
1da177e4 | 1458 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
b399151c | 1459 | c->x86_model = c->x86_stepping = 0; /* So far unknown... */ |
1da177e4 LT |
1460 | c->x86_vendor_id[0] = '\0'; /* Unset */ |
1461 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 1462 | c->x86_max_cores = 1; |
102bbe3a | 1463 | c->x86_coreid_bits = 0; |
79a8b9aa | 1464 | c->cu_id = 0xff; |
11fdd252 | 1465 | #ifdef CONFIG_X86_64 |
102bbe3a | 1466 | c->x86_clflush_size = 64; |
13c6c532 JB |
1467 | c->x86_phys_bits = 36; |
1468 | c->x86_virt_bits = 48; | |
102bbe3a YL |
1469 | #else |
1470 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 1471 | c->x86_clflush_size = 32; |
13c6c532 JB |
1472 | c->x86_phys_bits = 32; |
1473 | c->x86_virt_bits = 32; | |
102bbe3a YL |
1474 | #endif |
1475 | c->x86_cache_alignment = c->x86_clflush_size; | |
0e96f31e | 1476 | memset(&c->x86_capability, 0, sizeof(c->x86_capability)); |
b47ce1fe SC |
1477 | #ifdef CONFIG_X86_VMX_FEATURE_NAMES |
1478 | memset(&c->vmx_capability, 0, sizeof(c->vmx_capability)); | |
1479 | #endif | |
1da177e4 | 1480 | |
1da177e4 LT |
1481 | generic_identify(c); |
1482 | ||
3898534d | 1483 | if (this_cpu->c_identify) |
1da177e4 LT |
1484 | this_cpu->c_identify(c); |
1485 | ||
6a6256f9 | 1486 | /* Clear/Set all flags overridden by options, after probe */ |
8bf1ebca | 1487 | apply_forced_caps(c); |
2759c328 | 1488 | |
102bbe3a | 1489 | #ifdef CONFIG_X86_64 |
cb8cc442 | 1490 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
1491 | #endif |
1492 | ||
1da177e4 LT |
1493 | /* |
1494 | * Vendor-specific initialization. In this section we | |
1495 | * canonicalize the feature flags, meaning if there are | |
1496 | * features a certain CPU supports which CPUID doesn't | |
1497 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
1498 | * we handle them here. | |
1499 | * | |
1500 | * At the end of this section, c->x86_capability better | |
1501 | * indicate the features this CPU genuinely supports! | |
1502 | */ | |
1503 | if (this_cpu->c_init) | |
1504 | this_cpu->c_init(c); | |
1505 | ||
1506 | /* Disable the PN if appropriate */ | |
1507 | squash_the_stupid_serial_number(c); | |
1508 | ||
aa35f896 | 1509 | /* Set up SMEP/SMAP/UMIP */ |
b2cc2a07 PA |
1510 | setup_smep(c); |
1511 | setup_smap(c); | |
aa35f896 | 1512 | setup_umip(c); |
b2cc2a07 | 1513 | |
dd649bd0 | 1514 | /* Enable FSGSBASE instructions if available. */ |
b745cfba AL |
1515 | if (cpu_has(c, X86_FEATURE_FSGSBASE)) |
1516 | cr4_set_bits(X86_CR4_FSGSBASE); | |
dd649bd0 | 1517 | |
1da177e4 | 1518 | /* |
0f3fa48a IM |
1519 | * The vendor-specific functions might have changed features. |
1520 | * Now we do "generic changes." | |
1da177e4 LT |
1521 | */ |
1522 | ||
b38b0665 PA |
1523 | /* Filter out anything that depends on CPUID levels we don't have */ |
1524 | filter_cpuid_features(c, true); | |
1525 | ||
1da177e4 | 1526 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 1527 | if (!c->x86_model_id[0]) { |
02dde8b4 | 1528 | const char *p; |
1da177e4 | 1529 | p = table_lookup_model(c); |
34048c9e | 1530 | if (p) |
1da177e4 LT |
1531 | strcpy(c->x86_model_id, p); |
1532 | else | |
1533 | /* Last resort... */ | |
1534 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 1535 | c->x86, c->x86_model); |
1da177e4 LT |
1536 | } |
1537 | ||
102bbe3a YL |
1538 | #ifdef CONFIG_X86_64 |
1539 | detect_ht(c); | |
1540 | #endif | |
1541 | ||
49d859d7 | 1542 | x86_init_rdrand(c); |
06976945 | 1543 | setup_pku(c); |
3e0c3737 YL |
1544 | |
1545 | /* | |
6a6256f9 | 1546 | * Clear/Set all flags overridden by options, need do it |
3e0c3737 YL |
1547 | * before following smp all cpus cap AND. |
1548 | */ | |
8bf1ebca | 1549 | apply_forced_caps(c); |
3e0c3737 | 1550 | |
1da177e4 LT |
1551 | /* |
1552 | * On SMP, boot_cpu_data holds the common feature set between | |
1553 | * all CPUs; so make sure that we indicate which features are | |
1554 | * common between the CPUs. The first time this routine gets | |
1555 | * executed, c == &boot_cpu_data. | |
1556 | */ | |
34048c9e | 1557 | if (c != &boot_cpu_data) { |
1da177e4 | 1558 | /* AND the already accumulated flags with these */ |
9d31d35b | 1559 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 | 1560 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
65fc985b BP |
1561 | |
1562 | /* OR, i.e. replicate the bug flags */ | |
1563 | for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) | |
1564 | c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; | |
1da177e4 LT |
1565 | } |
1566 | ||
1567 | /* Init Machine Check Exception if available. */ | |
5e09954a | 1568 | mcheck_cpu_init(c); |
30d432df AK |
1569 | |
1570 | select_idle_routine(c); | |
102bbe3a | 1571 | |
de2d9445 | 1572 | #ifdef CONFIG_NUMA |
102bbe3a YL |
1573 | numa_add_cpu(smp_processor_id()); |
1574 | #endif | |
a6c4e076 | 1575 | } |
31ab269a | 1576 | |
8b6c0ab1 IM |
1577 | /* |
1578 | * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions | |
1579 | * on 32-bit kernels: | |
1580 | */ | |
cfda7bb9 AL |
1581 | #ifdef CONFIG_X86_32 |
1582 | void enable_sep_cpu(void) | |
1583 | { | |
8b6c0ab1 IM |
1584 | struct tss_struct *tss; |
1585 | int cpu; | |
cfda7bb9 | 1586 | |
b3edfda4 BP |
1587 | if (!boot_cpu_has(X86_FEATURE_SEP)) |
1588 | return; | |
1589 | ||
8b6c0ab1 | 1590 | cpu = get_cpu(); |
c482feef | 1591 | tss = &per_cpu(cpu_tss_rw, cpu); |
8b6c0ab1 | 1592 | |
8b6c0ab1 | 1593 | /* |
cf9328cc AL |
1594 | * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- |
1595 | * see the big comment in struct x86_hw_tss's definition. | |
8b6c0ab1 | 1596 | */ |
cfda7bb9 AL |
1597 | |
1598 | tss->x86_tss.ss1 = __KERNEL_CS; | |
8b6c0ab1 | 1599 | wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); |
4fe2d8b1 | 1600 | wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); |
4c8cd0c5 | 1601 | wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); |
8b6c0ab1 | 1602 | |
cfda7bb9 AL |
1603 | put_cpu(); |
1604 | } | |
e04d645f GC |
1605 | #endif |
1606 | ||
a6c4e076 JF |
1607 | void __init identify_boot_cpu(void) |
1608 | { | |
1609 | identify_cpu(&boot_cpu_data); | |
102bbe3a | 1610 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1611 | sysenter_setup(); |
6fe940d6 | 1612 | enable_sep_cpu(); |
102bbe3a | 1613 | #endif |
5b556332 | 1614 | cpu_detect_tlb(&boot_cpu_data); |
873d50d5 | 1615 | setup_cr_pinning(); |
95c5824f PG |
1616 | |
1617 | tsx_init(); | |
a6c4e076 | 1618 | } |
3b520b23 | 1619 | |
148f9bb8 | 1620 | void identify_secondary_cpu(struct cpuinfo_x86 *c) |
a6c4e076 JF |
1621 | { |
1622 | BUG_ON(c == &boot_cpu_data); | |
1623 | identify_cpu(c); | |
102bbe3a | 1624 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1625 | enable_sep_cpu(); |
102bbe3a | 1626 | #endif |
a6c4e076 | 1627 | mtrr_ap_init(); |
9d85eb91 | 1628 | validate_apic_and_package_id(c); |
77243971 | 1629 | x86_spec_ctrl_setup_ap(); |
7e5b3c26 | 1630 | update_srbds_msr(); |
1da177e4 LT |
1631 | } |
1632 | ||
191679fd AK |
1633 | static __init int setup_noclflush(char *arg) |
1634 | { | |
840d2830 | 1635 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); |
da4aaa7d | 1636 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); |
191679fd AK |
1637 | return 1; |
1638 | } | |
1639 | __setup("noclflush", setup_noclflush); | |
1640 | ||
148f9bb8 | 1641 | void print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 | 1642 | { |
02dde8b4 | 1643 | const char *vendor = NULL; |
1da177e4 | 1644 | |
0f3fa48a | 1645 | if (c->x86_vendor < X86_VENDOR_NUM) { |
1da177e4 | 1646 | vendor = this_cpu->c_vendor; |
0f3fa48a IM |
1647 | } else { |
1648 | if (c->cpuid_level >= 0) | |
1649 | vendor = c->x86_vendor_id; | |
1650 | } | |
1da177e4 | 1651 | |
bd32a8cf | 1652 | if (vendor && !strstr(c->x86_model_id, vendor)) |
1b74dde7 | 1653 | pr_cont("%s ", vendor); |
1da177e4 | 1654 | |
9d31d35b | 1655 | if (c->x86_model_id[0]) |
1b74dde7 | 1656 | pr_cont("%s", c->x86_model_id); |
1da177e4 | 1657 | else |
1b74dde7 | 1658 | pr_cont("%d86", c->x86); |
1da177e4 | 1659 | |
1b74dde7 | 1660 | pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); |
924e101a | 1661 | |
b399151c JZ |
1662 | if (c->x86_stepping || c->cpuid_level >= 0) |
1663 | pr_cont(", stepping: 0x%x)\n", c->x86_stepping); | |
1da177e4 | 1664 | else |
1b74dde7 | 1665 | pr_cont(")\n"); |
1da177e4 LT |
1666 | } |
1667 | ||
0c2a3913 AK |
1668 | /* |
1669 | * clearcpuid= was already parsed in fpu__init_parse_early_param. | |
1670 | * But we need to keep a dummy __setup around otherwise it would | |
1671 | * show up as an environment variable for init. | |
1672 | */ | |
1673 | static __init int setup_clearcpuid(char *arg) | |
ac72e788 | 1674 | { |
ac72e788 AK |
1675 | return 1; |
1676 | } | |
0c2a3913 | 1677 | __setup("clearcpuid=", setup_clearcpuid); |
ac72e788 | 1678 | |
d5494d4f | 1679 | #ifdef CONFIG_X86_64 |
e6401c13 AL |
1680 | DEFINE_PER_CPU_FIRST(struct fixed_percpu_data, |
1681 | fixed_percpu_data) __aligned(PAGE_SIZE) __visible; | |
1682 | EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data); | |
0f3fa48a | 1683 | |
bdf977b3 | 1684 | /* |
a7fcf28d AL |
1685 | * The following percpu variables are hot. Align current_task to |
1686 | * cacheline size such that they fall in the same cacheline. | |
bdf977b3 TH |
1687 | */ |
1688 | DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = | |
1689 | &init_task; | |
1690 | EXPORT_PER_CPU_SYMBOL(current_task); | |
d5494d4f | 1691 | |
e6401c13 | 1692 | DEFINE_PER_CPU(struct irq_stack *, hardirq_stack_ptr); |
277d5b40 | 1693 | DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; |
d5494d4f | 1694 | |
c2daa3be PZ |
1695 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1696 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
1697 | ||
d5494d4f YL |
1698 | /* May not be marked __init: used by software suspend */ |
1699 | void syscall_init(void) | |
1da177e4 | 1700 | { |
31ac34ca | 1701 | wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); |
bf904d27 | 1702 | wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); |
d56fe4bf IM |
1703 | |
1704 | #ifdef CONFIG_IA32_EMULATION | |
47edb651 | 1705 | wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); |
a76c7f46 | 1706 | /* |
487d1edb DV |
1707 | * This only works on Intel CPUs. |
1708 | * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. | |
1709 | * This does not cause SYSENTER to jump to the wrong location, because | |
1710 | * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). | |
a76c7f46 DV |
1711 | */ |
1712 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); | |
8e6b65a1 | 1713 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, |
1714 | (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); | |
4c8cd0c5 | 1715 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); |
d56fe4bf | 1716 | #else |
47edb651 | 1717 | wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); |
6b51311c | 1718 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); |
d56fe4bf IM |
1719 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); |
1720 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); | |
d5494d4f | 1721 | #endif |
03ae5768 | 1722 | |
d5494d4f YL |
1723 | /* Flags to clear on syscall */ |
1724 | wrmsrl(MSR_SYSCALL_MASK, | |
63bcff2a | 1725 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| |
8c7aa698 | 1726 | X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); |
1da177e4 | 1727 | } |
62111195 | 1728 | |
0f3fa48a | 1729 | #else /* CONFIG_X86_64 */ |
d5494d4f | 1730 | |
bdf977b3 TH |
1731 | DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; |
1732 | EXPORT_PER_CPU_SYMBOL(current_task); | |
c2daa3be PZ |
1733 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1734 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
bdf977b3 | 1735 | |
a7fcf28d AL |
1736 | /* |
1737 | * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find | |
1738 | * the top of the kernel stack. Use an extra percpu variable to track the | |
1739 | * top of the kernel stack directly. | |
1740 | */ | |
1741 | DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = | |
1742 | (unsigned long)&init_thread_union + THREAD_SIZE; | |
1743 | EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); | |
1744 | ||
050e9baa | 1745 | #ifdef CONFIG_STACKPROTECTOR |
53f82452 | 1746 | DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); |
60a5317f | 1747 | #endif |
d5494d4f | 1748 | |
0f3fa48a | 1749 | #endif /* CONFIG_X86_64 */ |
c5413fbe | 1750 | |
9766cdbc JSR |
1751 | /* |
1752 | * Clear all 6 debug registers: | |
1753 | */ | |
1754 | static void clear_all_debug_regs(void) | |
1755 | { | |
1756 | int i; | |
1757 | ||
1758 | for (i = 0; i < 8; i++) { | |
1759 | /* Ignore db4, db5 */ | |
1760 | if ((i == 4) || (i == 5)) | |
1761 | continue; | |
1762 | ||
1763 | set_debugreg(0, i); | |
1764 | } | |
1765 | } | |
c5413fbe | 1766 | |
0bb9fef9 JW |
1767 | #ifdef CONFIG_KGDB |
1768 | /* | |
1769 | * Restore debug regs if using kgdbwait and you have a kernel debugger | |
1770 | * connection established. | |
1771 | */ | |
1772 | static void dbg_restore_debug_regs(void) | |
1773 | { | |
1774 | if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) | |
1775 | arch_kgdb_ops.correct_hw_break(); | |
1776 | } | |
1777 | #else /* ! CONFIG_KGDB */ | |
1778 | #define dbg_restore_debug_regs() | |
1779 | #endif /* ! CONFIG_KGDB */ | |
1780 | ||
ce4b1b16 IM |
1781 | static void wait_for_master_cpu(int cpu) |
1782 | { | |
1783 | #ifdef CONFIG_SMP | |
1784 | /* | |
1785 | * wait for ACK from master CPU before continuing | |
1786 | * with AP initialization | |
1787 | */ | |
1788 | WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); | |
1789 | while (!cpumask_test_cpu(cpu, cpu_callout_mask)) | |
1790 | cpu_relax(); | |
1791 | #endif | |
1792 | } | |
1793 | ||
b2e2ba57 | 1794 | #ifdef CONFIG_X86_64 |
505b7899 | 1795 | static inline void setup_getcpu(int cpu) |
b2e2ba57 | 1796 | { |
22245bdf | 1797 | unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu)); |
b2e2ba57 CB |
1798 | struct desc_struct d = { }; |
1799 | ||
67e87d43 | 1800 | if (boot_cpu_has(X86_FEATURE_RDTSCP)) |
b2e2ba57 CB |
1801 | write_rdtscp_aux(cpudata); |
1802 | ||
1803 | /* Store CPU and node number in limit. */ | |
1804 | d.limit0 = cpudata; | |
1805 | d.limit1 = cpudata >> 16; | |
1806 | ||
1807 | d.type = 5; /* RO data, expand down, accessed */ | |
1808 | d.dpl = 3; /* Visible to user code */ | |
1809 | d.s = 1; /* Not a system segment */ | |
1810 | d.p = 1; /* Present */ | |
1811 | d.d = 1; /* 32-bit */ | |
1812 | ||
22245bdf | 1813 | write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S); |
b2e2ba57 | 1814 | } |
505b7899 TG |
1815 | |
1816 | static inline void ucode_cpu_init(int cpu) | |
1817 | { | |
1818 | if (cpu) | |
1819 | load_ucode_ap(); | |
1820 | } | |
1821 | ||
1822 | static inline void tss_setup_ist(struct tss_struct *tss) | |
1823 | { | |
1824 | /* Set up the per-CPU TSS IST stacks */ | |
1825 | tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF); | |
1826 | tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI); | |
1827 | tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB); | |
1828 | tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE); | |
1829 | } | |
1830 | ||
505b7899 TG |
1831 | #else /* CONFIG_X86_64 */ |
1832 | ||
1833 | static inline void setup_getcpu(int cpu) { } | |
1834 | ||
1835 | static inline void ucode_cpu_init(int cpu) | |
1836 | { | |
1837 | show_ucode_info_early(); | |
1838 | } | |
1839 | ||
1840 | static inline void tss_setup_ist(struct tss_struct *tss) { } | |
1841 | ||
505b7899 | 1842 | #endif /* !CONFIG_X86_64 */ |
b2e2ba57 | 1843 | |
111e7b15 TG |
1844 | static inline void tss_setup_io_bitmap(struct tss_struct *tss) |
1845 | { | |
1846 | tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID; | |
1847 | ||
1848 | #ifdef CONFIG_X86_IOPL_IOPERM | |
1849 | tss->io_bitmap.prev_max = 0; | |
1850 | tss->io_bitmap.prev_sequence = 0; | |
1851 | memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap)); | |
1852 | /* | |
1853 | * Invalidate the extra array entry past the end of the all | |
1854 | * permission bitmap as required by the hardware. | |
1855 | */ | |
1856 | tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL; | |
b2e2ba57 | 1857 | #endif |
111e7b15 | 1858 | } |
b2e2ba57 | 1859 | |
d2cbcc49 RR |
1860 | /* |
1861 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1862 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1863 | * and IDT. We reload them nevertheless, this function acts as a | |
1864 | * 'CPU state barrier', nothing should get across. | |
1865 | */ | |
148f9bb8 | 1866 | void cpu_init(void) |
1ba76586 | 1867 | { |
505b7899 TG |
1868 | struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); |
1869 | struct task_struct *cur = current; | |
f6ef7322 | 1870 | int cpu = raw_smp_processor_id(); |
1ba76586 | 1871 | |
ce4b1b16 IM |
1872 | wait_for_master_cpu(cpu); |
1873 | ||
505b7899 | 1874 | ucode_cpu_init(cpu); |
0f3fa48a | 1875 | |
e7a22c1e | 1876 | #ifdef CONFIG_NUMA |
27fd185f | 1877 | if (this_cpu_read(numa_node) == 0 && |
e534c7c5 LS |
1878 | early_cpu_to_node(cpu) != NUMA_NO_NODE) |
1879 | set_numa_node(early_cpu_to_node(cpu)); | |
e7a22c1e | 1880 | #endif |
b2e2ba57 | 1881 | setup_getcpu(cpu); |
1ba76586 | 1882 | |
2eaad1fd | 1883 | pr_debug("Initializing CPU#%d\n", cpu); |
1ba76586 | 1884 | |
505b7899 TG |
1885 | if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) || |
1886 | boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE)) | |
1887 | cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
1ba76586 YL |
1888 | |
1889 | /* | |
1890 | * Initialize the per-CPU GDT with the boot GDT, | |
1891 | * and set up the GDT descriptor: | |
1892 | */ | |
552be871 | 1893 | switch_to_new_gdt(cpu); |
cf910e83 | 1894 | load_current_idt(); |
1ba76586 | 1895 | |
505b7899 TG |
1896 | if (IS_ENABLED(CONFIG_X86_64)) { |
1897 | loadsegment(fs, 0); | |
1898 | memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1899 | syscall_init(); | |
1ba76586 | 1900 | |
505b7899 TG |
1901 | wrmsrl(MSR_FS_BASE, 0); |
1902 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1903 | barrier(); | |
1ba76586 | 1904 | |
505b7899 | 1905 | x2apic_setup(); |
1ba76586 YL |
1906 | } |
1907 | ||
f1f10076 | 1908 | mmgrab(&init_mm); |
505b7899 TG |
1909 | cur->active_mm = &init_mm; |
1910 | BUG_ON(cur->mm); | |
72c0098d | 1911 | initialize_tlbstate_and_flush(); |
505b7899 | 1912 | enter_lazy_tlb(&init_mm, cur); |
1ba76586 | 1913 | |
505b7899 TG |
1914 | /* Initialize the TSS. */ |
1915 | tss_setup_ist(tss); | |
111e7b15 | 1916 | tss_setup_io_bitmap(tss); |
72f5e08d | 1917 | set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); |
505b7899 | 1918 | |
1ba76586 | 1919 | load_TR_desc(); |
505b7899 TG |
1920 | /* |
1921 | * sp0 points to the entry trampoline stack regardless of what task | |
1922 | * is running. | |
1923 | */ | |
4fe2d8b1 | 1924 | load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); |
20bb8344 | 1925 | |
37868fe1 | 1926 | load_mm_ldt(&init_mm); |
1ba76586 | 1927 | |
0bb9fef9 JW |
1928 | clear_all_debug_regs(); |
1929 | dbg_restore_debug_regs(); | |
1ba76586 | 1930 | |
dc4e0021 | 1931 | doublefault_init_cpu_tss(); |
505b7899 | 1932 | |
21c4cd10 | 1933 | fpu__init_cpu(); |
1ba76586 | 1934 | |
1ba76586 YL |
1935 | if (is_uv_system()) |
1936 | uv_cpu_init(); | |
69218e47 | 1937 | |
69218e47 | 1938 | load_fixmap_gdt(cpu); |
1ba76586 YL |
1939 | } |
1940 | ||
1008c52c BP |
1941 | /* |
1942 | * The microcode loader calls this upon late microcode load to recheck features, | |
1943 | * only when microcode has been updated. Caller holds microcode_mutex and CPU | |
1944 | * hotplug lock. | |
1945 | */ | |
1946 | void microcode_check(void) | |
1947 | { | |
42ca8082 BP |
1948 | struct cpuinfo_x86 info; |
1949 | ||
1008c52c | 1950 | perf_check_microcode(); |
42ca8082 BP |
1951 | |
1952 | /* Reload CPUID max function as it might've changed. */ | |
1953 | info.cpuid_level = cpuid_eax(0); | |
1954 | ||
1955 | /* | |
1956 | * Copy all capability leafs to pick up the synthetic ones so that | |
1957 | * memcmp() below doesn't fail on that. The ones coming from CPUID will | |
1958 | * get overwritten in get_cpu_cap(). | |
1959 | */ | |
1960 | memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); | |
1961 | ||
1962 | get_cpu_cap(&info); | |
1963 | ||
1964 | if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) | |
1965 | return; | |
1966 | ||
1967 | pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); | |
1968 | pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); | |
1008c52c | 1969 | } |
9c92374b TG |
1970 | |
1971 | /* | |
1972 | * Invoked from core CPU hotplug code after hotplug operations | |
1973 | */ | |
1974 | void arch_smt_update(void) | |
1975 | { | |
1976 | /* Handle the speculative execution misfeatures */ | |
1977 | cpu_bugs_smt_update(); | |
6a1cb5f5 TG |
1978 | /* Check whether IPI broadcasting can be enabled */ |
1979 | apic_smt_update(); | |
9c92374b | 1980 | } |