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Commit | Line | Data |
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f0fc4aff | 1 | #include <linux/bootmem.h> |
9766cdbc | 2 | #include <linux/linkage.h> |
f0fc4aff | 3 | #include <linux/bitops.h> |
9766cdbc | 4 | #include <linux/kernel.h> |
f0fc4aff | 5 | #include <linux/module.h> |
9766cdbc JSR |
6 | #include <linux/percpu.h> |
7 | #include <linux/string.h> | |
1da177e4 | 8 | #include <linux/delay.h> |
9766cdbc JSR |
9 | #include <linux/sched.h> |
10 | #include <linux/init.h> | |
11 | #include <linux/kgdb.h> | |
1da177e4 | 12 | #include <linux/smp.h> |
9766cdbc JSR |
13 | #include <linux/io.h> |
14 | ||
15 | #include <asm/stackprotector.h> | |
cdd6c482 | 16 | #include <asm/perf_event.h> |
1da177e4 | 17 | #include <asm/mmu_context.h> |
9766cdbc JSR |
18 | #include <asm/hypervisor.h> |
19 | #include <asm/processor.h> | |
20 | #include <asm/sections.h> | |
8bdbd962 AC |
21 | #include <linux/topology.h> |
22 | #include <linux/cpumask.h> | |
9766cdbc JSR |
23 | #include <asm/pgtable.h> |
24 | #include <asm/atomic.h> | |
25 | #include <asm/proto.h> | |
26 | #include <asm/setup.h> | |
27 | #include <asm/apic.h> | |
28 | #include <asm/desc.h> | |
29 | #include <asm/i387.h> | |
27b07da7 | 30 | #include <asm/mtrr.h> |
8bdbd962 | 31 | #include <linux/numa.h> |
9766cdbc JSR |
32 | #include <asm/asm.h> |
33 | #include <asm/cpu.h> | |
a03a3e28 | 34 | #include <asm/mce.h> |
9766cdbc | 35 | #include <asm/msr.h> |
8d4a4300 | 36 | #include <asm/pat.h> |
e641f5f5 IM |
37 | |
38 | #ifdef CONFIG_X86_LOCAL_APIC | |
bdbcdd48 | 39 | #include <asm/uv/uv.h> |
1da177e4 LT |
40 | #endif |
41 | ||
42 | #include "cpu.h" | |
43 | ||
c2d1cec1 | 44 | /* all of these masks are initialized in setup_cpu_local_masks() */ |
c2d1cec1 | 45 | cpumask_var_t cpu_initialized_mask; |
9766cdbc JSR |
46 | cpumask_var_t cpu_callout_mask; |
47 | cpumask_var_t cpu_callin_mask; | |
c2d1cec1 MT |
48 | |
49 | /* representing cpus for which sibling maps can be computed */ | |
50 | cpumask_var_t cpu_sibling_setup_mask; | |
51 | ||
2f2f52ba | 52 | /* correctly size the local cpu masks */ |
4369f1fb | 53 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
54 | { |
55 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
56 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
57 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
58 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
59 | } | |
60 | ||
e8055139 OZ |
61 | static void __cpuinit default_init(struct cpuinfo_x86 *c) |
62 | { | |
63 | #ifdef CONFIG_X86_64 | |
27c13ece | 64 | cpu_detect_cache_sizes(c); |
e8055139 OZ |
65 | #else |
66 | /* Not much we can do here... */ | |
67 | /* Check if at least it has cpuid */ | |
68 | if (c->cpuid_level == -1) { | |
69 | /* No cpuid. It must be an ancient CPU */ | |
70 | if (c->x86 == 4) | |
71 | strcpy(c->x86_model_id, "486"); | |
72 | else if (c->x86 == 3) | |
73 | strcpy(c->x86_model_id, "386"); | |
74 | } | |
75 | #endif | |
76 | } | |
77 | ||
78 | static const struct cpu_dev __cpuinitconst default_cpu = { | |
79 | .c_init = default_init, | |
80 | .c_vendor = "Unknown", | |
81 | .c_x86_vendor = X86_VENDOR_UNKNOWN, | |
82 | }; | |
83 | ||
84 | static const struct cpu_dev *this_cpu __cpuinitdata = &default_cpu; | |
0a488a53 | 85 | |
06deef89 | 86 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 87 | #ifdef CONFIG_X86_64 |
06deef89 BG |
88 | /* |
89 | * We need valid kernel segments for data and code in long mode too | |
90 | * IRET will check the segment types kkeil 2000/10/28 | |
91 | * Also sysret mandates a special GDT layout | |
92 | * | |
9766cdbc | 93 | * TLS descriptors are currently at a different place compared to i386. |
06deef89 BG |
94 | * Hopefully nobody expects them at a fixed place (Wine?) |
95 | */ | |
1e5de182 AM |
96 | [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), |
97 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), | |
98 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), | |
99 | [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), | |
100 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), | |
101 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), | |
950ad7ff | 102 | #else |
1e5de182 AM |
103 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), |
104 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
105 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), | |
106 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), | |
bf504672 RR |
107 | /* |
108 | * Segments used for calling PnP BIOS have byte granularity. | |
109 | * They code segments and data segments have fixed 64k limits, | |
110 | * the transfer segment sizes are set at run time. | |
111 | */ | |
6842ef0e | 112 | /* 32-bit code */ |
1e5de182 | 113 | [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
6842ef0e | 114 | /* 16-bit code */ |
1e5de182 | 115 | [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 116 | /* 16-bit data */ |
1e5de182 | 117 | [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), |
6842ef0e | 118 | /* 16-bit data */ |
1e5de182 | 119 | [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), |
6842ef0e | 120 | /* 16-bit data */ |
1e5de182 | 121 | [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), |
bf504672 RR |
122 | /* |
123 | * The APM segments have byte granularity and their bases | |
124 | * are set at run time. All have 64k limits. | |
125 | */ | |
6842ef0e | 126 | /* 32-bit code */ |
1e5de182 | 127 | [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
bf504672 | 128 | /* 16-bit code */ |
1e5de182 | 129 | [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 130 | /* data */ |
72c4d853 | 131 | [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), |
bf504672 | 132 | |
1e5de182 AM |
133 | [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), |
134 | [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
60a5317f | 135 | GDT_STACK_CANARY_INIT |
950ad7ff | 136 | #endif |
06deef89 | 137 | } }; |
7a61d35d | 138 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 139 | |
0c752a93 SS |
140 | static int __init x86_xsave_setup(char *s) |
141 | { | |
142 | setup_clear_cpu_cap(X86_FEATURE_XSAVE); | |
6bad06b7 | 143 | setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); |
0c752a93 SS |
144 | return 1; |
145 | } | |
146 | __setup("noxsave", x86_xsave_setup); | |
147 | ||
6bad06b7 SS |
148 | static int __init x86_xsaveopt_setup(char *s) |
149 | { | |
150 | setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); | |
151 | return 1; | |
152 | } | |
153 | __setup("noxsaveopt", x86_xsaveopt_setup); | |
154 | ||
ba51dced | 155 | #ifdef CONFIG_X86_32 |
3bc9b76b | 156 | static int cachesize_override __cpuinitdata = -1; |
3bc9b76b | 157 | static int disable_x86_serial_nr __cpuinitdata = 1; |
1da177e4 | 158 | |
0a488a53 YL |
159 | static int __init cachesize_setup(char *str) |
160 | { | |
161 | get_option(&str, &cachesize_override); | |
162 | return 1; | |
163 | } | |
164 | __setup("cachesize=", cachesize_setup); | |
165 | ||
0a488a53 YL |
166 | static int __init x86_fxsr_setup(char *s) |
167 | { | |
168 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
169 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
170 | return 1; | |
171 | } | |
172 | __setup("nofxsr", x86_fxsr_setup); | |
173 | ||
174 | static int __init x86_sep_setup(char *s) | |
175 | { | |
176 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
177 | return 1; | |
178 | } | |
179 | __setup("nosep", x86_sep_setup); | |
180 | ||
181 | /* Standard macro to see if a specific flag is changeable */ | |
182 | static inline int flag_is_changeable_p(u32 flag) | |
183 | { | |
184 | u32 f1, f2; | |
185 | ||
94f6bac1 KH |
186 | /* |
187 | * Cyrix and IDT cpus allow disabling of CPUID | |
188 | * so the code below may return different results | |
189 | * when it is executed before and after enabling | |
190 | * the CPUID. Add "volatile" to not allow gcc to | |
191 | * optimize the subsequent calls to this function. | |
192 | */ | |
0f3fa48a IM |
193 | asm volatile ("pushfl \n\t" |
194 | "pushfl \n\t" | |
195 | "popl %0 \n\t" | |
196 | "movl %0, %1 \n\t" | |
197 | "xorl %2, %0 \n\t" | |
198 | "pushl %0 \n\t" | |
199 | "popfl \n\t" | |
200 | "pushfl \n\t" | |
201 | "popl %0 \n\t" | |
202 | "popfl \n\t" | |
203 | ||
94f6bac1 KH |
204 | : "=&r" (f1), "=&r" (f2) |
205 | : "ir" (flag)); | |
0a488a53 YL |
206 | |
207 | return ((f1^f2) & flag) != 0; | |
208 | } | |
209 | ||
210 | /* Probe for the CPUID instruction */ | |
211 | static int __cpuinit have_cpuid_p(void) | |
212 | { | |
213 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
214 | } | |
215 | ||
216 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
217 | { | |
0f3fa48a IM |
218 | unsigned long lo, hi; |
219 | ||
220 | if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) | |
221 | return; | |
222 | ||
223 | /* Disable processor serial number: */ | |
224 | ||
225 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
226 | lo |= 0x200000; | |
227 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
228 | ||
229 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
230 | clear_cpu_cap(c, X86_FEATURE_PN); | |
231 | ||
232 | /* Disabling the serial number may affect the cpuid level */ | |
233 | c->cpuid_level = cpuid_eax(0); | |
0a488a53 YL |
234 | } |
235 | ||
236 | static int __init x86_serial_nr_setup(char *s) | |
237 | { | |
238 | disable_x86_serial_nr = 0; | |
239 | return 1; | |
240 | } | |
241 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 242 | #else |
102bbe3a YL |
243 | static inline int flag_is_changeable_p(u32 flag) |
244 | { | |
245 | return 1; | |
246 | } | |
ba51dced YL |
247 | /* Probe for the CPUID instruction */ |
248 | static inline int have_cpuid_p(void) | |
249 | { | |
250 | return 1; | |
251 | } | |
102bbe3a YL |
252 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
253 | { | |
254 | } | |
ba51dced | 255 | #endif |
0a488a53 | 256 | |
b38b0665 PA |
257 | /* |
258 | * Some CPU features depend on higher CPUID levels, which may not always | |
259 | * be available due to CPUID level capping or broken virtualization | |
260 | * software. Add those features to this table to auto-disable them. | |
261 | */ | |
262 | struct cpuid_dependent_feature { | |
263 | u32 feature; | |
264 | u32 level; | |
265 | }; | |
0f3fa48a | 266 | |
b38b0665 PA |
267 | static const struct cpuid_dependent_feature __cpuinitconst |
268 | cpuid_dependent_features[] = { | |
269 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
270 | { X86_FEATURE_DCA, 0x00000009 }, | |
271 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
272 | { 0, 0 } | |
273 | }; | |
274 | ||
275 | static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) | |
276 | { | |
277 | const struct cpuid_dependent_feature *df; | |
9766cdbc | 278 | |
b38b0665 | 279 | for (df = cpuid_dependent_features; df->feature; df++) { |
0f3fa48a IM |
280 | |
281 | if (!cpu_has(c, df->feature)) | |
282 | continue; | |
b38b0665 PA |
283 | /* |
284 | * Note: cpuid_level is set to -1 if unavailable, but | |
285 | * extended_extended_level is set to 0 if unavailable | |
286 | * and the legitimate extended levels are all negative | |
287 | * when signed; hence the weird messing around with | |
288 | * signs here... | |
289 | */ | |
0f3fa48a | 290 | if (!((s32)df->level < 0 ? |
f6db44df | 291 | (u32)df->level > (u32)c->extended_cpuid_level : |
0f3fa48a IM |
292 | (s32)df->level > (s32)c->cpuid_level)) |
293 | continue; | |
294 | ||
295 | clear_cpu_cap(c, df->feature); | |
296 | if (!warn) | |
297 | continue; | |
298 | ||
299 | printk(KERN_WARNING | |
300 | "CPU: CPU feature %s disabled, no CPUID level 0x%x\n", | |
301 | x86_cap_flags[df->feature], df->level); | |
b38b0665 | 302 | } |
f6db44df | 303 | } |
b38b0665 | 304 | |
102bbe3a YL |
305 | /* |
306 | * Naming convention should be: <Name> [(<Codename>)] | |
307 | * This table only is used unless init_<vendor>() below doesn't set it; | |
0f3fa48a IM |
308 | * in particular, if CPUID levels 0x80000002..4 are supported, this |
309 | * isn't used | |
102bbe3a YL |
310 | */ |
311 | ||
312 | /* Look up CPU names by table lookup. */ | |
02dde8b4 | 313 | static const char *__cpuinit table_lookup_model(struct cpuinfo_x86 *c) |
102bbe3a | 314 | { |
02dde8b4 | 315 | const struct cpu_model_info *info; |
102bbe3a YL |
316 | |
317 | if (c->x86_model >= 16) | |
318 | return NULL; /* Range check */ | |
319 | ||
320 | if (!this_cpu) | |
321 | return NULL; | |
322 | ||
323 | info = this_cpu->c_models; | |
324 | ||
325 | while (info && info->family) { | |
326 | if (info->family == c->x86) | |
327 | return info->model_names[c->x86_model]; | |
328 | info++; | |
329 | } | |
330 | return NULL; /* Not found */ | |
331 | } | |
332 | ||
3e0c3737 YL |
333 | __u32 cpu_caps_cleared[NCAPINTS] __cpuinitdata; |
334 | __u32 cpu_caps_set[NCAPINTS] __cpuinitdata; | |
7d851c8d | 335 | |
11e3a840 JF |
336 | void load_percpu_segment(int cpu) |
337 | { | |
338 | #ifdef CONFIG_X86_32 | |
339 | loadsegment(fs, __KERNEL_PERCPU); | |
340 | #else | |
341 | loadsegment(gs, 0); | |
342 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); | |
343 | #endif | |
60a5317f | 344 | load_stack_canary_segment(); |
11e3a840 JF |
345 | } |
346 | ||
0f3fa48a IM |
347 | /* |
348 | * Current gdt points %fs at the "master" per-cpu area: after this, | |
349 | * it's on the real one. | |
350 | */ | |
552be871 | 351 | void switch_to_new_gdt(int cpu) |
9d31d35b YL |
352 | { |
353 | struct desc_ptr gdt_descr; | |
354 | ||
2697fbd5 | 355 | gdt_descr.address = (long)get_cpu_gdt_table(cpu); |
9d31d35b YL |
356 | gdt_descr.size = GDT_SIZE - 1; |
357 | load_gdt(&gdt_descr); | |
2697fbd5 | 358 | /* Reload the per-cpu base */ |
11e3a840 JF |
359 | |
360 | load_percpu_segment(cpu); | |
9d31d35b YL |
361 | } |
362 | ||
02dde8b4 | 363 | static const struct cpu_dev *__cpuinitdata cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 364 | |
1b05d60d | 365 | static void __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
366 | { |
367 | unsigned int *v; | |
368 | char *p, *q; | |
369 | ||
3da99c97 | 370 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 371 | return; |
1da177e4 | 372 | |
0f3fa48a | 373 | v = (unsigned int *)c->x86_model_id; |
1da177e4 LT |
374 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); |
375 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
376 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
377 | c->x86_model_id[48] = 0; | |
378 | ||
0f3fa48a IM |
379 | /* |
380 | * Intel chips right-justify this string for some dumb reason; | |
381 | * undo that brain damage: | |
382 | */ | |
1da177e4 | 383 | p = q = &c->x86_model_id[0]; |
34048c9e | 384 | while (*p == ' ') |
9766cdbc | 385 | p++; |
34048c9e | 386 | if (p != q) { |
9766cdbc JSR |
387 | while (*p) |
388 | *q++ = *p++; | |
389 | while (q <= &c->x86_model_id[48]) | |
390 | *q++ = '\0'; /* Zero-pad the rest */ | |
1da177e4 | 391 | } |
1da177e4 LT |
392 | } |
393 | ||
27c13ece | 394 | void __cpuinit cpu_detect_cache_sizes(struct cpuinfo_x86 *c) |
1da177e4 | 395 | { |
9d31d35b | 396 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 397 | |
3da99c97 | 398 | n = c->extended_cpuid_level; |
1da177e4 LT |
399 | |
400 | if (n >= 0x80000005) { | |
9d31d35b | 401 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
9d31d35b | 402 | c->x86_cache_size = (ecx>>24) + (edx>>24); |
140fc727 YL |
403 | #ifdef CONFIG_X86_64 |
404 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
405 | c->x86_tlbsize = 0; | |
406 | #endif | |
1da177e4 LT |
407 | } |
408 | ||
409 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
410 | return; | |
411 | ||
0a488a53 | 412 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 413 | l2size = ecx >> 16; |
34048c9e | 414 | |
140fc727 YL |
415 | #ifdef CONFIG_X86_64 |
416 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
417 | #else | |
1da177e4 LT |
418 | /* do processor-specific cache resizing */ |
419 | if (this_cpu->c_size_cache) | |
34048c9e | 420 | l2size = this_cpu->c_size_cache(c, l2size); |
1da177e4 LT |
421 | |
422 | /* Allow user to override all this if necessary. */ | |
423 | if (cachesize_override != -1) | |
424 | l2size = cachesize_override; | |
425 | ||
34048c9e | 426 | if (l2size == 0) |
1da177e4 | 427 | return; /* Again, no L2 cache is possible */ |
140fc727 | 428 | #endif |
1da177e4 LT |
429 | |
430 | c->x86_cache_size = l2size; | |
1da177e4 LT |
431 | } |
432 | ||
9d31d35b | 433 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 434 | { |
97e4db7c | 435 | #ifdef CONFIG_X86_HT |
0a488a53 YL |
436 | u32 eax, ebx, ecx, edx; |
437 | int index_msb, core_bits; | |
2eaad1fd | 438 | static bool printed; |
1da177e4 | 439 | |
0a488a53 | 440 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 441 | return; |
1da177e4 | 442 | |
0a488a53 YL |
443 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
444 | goto out; | |
1da177e4 | 445 | |
1cd78776 YL |
446 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
447 | return; | |
1da177e4 | 448 | |
0a488a53 | 449 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 450 | |
9d31d35b YL |
451 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
452 | ||
453 | if (smp_num_siblings == 1) { | |
2eaad1fd | 454 | printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n"); |
0f3fa48a IM |
455 | goto out; |
456 | } | |
9d31d35b | 457 | |
0f3fa48a IM |
458 | if (smp_num_siblings <= 1) |
459 | goto out; | |
9d31d35b | 460 | |
0f3fa48a IM |
461 | if (smp_num_siblings > nr_cpu_ids) { |
462 | pr_warning("CPU: Unsupported number of siblings %d", | |
463 | smp_num_siblings); | |
464 | smp_num_siblings = 1; | |
465 | return; | |
466 | } | |
9d31d35b | 467 | |
0f3fa48a IM |
468 | index_msb = get_count_order(smp_num_siblings); |
469 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); | |
9d31d35b | 470 | |
0f3fa48a | 471 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
9d31d35b | 472 | |
0f3fa48a | 473 | index_msb = get_count_order(smp_num_siblings); |
9d31d35b | 474 | |
0f3fa48a | 475 | core_bits = get_count_order(c->x86_max_cores); |
9d31d35b | 476 | |
0f3fa48a IM |
477 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & |
478 | ((1 << core_bits) - 1); | |
1da177e4 | 479 | |
0a488a53 | 480 | out: |
2eaad1fd | 481 | if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { |
0a488a53 YL |
482 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", |
483 | c->phys_proc_id); | |
484 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
485 | c->cpu_core_id); | |
2eaad1fd | 486 | printed = 1; |
9d31d35b | 487 | } |
9d31d35b | 488 | #endif |
97e4db7c | 489 | } |
1da177e4 | 490 | |
3da99c97 | 491 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
492 | { |
493 | char *v = c->x86_vendor_id; | |
0f3fa48a | 494 | int i; |
1da177e4 LT |
495 | |
496 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
497 | if (!cpu_devs[i]) |
498 | break; | |
499 | ||
500 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
501 | (cpu_devs[i]->c_ident[1] && | |
502 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
0f3fa48a | 503 | |
10a434fc YL |
504 | this_cpu = cpu_devs[i]; |
505 | c->x86_vendor = this_cpu->c_x86_vendor; | |
506 | return; | |
1da177e4 LT |
507 | } |
508 | } | |
10a434fc | 509 | |
a9c56953 MK |
510 | printk_once(KERN_ERR |
511 | "CPU: vendor_id '%s' unknown, using generic init.\n" \ | |
512 | "CPU: Your system may be unstable.\n", v); | |
10a434fc | 513 | |
fe38d855 CE |
514 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
515 | this_cpu = &default_cpu; | |
1da177e4 LT |
516 | } |
517 | ||
9d31d35b | 518 | void __cpuinit cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 519 | { |
1da177e4 | 520 | /* Get vendor name */ |
4a148513 HH |
521 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
522 | (unsigned int *)&c->x86_vendor_id[0], | |
523 | (unsigned int *)&c->x86_vendor_id[8], | |
524 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 525 | |
1da177e4 | 526 | c->x86 = 4; |
9d31d35b | 527 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
528 | if (c->cpuid_level >= 0x00000001) { |
529 | u32 junk, tfms, cap0, misc; | |
0f3fa48a | 530 | |
1da177e4 | 531 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
9d31d35b YL |
532 | c->x86 = (tfms >> 8) & 0xf; |
533 | c->x86_model = (tfms >> 4) & 0xf; | |
534 | c->x86_mask = tfms & 0xf; | |
0f3fa48a | 535 | |
f5f786d0 | 536 | if (c->x86 == 0xf) |
1da177e4 | 537 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 538 | if (c->x86 >= 0x6) |
9d31d35b | 539 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
0f3fa48a | 540 | |
d4387bd3 | 541 | if (cap0 & (1<<19)) { |
d4387bd3 | 542 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 543 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 544 | } |
1da177e4 | 545 | } |
1da177e4 | 546 | } |
3da99c97 | 547 | |
c2b9ff24 | 548 | void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) |
093af8d7 YL |
549 | { |
550 | u32 tfms, xlvl; | |
3da99c97 | 551 | u32 ebx; |
093af8d7 | 552 | |
3da99c97 YL |
553 | /* Intel-defined flags: level 0x00000001 */ |
554 | if (c->cpuid_level >= 0x00000001) { | |
555 | u32 capability, excap; | |
0f3fa48a | 556 | |
3da99c97 YL |
557 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); |
558 | c->x86_capability[0] = capability; | |
559 | c->x86_capability[4] = excap; | |
560 | } | |
093af8d7 | 561 | |
bdc802dc PA |
562 | /* Additional Intel-defined flags: level 0x00000007 */ |
563 | if (c->cpuid_level >= 0x00000007) { | |
564 | u32 eax, ebx, ecx, edx; | |
565 | ||
566 | cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); | |
567 | ||
568 | if (eax > 0) | |
569 | c->x86_capability[9] = ebx; | |
570 | } | |
571 | ||
3da99c97 YL |
572 | /* AMD-defined flags: level 0x80000001 */ |
573 | xlvl = cpuid_eax(0x80000000); | |
574 | c->extended_cpuid_level = xlvl; | |
0f3fa48a | 575 | |
3da99c97 YL |
576 | if ((xlvl & 0xffff0000) == 0x80000000) { |
577 | if (xlvl >= 0x80000001) { | |
578 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
579 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 580 | } |
093af8d7 | 581 | } |
093af8d7 | 582 | |
5122c890 YL |
583 | if (c->extended_cpuid_level >= 0x80000008) { |
584 | u32 eax = cpuid_eax(0x80000008); | |
585 | ||
586 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
587 | c->x86_phys_bits = eax & 0xff; | |
093af8d7 | 588 | } |
13c6c532 JB |
589 | #ifdef CONFIG_X86_32 |
590 | else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) | |
591 | c->x86_phys_bits = 36; | |
5122c890 | 592 | #endif |
e3224234 YL |
593 | |
594 | if (c->extended_cpuid_level >= 0x80000007) | |
595 | c->x86_power = cpuid_edx(0x80000007); | |
093af8d7 | 596 | |
1dedefd1 | 597 | init_scattered_cpuid_features(c); |
093af8d7 | 598 | } |
1da177e4 | 599 | |
aef93c8b YL |
600 | static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
601 | { | |
602 | #ifdef CONFIG_X86_32 | |
603 | int i; | |
604 | ||
605 | /* | |
606 | * First of all, decide if this is a 486 or higher | |
607 | * It's a 486 if we can modify the AC flag | |
608 | */ | |
609 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
610 | c->x86 = 4; | |
611 | else | |
612 | c->x86 = 3; | |
613 | ||
614 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
615 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
616 | c->x86_vendor_id[0] = 0; | |
617 | cpu_devs[i]->c_identify(c); | |
618 | if (c->x86_vendor_id[0]) { | |
619 | get_cpu_vendor(c); | |
620 | break; | |
621 | } | |
622 | } | |
623 | #endif | |
624 | } | |
625 | ||
34048c9e PC |
626 | /* |
627 | * Do minimum CPU detection early. | |
628 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
629 | * cache alignment. | |
630 | * The others are not touched to avoid unwanted side effects. | |
631 | * | |
632 | * WARNING: this function is only called on the BP. Don't add code here | |
633 | * that is supposed to run on all CPUs. | |
634 | */ | |
3da99c97 | 635 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 636 | { |
6627d242 YL |
637 | #ifdef CONFIG_X86_64 |
638 | c->x86_clflush_size = 64; | |
13c6c532 JB |
639 | c->x86_phys_bits = 36; |
640 | c->x86_virt_bits = 48; | |
6627d242 | 641 | #else |
d4387bd3 | 642 | c->x86_clflush_size = 32; |
13c6c532 JB |
643 | c->x86_phys_bits = 32; |
644 | c->x86_virt_bits = 32; | |
6627d242 | 645 | #endif |
0a488a53 | 646 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 647 | |
3da99c97 | 648 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 649 | c->extended_cpuid_level = 0; |
d7cd5611 | 650 | |
aef93c8b YL |
651 | if (!have_cpuid_p()) |
652 | identify_cpu_without_cpuid(c); | |
653 | ||
654 | /* cyrix could have cpuid enabled via c_identify()*/ | |
d7cd5611 RR |
655 | if (!have_cpuid_p()) |
656 | return; | |
657 | ||
658 | cpu_detect(c); | |
659 | ||
3da99c97 | 660 | get_cpu_vendor(c); |
2b16a235 | 661 | |
3da99c97 | 662 | get_cpu_cap(c); |
12cf105c | 663 | |
10a434fc YL |
664 | if (this_cpu->c_early_init) |
665 | this_cpu->c_early_init(c); | |
093af8d7 | 666 | |
1c4acdb4 | 667 | #ifdef CONFIG_SMP |
bfcb4c1b | 668 | c->cpu_index = boot_cpu_id; |
1c4acdb4 | 669 | #endif |
b38b0665 | 670 | filter_cpuid_features(c, false); |
d7cd5611 RR |
671 | } |
672 | ||
9d31d35b YL |
673 | void __init early_cpu_init(void) |
674 | { | |
02dde8b4 | 675 | const struct cpu_dev *const *cdev; |
10a434fc YL |
676 | int count = 0; |
677 | ||
31c997ca | 678 | #ifdef PROCESSOR_SELECT |
9766cdbc | 679 | printk(KERN_INFO "KERNEL supported cpus:\n"); |
31c997ca IM |
680 | #endif |
681 | ||
10a434fc | 682 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { |
02dde8b4 | 683 | const struct cpu_dev *cpudev = *cdev; |
9d31d35b | 684 | |
10a434fc YL |
685 | if (count >= X86_VENDOR_NUM) |
686 | break; | |
687 | cpu_devs[count] = cpudev; | |
688 | count++; | |
689 | ||
31c997ca IM |
690 | #ifdef PROCESSOR_SELECT |
691 | { | |
692 | unsigned int j; | |
693 | ||
694 | for (j = 0; j < 2; j++) { | |
695 | if (!cpudev->c_ident[j]) | |
696 | continue; | |
697 | printk(KERN_INFO " %s %s\n", cpudev->c_vendor, | |
698 | cpudev->c_ident[j]); | |
699 | } | |
10a434fc | 700 | } |
0388423d | 701 | #endif |
10a434fc | 702 | } |
9d31d35b | 703 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 704 | } |
093af8d7 | 705 | |
b6734c35 PA |
706 | /* |
707 | * The NOPL instruction is supposed to exist on all CPUs with | |
ba0593bf | 708 | * family >= 6; unfortunately, that's not true in practice because |
b6734c35 | 709 | * of early VIA chips and (more importantly) broken virtualizers that |
ba0593bf PA |
710 | * are not easy to detect. In the latter case it doesn't even *fail* |
711 | * reliably, so probing for it doesn't even work. Disable it completely | |
712 | * unless we can find a reliable way to detect all the broken cases. | |
b6734c35 PA |
713 | */ |
714 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
715 | { | |
b6734c35 | 716 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
d7cd5611 RR |
717 | } |
718 | ||
34048c9e | 719 | static void __cpuinit generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 720 | { |
aef93c8b | 721 | c->extended_cpuid_level = 0; |
1da177e4 | 722 | |
3da99c97 | 723 | if (!have_cpuid_p()) |
aef93c8b | 724 | identify_cpu_without_cpuid(c); |
1d67953f | 725 | |
aef93c8b | 726 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 727 | if (!have_cpuid_p()) |
aef93c8b | 728 | return; |
1da177e4 | 729 | |
3da99c97 | 730 | cpu_detect(c); |
1da177e4 | 731 | |
3da99c97 | 732 | get_cpu_vendor(c); |
1da177e4 | 733 | |
3da99c97 | 734 | get_cpu_cap(c); |
1da177e4 | 735 | |
3da99c97 YL |
736 | if (c->cpuid_level >= 0x00000001) { |
737 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e YL |
738 | #ifdef CONFIG_X86_32 |
739 | # ifdef CONFIG_X86_HT | |
cb8cc442 | 740 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 741 | # else |
3da99c97 | 742 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
743 | # endif |
744 | #endif | |
1da177e4 | 745 | |
b89d3b3e YL |
746 | #ifdef CONFIG_X86_HT |
747 | c->phys_proc_id = c->initial_apicid; | |
1e9f28fa | 748 | #endif |
3da99c97 | 749 | } |
1da177e4 | 750 | |
1b05d60d | 751 | get_model_name(c); /* Default name */ |
1da177e4 | 752 | |
3da99c97 | 753 | detect_nopl(c); |
1da177e4 | 754 | } |
1da177e4 LT |
755 | |
756 | /* | |
757 | * This does the hard work of actually picking apart the CPU stuff... | |
758 | */ | |
9a250347 | 759 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
760 | { |
761 | int i; | |
762 | ||
763 | c->loops_per_jiffy = loops_per_jiffy; | |
764 | c->x86_cache_size = -1; | |
765 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
766 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
767 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
768 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 769 | c->x86_max_cores = 1; |
102bbe3a | 770 | c->x86_coreid_bits = 0; |
11fdd252 | 771 | #ifdef CONFIG_X86_64 |
102bbe3a | 772 | c->x86_clflush_size = 64; |
13c6c532 JB |
773 | c->x86_phys_bits = 36; |
774 | c->x86_virt_bits = 48; | |
102bbe3a YL |
775 | #else |
776 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 777 | c->x86_clflush_size = 32; |
13c6c532 JB |
778 | c->x86_phys_bits = 32; |
779 | c->x86_virt_bits = 32; | |
102bbe3a YL |
780 | #endif |
781 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
782 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
783 | ||
1da177e4 LT |
784 | generic_identify(c); |
785 | ||
3898534d | 786 | if (this_cpu->c_identify) |
1da177e4 LT |
787 | this_cpu->c_identify(c); |
788 | ||
2759c328 YL |
789 | /* Clear/Set all flags overriden by options, after probe */ |
790 | for (i = 0; i < NCAPINTS; i++) { | |
791 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
792 | c->x86_capability[i] |= cpu_caps_set[i]; | |
793 | } | |
794 | ||
102bbe3a | 795 | #ifdef CONFIG_X86_64 |
cb8cc442 | 796 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
797 | #endif |
798 | ||
1da177e4 LT |
799 | /* |
800 | * Vendor-specific initialization. In this section we | |
801 | * canonicalize the feature flags, meaning if there are | |
802 | * features a certain CPU supports which CPUID doesn't | |
803 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
804 | * we handle them here. | |
805 | * | |
806 | * At the end of this section, c->x86_capability better | |
807 | * indicate the features this CPU genuinely supports! | |
808 | */ | |
809 | if (this_cpu->c_init) | |
810 | this_cpu->c_init(c); | |
811 | ||
812 | /* Disable the PN if appropriate */ | |
813 | squash_the_stupid_serial_number(c); | |
814 | ||
815 | /* | |
0f3fa48a IM |
816 | * The vendor-specific functions might have changed features. |
817 | * Now we do "generic changes." | |
1da177e4 LT |
818 | */ |
819 | ||
b38b0665 PA |
820 | /* Filter out anything that depends on CPUID levels we don't have */ |
821 | filter_cpuid_features(c, true); | |
822 | ||
1da177e4 | 823 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 824 | if (!c->x86_model_id[0]) { |
02dde8b4 | 825 | const char *p; |
1da177e4 | 826 | p = table_lookup_model(c); |
34048c9e | 827 | if (p) |
1da177e4 LT |
828 | strcpy(c->x86_model_id, p); |
829 | else | |
830 | /* Last resort... */ | |
831 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 832 | c->x86, c->x86_model); |
1da177e4 LT |
833 | } |
834 | ||
102bbe3a YL |
835 | #ifdef CONFIG_X86_64 |
836 | detect_ht(c); | |
837 | #endif | |
838 | ||
88b094fb | 839 | init_hypervisor(c); |
3e0c3737 YL |
840 | |
841 | /* | |
842 | * Clear/Set all flags overriden by options, need do it | |
843 | * before following smp all cpus cap AND. | |
844 | */ | |
845 | for (i = 0; i < NCAPINTS; i++) { | |
846 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
847 | c->x86_capability[i] |= cpu_caps_set[i]; | |
848 | } | |
849 | ||
1da177e4 LT |
850 | /* |
851 | * On SMP, boot_cpu_data holds the common feature set between | |
852 | * all CPUs; so make sure that we indicate which features are | |
853 | * common between the CPUs. The first time this routine gets | |
854 | * executed, c == &boot_cpu_data. | |
855 | */ | |
34048c9e | 856 | if (c != &boot_cpu_data) { |
1da177e4 | 857 | /* AND the already accumulated flags with these */ |
9d31d35b | 858 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 LT |
859 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
860 | } | |
861 | ||
862 | /* Init Machine Check Exception if available. */ | |
5e09954a | 863 | mcheck_cpu_init(c); |
30d432df AK |
864 | |
865 | select_idle_routine(c); | |
102bbe3a YL |
866 | |
867 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) | |
868 | numa_add_cpu(smp_processor_id()); | |
869 | #endif | |
a6c4e076 | 870 | } |
31ab269a | 871 | |
e04d645f GC |
872 | #ifdef CONFIG_X86_64 |
873 | static void vgetcpu_set_mode(void) | |
874 | { | |
875 | if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) | |
876 | vgetcpu_mode = VGETCPU_RDTSCP; | |
877 | else | |
878 | vgetcpu_mode = VGETCPU_LSL; | |
879 | } | |
880 | #endif | |
881 | ||
a6c4e076 JF |
882 | void __init identify_boot_cpu(void) |
883 | { | |
884 | identify_cpu(&boot_cpu_data); | |
30e1e6d1 | 885 | init_c1e_mask(); |
102bbe3a | 886 | #ifdef CONFIG_X86_32 |
a6c4e076 | 887 | sysenter_setup(); |
6fe940d6 | 888 | enable_sep_cpu(); |
e04d645f GC |
889 | #else |
890 | vgetcpu_set_mode(); | |
102bbe3a | 891 | #endif |
cdd6c482 | 892 | init_hw_perf_events(); |
a6c4e076 | 893 | } |
3b520b23 | 894 | |
a6c4e076 JF |
895 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) |
896 | { | |
897 | BUG_ON(c == &boot_cpu_data); | |
898 | identify_cpu(c); | |
102bbe3a | 899 | #ifdef CONFIG_X86_32 |
a6c4e076 | 900 | enable_sep_cpu(); |
102bbe3a | 901 | #endif |
a6c4e076 | 902 | mtrr_ap_init(); |
1da177e4 LT |
903 | } |
904 | ||
a0854a46 | 905 | struct msr_range { |
0f3fa48a IM |
906 | unsigned min; |
907 | unsigned max; | |
a0854a46 | 908 | }; |
1da177e4 | 909 | |
02dde8b4 | 910 | static const struct msr_range msr_range_array[] __cpuinitconst = { |
a0854a46 YL |
911 | { 0x00000000, 0x00000418}, |
912 | { 0xc0000000, 0xc000040b}, | |
913 | { 0xc0010000, 0xc0010142}, | |
914 | { 0xc0011000, 0xc001103b}, | |
915 | }; | |
1da177e4 | 916 | |
a0854a46 YL |
917 | static void __cpuinit print_cpu_msr(void) |
918 | { | |
0f3fa48a | 919 | unsigned index_min, index_max; |
a0854a46 YL |
920 | unsigned index; |
921 | u64 val; | |
922 | int i; | |
a0854a46 YL |
923 | |
924 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
925 | index_min = msr_range_array[i].min; | |
926 | index_max = msr_range_array[i].max; | |
0f3fa48a | 927 | |
a0854a46 YL |
928 | for (index = index_min; index < index_max; index++) { |
929 | if (rdmsrl_amd_safe(index, &val)) | |
930 | continue; | |
931 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1da177e4 | 932 | } |
a0854a46 YL |
933 | } |
934 | } | |
94605eff | 935 | |
a0854a46 | 936 | static int show_msr __cpuinitdata; |
0f3fa48a | 937 | |
a0854a46 YL |
938 | static __init int setup_show_msr(char *arg) |
939 | { | |
940 | int num; | |
3dd9d514 | 941 | |
a0854a46 | 942 | get_option(&arg, &num); |
3dd9d514 | 943 | |
a0854a46 YL |
944 | if (num > 0) |
945 | show_msr = num; | |
946 | return 1; | |
1da177e4 | 947 | } |
a0854a46 | 948 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 949 | |
191679fd AK |
950 | static __init int setup_noclflush(char *arg) |
951 | { | |
952 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
953 | return 1; | |
954 | } | |
955 | __setup("noclflush", setup_noclflush); | |
956 | ||
3bc9b76b | 957 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 | 958 | { |
02dde8b4 | 959 | const char *vendor = NULL; |
1da177e4 | 960 | |
0f3fa48a | 961 | if (c->x86_vendor < X86_VENDOR_NUM) { |
1da177e4 | 962 | vendor = this_cpu->c_vendor; |
0f3fa48a IM |
963 | } else { |
964 | if (c->cpuid_level >= 0) | |
965 | vendor = c->x86_vendor_id; | |
966 | } | |
1da177e4 | 967 | |
bd32a8cf | 968 | if (vendor && !strstr(c->x86_model_id, vendor)) |
9d31d35b | 969 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 970 | |
9d31d35b YL |
971 | if (c->x86_model_id[0]) |
972 | printk(KERN_CONT "%s", c->x86_model_id); | |
1da177e4 | 973 | else |
9d31d35b | 974 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 975 | |
34048c9e | 976 | if (c->x86_mask || c->cpuid_level >= 0) |
9d31d35b | 977 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); |
1da177e4 | 978 | else |
9d31d35b | 979 | printk(KERN_CONT "\n"); |
a0854a46 YL |
980 | |
981 | #ifdef CONFIG_SMP | |
982 | if (c->cpu_index < show_msr) | |
983 | print_cpu_msr(); | |
984 | #else | |
985 | if (show_msr) | |
986 | print_cpu_msr(); | |
987 | #endif | |
1da177e4 LT |
988 | } |
989 | ||
ac72e788 AK |
990 | static __init int setup_disablecpuid(char *arg) |
991 | { | |
992 | int bit; | |
0f3fa48a | 993 | |
ac72e788 AK |
994 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) |
995 | setup_clear_cpu_cap(bit); | |
996 | else | |
997 | return 0; | |
0f3fa48a | 998 | |
ac72e788 AK |
999 | return 1; |
1000 | } | |
1001 | __setup("clearcpuid=", setup_disablecpuid); | |
1002 | ||
d5494d4f | 1003 | #ifdef CONFIG_X86_64 |
9ff80942 | 1004 | struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table }; |
d5494d4f | 1005 | |
947e76cd BG |
1006 | DEFINE_PER_CPU_FIRST(union irq_stack_union, |
1007 | irq_stack_union) __aligned(PAGE_SIZE); | |
0f3fa48a | 1008 | |
bdf977b3 TH |
1009 | /* |
1010 | * The following four percpu variables are hot. Align current_task to | |
1011 | * cacheline size such that all four fall in the same cacheline. | |
1012 | */ | |
1013 | DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = | |
1014 | &init_task; | |
1015 | EXPORT_PER_CPU_SYMBOL(current_task); | |
d5494d4f | 1016 | |
9af45651 BG |
1017 | DEFINE_PER_CPU(unsigned long, kernel_stack) = |
1018 | (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; | |
1019 | EXPORT_PER_CPU_SYMBOL(kernel_stack); | |
1020 | ||
bdf977b3 TH |
1021 | DEFINE_PER_CPU(char *, irq_stack_ptr) = |
1022 | init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; | |
1023 | ||
56895530 | 1024 | DEFINE_PER_CPU(unsigned int, irq_count) = -1; |
d5494d4f | 1025 | |
0f3fa48a IM |
1026 | /* |
1027 | * Special IST stacks which the CPU switches to when it calls | |
1028 | * an IST-marked descriptor entry. Up to 7 stacks (hardware | |
1029 | * limit), all of them are 4K, except the debug stack which | |
1030 | * is 8K. | |
1031 | */ | |
1032 | static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { | |
1033 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
1034 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
1035 | }; | |
1036 | ||
92d65b23 | 1037 | static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks |
3e352aa8 | 1038 | [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); |
d5494d4f | 1039 | |
d5494d4f YL |
1040 | /* May not be marked __init: used by software suspend */ |
1041 | void syscall_init(void) | |
1da177e4 | 1042 | { |
d5494d4f YL |
1043 | /* |
1044 | * LSTAR and STAR live in a bit strange symbiosis. | |
1045 | * They both write to the same internal register. STAR allows to | |
1046 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
1047 | */ | |
1048 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
1049 | wrmsrl(MSR_LSTAR, system_call); | |
1050 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
03ae5768 | 1051 | |
d5494d4f YL |
1052 | #ifdef CONFIG_IA32_EMULATION |
1053 | syscall32_cpu_init(); | |
1054 | #endif | |
03ae5768 | 1055 | |
d5494d4f YL |
1056 | /* Flags to clear on syscall */ |
1057 | wrmsrl(MSR_SYSCALL_MASK, | |
1058 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); | |
1da177e4 | 1059 | } |
62111195 | 1060 | |
d5494d4f YL |
1061 | unsigned long kernel_eflags; |
1062 | ||
1063 | /* | |
1064 | * Copies of the original ist values from the tss are only accessed during | |
1065 | * debugging, no special alignment required. | |
1066 | */ | |
1067 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
1068 | ||
0f3fa48a | 1069 | #else /* CONFIG_X86_64 */ |
d5494d4f | 1070 | |
bdf977b3 TH |
1071 | DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; |
1072 | EXPORT_PER_CPU_SYMBOL(current_task); | |
1073 | ||
60a5317f | 1074 | #ifdef CONFIG_CC_STACKPROTECTOR |
53f82452 | 1075 | DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); |
60a5317f | 1076 | #endif |
d5494d4f | 1077 | |
60a5317f | 1078 | /* Make sure %fs and %gs are initialized properly in idle threads */ |
6b2fb3c6 | 1079 | struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) |
f95d47ca JF |
1080 | { |
1081 | memset(regs, 0, sizeof(struct pt_regs)); | |
65ea5b03 | 1082 | regs->fs = __KERNEL_PERCPU; |
60a5317f | 1083 | regs->gs = __KERNEL_STACK_CANARY; |
0f3fa48a | 1084 | |
f95d47ca JF |
1085 | return regs; |
1086 | } | |
0f3fa48a | 1087 | #endif /* CONFIG_X86_64 */ |
c5413fbe | 1088 | |
9766cdbc JSR |
1089 | /* |
1090 | * Clear all 6 debug registers: | |
1091 | */ | |
1092 | static void clear_all_debug_regs(void) | |
1093 | { | |
1094 | int i; | |
1095 | ||
1096 | for (i = 0; i < 8; i++) { | |
1097 | /* Ignore db4, db5 */ | |
1098 | if ((i == 4) || (i == 5)) | |
1099 | continue; | |
1100 | ||
1101 | set_debugreg(0, i); | |
1102 | } | |
1103 | } | |
c5413fbe | 1104 | |
0bb9fef9 JW |
1105 | #ifdef CONFIG_KGDB |
1106 | /* | |
1107 | * Restore debug regs if using kgdbwait and you have a kernel debugger | |
1108 | * connection established. | |
1109 | */ | |
1110 | static void dbg_restore_debug_regs(void) | |
1111 | { | |
1112 | if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) | |
1113 | arch_kgdb_ops.correct_hw_break(); | |
1114 | } | |
1115 | #else /* ! CONFIG_KGDB */ | |
1116 | #define dbg_restore_debug_regs() | |
1117 | #endif /* ! CONFIG_KGDB */ | |
1118 | ||
d2cbcc49 RR |
1119 | /* |
1120 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1121 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1122 | * and IDT. We reload them nevertheless, this function acts as a | |
1123 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 1124 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 1125 | */ |
1ba76586 | 1126 | #ifdef CONFIG_X86_64 |
0f3fa48a | 1127 | |
1ba76586 YL |
1128 | void __cpuinit cpu_init(void) |
1129 | { | |
0fe1e009 | 1130 | struct orig_ist *oist; |
1ba76586 | 1131 | struct task_struct *me; |
0f3fa48a IM |
1132 | struct tss_struct *t; |
1133 | unsigned long v; | |
1134 | int cpu; | |
1ba76586 YL |
1135 | int i; |
1136 | ||
0f3fa48a IM |
1137 | cpu = stack_smp_processor_id(); |
1138 | t = &per_cpu(init_tss, cpu); | |
0fe1e009 | 1139 | oist = &per_cpu(orig_ist, cpu); |
0f3fa48a | 1140 | |
e7a22c1e | 1141 | #ifdef CONFIG_NUMA |
e534c7c5 LS |
1142 | if (cpu != 0 && percpu_read(numa_node) == 0 && |
1143 | early_cpu_to_node(cpu) != NUMA_NO_NODE) | |
1144 | set_numa_node(early_cpu_to_node(cpu)); | |
e7a22c1e | 1145 | #endif |
1ba76586 YL |
1146 | |
1147 | me = current; | |
1148 | ||
c2d1cec1 | 1149 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) |
1ba76586 YL |
1150 | panic("CPU#%d already initialized!\n", cpu); |
1151 | ||
2eaad1fd | 1152 | pr_debug("Initializing CPU#%d\n", cpu); |
1ba76586 YL |
1153 | |
1154 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
1155 | ||
1156 | /* | |
1157 | * Initialize the per-CPU GDT with the boot GDT, | |
1158 | * and set up the GDT descriptor: | |
1159 | */ | |
1160 | ||
552be871 | 1161 | switch_to_new_gdt(cpu); |
2697fbd5 BG |
1162 | loadsegment(fs, 0); |
1163 | ||
1ba76586 YL |
1164 | load_idt((const struct desc_ptr *)&idt_descr); |
1165 | ||
1166 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1167 | syscall_init(); | |
1168 | ||
1169 | wrmsrl(MSR_FS_BASE, 0); | |
1170 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1171 | barrier(); | |
1172 | ||
4763ed4d | 1173 | x86_configure_nx(); |
06cd9a7d | 1174 | if (cpu != 0) |
1ba76586 YL |
1175 | enable_x2apic(); |
1176 | ||
1177 | /* | |
1178 | * set up and load the per-CPU TSS | |
1179 | */ | |
0fe1e009 | 1180 | if (!oist->ist[0]) { |
92d65b23 | 1181 | char *estacks = per_cpu(exception_stacks, cpu); |
0f3fa48a | 1182 | |
1ba76586 | 1183 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
0f3fa48a | 1184 | estacks += exception_stack_sizes[v]; |
0fe1e009 | 1185 | oist->ist[v] = t->x86_tss.ist[v] = |
1ba76586 YL |
1186 | (unsigned long)estacks; |
1187 | } | |
1188 | } | |
1189 | ||
1190 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
0f3fa48a | 1191 | |
1ba76586 YL |
1192 | /* |
1193 | * <= is required because the CPU will access up to | |
1194 | * 8 bits beyond the end of the IO permission bitmap. | |
1195 | */ | |
1196 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1197 | t->io_bitmap[i] = ~0UL; | |
1198 | ||
1199 | atomic_inc(&init_mm.mm_count); | |
1200 | me->active_mm = &init_mm; | |
8c5dfd25 | 1201 | BUG_ON(me->mm); |
1ba76586 YL |
1202 | enter_lazy_tlb(&init_mm, me); |
1203 | ||
1204 | load_sp0(t, ¤t->thread); | |
1205 | set_tss_desc(cpu, t); | |
1206 | load_TR_desc(); | |
1207 | load_LDT(&init_mm.context); | |
1208 | ||
0bb9fef9 JW |
1209 | clear_all_debug_regs(); |
1210 | dbg_restore_debug_regs(); | |
1ba76586 YL |
1211 | |
1212 | fpu_init(); | |
0e49bf66 | 1213 | xsave_init(); |
1ba76586 YL |
1214 | |
1215 | raw_local_save_flags(kernel_eflags); | |
1216 | ||
1217 | if (is_uv_system()) | |
1218 | uv_cpu_init(); | |
1219 | } | |
1220 | ||
1221 | #else | |
1222 | ||
d2cbcc49 | 1223 | void __cpuinit cpu_init(void) |
9ee79a3d | 1224 | { |
d2cbcc49 RR |
1225 | int cpu = smp_processor_id(); |
1226 | struct task_struct *curr = current; | |
34048c9e | 1227 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 1228 | struct thread_struct *thread = &curr->thread; |
62111195 | 1229 | |
c2d1cec1 | 1230 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { |
62111195 | 1231 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); |
9766cdbc JSR |
1232 | for (;;) |
1233 | local_irq_enable(); | |
62111195 JF |
1234 | } |
1235 | ||
1236 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1237 | ||
1238 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
1239 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 1240 | |
4d37e7e3 | 1241 | load_idt(&idt_descr); |
552be871 | 1242 | switch_to_new_gdt(cpu); |
1da177e4 | 1243 | |
1da177e4 LT |
1244 | /* |
1245 | * Set up and load the per-CPU TSS and LDT | |
1246 | */ | |
1247 | atomic_inc(&init_mm.mm_count); | |
62111195 | 1248 | curr->active_mm = &init_mm; |
8c5dfd25 | 1249 | BUG_ON(curr->mm); |
62111195 | 1250 | enter_lazy_tlb(&init_mm, curr); |
1da177e4 | 1251 | |
faca6227 | 1252 | load_sp0(t, thread); |
34048c9e | 1253 | set_tss_desc(cpu, t); |
1da177e4 LT |
1254 | load_TR_desc(); |
1255 | load_LDT(&init_mm.context); | |
1256 | ||
f9a196b8 TG |
1257 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); |
1258 | ||
22c4e308 | 1259 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1260 | /* Set up doublefault TSS pointer in the GDT */ |
1261 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1262 | #endif |
1da177e4 | 1263 | |
9766cdbc | 1264 | clear_all_debug_regs(); |
0bb9fef9 | 1265 | dbg_restore_debug_regs(); |
1da177e4 LT |
1266 | |
1267 | /* | |
1268 | * Force FPU initialization: | |
1269 | */ | |
c9ad4882 | 1270 | current_thread_info()->status = 0; |
1da177e4 LT |
1271 | clear_used_math(); |
1272 | mxcsr_feature_mask_init(); | |
dc1e35c6 | 1273 | |
0e49bf66 | 1274 | fpu_init(); |
dc1e35c6 | 1275 | xsave_init(); |
1da177e4 | 1276 | } |
1ba76586 | 1277 | #endif |