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Commit | Line | Data |
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457c8996 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
2458e53f KS |
2 | /* cpu_feature_enabled() cannot be used this early */ |
3 | #define USE_EARLY_PGTABLE_L5 | |
4 | ||
57c8a661 | 5 | #include <linux/memblock.h> |
9766cdbc | 6 | #include <linux/linkage.h> |
f0fc4aff | 7 | #include <linux/bitops.h> |
9766cdbc | 8 | #include <linux/kernel.h> |
186f4360 | 9 | #include <linux/export.h> |
9766cdbc JSR |
10 | #include <linux/percpu.h> |
11 | #include <linux/string.h> | |
ee098e1a | 12 | #include <linux/ctype.h> |
1da177e4 | 13 | #include <linux/delay.h> |
68e21be2 | 14 | #include <linux/sched/mm.h> |
e6017571 | 15 | #include <linux/sched/clock.h> |
9164bb4a | 16 | #include <linux/sched/task.h> |
9766cdbc | 17 | #include <linux/init.h> |
0f46efeb | 18 | #include <linux/kprobes.h> |
9766cdbc | 19 | #include <linux/kgdb.h> |
1da177e4 | 20 | #include <linux/smp.h> |
9766cdbc | 21 | #include <linux/io.h> |
b51ef52d | 22 | #include <linux/syscore_ops.h> |
9766cdbc JSR |
23 | |
24 | #include <asm/stackprotector.h> | |
cdd6c482 | 25 | #include <asm/perf_event.h> |
1da177e4 | 26 | #include <asm/mmu_context.h> |
49d859d7 | 27 | #include <asm/archrandom.h> |
9766cdbc JSR |
28 | #include <asm/hypervisor.h> |
29 | #include <asm/processor.h> | |
1e02ce4c | 30 | #include <asm/tlbflush.h> |
f649e938 | 31 | #include <asm/debugreg.h> |
9766cdbc | 32 | #include <asm/sections.h> |
f40c3300 | 33 | #include <asm/vsyscall.h> |
8bdbd962 AC |
34 | #include <linux/topology.h> |
35 | #include <linux/cpumask.h> | |
9766cdbc | 36 | #include <asm/pgtable.h> |
60063497 | 37 | #include <linux/atomic.h> |
9766cdbc JSR |
38 | #include <asm/proto.h> |
39 | #include <asm/setup.h> | |
40 | #include <asm/apic.h> | |
41 | #include <asm/desc.h> | |
78f7f1e5 | 42 | #include <asm/fpu/internal.h> |
27b07da7 | 43 | #include <asm/mtrr.h> |
0274f955 | 44 | #include <asm/hwcap2.h> |
8bdbd962 | 45 | #include <linux/numa.h> |
9766cdbc | 46 | #include <asm/asm.h> |
0f6ff2bc | 47 | #include <asm/bugs.h> |
9766cdbc | 48 | #include <asm/cpu.h> |
a03a3e28 | 49 | #include <asm/mce.h> |
9766cdbc | 50 | #include <asm/msr.h> |
8d4a4300 | 51 | #include <asm/pat.h> |
d288e1cf FY |
52 | #include <asm/microcode.h> |
53 | #include <asm/microcode_intel.h> | |
fec9434a DW |
54 | #include <asm/intel-family.h> |
55 | #include <asm/cpu_device_id.h> | |
bdbcdd48 | 56 | #include <asm/uv/uv.h> |
1da177e4 LT |
57 | |
58 | #include "cpu.h" | |
59 | ||
0274f955 GA |
60 | u32 elf_hwcap2 __read_mostly; |
61 | ||
c2d1cec1 | 62 | /* all of these masks are initialized in setup_cpu_local_masks() */ |
c2d1cec1 | 63 | cpumask_var_t cpu_initialized_mask; |
9766cdbc JSR |
64 | cpumask_var_t cpu_callout_mask; |
65 | cpumask_var_t cpu_callin_mask; | |
c2d1cec1 MT |
66 | |
67 | /* representing cpus for which sibling maps can be computed */ | |
68 | cpumask_var_t cpu_sibling_setup_mask; | |
69 | ||
f8b64d08 BP |
70 | /* Number of siblings per CPU package */ |
71 | int smp_num_siblings = 1; | |
72 | EXPORT_SYMBOL(smp_num_siblings); | |
73 | ||
74 | /* Last level cache ID of each logical CPU */ | |
75 | DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; | |
76 | ||
2f2f52ba | 77 | /* correctly size the local cpu masks */ |
4369f1fb | 78 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
79 | { |
80 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
81 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
82 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
83 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
84 | } | |
85 | ||
148f9bb8 | 86 | static void default_init(struct cpuinfo_x86 *c) |
e8055139 OZ |
87 | { |
88 | #ifdef CONFIG_X86_64 | |
27c13ece | 89 | cpu_detect_cache_sizes(c); |
e8055139 OZ |
90 | #else |
91 | /* Not much we can do here... */ | |
92 | /* Check if at least it has cpuid */ | |
93 | if (c->cpuid_level == -1) { | |
94 | /* No cpuid. It must be an ancient CPU */ | |
95 | if (c->x86 == 4) | |
96 | strcpy(c->x86_model_id, "486"); | |
97 | else if (c->x86 == 3) | |
98 | strcpy(c->x86_model_id, "386"); | |
99 | } | |
100 | #endif | |
101 | } | |
102 | ||
148f9bb8 | 103 | static const struct cpu_dev default_cpu = { |
e8055139 OZ |
104 | .c_init = default_init, |
105 | .c_vendor = "Unknown", | |
106 | .c_x86_vendor = X86_VENDOR_UNKNOWN, | |
107 | }; | |
108 | ||
148f9bb8 | 109 | static const struct cpu_dev *this_cpu = &default_cpu; |
0a488a53 | 110 | |
06deef89 | 111 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 112 | #ifdef CONFIG_X86_64 |
06deef89 BG |
113 | /* |
114 | * We need valid kernel segments for data and code in long mode too | |
115 | * IRET will check the segment types kkeil 2000/10/28 | |
116 | * Also sysret mandates a special GDT layout | |
117 | * | |
9766cdbc | 118 | * TLS descriptors are currently at a different place compared to i386. |
06deef89 BG |
119 | * Hopefully nobody expects them at a fixed place (Wine?) |
120 | */ | |
1e5de182 AM |
121 | [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), |
122 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), | |
123 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), | |
124 | [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), | |
125 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), | |
126 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), | |
950ad7ff | 127 | #else |
1e5de182 AM |
128 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), |
129 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
130 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), | |
131 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), | |
bf504672 RR |
132 | /* |
133 | * Segments used for calling PnP BIOS have byte granularity. | |
134 | * They code segments and data segments have fixed 64k limits, | |
135 | * the transfer segment sizes are set at run time. | |
136 | */ | |
6842ef0e | 137 | /* 32-bit code */ |
1e5de182 | 138 | [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
6842ef0e | 139 | /* 16-bit code */ |
1e5de182 | 140 | [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 141 | /* 16-bit data */ |
1e5de182 | 142 | [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), |
6842ef0e | 143 | /* 16-bit data */ |
1e5de182 | 144 | [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), |
6842ef0e | 145 | /* 16-bit data */ |
1e5de182 | 146 | [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), |
bf504672 RR |
147 | /* |
148 | * The APM segments have byte granularity and their bases | |
149 | * are set at run time. All have 64k limits. | |
150 | */ | |
6842ef0e | 151 | /* 32-bit code */ |
1e5de182 | 152 | [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
bf504672 | 153 | /* 16-bit code */ |
1e5de182 | 154 | [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 155 | /* data */ |
72c4d853 | 156 | [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), |
bf504672 | 157 | |
1e5de182 AM |
158 | [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), |
159 | [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
60a5317f | 160 | GDT_STACK_CANARY_INIT |
950ad7ff | 161 | #endif |
06deef89 | 162 | } }; |
7a61d35d | 163 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 164 | |
8c3641e9 | 165 | static int __init x86_mpx_setup(char *s) |
0c752a93 | 166 | { |
8c3641e9 | 167 | /* require an exact match without trailing characters */ |
2cd3949f DH |
168 | if (strlen(s)) |
169 | return 0; | |
0c752a93 | 170 | |
8c3641e9 DH |
171 | /* do not emit a message if the feature is not present */ |
172 | if (!boot_cpu_has(X86_FEATURE_MPX)) | |
173 | return 1; | |
6bad06b7 | 174 | |
8c3641e9 DH |
175 | setup_clear_cpu_cap(X86_FEATURE_MPX); |
176 | pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); | |
b6f42a4a FY |
177 | return 1; |
178 | } | |
8c3641e9 | 179 | __setup("nompx", x86_mpx_setup); |
b6f42a4a | 180 | |
0790c9aa | 181 | #ifdef CONFIG_X86_64 |
c7ad5ad2 | 182 | static int __init x86_nopcid_setup(char *s) |
0790c9aa | 183 | { |
c7ad5ad2 AL |
184 | /* nopcid doesn't accept parameters */ |
185 | if (s) | |
186 | return -EINVAL; | |
0790c9aa AL |
187 | |
188 | /* do not emit a message if the feature is not present */ | |
189 | if (!boot_cpu_has(X86_FEATURE_PCID)) | |
c7ad5ad2 | 190 | return 0; |
0790c9aa AL |
191 | |
192 | setup_clear_cpu_cap(X86_FEATURE_PCID); | |
193 | pr_info("nopcid: PCID feature disabled\n"); | |
c7ad5ad2 | 194 | return 0; |
0790c9aa | 195 | } |
c7ad5ad2 | 196 | early_param("nopcid", x86_nopcid_setup); |
0790c9aa AL |
197 | #endif |
198 | ||
d12a72b8 AL |
199 | static int __init x86_noinvpcid_setup(char *s) |
200 | { | |
201 | /* noinvpcid doesn't accept parameters */ | |
202 | if (s) | |
203 | return -EINVAL; | |
204 | ||
205 | /* do not emit a message if the feature is not present */ | |
206 | if (!boot_cpu_has(X86_FEATURE_INVPCID)) | |
207 | return 0; | |
208 | ||
209 | setup_clear_cpu_cap(X86_FEATURE_INVPCID); | |
210 | pr_info("noinvpcid: INVPCID feature disabled\n"); | |
211 | return 0; | |
212 | } | |
213 | early_param("noinvpcid", x86_noinvpcid_setup); | |
214 | ||
ba51dced | 215 | #ifdef CONFIG_X86_32 |
148f9bb8 PG |
216 | static int cachesize_override = -1; |
217 | static int disable_x86_serial_nr = 1; | |
1da177e4 | 218 | |
0a488a53 YL |
219 | static int __init cachesize_setup(char *str) |
220 | { | |
221 | get_option(&str, &cachesize_override); | |
222 | return 1; | |
223 | } | |
224 | __setup("cachesize=", cachesize_setup); | |
225 | ||
0a488a53 YL |
226 | static int __init x86_sep_setup(char *s) |
227 | { | |
228 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
229 | return 1; | |
230 | } | |
231 | __setup("nosep", x86_sep_setup); | |
232 | ||
233 | /* Standard macro to see if a specific flag is changeable */ | |
234 | static inline int flag_is_changeable_p(u32 flag) | |
235 | { | |
236 | u32 f1, f2; | |
237 | ||
94f6bac1 KH |
238 | /* |
239 | * Cyrix and IDT cpus allow disabling of CPUID | |
240 | * so the code below may return different results | |
241 | * when it is executed before and after enabling | |
242 | * the CPUID. Add "volatile" to not allow gcc to | |
243 | * optimize the subsequent calls to this function. | |
244 | */ | |
0f3fa48a IM |
245 | asm volatile ("pushfl \n\t" |
246 | "pushfl \n\t" | |
247 | "popl %0 \n\t" | |
248 | "movl %0, %1 \n\t" | |
249 | "xorl %2, %0 \n\t" | |
250 | "pushl %0 \n\t" | |
251 | "popfl \n\t" | |
252 | "pushfl \n\t" | |
253 | "popl %0 \n\t" | |
254 | "popfl \n\t" | |
255 | ||
94f6bac1 KH |
256 | : "=&r" (f1), "=&r" (f2) |
257 | : "ir" (flag)); | |
0a488a53 YL |
258 | |
259 | return ((f1^f2) & flag) != 0; | |
260 | } | |
261 | ||
262 | /* Probe for the CPUID instruction */ | |
148f9bb8 | 263 | int have_cpuid_p(void) |
0a488a53 YL |
264 | { |
265 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
266 | } | |
267 | ||
148f9bb8 | 268 | static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
0a488a53 | 269 | { |
0f3fa48a IM |
270 | unsigned long lo, hi; |
271 | ||
272 | if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) | |
273 | return; | |
274 | ||
275 | /* Disable processor serial number: */ | |
276 | ||
277 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
278 | lo |= 0x200000; | |
279 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
280 | ||
1b74dde7 | 281 | pr_notice("CPU serial number disabled.\n"); |
0f3fa48a IM |
282 | clear_cpu_cap(c, X86_FEATURE_PN); |
283 | ||
284 | /* Disabling the serial number may affect the cpuid level */ | |
285 | c->cpuid_level = cpuid_eax(0); | |
0a488a53 YL |
286 | } |
287 | ||
288 | static int __init x86_serial_nr_setup(char *s) | |
289 | { | |
290 | disable_x86_serial_nr = 0; | |
291 | return 1; | |
292 | } | |
293 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 294 | #else |
102bbe3a YL |
295 | static inline int flag_is_changeable_p(u32 flag) |
296 | { | |
297 | return 1; | |
298 | } | |
102bbe3a YL |
299 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
300 | { | |
301 | } | |
ba51dced | 302 | #endif |
0a488a53 | 303 | |
de5397ad FY |
304 | static __init int setup_disable_smep(char *arg) |
305 | { | |
b2cc2a07 | 306 | setup_clear_cpu_cap(X86_FEATURE_SMEP); |
0f6ff2bc DH |
307 | /* Check for things that depend on SMEP being enabled: */ |
308 | check_mpx_erratum(&boot_cpu_data); | |
de5397ad FY |
309 | return 1; |
310 | } | |
311 | __setup("nosmep", setup_disable_smep); | |
312 | ||
b2cc2a07 | 313 | static __always_inline void setup_smep(struct cpuinfo_x86 *c) |
de5397ad | 314 | { |
b2cc2a07 | 315 | if (cpu_has(c, X86_FEATURE_SMEP)) |
375074cc | 316 | cr4_set_bits(X86_CR4_SMEP); |
de5397ad FY |
317 | } |
318 | ||
52b6179a PA |
319 | static __init int setup_disable_smap(char *arg) |
320 | { | |
b2cc2a07 | 321 | setup_clear_cpu_cap(X86_FEATURE_SMAP); |
52b6179a PA |
322 | return 1; |
323 | } | |
324 | __setup("nosmap", setup_disable_smap); | |
325 | ||
b2cc2a07 PA |
326 | static __always_inline void setup_smap(struct cpuinfo_x86 *c) |
327 | { | |
581b7f15 | 328 | unsigned long eflags = native_save_fl(); |
b2cc2a07 PA |
329 | |
330 | /* This should have been cleared long ago */ | |
b2cc2a07 PA |
331 | BUG_ON(eflags & X86_EFLAGS_AC); |
332 | ||
03bbd596 PA |
333 | if (cpu_has(c, X86_FEATURE_SMAP)) { |
334 | #ifdef CONFIG_X86_SMAP | |
375074cc | 335 | cr4_set_bits(X86_CR4_SMAP); |
03bbd596 | 336 | #else |
375074cc | 337 | cr4_clear_bits(X86_CR4_SMAP); |
03bbd596 PA |
338 | #endif |
339 | } | |
de5397ad FY |
340 | } |
341 | ||
aa35f896 RN |
342 | static __always_inline void setup_umip(struct cpuinfo_x86 *c) |
343 | { | |
344 | /* Check the boot processor, plus build option for UMIP. */ | |
345 | if (!cpu_feature_enabled(X86_FEATURE_UMIP)) | |
346 | goto out; | |
347 | ||
348 | /* Check the current processor's cpuid bits. */ | |
349 | if (!cpu_has(c, X86_FEATURE_UMIP)) | |
350 | goto out; | |
351 | ||
352 | cr4_set_bits(X86_CR4_UMIP); | |
353 | ||
438cbf88 | 354 | pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n"); |
770c7755 | 355 | |
aa35f896 RN |
356 | return; |
357 | ||
358 | out: | |
359 | /* | |
360 | * Make sure UMIP is disabled in case it was enabled in a | |
361 | * previous boot (e.g., via kexec). | |
362 | */ | |
363 | cr4_clear_bits(X86_CR4_UMIP); | |
364 | } | |
365 | ||
7652ac92 TG |
366 | static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); |
367 | static unsigned long cr4_pinned_bits __ro_after_init; | |
368 | ||
369 | void native_write_cr0(unsigned long val) | |
370 | { | |
371 | unsigned long bits_missing = 0; | |
372 | ||
373 | set_register: | |
374 | asm volatile("mov %0,%%cr0": "+r" (val), "+m" (__force_order)); | |
375 | ||
376 | if (static_branch_likely(&cr_pinning)) { | |
377 | if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) { | |
378 | bits_missing = X86_CR0_WP; | |
379 | val |= bits_missing; | |
380 | goto set_register; | |
381 | } | |
382 | /* Warn after we've set the missing bits. */ | |
383 | WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n"); | |
384 | } | |
385 | } | |
386 | EXPORT_SYMBOL(native_write_cr0); | |
387 | ||
388 | void native_write_cr4(unsigned long val) | |
389 | { | |
390 | unsigned long bits_missing = 0; | |
391 | ||
392 | set_register: | |
393 | asm volatile("mov %0,%%cr4": "+r" (val), "+m" (cr4_pinned_bits)); | |
394 | ||
395 | if (static_branch_likely(&cr_pinning)) { | |
396 | if (unlikely((val & cr4_pinned_bits) != cr4_pinned_bits)) { | |
397 | bits_missing = ~val & cr4_pinned_bits; | |
398 | val |= bits_missing; | |
399 | goto set_register; | |
400 | } | |
401 | /* Warn after we've set the missing bits. */ | |
402 | WARN_ONCE(bits_missing, "CR4 bits went missing: %lx!?\n", | |
403 | bits_missing); | |
404 | } | |
405 | } | |
406 | EXPORT_SYMBOL(native_write_cr4); | |
407 | ||
408 | void cr4_init(void) | |
409 | { | |
410 | unsigned long cr4 = __read_cr4(); | |
411 | ||
412 | if (boot_cpu_has(X86_FEATURE_PCID)) | |
413 | cr4 |= X86_CR4_PCIDE; | |
414 | if (static_branch_likely(&cr_pinning)) | |
415 | cr4 |= cr4_pinned_bits; | |
416 | ||
417 | __write_cr4(cr4); | |
418 | ||
419 | /* Initialize cr4 shadow for this CPU. */ | |
420 | this_cpu_write(cpu_tlbstate.cr4, cr4); | |
421 | } | |
873d50d5 KC |
422 | |
423 | /* | |
424 | * Once CPU feature detection is finished (and boot params have been | |
425 | * parsed), record any of the sensitive CR bits that are set, and | |
426 | * enable CR pinning. | |
427 | */ | |
428 | static void __init setup_cr_pinning(void) | |
429 | { | |
430 | unsigned long mask; | |
431 | ||
432 | mask = (X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP); | |
433 | cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & mask; | |
434 | static_key_enable(&cr_pinning.key); | |
435 | } | |
436 | ||
06976945 DH |
437 | /* |
438 | * Protection Keys are not available in 32-bit mode. | |
439 | */ | |
440 | static bool pku_disabled; | |
441 | ||
442 | static __always_inline void setup_pku(struct cpuinfo_x86 *c) | |
443 | { | |
a5eff725 SAS |
444 | struct pkru_state *pk; |
445 | ||
e8df1a95 DH |
446 | /* check the boot processor, plus compile options for PKU: */ |
447 | if (!cpu_feature_enabled(X86_FEATURE_PKU)) | |
448 | return; | |
449 | /* checks the actual processor's cpuid bits: */ | |
06976945 DH |
450 | if (!cpu_has(c, X86_FEATURE_PKU)) |
451 | return; | |
452 | if (pku_disabled) | |
453 | return; | |
454 | ||
455 | cr4_set_bits(X86_CR4_PKE); | |
a5eff725 SAS |
456 | pk = get_xsave_addr(&init_fpstate.xsave, XFEATURE_PKRU); |
457 | if (pk) | |
458 | pk->pkru = init_pkru_value; | |
06976945 DH |
459 | /* |
460 | * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE | |
461 | * cpuid bit to be set. We need to ensure that we | |
462 | * update that bit in this CPU's "cpu_info". | |
463 | */ | |
464 | get_cpu_cap(c); | |
465 | } | |
466 | ||
467 | #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS | |
468 | static __init int setup_disable_pku(char *arg) | |
469 | { | |
470 | /* | |
471 | * Do not clear the X86_FEATURE_PKU bit. All of the | |
472 | * runtime checks are against OSPKE so clearing the | |
473 | * bit does nothing. | |
474 | * | |
475 | * This way, we will see "pku" in cpuinfo, but not | |
476 | * "ospke", which is exactly what we want. It shows | |
477 | * that the CPU has PKU, but the OS has not enabled it. | |
478 | * This happens to be exactly how a system would look | |
479 | * if we disabled the config option. | |
480 | */ | |
481 | pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); | |
482 | pku_disabled = true; | |
483 | return 1; | |
484 | } | |
485 | __setup("nopku", setup_disable_pku); | |
486 | #endif /* CONFIG_X86_64 */ | |
487 | ||
b38b0665 PA |
488 | /* |
489 | * Some CPU features depend on higher CPUID levels, which may not always | |
490 | * be available due to CPUID level capping or broken virtualization | |
491 | * software. Add those features to this table to auto-disable them. | |
492 | */ | |
493 | struct cpuid_dependent_feature { | |
494 | u32 feature; | |
495 | u32 level; | |
496 | }; | |
0f3fa48a | 497 | |
148f9bb8 | 498 | static const struct cpuid_dependent_feature |
b38b0665 PA |
499 | cpuid_dependent_features[] = { |
500 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
501 | { X86_FEATURE_DCA, 0x00000009 }, | |
502 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
503 | { 0, 0 } | |
504 | }; | |
505 | ||
148f9bb8 | 506 | static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) |
b38b0665 PA |
507 | { |
508 | const struct cpuid_dependent_feature *df; | |
9766cdbc | 509 | |
b38b0665 | 510 | for (df = cpuid_dependent_features; df->feature; df++) { |
0f3fa48a IM |
511 | |
512 | if (!cpu_has(c, df->feature)) | |
513 | continue; | |
b38b0665 PA |
514 | /* |
515 | * Note: cpuid_level is set to -1 if unavailable, but | |
516 | * extended_extended_level is set to 0 if unavailable | |
517 | * and the legitimate extended levels are all negative | |
518 | * when signed; hence the weird messing around with | |
519 | * signs here... | |
520 | */ | |
0f3fa48a | 521 | if (!((s32)df->level < 0 ? |
f6db44df | 522 | (u32)df->level > (u32)c->extended_cpuid_level : |
0f3fa48a IM |
523 | (s32)df->level > (s32)c->cpuid_level)) |
524 | continue; | |
525 | ||
526 | clear_cpu_cap(c, df->feature); | |
527 | if (!warn) | |
528 | continue; | |
529 | ||
1b74dde7 CY |
530 | pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", |
531 | x86_cap_flag(df->feature), df->level); | |
b38b0665 | 532 | } |
f6db44df | 533 | } |
b38b0665 | 534 | |
102bbe3a YL |
535 | /* |
536 | * Naming convention should be: <Name> [(<Codename>)] | |
537 | * This table only is used unless init_<vendor>() below doesn't set it; | |
0f3fa48a IM |
538 | * in particular, if CPUID levels 0x80000002..4 are supported, this |
539 | * isn't used | |
102bbe3a YL |
540 | */ |
541 | ||
542 | /* Look up CPU names by table lookup. */ | |
148f9bb8 | 543 | static const char *table_lookup_model(struct cpuinfo_x86 *c) |
102bbe3a | 544 | { |
09dc68d9 JB |
545 | #ifdef CONFIG_X86_32 |
546 | const struct legacy_cpu_model_info *info; | |
102bbe3a YL |
547 | |
548 | if (c->x86_model >= 16) | |
549 | return NULL; /* Range check */ | |
550 | ||
551 | if (!this_cpu) | |
552 | return NULL; | |
553 | ||
09dc68d9 | 554 | info = this_cpu->legacy_models; |
102bbe3a | 555 | |
09dc68d9 | 556 | while (info->family) { |
102bbe3a YL |
557 | if (info->family == c->x86) |
558 | return info->model_names[c->x86_model]; | |
559 | info++; | |
560 | } | |
09dc68d9 | 561 | #endif |
102bbe3a YL |
562 | return NULL; /* Not found */ |
563 | } | |
564 | ||
6cbd2171 TG |
565 | __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; |
566 | __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; | |
7d851c8d | 567 | |
11e3a840 JF |
568 | void load_percpu_segment(int cpu) |
569 | { | |
570 | #ifdef CONFIG_X86_32 | |
571 | loadsegment(fs, __KERNEL_PERCPU); | |
572 | #else | |
45e876f7 | 573 | __loadsegment_simple(gs, 0); |
35060ed6 | 574 | wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); |
11e3a840 | 575 | #endif |
60a5317f | 576 | load_stack_canary_segment(); |
11e3a840 JF |
577 | } |
578 | ||
72f5e08d AL |
579 | #ifdef CONFIG_X86_32 |
580 | /* The 32-bit entry code needs to find cpu_entry_area. */ | |
581 | DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); | |
582 | #endif | |
583 | ||
45fc8757 TG |
584 | /* Load the original GDT from the per-cpu structure */ |
585 | void load_direct_gdt(int cpu) | |
586 | { | |
587 | struct desc_ptr gdt_descr; | |
588 | ||
589 | gdt_descr.address = (long)get_cpu_gdt_rw(cpu); | |
590 | gdt_descr.size = GDT_SIZE - 1; | |
591 | load_gdt(&gdt_descr); | |
592 | } | |
593 | EXPORT_SYMBOL_GPL(load_direct_gdt); | |
594 | ||
69218e47 TG |
595 | /* Load a fixmap remapping of the per-cpu GDT */ |
596 | void load_fixmap_gdt(int cpu) | |
597 | { | |
598 | struct desc_ptr gdt_descr; | |
599 | ||
600 | gdt_descr.address = (long)get_cpu_gdt_ro(cpu); | |
601 | gdt_descr.size = GDT_SIZE - 1; | |
602 | load_gdt(&gdt_descr); | |
603 | } | |
45fc8757 | 604 | EXPORT_SYMBOL_GPL(load_fixmap_gdt); |
69218e47 | 605 | |
0f3fa48a IM |
606 | /* |
607 | * Current gdt points %fs at the "master" per-cpu area: after this, | |
608 | * it's on the real one. | |
609 | */ | |
552be871 | 610 | void switch_to_new_gdt(int cpu) |
9d31d35b | 611 | { |
45fc8757 TG |
612 | /* Load the original GDT */ |
613 | load_direct_gdt(cpu); | |
2697fbd5 | 614 | /* Reload the per-cpu base */ |
11e3a840 | 615 | load_percpu_segment(cpu); |
9d31d35b YL |
616 | } |
617 | ||
148f9bb8 | 618 | static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 619 | |
148f9bb8 | 620 | static void get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
621 | { |
622 | unsigned int *v; | |
ee098e1a | 623 | char *p, *q, *s; |
1da177e4 | 624 | |
3da99c97 | 625 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 626 | return; |
1da177e4 | 627 | |
0f3fa48a | 628 | v = (unsigned int *)c->x86_model_id; |
1da177e4 LT |
629 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); |
630 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
631 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
632 | c->x86_model_id[48] = 0; | |
633 | ||
ee098e1a BP |
634 | /* Trim whitespace */ |
635 | p = q = s = &c->x86_model_id[0]; | |
636 | ||
637 | while (*p == ' ') | |
638 | p++; | |
639 | ||
640 | while (*p) { | |
641 | /* Note the last non-whitespace index */ | |
642 | if (!isspace(*p)) | |
643 | s = q; | |
644 | ||
645 | *q++ = *p++; | |
646 | } | |
647 | ||
648 | *(s + 1) = '\0'; | |
1da177e4 LT |
649 | } |
650 | ||
9305bd6c | 651 | void detect_num_cpu_cores(struct cpuinfo_x86 *c) |
2cc61be6 DW |
652 | { |
653 | unsigned int eax, ebx, ecx, edx; | |
654 | ||
9305bd6c | 655 | c->x86_max_cores = 1; |
2cc61be6 | 656 | if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) |
9305bd6c | 657 | return; |
2cc61be6 DW |
658 | |
659 | cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); | |
660 | if (eax & 0x1f) | |
9305bd6c | 661 | c->x86_max_cores = (eax >> 26) + 1; |
2cc61be6 DW |
662 | } |
663 | ||
148f9bb8 | 664 | void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) |
1da177e4 | 665 | { |
9d31d35b | 666 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 667 | |
3da99c97 | 668 | n = c->extended_cpuid_level; |
1da177e4 LT |
669 | |
670 | if (n >= 0x80000005) { | |
9d31d35b | 671 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
9d31d35b | 672 | c->x86_cache_size = (ecx>>24) + (edx>>24); |
140fc727 YL |
673 | #ifdef CONFIG_X86_64 |
674 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
675 | c->x86_tlbsize = 0; | |
676 | #endif | |
1da177e4 LT |
677 | } |
678 | ||
679 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
680 | return; | |
681 | ||
0a488a53 | 682 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 683 | l2size = ecx >> 16; |
34048c9e | 684 | |
140fc727 YL |
685 | #ifdef CONFIG_X86_64 |
686 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
687 | #else | |
1da177e4 | 688 | /* do processor-specific cache resizing */ |
09dc68d9 JB |
689 | if (this_cpu->legacy_cache_size) |
690 | l2size = this_cpu->legacy_cache_size(c, l2size); | |
1da177e4 LT |
691 | |
692 | /* Allow user to override all this if necessary. */ | |
693 | if (cachesize_override != -1) | |
694 | l2size = cachesize_override; | |
695 | ||
34048c9e | 696 | if (l2size == 0) |
1da177e4 | 697 | return; /* Again, no L2 cache is possible */ |
140fc727 | 698 | #endif |
1da177e4 LT |
699 | |
700 | c->x86_cache_size = l2size; | |
1da177e4 LT |
701 | } |
702 | ||
e0ba94f1 AS |
703 | u16 __read_mostly tlb_lli_4k[NR_INFO]; |
704 | u16 __read_mostly tlb_lli_2m[NR_INFO]; | |
705 | u16 __read_mostly tlb_lli_4m[NR_INFO]; | |
706 | u16 __read_mostly tlb_lld_4k[NR_INFO]; | |
707 | u16 __read_mostly tlb_lld_2m[NR_INFO]; | |
708 | u16 __read_mostly tlb_lld_4m[NR_INFO]; | |
dd360393 | 709 | u16 __read_mostly tlb_lld_1g[NR_INFO]; |
e0ba94f1 | 710 | |
f94fe119 | 711 | static void cpu_detect_tlb(struct cpuinfo_x86 *c) |
e0ba94f1 AS |
712 | { |
713 | if (this_cpu->c_detect_tlb) | |
714 | this_cpu->c_detect_tlb(c); | |
715 | ||
f94fe119 | 716 | pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", |
e0ba94f1 | 717 | tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], |
f94fe119 SH |
718 | tlb_lli_4m[ENTRIES]); |
719 | ||
720 | pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", | |
721 | tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], | |
722 | tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); | |
e0ba94f1 AS |
723 | } |
724 | ||
545401f4 | 725 | int detect_ht_early(struct cpuinfo_x86 *c) |
1da177e4 | 726 | { |
c8e56d20 | 727 | #ifdef CONFIG_SMP |
0a488a53 | 728 | u32 eax, ebx, ecx, edx; |
1da177e4 | 729 | |
0a488a53 | 730 | if (!cpu_has(c, X86_FEATURE_HT)) |
545401f4 | 731 | return -1; |
1da177e4 | 732 | |
0a488a53 | 733 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
545401f4 | 734 | return -1; |
1da177e4 | 735 | |
1cd78776 | 736 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
545401f4 | 737 | return -1; |
1da177e4 | 738 | |
0a488a53 | 739 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 740 | |
9d31d35b | 741 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
545401f4 | 742 | if (smp_num_siblings == 1) |
1b74dde7 | 743 | pr_info_once("CPU0: Hyper-Threading is disabled\n"); |
545401f4 TG |
744 | #endif |
745 | return 0; | |
746 | } | |
9d31d35b | 747 | |
545401f4 TG |
748 | void detect_ht(struct cpuinfo_x86 *c) |
749 | { | |
750 | #ifdef CONFIG_SMP | |
751 | int index_msb, core_bits; | |
55e6d279 | 752 | |
545401f4 | 753 | if (detect_ht_early(c) < 0) |
55e6d279 | 754 | return; |
9d31d35b | 755 | |
0f3fa48a IM |
756 | index_msb = get_count_order(smp_num_siblings); |
757 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); | |
9d31d35b | 758 | |
0f3fa48a | 759 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
9d31d35b | 760 | |
0f3fa48a | 761 | index_msb = get_count_order(smp_num_siblings); |
9d31d35b | 762 | |
0f3fa48a | 763 | core_bits = get_count_order(c->x86_max_cores); |
9d31d35b | 764 | |
0f3fa48a IM |
765 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & |
766 | ((1 << core_bits) - 1); | |
9d31d35b | 767 | #endif |
97e4db7c | 768 | } |
1da177e4 | 769 | |
148f9bb8 | 770 | static void get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
771 | { |
772 | char *v = c->x86_vendor_id; | |
0f3fa48a | 773 | int i; |
1da177e4 LT |
774 | |
775 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
776 | if (!cpu_devs[i]) |
777 | break; | |
778 | ||
779 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
780 | (cpu_devs[i]->c_ident[1] && | |
781 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
0f3fa48a | 782 | |
10a434fc YL |
783 | this_cpu = cpu_devs[i]; |
784 | c->x86_vendor = this_cpu->c_x86_vendor; | |
785 | return; | |
1da177e4 LT |
786 | } |
787 | } | |
10a434fc | 788 | |
1b74dde7 CY |
789 | pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ |
790 | "CPU: Your system may be unstable.\n", v); | |
10a434fc | 791 | |
fe38d855 CE |
792 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
793 | this_cpu = &default_cpu; | |
1da177e4 LT |
794 | } |
795 | ||
148f9bb8 | 796 | void cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 797 | { |
1da177e4 | 798 | /* Get vendor name */ |
4a148513 HH |
799 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
800 | (unsigned int *)&c->x86_vendor_id[0], | |
801 | (unsigned int *)&c->x86_vendor_id[8], | |
802 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 803 | |
1da177e4 | 804 | c->x86 = 4; |
9d31d35b | 805 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
806 | if (c->cpuid_level >= 0x00000001) { |
807 | u32 junk, tfms, cap0, misc; | |
0f3fa48a | 808 | |
1da177e4 | 809 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
99f925ce BP |
810 | c->x86 = x86_family(tfms); |
811 | c->x86_model = x86_model(tfms); | |
b399151c | 812 | c->x86_stepping = x86_stepping(tfms); |
0f3fa48a | 813 | |
d4387bd3 | 814 | if (cap0 & (1<<19)) { |
d4387bd3 | 815 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 816 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 817 | } |
1da177e4 | 818 | } |
1da177e4 | 819 | } |
3da99c97 | 820 | |
8bf1ebca AL |
821 | static void apply_forced_caps(struct cpuinfo_x86 *c) |
822 | { | |
823 | int i; | |
824 | ||
6cbd2171 | 825 | for (i = 0; i < NCAPINTS + NBUGINTS; i++) { |
8bf1ebca AL |
826 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; |
827 | c->x86_capability[i] |= cpu_caps_set[i]; | |
828 | } | |
829 | } | |
830 | ||
7fcae111 DW |
831 | static void init_speculation_control(struct cpuinfo_x86 *c) |
832 | { | |
833 | /* | |
834 | * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, | |
835 | * and they also have a different bit for STIBP support. Also, | |
836 | * a hypervisor might have set the individual AMD bits even on | |
837 | * Intel CPUs, for finer-grained selection of what's available. | |
7fcae111 DW |
838 | */ |
839 | if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { | |
840 | set_cpu_cap(c, X86_FEATURE_IBRS); | |
841 | set_cpu_cap(c, X86_FEATURE_IBPB); | |
7eb8956a | 842 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); |
7fcae111 | 843 | } |
e7c587da | 844 | |
7fcae111 DW |
845 | if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) |
846 | set_cpu_cap(c, X86_FEATURE_STIBP); | |
e7c587da | 847 | |
bc226f07 TL |
848 | if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || |
849 | cpu_has(c, X86_FEATURE_VIRT_SSBD)) | |
52817587 TG |
850 | set_cpu_cap(c, X86_FEATURE_SSBD); |
851 | ||
7eb8956a | 852 | if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { |
e7c587da | 853 | set_cpu_cap(c, X86_FEATURE_IBRS); |
7eb8956a TG |
854 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); |
855 | } | |
e7c587da BP |
856 | |
857 | if (cpu_has(c, X86_FEATURE_AMD_IBPB)) | |
858 | set_cpu_cap(c, X86_FEATURE_IBPB); | |
859 | ||
7eb8956a | 860 | if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { |
e7c587da | 861 | set_cpu_cap(c, X86_FEATURE_STIBP); |
7eb8956a TG |
862 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); |
863 | } | |
6ac2f49e KRW |
864 | |
865 | if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { | |
866 | set_cpu_cap(c, X86_FEATURE_SSBD); | |
867 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); | |
868 | clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); | |
869 | } | |
7fcae111 DW |
870 | } |
871 | ||
45fc56e6 BP |
872 | static void init_cqm(struct cpuinfo_x86 *c) |
873 | { | |
acec0ce0 FY |
874 | if (!cpu_has(c, X86_FEATURE_CQM_LLC)) { |
875 | c->x86_cache_max_rmid = -1; | |
876 | c->x86_cache_occ_scale = -1; | |
877 | return; | |
878 | } | |
45fc56e6 | 879 | |
acec0ce0 FY |
880 | /* will be overridden if occupancy monitoring exists */ |
881 | c->x86_cache_max_rmid = cpuid_ebx(0xf); | |
882 | ||
883 | if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC) || | |
884 | cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL) || | |
885 | cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)) { | |
886 | u32 eax, ebx, ecx, edx; | |
887 | ||
888 | /* QoS sub-leaf, EAX=0Fh, ECX=1 */ | |
889 | cpuid_count(0xf, 1, &eax, &ebx, &ecx, &edx); | |
890 | ||
891 | c->x86_cache_max_rmid = ecx; | |
892 | c->x86_cache_occ_scale = ebx; | |
45fc56e6 BP |
893 | } |
894 | } | |
895 | ||
148f9bb8 | 896 | void get_cpu_cap(struct cpuinfo_x86 *c) |
093af8d7 | 897 | { |
39c06df4 | 898 | u32 eax, ebx, ecx, edx; |
093af8d7 | 899 | |
3da99c97 YL |
900 | /* Intel-defined flags: level 0x00000001 */ |
901 | if (c->cpuid_level >= 0x00000001) { | |
39c06df4 | 902 | cpuid(0x00000001, &eax, &ebx, &ecx, &edx); |
0f3fa48a | 903 | |
39c06df4 BP |
904 | c->x86_capability[CPUID_1_ECX] = ecx; |
905 | c->x86_capability[CPUID_1_EDX] = edx; | |
3da99c97 | 906 | } |
093af8d7 | 907 | |
3df8d920 AL |
908 | /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ |
909 | if (c->cpuid_level >= 0x00000006) | |
910 | c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); | |
911 | ||
bdc802dc PA |
912 | /* Additional Intel-defined flags: level 0x00000007 */ |
913 | if (c->cpuid_level >= 0x00000007) { | |
bdc802dc | 914 | cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); |
39c06df4 | 915 | c->x86_capability[CPUID_7_0_EBX] = ebx; |
dfb4a70f | 916 | c->x86_capability[CPUID_7_ECX] = ecx; |
95ca0ee8 | 917 | c->x86_capability[CPUID_7_EDX] = edx; |
b302e4b1 FY |
918 | |
919 | /* Check valid sub-leaf index before accessing it */ | |
920 | if (eax >= 1) { | |
921 | cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx); | |
922 | c->x86_capability[CPUID_7_1_EAX] = eax; | |
923 | } | |
bdc802dc PA |
924 | } |
925 | ||
6229ad27 FY |
926 | /* Extended state features: level 0x0000000d */ |
927 | if (c->cpuid_level >= 0x0000000d) { | |
6229ad27 FY |
928 | cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); |
929 | ||
39c06df4 | 930 | c->x86_capability[CPUID_D_1_EAX] = eax; |
6229ad27 FY |
931 | } |
932 | ||
3da99c97 | 933 | /* AMD-defined flags: level 0x80000001 */ |
39c06df4 BP |
934 | eax = cpuid_eax(0x80000000); |
935 | c->extended_cpuid_level = eax; | |
936 | ||
937 | if ((eax & 0xffff0000) == 0x80000000) { | |
938 | if (eax >= 0x80000001) { | |
939 | cpuid(0x80000001, &eax, &ebx, &ecx, &edx); | |
0f3fa48a | 940 | |
39c06df4 BP |
941 | c->x86_capability[CPUID_8000_0001_ECX] = ecx; |
942 | c->x86_capability[CPUID_8000_0001_EDX] = edx; | |
093af8d7 | 943 | } |
093af8d7 | 944 | } |
093af8d7 | 945 | |
71faad43 YG |
946 | if (c->extended_cpuid_level >= 0x80000007) { |
947 | cpuid(0x80000007, &eax, &ebx, &ecx, &edx); | |
948 | ||
949 | c->x86_capability[CPUID_8000_0007_EBX] = ebx; | |
950 | c->x86_power = edx; | |
951 | } | |
952 | ||
c65732e4 TG |
953 | if (c->extended_cpuid_level >= 0x80000008) { |
954 | cpuid(0x80000008, &eax, &ebx, &ecx, &edx); | |
955 | c->x86_capability[CPUID_8000_0008_EBX] = ebx; | |
956 | } | |
957 | ||
2ccd71f1 | 958 | if (c->extended_cpuid_level >= 0x8000000a) |
39c06df4 | 959 | c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); |
093af8d7 | 960 | |
1dedefd1 | 961 | init_scattered_cpuid_features(c); |
7fcae111 | 962 | init_speculation_control(c); |
45fc56e6 | 963 | init_cqm(c); |
60d34501 AL |
964 | |
965 | /* | |
966 | * Clear/Set all flags overridden by options, after probe. | |
967 | * This needs to happen each time we re-probe, which may happen | |
968 | * several times during CPU initialization. | |
969 | */ | |
970 | apply_forced_caps(c); | |
093af8d7 | 971 | } |
1da177e4 | 972 | |
405c018a | 973 | void get_cpu_address_sizes(struct cpuinfo_x86 *c) |
d94a155c KS |
974 | { |
975 | u32 eax, ebx, ecx, edx; | |
976 | ||
977 | if (c->extended_cpuid_level >= 0x80000008) { | |
978 | cpuid(0x80000008, &eax, &ebx, &ecx, &edx); | |
979 | ||
980 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
981 | c->x86_phys_bits = eax & 0xff; | |
d94a155c KS |
982 | } |
983 | #ifdef CONFIG_X86_32 | |
984 | else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) | |
985 | c->x86_phys_bits = 36; | |
986 | #endif | |
cc51e542 | 987 | c->x86_cache_bits = c->x86_phys_bits; |
d94a155c KS |
988 | } |
989 | ||
148f9bb8 | 990 | static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
aef93c8b YL |
991 | { |
992 | #ifdef CONFIG_X86_32 | |
993 | int i; | |
994 | ||
995 | /* | |
996 | * First of all, decide if this is a 486 or higher | |
997 | * It's a 486 if we can modify the AC flag | |
998 | */ | |
999 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
1000 | c->x86 = 4; | |
1001 | else | |
1002 | c->x86 = 3; | |
1003 | ||
1004 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
1005 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
1006 | c->x86_vendor_id[0] = 0; | |
1007 | cpu_devs[i]->c_identify(c); | |
1008 | if (c->x86_vendor_id[0]) { | |
1009 | get_cpu_vendor(c); | |
1010 | break; | |
1011 | } | |
1012 | } | |
1013 | #endif | |
1014 | } | |
1015 | ||
36ad3513 TG |
1016 | #define NO_SPECULATION BIT(0) |
1017 | #define NO_MELTDOWN BIT(1) | |
1018 | #define NO_SSB BIT(2) | |
1019 | #define NO_L1TF BIT(3) | |
ed5194c2 | 1020 | #define NO_MDS BIT(4) |
e261f209 | 1021 | #define MSBDS_ONLY BIT(5) |
f36cf386 | 1022 | #define NO_SWAPGS BIT(6) |
36ad3513 TG |
1023 | |
1024 | #define VULNWL(_vendor, _family, _model, _whitelist) \ | |
1025 | { X86_VENDOR_##_vendor, _family, _model, X86_FEATURE_ANY, _whitelist } | |
1026 | ||
1027 | #define VULNWL_INTEL(model, whitelist) \ | |
1028 | VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist) | |
1029 | ||
1030 | #define VULNWL_AMD(family, whitelist) \ | |
1031 | VULNWL(AMD, family, X86_MODEL_ANY, whitelist) | |
1032 | ||
1033 | #define VULNWL_HYGON(family, whitelist) \ | |
1034 | VULNWL(HYGON, family, X86_MODEL_ANY, whitelist) | |
1035 | ||
1036 | static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { | |
1037 | VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), | |
1038 | VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), | |
1039 | VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), | |
1040 | VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), | |
1041 | ||
ed5194c2 | 1042 | /* Intel Family 6 */ |
36ad3513 TG |
1043 | VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION), |
1044 | VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION), | |
1045 | VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION), | |
1046 | VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION), | |
1047 | VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION), | |
1048 | ||
f36cf386 | 1049 | VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS), |
5ebb34ed | 1050 | VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS), |
f36cf386 TG |
1051 | VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS), |
1052 | VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS), | |
1053 | VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS), | |
1054 | VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS), | |
36ad3513 TG |
1055 | |
1056 | VULNWL_INTEL(CORE_YONAH, NO_SSB), | |
1057 | ||
f36cf386 | 1058 | VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS), |
0cc5359d | 1059 | VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS), |
36ad3513 | 1060 | |
f36cf386 | 1061 | VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS), |
5ebb34ed | 1062 | VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS), |
f36cf386 TG |
1063 | VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS), |
1064 | ||
1065 | /* | |
1066 | * Technically, swapgs isn't serializing on AMD (despite it previously | |
1067 | * being documented as such in the APM). But according to AMD, %gs is | |
1068 | * updated non-speculatively, and the issuing of %gs-relative memory | |
1069 | * operands will be blocked until the %gs update completes, which is | |
1070 | * good enough for our purposes. | |
1071 | */ | |
ed5194c2 AK |
1072 | |
1073 | /* AMD Family 0xf - 0x12 */ | |
f36cf386 TG |
1074 | VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS), |
1075 | VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS), | |
1076 | VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS), | |
1077 | VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS), | |
36ad3513 TG |
1078 | |
1079 | /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ | |
f36cf386 TG |
1080 | VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS), |
1081 | VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS), | |
fec9434a DW |
1082 | {} |
1083 | }; | |
1084 | ||
36ad3513 TG |
1085 | static bool __init cpu_matches(unsigned long which) |
1086 | { | |
1087 | const struct x86_cpu_id *m = x86_match_cpu(cpu_vuln_whitelist); | |
c456442c | 1088 | |
36ad3513 TG |
1089 | return m && !!(m->driver_data & which); |
1090 | } | |
17dbca11 | 1091 | |
4a28bfe3 | 1092 | static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) |
fec9434a DW |
1093 | { |
1094 | u64 ia32_cap = 0; | |
1095 | ||
36ad3513 | 1096 | if (cpu_matches(NO_SPECULATION)) |
8ecc4979 DB |
1097 | return; |
1098 | ||
1099 | setup_force_cpu_bug(X86_BUG_SPECTRE_V1); | |
1100 | setup_force_cpu_bug(X86_BUG_SPECTRE_V2); | |
1101 | ||
77243971 KRW |
1102 | if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES)) |
1103 | rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); | |
1104 | ||
36ad3513 | 1105 | if (!cpu_matches(NO_SSB) && !(ia32_cap & ARCH_CAP_SSB_NO) && |
24809860 | 1106 | !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) |
c456442c KRW |
1107 | setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); |
1108 | ||
706d5168 SP |
1109 | if (ia32_cap & ARCH_CAP_IBRS_ALL) |
1110 | setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); | |
1111 | ||
e261f209 | 1112 | if (!cpu_matches(NO_MDS) && !(ia32_cap & ARCH_CAP_MDS_NO)) { |
ed5194c2 | 1113 | setup_force_cpu_bug(X86_BUG_MDS); |
e261f209 TG |
1114 | if (cpu_matches(MSBDS_ONLY)) |
1115 | setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); | |
1116 | } | |
ed5194c2 | 1117 | |
f36cf386 TG |
1118 | if (!cpu_matches(NO_SWAPGS)) |
1119 | setup_force_cpu_bug(X86_BUG_SWAPGS); | |
1120 | ||
36ad3513 | 1121 | if (cpu_matches(NO_MELTDOWN)) |
4a28bfe3 | 1122 | return; |
fec9434a | 1123 | |
fec9434a DW |
1124 | /* Rogue Data Cache Load? No! */ |
1125 | if (ia32_cap & ARCH_CAP_RDCL_NO) | |
4a28bfe3 | 1126 | return; |
fec9434a | 1127 | |
4a28bfe3 | 1128 | setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); |
17dbca11 | 1129 | |
36ad3513 | 1130 | if (cpu_matches(NO_L1TF)) |
17dbca11 AK |
1131 | return; |
1132 | ||
1133 | setup_force_cpu_bug(X86_BUG_L1TF); | |
fec9434a DW |
1134 | } |
1135 | ||
8990cac6 PT |
1136 | /* |
1137 | * The NOPL instruction is supposed to exist on all CPUs of family >= 6; | |
1138 | * unfortunately, that's not true in practice because of early VIA | |
1139 | * chips and (more importantly) broken virtualizers that are not easy | |
1140 | * to detect. In the latter case it doesn't even *fail* reliably, so | |
1141 | * probing for it doesn't even work. Disable it completely on 32-bit | |
1142 | * unless we can find a reliable way to detect all the broken cases. | |
1143 | * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). | |
1144 | */ | |
9b3661cd | 1145 | static void detect_nopl(void) |
8990cac6 PT |
1146 | { |
1147 | #ifdef CONFIG_X86_32 | |
9b3661cd | 1148 | setup_clear_cpu_cap(X86_FEATURE_NOPL); |
8990cac6 | 1149 | #else |
9b3661cd | 1150 | setup_force_cpu_cap(X86_FEATURE_NOPL); |
8990cac6 PT |
1151 | #endif |
1152 | } | |
1153 | ||
34048c9e PC |
1154 | /* |
1155 | * Do minimum CPU detection early. | |
1156 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
1157 | * cache alignment. | |
1158 | * The others are not touched to avoid unwanted side effects. | |
1159 | * | |
a1652bb8 JD |
1160 | * WARNING: this function is only called on the boot CPU. Don't add code |
1161 | * here that is supposed to run on all CPUs. | |
34048c9e | 1162 | */ |
3da99c97 | 1163 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 1164 | { |
6627d242 YL |
1165 | #ifdef CONFIG_X86_64 |
1166 | c->x86_clflush_size = 64; | |
13c6c532 JB |
1167 | c->x86_phys_bits = 36; |
1168 | c->x86_virt_bits = 48; | |
6627d242 | 1169 | #else |
d4387bd3 | 1170 | c->x86_clflush_size = 32; |
13c6c532 JB |
1171 | c->x86_phys_bits = 32; |
1172 | c->x86_virt_bits = 32; | |
6627d242 | 1173 | #endif |
0a488a53 | 1174 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 1175 | |
0e96f31e | 1176 | memset(&c->x86_capability, 0, sizeof(c->x86_capability)); |
0a488a53 | 1177 | c->extended_cpuid_level = 0; |
d7cd5611 | 1178 | |
2893cc8f MW |
1179 | if (!have_cpuid_p()) |
1180 | identify_cpu_without_cpuid(c); | |
1181 | ||
aef93c8b | 1182 | /* cyrix could have cpuid enabled via c_identify()*/ |
05fb3c19 AL |
1183 | if (have_cpuid_p()) { |
1184 | cpu_detect(c); | |
1185 | get_cpu_vendor(c); | |
1186 | get_cpu_cap(c); | |
d94a155c | 1187 | get_cpu_address_sizes(c); |
78d1b296 | 1188 | setup_force_cpu_cap(X86_FEATURE_CPUID); |
d7cd5611 | 1189 | |
05fb3c19 AL |
1190 | if (this_cpu->c_early_init) |
1191 | this_cpu->c_early_init(c); | |
12cf105c | 1192 | |
05fb3c19 AL |
1193 | c->cpu_index = 0; |
1194 | filter_cpuid_features(c, false); | |
093af8d7 | 1195 | |
05fb3c19 AL |
1196 | if (this_cpu->c_bsp_init) |
1197 | this_cpu->c_bsp_init(c); | |
78d1b296 | 1198 | } else { |
78d1b296 | 1199 | setup_clear_cpu_cap(X86_FEATURE_CPUID); |
05fb3c19 | 1200 | } |
c3b83598 BP |
1201 | |
1202 | setup_force_cpu_cap(X86_FEATURE_ALWAYS); | |
a89f040f | 1203 | |
4a28bfe3 | 1204 | cpu_set_bug_bits(c); |
99c6fa25 | 1205 | |
db52ef74 | 1206 | fpu__init_system(c); |
b8b7abae AL |
1207 | |
1208 | #ifdef CONFIG_X86_32 | |
1209 | /* | |
1210 | * Regardless of whether PCID is enumerated, the SDM says | |
1211 | * that it can't be enabled in 32-bit mode. | |
1212 | */ | |
1213 | setup_clear_cpu_cap(X86_FEATURE_PCID); | |
1214 | #endif | |
372fddf7 KS |
1215 | |
1216 | /* | |
1217 | * Later in the boot process pgtable_l5_enabled() relies on | |
1218 | * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not | |
1219 | * enabled by this point we need to clear the feature bit to avoid | |
1220 | * false-positives at the later stage. | |
1221 | * | |
1222 | * pgtable_l5_enabled() can be false here for several reasons: | |
1223 | * - 5-level paging is disabled compile-time; | |
1224 | * - it's 32-bit kernel; | |
1225 | * - machine doesn't support 5-level paging; | |
1226 | * - user specified 'no5lvl' in kernel command line. | |
1227 | */ | |
1228 | if (!pgtable_l5_enabled()) | |
1229 | setup_clear_cpu_cap(X86_FEATURE_LA57); | |
8990cac6 | 1230 | |
9b3661cd | 1231 | detect_nopl(); |
d7cd5611 RR |
1232 | } |
1233 | ||
9d31d35b YL |
1234 | void __init early_cpu_init(void) |
1235 | { | |
02dde8b4 | 1236 | const struct cpu_dev *const *cdev; |
10a434fc YL |
1237 | int count = 0; |
1238 | ||
ac23f253 | 1239 | #ifdef CONFIG_PROCESSOR_SELECT |
1b74dde7 | 1240 | pr_info("KERNEL supported cpus:\n"); |
31c997ca IM |
1241 | #endif |
1242 | ||
10a434fc | 1243 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { |
02dde8b4 | 1244 | const struct cpu_dev *cpudev = *cdev; |
9d31d35b | 1245 | |
10a434fc YL |
1246 | if (count >= X86_VENDOR_NUM) |
1247 | break; | |
1248 | cpu_devs[count] = cpudev; | |
1249 | count++; | |
1250 | ||
ac23f253 | 1251 | #ifdef CONFIG_PROCESSOR_SELECT |
31c997ca IM |
1252 | { |
1253 | unsigned int j; | |
1254 | ||
1255 | for (j = 0; j < 2; j++) { | |
1256 | if (!cpudev->c_ident[j]) | |
1257 | continue; | |
1b74dde7 | 1258 | pr_info(" %s %s\n", cpudev->c_vendor, |
31c997ca IM |
1259 | cpudev->c_ident[j]); |
1260 | } | |
10a434fc | 1261 | } |
0388423d | 1262 | #endif |
10a434fc | 1263 | } |
9d31d35b | 1264 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 1265 | } |
093af8d7 | 1266 | |
7a5d6704 AL |
1267 | static void detect_null_seg_behavior(struct cpuinfo_x86 *c) |
1268 | { | |
1269 | #ifdef CONFIG_X86_64 | |
58a5aac5 | 1270 | /* |
7a5d6704 AL |
1271 | * Empirically, writing zero to a segment selector on AMD does |
1272 | * not clear the base, whereas writing zero to a segment | |
1273 | * selector on Intel does clear the base. Intel's behavior | |
1274 | * allows slightly faster context switches in the common case | |
1275 | * where GS is unused by the prev and next threads. | |
58a5aac5 | 1276 | * |
7a5d6704 AL |
1277 | * Since neither vendor documents this anywhere that I can see, |
1278 | * detect it directly instead of hardcoding the choice by | |
1279 | * vendor. | |
1280 | * | |
1281 | * I've designated AMD's behavior as the "bug" because it's | |
1282 | * counterintuitive and less friendly. | |
58a5aac5 | 1283 | */ |
7a5d6704 AL |
1284 | |
1285 | unsigned long old_base, tmp; | |
1286 | rdmsrl(MSR_FS_BASE, old_base); | |
1287 | wrmsrl(MSR_FS_BASE, 1); | |
1288 | loadsegment(fs, 0); | |
1289 | rdmsrl(MSR_FS_BASE, tmp); | |
1290 | if (tmp != 0) | |
1291 | set_cpu_bug(c, X86_BUG_NULL_SEG); | |
1292 | wrmsrl(MSR_FS_BASE, old_base); | |
366d4a43 | 1293 | #endif |
d7cd5611 RR |
1294 | } |
1295 | ||
148f9bb8 | 1296 | static void generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 1297 | { |
aef93c8b | 1298 | c->extended_cpuid_level = 0; |
1da177e4 | 1299 | |
3da99c97 | 1300 | if (!have_cpuid_p()) |
aef93c8b | 1301 | identify_cpu_without_cpuid(c); |
1d67953f | 1302 | |
aef93c8b | 1303 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 1304 | if (!have_cpuid_p()) |
aef93c8b | 1305 | return; |
1da177e4 | 1306 | |
3da99c97 | 1307 | cpu_detect(c); |
1da177e4 | 1308 | |
3da99c97 | 1309 | get_cpu_vendor(c); |
1da177e4 | 1310 | |
3da99c97 | 1311 | get_cpu_cap(c); |
1da177e4 | 1312 | |
d94a155c KS |
1313 | get_cpu_address_sizes(c); |
1314 | ||
3da99c97 YL |
1315 | if (c->cpuid_level >= 0x00000001) { |
1316 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e | 1317 | #ifdef CONFIG_X86_32 |
c8e56d20 | 1318 | # ifdef CONFIG_SMP |
cb8cc442 | 1319 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 1320 | # else |
3da99c97 | 1321 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
1322 | # endif |
1323 | #endif | |
b89d3b3e | 1324 | c->phys_proc_id = c->initial_apicid; |
3da99c97 | 1325 | } |
1da177e4 | 1326 | |
1b05d60d | 1327 | get_model_name(c); /* Default name */ |
1da177e4 | 1328 | |
7a5d6704 | 1329 | detect_null_seg_behavior(c); |
0230bb03 AL |
1330 | |
1331 | /* | |
1332 | * ESPFIX is a strange bug. All real CPUs have it. Paravirt | |
1333 | * systems that run Linux at CPL > 0 may or may not have the | |
1334 | * issue, but, even if they have the issue, there's absolutely | |
1335 | * nothing we can do about it because we can't use the real IRET | |
1336 | * instruction. | |
1337 | * | |
1338 | * NB: For the time being, only 32-bit kernels support | |
1339 | * X86_BUG_ESPFIX as such. 64-bit kernels directly choose | |
1340 | * whether to apply espfix using paravirt hooks. If any | |
1341 | * non-paravirt system ever shows up that does *not* have the | |
1342 | * ESPFIX issue, we can change this. | |
1343 | */ | |
1344 | #ifdef CONFIG_X86_32 | |
9bad5658 | 1345 | # ifdef CONFIG_PARAVIRT_XXL |
0230bb03 AL |
1346 | do { |
1347 | extern void native_iret(void); | |
5c83511b | 1348 | if (pv_ops.cpu.iret == native_iret) |
0230bb03 AL |
1349 | set_cpu_bug(c, X86_BUG_ESPFIX); |
1350 | } while (0); | |
1351 | # else | |
1352 | set_cpu_bug(c, X86_BUG_ESPFIX); | |
1353 | # endif | |
1354 | #endif | |
1da177e4 | 1355 | } |
1da177e4 | 1356 | |
cbc82b17 PWJ |
1357 | static void x86_init_cache_qos(struct cpuinfo_x86 *c) |
1358 | { | |
1359 | /* | |
1360 | * The heavy lifting of max_rmid and cache_occ_scale are handled | |
1361 | * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu | |
1362 | * in case CQM bits really aren't there in this CPU. | |
1363 | */ | |
1364 | if (c != &boot_cpu_data) { | |
1365 | boot_cpu_data.x86_cache_max_rmid = | |
1366 | min(boot_cpu_data.x86_cache_max_rmid, | |
1367 | c->x86_cache_max_rmid); | |
1368 | } | |
1369 | } | |
1370 | ||
d49597fd | 1371 | /* |
9d85eb91 TG |
1372 | * Validate that ACPI/mptables have the same information about the |
1373 | * effective APIC id and update the package map. | |
d49597fd | 1374 | */ |
9d85eb91 | 1375 | static void validate_apic_and_package_id(struct cpuinfo_x86 *c) |
d49597fd TG |
1376 | { |
1377 | #ifdef CONFIG_SMP | |
9d85eb91 | 1378 | unsigned int apicid, cpu = smp_processor_id(); |
d49597fd TG |
1379 | |
1380 | apicid = apic->cpu_present_to_apicid(cpu); | |
d49597fd | 1381 | |
9d85eb91 TG |
1382 | if (apicid != c->apicid) { |
1383 | pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", | |
d49597fd | 1384 | cpu, apicid, c->initial_apicid); |
d49597fd | 1385 | } |
9d85eb91 | 1386 | BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); |
212bf4fd | 1387 | BUG_ON(topology_update_die_map(c->cpu_die_id, cpu)); |
d49597fd TG |
1388 | #else |
1389 | c->logical_proc_id = 0; | |
1390 | #endif | |
1391 | } | |
1392 | ||
1da177e4 LT |
1393 | /* |
1394 | * This does the hard work of actually picking apart the CPU stuff... | |
1395 | */ | |
148f9bb8 | 1396 | static void identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
1397 | { |
1398 | int i; | |
1399 | ||
1400 | c->loops_per_jiffy = loops_per_jiffy; | |
24dbc600 | 1401 | c->x86_cache_size = 0; |
1da177e4 | 1402 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
b399151c | 1403 | c->x86_model = c->x86_stepping = 0; /* So far unknown... */ |
1da177e4 LT |
1404 | c->x86_vendor_id[0] = '\0'; /* Unset */ |
1405 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 1406 | c->x86_max_cores = 1; |
102bbe3a | 1407 | c->x86_coreid_bits = 0; |
79a8b9aa | 1408 | c->cu_id = 0xff; |
11fdd252 | 1409 | #ifdef CONFIG_X86_64 |
102bbe3a | 1410 | c->x86_clflush_size = 64; |
13c6c532 JB |
1411 | c->x86_phys_bits = 36; |
1412 | c->x86_virt_bits = 48; | |
102bbe3a YL |
1413 | #else |
1414 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 1415 | c->x86_clflush_size = 32; |
13c6c532 JB |
1416 | c->x86_phys_bits = 32; |
1417 | c->x86_virt_bits = 32; | |
102bbe3a YL |
1418 | #endif |
1419 | c->x86_cache_alignment = c->x86_clflush_size; | |
0e96f31e | 1420 | memset(&c->x86_capability, 0, sizeof(c->x86_capability)); |
1da177e4 | 1421 | |
1da177e4 LT |
1422 | generic_identify(c); |
1423 | ||
3898534d | 1424 | if (this_cpu->c_identify) |
1da177e4 LT |
1425 | this_cpu->c_identify(c); |
1426 | ||
6a6256f9 | 1427 | /* Clear/Set all flags overridden by options, after probe */ |
8bf1ebca | 1428 | apply_forced_caps(c); |
2759c328 | 1429 | |
102bbe3a | 1430 | #ifdef CONFIG_X86_64 |
cb8cc442 | 1431 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
1432 | #endif |
1433 | ||
1da177e4 LT |
1434 | /* |
1435 | * Vendor-specific initialization. In this section we | |
1436 | * canonicalize the feature flags, meaning if there are | |
1437 | * features a certain CPU supports which CPUID doesn't | |
1438 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
1439 | * we handle them here. | |
1440 | * | |
1441 | * At the end of this section, c->x86_capability better | |
1442 | * indicate the features this CPU genuinely supports! | |
1443 | */ | |
1444 | if (this_cpu->c_init) | |
1445 | this_cpu->c_init(c); | |
1446 | ||
1447 | /* Disable the PN if appropriate */ | |
1448 | squash_the_stupid_serial_number(c); | |
1449 | ||
aa35f896 | 1450 | /* Set up SMEP/SMAP/UMIP */ |
b2cc2a07 PA |
1451 | setup_smep(c); |
1452 | setup_smap(c); | |
aa35f896 | 1453 | setup_umip(c); |
b2cc2a07 | 1454 | |
1da177e4 | 1455 | /* |
0f3fa48a IM |
1456 | * The vendor-specific functions might have changed features. |
1457 | * Now we do "generic changes." | |
1da177e4 LT |
1458 | */ |
1459 | ||
b38b0665 PA |
1460 | /* Filter out anything that depends on CPUID levels we don't have */ |
1461 | filter_cpuid_features(c, true); | |
1462 | ||
1da177e4 | 1463 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 1464 | if (!c->x86_model_id[0]) { |
02dde8b4 | 1465 | const char *p; |
1da177e4 | 1466 | p = table_lookup_model(c); |
34048c9e | 1467 | if (p) |
1da177e4 LT |
1468 | strcpy(c->x86_model_id, p); |
1469 | else | |
1470 | /* Last resort... */ | |
1471 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 1472 | c->x86, c->x86_model); |
1da177e4 LT |
1473 | } |
1474 | ||
102bbe3a YL |
1475 | #ifdef CONFIG_X86_64 |
1476 | detect_ht(c); | |
1477 | #endif | |
1478 | ||
49d859d7 | 1479 | x86_init_rdrand(c); |
cbc82b17 | 1480 | x86_init_cache_qos(c); |
06976945 | 1481 | setup_pku(c); |
3e0c3737 YL |
1482 | |
1483 | /* | |
6a6256f9 | 1484 | * Clear/Set all flags overridden by options, need do it |
3e0c3737 YL |
1485 | * before following smp all cpus cap AND. |
1486 | */ | |
8bf1ebca | 1487 | apply_forced_caps(c); |
3e0c3737 | 1488 | |
1da177e4 LT |
1489 | /* |
1490 | * On SMP, boot_cpu_data holds the common feature set between | |
1491 | * all CPUs; so make sure that we indicate which features are | |
1492 | * common between the CPUs. The first time this routine gets | |
1493 | * executed, c == &boot_cpu_data. | |
1494 | */ | |
34048c9e | 1495 | if (c != &boot_cpu_data) { |
1da177e4 | 1496 | /* AND the already accumulated flags with these */ |
9d31d35b | 1497 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 | 1498 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
65fc985b BP |
1499 | |
1500 | /* OR, i.e. replicate the bug flags */ | |
1501 | for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) | |
1502 | c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; | |
1da177e4 LT |
1503 | } |
1504 | ||
1505 | /* Init Machine Check Exception if available. */ | |
5e09954a | 1506 | mcheck_cpu_init(c); |
30d432df AK |
1507 | |
1508 | select_idle_routine(c); | |
102bbe3a | 1509 | |
de2d9445 | 1510 | #ifdef CONFIG_NUMA |
102bbe3a YL |
1511 | numa_add_cpu(smp_processor_id()); |
1512 | #endif | |
a6c4e076 | 1513 | } |
31ab269a | 1514 | |
8b6c0ab1 IM |
1515 | /* |
1516 | * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions | |
1517 | * on 32-bit kernels: | |
1518 | */ | |
cfda7bb9 AL |
1519 | #ifdef CONFIG_X86_32 |
1520 | void enable_sep_cpu(void) | |
1521 | { | |
8b6c0ab1 IM |
1522 | struct tss_struct *tss; |
1523 | int cpu; | |
cfda7bb9 | 1524 | |
b3edfda4 BP |
1525 | if (!boot_cpu_has(X86_FEATURE_SEP)) |
1526 | return; | |
1527 | ||
8b6c0ab1 | 1528 | cpu = get_cpu(); |
c482feef | 1529 | tss = &per_cpu(cpu_tss_rw, cpu); |
8b6c0ab1 | 1530 | |
8b6c0ab1 | 1531 | /* |
cf9328cc AL |
1532 | * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- |
1533 | * see the big comment in struct x86_hw_tss's definition. | |
8b6c0ab1 | 1534 | */ |
cfda7bb9 AL |
1535 | |
1536 | tss->x86_tss.ss1 = __KERNEL_CS; | |
8b6c0ab1 | 1537 | wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); |
4fe2d8b1 | 1538 | wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); |
4c8cd0c5 | 1539 | wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); |
8b6c0ab1 | 1540 | |
cfda7bb9 AL |
1541 | put_cpu(); |
1542 | } | |
e04d645f GC |
1543 | #endif |
1544 | ||
a6c4e076 JF |
1545 | void __init identify_boot_cpu(void) |
1546 | { | |
1547 | identify_cpu(&boot_cpu_data); | |
102bbe3a | 1548 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1549 | sysenter_setup(); |
6fe940d6 | 1550 | enable_sep_cpu(); |
102bbe3a | 1551 | #endif |
5b556332 | 1552 | cpu_detect_tlb(&boot_cpu_data); |
873d50d5 | 1553 | setup_cr_pinning(); |
a6c4e076 | 1554 | } |
3b520b23 | 1555 | |
148f9bb8 | 1556 | void identify_secondary_cpu(struct cpuinfo_x86 *c) |
a6c4e076 JF |
1557 | { |
1558 | BUG_ON(c == &boot_cpu_data); | |
1559 | identify_cpu(c); | |
102bbe3a | 1560 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1561 | enable_sep_cpu(); |
102bbe3a | 1562 | #endif |
a6c4e076 | 1563 | mtrr_ap_init(); |
9d85eb91 | 1564 | validate_apic_and_package_id(c); |
77243971 | 1565 | x86_spec_ctrl_setup_ap(); |
1da177e4 LT |
1566 | } |
1567 | ||
191679fd AK |
1568 | static __init int setup_noclflush(char *arg) |
1569 | { | |
840d2830 | 1570 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); |
da4aaa7d | 1571 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); |
191679fd AK |
1572 | return 1; |
1573 | } | |
1574 | __setup("noclflush", setup_noclflush); | |
1575 | ||
148f9bb8 | 1576 | void print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 | 1577 | { |
02dde8b4 | 1578 | const char *vendor = NULL; |
1da177e4 | 1579 | |
0f3fa48a | 1580 | if (c->x86_vendor < X86_VENDOR_NUM) { |
1da177e4 | 1581 | vendor = this_cpu->c_vendor; |
0f3fa48a IM |
1582 | } else { |
1583 | if (c->cpuid_level >= 0) | |
1584 | vendor = c->x86_vendor_id; | |
1585 | } | |
1da177e4 | 1586 | |
bd32a8cf | 1587 | if (vendor && !strstr(c->x86_model_id, vendor)) |
1b74dde7 | 1588 | pr_cont("%s ", vendor); |
1da177e4 | 1589 | |
9d31d35b | 1590 | if (c->x86_model_id[0]) |
1b74dde7 | 1591 | pr_cont("%s", c->x86_model_id); |
1da177e4 | 1592 | else |
1b74dde7 | 1593 | pr_cont("%d86", c->x86); |
1da177e4 | 1594 | |
1b74dde7 | 1595 | pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); |
924e101a | 1596 | |
b399151c JZ |
1597 | if (c->x86_stepping || c->cpuid_level >= 0) |
1598 | pr_cont(", stepping: 0x%x)\n", c->x86_stepping); | |
1da177e4 | 1599 | else |
1b74dde7 | 1600 | pr_cont(")\n"); |
1da177e4 LT |
1601 | } |
1602 | ||
0c2a3913 AK |
1603 | /* |
1604 | * clearcpuid= was already parsed in fpu__init_parse_early_param. | |
1605 | * But we need to keep a dummy __setup around otherwise it would | |
1606 | * show up as an environment variable for init. | |
1607 | */ | |
1608 | static __init int setup_clearcpuid(char *arg) | |
ac72e788 | 1609 | { |
ac72e788 AK |
1610 | return 1; |
1611 | } | |
0c2a3913 | 1612 | __setup("clearcpuid=", setup_clearcpuid); |
ac72e788 | 1613 | |
d5494d4f | 1614 | #ifdef CONFIG_X86_64 |
e6401c13 AL |
1615 | DEFINE_PER_CPU_FIRST(struct fixed_percpu_data, |
1616 | fixed_percpu_data) __aligned(PAGE_SIZE) __visible; | |
1617 | EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data); | |
0f3fa48a | 1618 | |
bdf977b3 | 1619 | /* |
a7fcf28d AL |
1620 | * The following percpu variables are hot. Align current_task to |
1621 | * cacheline size such that they fall in the same cacheline. | |
bdf977b3 TH |
1622 | */ |
1623 | DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = | |
1624 | &init_task; | |
1625 | EXPORT_PER_CPU_SYMBOL(current_task); | |
d5494d4f | 1626 | |
e6401c13 | 1627 | DEFINE_PER_CPU(struct irq_stack *, hardirq_stack_ptr); |
277d5b40 | 1628 | DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; |
d5494d4f | 1629 | |
c2daa3be PZ |
1630 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1631 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
1632 | ||
d5494d4f YL |
1633 | /* May not be marked __init: used by software suspend */ |
1634 | void syscall_init(void) | |
1da177e4 | 1635 | { |
31ac34ca | 1636 | wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); |
bf904d27 | 1637 | wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); |
d56fe4bf IM |
1638 | |
1639 | #ifdef CONFIG_IA32_EMULATION | |
47edb651 | 1640 | wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); |
a76c7f46 | 1641 | /* |
487d1edb DV |
1642 | * This only works on Intel CPUs. |
1643 | * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. | |
1644 | * This does not cause SYSENTER to jump to the wrong location, because | |
1645 | * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). | |
a76c7f46 DV |
1646 | */ |
1647 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); | |
8e6b65a1 | 1648 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, |
1649 | (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); | |
4c8cd0c5 | 1650 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); |
d56fe4bf | 1651 | #else |
47edb651 | 1652 | wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); |
6b51311c | 1653 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); |
d56fe4bf IM |
1654 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); |
1655 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); | |
d5494d4f | 1656 | #endif |
03ae5768 | 1657 | |
d5494d4f YL |
1658 | /* Flags to clear on syscall */ |
1659 | wrmsrl(MSR_SYSCALL_MASK, | |
63bcff2a | 1660 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| |
8c7aa698 | 1661 | X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); |
1da177e4 | 1662 | } |
62111195 | 1663 | |
42181186 | 1664 | DEFINE_PER_CPU(int, debug_stack_usage); |
629f4f9d | 1665 | DEFINE_PER_CPU(u32, debug_idt_ctr); |
f8988175 | 1666 | |
228bdaa9 SR |
1667 | void debug_stack_set_zero(void) |
1668 | { | |
629f4f9d SA |
1669 | this_cpu_inc(debug_idt_ctr); |
1670 | load_current_idt(); | |
228bdaa9 | 1671 | } |
0f46efeb | 1672 | NOKPROBE_SYMBOL(debug_stack_set_zero); |
228bdaa9 SR |
1673 | |
1674 | void debug_stack_reset(void) | |
1675 | { | |
629f4f9d | 1676 | if (WARN_ON(!this_cpu_read(debug_idt_ctr))) |
f8988175 | 1677 | return; |
629f4f9d SA |
1678 | if (this_cpu_dec_return(debug_idt_ctr) == 0) |
1679 | load_current_idt(); | |
228bdaa9 | 1680 | } |
0f46efeb | 1681 | NOKPROBE_SYMBOL(debug_stack_reset); |
228bdaa9 | 1682 | |
0f3fa48a | 1683 | #else /* CONFIG_X86_64 */ |
d5494d4f | 1684 | |
bdf977b3 TH |
1685 | DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; |
1686 | EXPORT_PER_CPU_SYMBOL(current_task); | |
c2daa3be PZ |
1687 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1688 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
bdf977b3 | 1689 | |
a7fcf28d AL |
1690 | /* |
1691 | * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find | |
1692 | * the top of the kernel stack. Use an extra percpu variable to track the | |
1693 | * top of the kernel stack directly. | |
1694 | */ | |
1695 | DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = | |
1696 | (unsigned long)&init_thread_union + THREAD_SIZE; | |
1697 | EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); | |
1698 | ||
050e9baa | 1699 | #ifdef CONFIG_STACKPROTECTOR |
53f82452 | 1700 | DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); |
60a5317f | 1701 | #endif |
d5494d4f | 1702 | |
0f3fa48a | 1703 | #endif /* CONFIG_X86_64 */ |
c5413fbe | 1704 | |
9766cdbc JSR |
1705 | /* |
1706 | * Clear all 6 debug registers: | |
1707 | */ | |
1708 | static void clear_all_debug_regs(void) | |
1709 | { | |
1710 | int i; | |
1711 | ||
1712 | for (i = 0; i < 8; i++) { | |
1713 | /* Ignore db4, db5 */ | |
1714 | if ((i == 4) || (i == 5)) | |
1715 | continue; | |
1716 | ||
1717 | set_debugreg(0, i); | |
1718 | } | |
1719 | } | |
c5413fbe | 1720 | |
0bb9fef9 JW |
1721 | #ifdef CONFIG_KGDB |
1722 | /* | |
1723 | * Restore debug regs if using kgdbwait and you have a kernel debugger | |
1724 | * connection established. | |
1725 | */ | |
1726 | static void dbg_restore_debug_regs(void) | |
1727 | { | |
1728 | if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) | |
1729 | arch_kgdb_ops.correct_hw_break(); | |
1730 | } | |
1731 | #else /* ! CONFIG_KGDB */ | |
1732 | #define dbg_restore_debug_regs() | |
1733 | #endif /* ! CONFIG_KGDB */ | |
1734 | ||
ce4b1b16 IM |
1735 | static void wait_for_master_cpu(int cpu) |
1736 | { | |
1737 | #ifdef CONFIG_SMP | |
1738 | /* | |
1739 | * wait for ACK from master CPU before continuing | |
1740 | * with AP initialization | |
1741 | */ | |
1742 | WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); | |
1743 | while (!cpumask_test_cpu(cpu, cpu_callout_mask)) | |
1744 | cpu_relax(); | |
1745 | #endif | |
1746 | } | |
1747 | ||
b2e2ba57 | 1748 | #ifdef CONFIG_X86_64 |
505b7899 | 1749 | static inline void setup_getcpu(int cpu) |
b2e2ba57 | 1750 | { |
22245bdf | 1751 | unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu)); |
b2e2ba57 CB |
1752 | struct desc_struct d = { }; |
1753 | ||
67e87d43 | 1754 | if (boot_cpu_has(X86_FEATURE_RDTSCP)) |
b2e2ba57 CB |
1755 | write_rdtscp_aux(cpudata); |
1756 | ||
1757 | /* Store CPU and node number in limit. */ | |
1758 | d.limit0 = cpudata; | |
1759 | d.limit1 = cpudata >> 16; | |
1760 | ||
1761 | d.type = 5; /* RO data, expand down, accessed */ | |
1762 | d.dpl = 3; /* Visible to user code */ | |
1763 | d.s = 1; /* Not a system segment */ | |
1764 | d.p = 1; /* Present */ | |
1765 | d.d = 1; /* 32-bit */ | |
1766 | ||
22245bdf | 1767 | write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S); |
b2e2ba57 | 1768 | } |
505b7899 TG |
1769 | |
1770 | static inline void ucode_cpu_init(int cpu) | |
1771 | { | |
1772 | if (cpu) | |
1773 | load_ucode_ap(); | |
1774 | } | |
1775 | ||
1776 | static inline void tss_setup_ist(struct tss_struct *tss) | |
1777 | { | |
1778 | /* Set up the per-CPU TSS IST stacks */ | |
1779 | tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF); | |
1780 | tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI); | |
1781 | tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB); | |
1782 | tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE); | |
1783 | } | |
1784 | ||
1785 | static inline void gdt_setup_doublefault_tss(int cpu) { } | |
1786 | ||
1787 | #else /* CONFIG_X86_64 */ | |
1788 | ||
1789 | static inline void setup_getcpu(int cpu) { } | |
1790 | ||
1791 | static inline void ucode_cpu_init(int cpu) | |
1792 | { | |
1793 | show_ucode_info_early(); | |
1794 | } | |
1795 | ||
1796 | static inline void tss_setup_ist(struct tss_struct *tss) { } | |
1797 | ||
1798 | static inline void gdt_setup_doublefault_tss(int cpu) | |
1799 | { | |
1800 | #ifdef CONFIG_DOUBLEFAULT | |
1801 | /* Set up the doublefault TSS pointer in the GDT */ | |
1802 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
b2e2ba57 | 1803 | #endif |
505b7899 TG |
1804 | } |
1805 | #endif /* !CONFIG_X86_64 */ | |
b2e2ba57 | 1806 | |
d2cbcc49 RR |
1807 | /* |
1808 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1809 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1810 | * and IDT. We reload them nevertheless, this function acts as a | |
1811 | * 'CPU state barrier', nothing should get across. | |
1812 | */ | |
148f9bb8 | 1813 | void cpu_init(void) |
1ba76586 | 1814 | { |
505b7899 TG |
1815 | struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); |
1816 | struct task_struct *cur = current; | |
f6ef7322 | 1817 | int cpu = raw_smp_processor_id(); |
1ba76586 | 1818 | |
ce4b1b16 IM |
1819 | wait_for_master_cpu(cpu); |
1820 | ||
505b7899 | 1821 | ucode_cpu_init(cpu); |
0f3fa48a | 1822 | |
e7a22c1e | 1823 | #ifdef CONFIG_NUMA |
27fd185f | 1824 | if (this_cpu_read(numa_node) == 0 && |
e534c7c5 LS |
1825 | early_cpu_to_node(cpu) != NUMA_NO_NODE) |
1826 | set_numa_node(early_cpu_to_node(cpu)); | |
e7a22c1e | 1827 | #endif |
b2e2ba57 | 1828 | setup_getcpu(cpu); |
1ba76586 | 1829 | |
2eaad1fd | 1830 | pr_debug("Initializing CPU#%d\n", cpu); |
1ba76586 | 1831 | |
505b7899 TG |
1832 | if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) || |
1833 | boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE)) | |
1834 | cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
1ba76586 YL |
1835 | |
1836 | /* | |
1837 | * Initialize the per-CPU GDT with the boot GDT, | |
1838 | * and set up the GDT descriptor: | |
1839 | */ | |
552be871 | 1840 | switch_to_new_gdt(cpu); |
cf910e83 | 1841 | load_current_idt(); |
1ba76586 | 1842 | |
505b7899 TG |
1843 | if (IS_ENABLED(CONFIG_X86_64)) { |
1844 | loadsegment(fs, 0); | |
1845 | memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1846 | syscall_init(); | |
1ba76586 | 1847 | |
505b7899 TG |
1848 | wrmsrl(MSR_FS_BASE, 0); |
1849 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1850 | barrier(); | |
1ba76586 | 1851 | |
505b7899 | 1852 | x2apic_setup(); |
1ba76586 YL |
1853 | } |
1854 | ||
f1f10076 | 1855 | mmgrab(&init_mm); |
505b7899 TG |
1856 | cur->active_mm = &init_mm; |
1857 | BUG_ON(cur->mm); | |
72c0098d | 1858 | initialize_tlbstate_and_flush(); |
505b7899 | 1859 | enter_lazy_tlb(&init_mm, cur); |
1ba76586 | 1860 | |
505b7899 TG |
1861 | /* Initialize the TSS. */ |
1862 | tss_setup_ist(tss); | |
ecc7e37d | 1863 | tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID; |
f5848e5f | 1864 | tss->io_bitmap.prev_max = 0; |
060aa16f | 1865 | tss->io_bitmap.prev_sequence = 0; |
f5848e5f | 1866 | memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap)); |
c8137ace TG |
1867 | /* |
1868 | * Invalidate the extra array entry past the end of the all | |
1869 | * permission bitmap as required by the hardware. | |
1870 | */ | |
1871 | tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL; | |
72f5e08d | 1872 | set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); |
505b7899 | 1873 | |
1ba76586 | 1874 | load_TR_desc(); |
505b7899 TG |
1875 | /* |
1876 | * sp0 points to the entry trampoline stack regardless of what task | |
1877 | * is running. | |
1878 | */ | |
4fe2d8b1 | 1879 | load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); |
20bb8344 | 1880 | |
37868fe1 | 1881 | load_mm_ldt(&init_mm); |
1ba76586 | 1882 | |
0bb9fef9 JW |
1883 | clear_all_debug_regs(); |
1884 | dbg_restore_debug_regs(); | |
1ba76586 | 1885 | |
505b7899 TG |
1886 | gdt_setup_doublefault_tss(cpu); |
1887 | ||
21c4cd10 | 1888 | fpu__init_cpu(); |
1ba76586 | 1889 | |
1ba76586 YL |
1890 | if (is_uv_system()) |
1891 | uv_cpu_init(); | |
69218e47 | 1892 | |
69218e47 | 1893 | load_fixmap_gdt(cpu); |
1ba76586 YL |
1894 | } |
1895 | ||
1008c52c BP |
1896 | /* |
1897 | * The microcode loader calls this upon late microcode load to recheck features, | |
1898 | * only when microcode has been updated. Caller holds microcode_mutex and CPU | |
1899 | * hotplug lock. | |
1900 | */ | |
1901 | void microcode_check(void) | |
1902 | { | |
42ca8082 BP |
1903 | struct cpuinfo_x86 info; |
1904 | ||
1008c52c | 1905 | perf_check_microcode(); |
42ca8082 BP |
1906 | |
1907 | /* Reload CPUID max function as it might've changed. */ | |
1908 | info.cpuid_level = cpuid_eax(0); | |
1909 | ||
1910 | /* | |
1911 | * Copy all capability leafs to pick up the synthetic ones so that | |
1912 | * memcmp() below doesn't fail on that. The ones coming from CPUID will | |
1913 | * get overwritten in get_cpu_cap(). | |
1914 | */ | |
1915 | memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); | |
1916 | ||
1917 | get_cpu_cap(&info); | |
1918 | ||
1919 | if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) | |
1920 | return; | |
1921 | ||
1922 | pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); | |
1923 | pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); | |
1008c52c | 1924 | } |
9c92374b TG |
1925 | |
1926 | /* | |
1927 | * Invoked from core CPU hotplug code after hotplug operations | |
1928 | */ | |
1929 | void arch_smt_update(void) | |
1930 | { | |
1931 | /* Handle the speculative execution misfeatures */ | |
1932 | cpu_bugs_smt_update(); | |
6a1cb5f5 TG |
1933 | /* Check whether IPI broadcasting can be enabled */ |
1934 | apic_smt_update(); | |
9c92374b | 1935 | } |