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1da177e4 LT |
1 | #include <linux/init.h> |
2 | #include <linux/string.h> | |
3 | #include <linux/delay.h> | |
4 | #include <linux/smp.h> | |
5 | #include <linux/module.h> | |
6 | #include <linux/percpu.h> | |
2b932f6c | 7 | #include <linux/bootmem.h> |
1da177e4 LT |
8 | #include <asm/semaphore.h> |
9 | #include <asm/processor.h> | |
10 | #include <asm/i387.h> | |
11 | #include <asm/msr.h> | |
12 | #include <asm/io.h> | |
13 | #include <asm/mmu_context.h> | |
27b07da7 | 14 | #include <asm/mtrr.h> |
a03a3e28 | 15 | #include <asm/mce.h> |
1da177e4 LT |
16 | #ifdef CONFIG_X86_LOCAL_APIC |
17 | #include <asm/mpspec.h> | |
18 | #include <asm/apic.h> | |
19 | #include <mach_apic.h> | |
20 | #endif | |
21 | ||
22 | #include "cpu.h" | |
23 | ||
7a61d35d | 24 | DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = { |
6842ef0e GOC |
25 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, |
26 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, | |
27 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, | |
28 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, | |
bf504672 RR |
29 | /* |
30 | * Segments used for calling PnP BIOS have byte granularity. | |
31 | * They code segments and data segments have fixed 64k limits, | |
32 | * the transfer segment sizes are set at run time. | |
33 | */ | |
6842ef0e GOC |
34 | /* 32-bit code */ |
35 | [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, | |
36 | /* 16-bit code */ | |
37 | [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, | |
38 | /* 16-bit data */ | |
39 | [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, | |
40 | /* 16-bit data */ | |
41 | [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, | |
42 | /* 16-bit data */ | |
43 | [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, | |
bf504672 RR |
44 | /* |
45 | * The APM segments have byte granularity and their bases | |
46 | * are set at run time. All have 64k limits. | |
47 | */ | |
6842ef0e GOC |
48 | /* 32-bit code */ |
49 | [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, | |
bf504672 | 50 | /* 16-bit code */ |
6842ef0e GOC |
51 | [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, |
52 | /* data */ | |
53 | [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, | |
bf504672 | 54 | |
6842ef0e GOC |
55 | [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, |
56 | [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } }, | |
7a61d35d JF |
57 | } }; |
58 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); | |
ae1ee11b | 59 | |
7d851c8d AK |
60 | __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; |
61 | ||
3bc9b76b | 62 | static int cachesize_override __cpuinitdata = -1; |
3bc9b76b | 63 | static int disable_x86_serial_nr __cpuinitdata = 1; |
1da177e4 LT |
64 | |
65 | struct cpu_dev * cpu_devs[X86_VENDOR_NUM] = {}; | |
66 | ||
b4af3f7c | 67 | static void __cpuinit default_init(struct cpuinfo_x86 * c) |
1da177e4 LT |
68 | { |
69 | /* Not much we can do here... */ | |
70 | /* Check if at least it has cpuid */ | |
71 | if (c->cpuid_level == -1) { | |
72 | /* No cpuid. It must be an ancient CPU */ | |
73 | if (c->x86 == 4) | |
74 | strcpy(c->x86_model_id, "486"); | |
75 | else if (c->x86 == 3) | |
76 | strcpy(c->x86_model_id, "386"); | |
77 | } | |
78 | } | |
79 | ||
95414930 | 80 | static struct cpu_dev __cpuinitdata default_cpu = { |
1da177e4 | 81 | .c_init = default_init, |
fe38d855 | 82 | .c_vendor = "Unknown", |
1da177e4 | 83 | }; |
9dbeeec9 | 84 | static struct cpu_dev * this_cpu __cpuinitdata = &default_cpu; |
1da177e4 LT |
85 | |
86 | static int __init cachesize_setup(char *str) | |
87 | { | |
88 | get_option (&str, &cachesize_override); | |
89 | return 1; | |
90 | } | |
91 | __setup("cachesize=", cachesize_setup); | |
92 | ||
3bc9b76b | 93 | int __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
94 | { |
95 | unsigned int *v; | |
96 | char *p, *q; | |
97 | ||
98 | if (cpuid_eax(0x80000000) < 0x80000004) | |
99 | return 0; | |
100 | ||
101 | v = (unsigned int *) c->x86_model_id; | |
102 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
103 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
104 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
105 | c->x86_model_id[48] = 0; | |
106 | ||
107 | /* Intel chips right-justify this string for some dumb reason; | |
108 | undo that brain damage */ | |
109 | p = q = &c->x86_model_id[0]; | |
110 | while ( *p == ' ' ) | |
111 | p++; | |
112 | if ( p != q ) { | |
113 | while ( *p ) | |
114 | *q++ = *p++; | |
115 | while ( q <= &c->x86_model_id[48] ) | |
116 | *q++ = '\0'; /* Zero-pad the rest */ | |
117 | } | |
118 | ||
119 | return 1; | |
120 | } | |
121 | ||
122 | ||
3bc9b76b | 123 | void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) |
1da177e4 LT |
124 | { |
125 | unsigned int n, dummy, ecx, edx, l2size; | |
126 | ||
127 | n = cpuid_eax(0x80000000); | |
128 | ||
129 | if (n >= 0x80000005) { | |
130 | cpuid(0x80000005, &dummy, &dummy, &ecx, &edx); | |
131 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", | |
132 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); | |
133 | c->x86_cache_size=(ecx>>24)+(edx>>24); | |
134 | } | |
135 | ||
136 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
137 | return; | |
138 | ||
139 | ecx = cpuid_ecx(0x80000006); | |
140 | l2size = ecx >> 16; | |
141 | ||
142 | /* do processor-specific cache resizing */ | |
143 | if (this_cpu->c_size_cache) | |
144 | l2size = this_cpu->c_size_cache(c,l2size); | |
145 | ||
146 | /* Allow user to override all this if necessary. */ | |
147 | if (cachesize_override != -1) | |
148 | l2size = cachesize_override; | |
149 | ||
150 | if ( l2size == 0 ) | |
151 | return; /* Again, no L2 cache is possible */ | |
152 | ||
153 | c->x86_cache_size = l2size; | |
154 | ||
155 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
156 | l2size, ecx & 0xFF); | |
157 | } | |
158 | ||
159 | /* Naming convention should be: <Name> [(<Codename>)] */ | |
160 | /* This table only is used unless init_<vendor>() below doesn't set it; */ | |
161 | /* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */ | |
162 | ||
163 | /* Look up CPU names by table lookup. */ | |
3bc9b76b | 164 | static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c) |
1da177e4 LT |
165 | { |
166 | struct cpu_model_info *info; | |
167 | ||
168 | if ( c->x86_model >= 16 ) | |
169 | return NULL; /* Range check */ | |
170 | ||
171 | if (!this_cpu) | |
172 | return NULL; | |
173 | ||
174 | info = this_cpu->c_models; | |
175 | ||
176 | while (info && info->family) { | |
177 | if (info->family == c->x86) | |
178 | return info->model_names[c->x86_model]; | |
179 | info++; | |
180 | } | |
181 | return NULL; /* Not found */ | |
182 | } | |
183 | ||
184 | ||
3bc9b76b | 185 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c, int early) |
1da177e4 LT |
186 | { |
187 | char *v = c->x86_vendor_id; | |
188 | int i; | |
fe38d855 | 189 | static int printed; |
1da177e4 LT |
190 | |
191 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
192 | if (cpu_devs[i]) { | |
193 | if (!strcmp(v,cpu_devs[i]->c_ident[0]) || | |
194 | (cpu_devs[i]->c_ident[1] && | |
195 | !strcmp(v,cpu_devs[i]->c_ident[1]))) { | |
196 | c->x86_vendor = i; | |
197 | if (!early) | |
198 | this_cpu = cpu_devs[i]; | |
fe38d855 | 199 | return; |
1da177e4 LT |
200 | } |
201 | } | |
202 | } | |
fe38d855 CE |
203 | if (!printed) { |
204 | printed++; | |
205 | printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n"); | |
206 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); | |
207 | } | |
208 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
209 | this_cpu = &default_cpu; | |
1da177e4 LT |
210 | } |
211 | ||
212 | ||
213 | static int __init x86_fxsr_setup(char * s) | |
214 | { | |
13530257 AK |
215 | setup_clear_cpu_cap(X86_FEATURE_FXSR); |
216 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
1da177e4 LT |
217 | return 1; |
218 | } | |
219 | __setup("nofxsr", x86_fxsr_setup); | |
220 | ||
221 | ||
4f886511 CE |
222 | static int __init x86_sep_setup(char * s) |
223 | { | |
13530257 | 224 | setup_clear_cpu_cap(X86_FEATURE_SEP); |
4f886511 CE |
225 | return 1; |
226 | } | |
227 | __setup("nosep", x86_sep_setup); | |
228 | ||
229 | ||
1da177e4 LT |
230 | /* Standard macro to see if a specific flag is changeable */ |
231 | static inline int flag_is_changeable_p(u32 flag) | |
232 | { | |
233 | u32 f1, f2; | |
234 | ||
235 | asm("pushfl\n\t" | |
236 | "pushfl\n\t" | |
237 | "popl %0\n\t" | |
238 | "movl %0,%1\n\t" | |
239 | "xorl %2,%0\n\t" | |
240 | "pushl %0\n\t" | |
241 | "popfl\n\t" | |
242 | "pushfl\n\t" | |
243 | "popl %0\n\t" | |
244 | "popfl\n\t" | |
245 | : "=&r" (f1), "=&r" (f2) | |
246 | : "ir" (flag)); | |
247 | ||
248 | return ((f1^f2) & flag) != 0; | |
249 | } | |
250 | ||
251 | ||
252 | /* Probe for the CPUID instruction */ | |
3bc9b76b | 253 | static int __cpuinit have_cpuid_p(void) |
1da177e4 LT |
254 | { |
255 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
256 | } | |
257 | ||
d7cd5611 | 258 | void __init cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 259 | { |
1da177e4 | 260 | /* Get vendor name */ |
4a148513 HH |
261 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
262 | (unsigned int *)&c->x86_vendor_id[0], | |
263 | (unsigned int *)&c->x86_vendor_id[8], | |
264 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 265 | |
1da177e4 LT |
266 | c->x86 = 4; |
267 | if (c->cpuid_level >= 0x00000001) { | |
268 | u32 junk, tfms, cap0, misc; | |
269 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
270 | c->x86 = (tfms >> 8) & 15; | |
271 | c->x86_model = (tfms >> 4) & 15; | |
f5f786d0 | 272 | if (c->x86 == 0xf) |
1da177e4 | 273 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 274 | if (c->x86 >= 0x6) |
1da177e4 | 275 | c->x86_model += ((tfms >> 16) & 0xF) << 4; |
1da177e4 | 276 | c->x86_mask = tfms & 15; |
d4387bd3 | 277 | if (cap0 & (1<<19)) { |
1da177e4 | 278 | c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8; |
d4387bd3 HY |
279 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
280 | } | |
1da177e4 | 281 | } |
1da177e4 | 282 | } |
093af8d7 YL |
283 | static void __cpuinit early_get_cap(struct cpuinfo_x86 *c) |
284 | { | |
285 | u32 tfms, xlvl; | |
4a148513 | 286 | unsigned int ebx; |
093af8d7 YL |
287 | |
288 | memset(&c->x86_capability, 0, sizeof c->x86_capability); | |
289 | if (have_cpuid_p()) { | |
290 | /* Intel-defined flags: level 0x00000001 */ | |
291 | if (c->cpuid_level >= 0x00000001) { | |
292 | u32 capability, excap; | |
293 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); | |
294 | c->x86_capability[0] = capability; | |
295 | c->x86_capability[4] = excap; | |
296 | } | |
297 | ||
298 | /* AMD-defined flags: level 0x80000001 */ | |
299 | xlvl = cpuid_eax(0x80000000); | |
300 | if ((xlvl & 0xffff0000) == 0x80000000) { | |
301 | if (xlvl >= 0x80000001) { | |
302 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
303 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
304 | } | |
305 | } | |
306 | ||
307 | } | |
308 | ||
309 | } | |
1da177e4 | 310 | |
d7cd5611 RR |
311 | /* Do minimum CPU detection early. |
312 | Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment. | |
313 | The others are not touched to avoid unwanted side effects. | |
314 | ||
315 | WARNING: this function is only called on the BP. Don't add code here | |
316 | that is supposed to run on all CPUs. */ | |
317 | static void __init early_cpu_detect(void) | |
318 | { | |
319 | struct cpuinfo_x86 *c = &boot_cpu_data; | |
320 | ||
321 | c->x86_cache_alignment = 32; | |
d4387bd3 | 322 | c->x86_clflush_size = 32; |
d7cd5611 RR |
323 | |
324 | if (!have_cpuid_p()) | |
325 | return; | |
326 | ||
327 | cpu_detect(c); | |
328 | ||
329 | get_cpu_vendor(c, 1); | |
2b16a235 | 330 | |
03ae5768 TP |
331 | if (c->x86_vendor != X86_VENDOR_UNKNOWN && |
332 | cpu_devs[c->x86_vendor]->c_early_init) | |
333 | cpu_devs[c->x86_vendor]->c_early_init(c); | |
093af8d7 YL |
334 | |
335 | early_get_cap(c); | |
d7cd5611 RR |
336 | } |
337 | ||
68bbc172 | 338 | static void __cpuinit generic_identify(struct cpuinfo_x86 * c) |
1da177e4 LT |
339 | { |
340 | u32 tfms, xlvl; | |
4a148513 | 341 | unsigned int ebx; |
1da177e4 LT |
342 | |
343 | if (have_cpuid_p()) { | |
344 | /* Get vendor name */ | |
4a148513 HH |
345 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
346 | (unsigned int *)&c->x86_vendor_id[0], | |
347 | (unsigned int *)&c->x86_vendor_id[8], | |
348 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 LT |
349 | |
350 | get_cpu_vendor(c, 0); | |
351 | /* Initialize the standard set of capabilities */ | |
352 | /* Note that the vendor-specific code below might override */ | |
353 | ||
354 | /* Intel-defined flags: level 0x00000001 */ | |
355 | if ( c->cpuid_level >= 0x00000001 ) { | |
356 | u32 capability, excap; | |
1e9f28fa | 357 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); |
1da177e4 LT |
358 | c->x86_capability[0] = capability; |
359 | c->x86_capability[4] = excap; | |
360 | c->x86 = (tfms >> 8) & 15; | |
361 | c->x86_model = (tfms >> 4) & 15; | |
ed2da193 | 362 | if (c->x86 == 0xf) |
1da177e4 | 363 | c->x86 += (tfms >> 20) & 0xff; |
ed2da193 | 364 | if (c->x86 >= 0x6) |
1da177e4 | 365 | c->x86_model += ((tfms >> 16) & 0xF) << 4; |
1da177e4 | 366 | c->x86_mask = tfms & 15; |
96c52749 | 367 | #ifdef CONFIG_X86_HT |
1e9f28fa SS |
368 | c->apicid = phys_pkg_id((ebx >> 24) & 0xFF, 0); |
369 | #else | |
370 | c->apicid = (ebx >> 24) & 0xFF; | |
371 | #endif | |
770d132f AK |
372 | if (c->x86_capability[0] & (1<<19)) |
373 | c->x86_clflush_size = ((ebx >> 8) & 0xff) * 8; | |
1da177e4 LT |
374 | } else { |
375 | /* Have CPUID level 0 only - unheard of */ | |
376 | c->x86 = 4; | |
377 | } | |
378 | ||
379 | /* AMD-defined flags: level 0x80000001 */ | |
380 | xlvl = cpuid_eax(0x80000000); | |
381 | if ( (xlvl & 0xffff0000) == 0x80000000 ) { | |
382 | if ( xlvl >= 0x80000001 ) { | |
383 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
384 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
385 | } | |
386 | if ( xlvl >= 0x80000004 ) | |
387 | get_model_name(c); /* Default name */ | |
388 | } | |
1d67953f VP |
389 | |
390 | init_scattered_cpuid_features(c); | |
1da177e4 | 391 | } |
2e664aa2 | 392 | |
2e664aa2 | 393 | #ifdef CONFIG_X86_HT |
4b89aff9 | 394 | c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff; |
2e664aa2 | 395 | #endif |
1da177e4 LT |
396 | } |
397 | ||
3bc9b76b | 398 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
1da177e4 LT |
399 | { |
400 | if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr ) { | |
401 | /* Disable processor serial number */ | |
402 | unsigned long lo,hi; | |
403 | rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi); | |
404 | lo |= 0x200000; | |
405 | wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi); | |
406 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
407 | clear_bit(X86_FEATURE_PN, c->x86_capability); | |
408 | ||
409 | /* Disabling the serial number may affect the cpuid level */ | |
410 | c->cpuid_level = cpuid_eax(0); | |
411 | } | |
412 | } | |
413 | ||
414 | static int __init x86_serial_nr_setup(char *s) | |
415 | { | |
416 | disable_x86_serial_nr = 0; | |
417 | return 1; | |
418 | } | |
419 | __setup("serialnumber", x86_serial_nr_setup); | |
420 | ||
421 | ||
422 | ||
423 | /* | |
424 | * This does the hard work of actually picking apart the CPU stuff... | |
425 | */ | |
1a53905a | 426 | void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
427 | { |
428 | int i; | |
429 | ||
430 | c->loops_per_jiffy = loops_per_jiffy; | |
431 | c->x86_cache_size = -1; | |
432 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
433 | c->cpuid_level = -1; /* CPUID not detected */ | |
434 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ | |
435 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
436 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 437 | c->x86_max_cores = 1; |
770d132f | 438 | c->x86_clflush_size = 32; |
1da177e4 LT |
439 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
440 | ||
441 | if (!have_cpuid_p()) { | |
442 | /* First of all, decide if this is a 486 or higher */ | |
443 | /* It's a 486 if we can modify the AC flag */ | |
444 | if ( flag_is_changeable_p(X86_EFLAGS_AC) ) | |
445 | c->x86 = 4; | |
446 | else | |
447 | c->x86 = 3; | |
448 | } | |
449 | ||
450 | generic_identify(c); | |
451 | ||
3898534d | 452 | if (this_cpu->c_identify) |
1da177e4 LT |
453 | this_cpu->c_identify(c); |
454 | ||
1da177e4 LT |
455 | /* |
456 | * Vendor-specific initialization. In this section we | |
457 | * canonicalize the feature flags, meaning if there are | |
458 | * features a certain CPU supports which CPUID doesn't | |
459 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
460 | * we handle them here. | |
461 | * | |
462 | * At the end of this section, c->x86_capability better | |
463 | * indicate the features this CPU genuinely supports! | |
464 | */ | |
465 | if (this_cpu->c_init) | |
466 | this_cpu->c_init(c); | |
467 | ||
468 | /* Disable the PN if appropriate */ | |
469 | squash_the_stupid_serial_number(c); | |
470 | ||
471 | /* | |
472 | * The vendor-specific functions might have changed features. Now | |
473 | * we do "generic changes." | |
474 | */ | |
475 | ||
1da177e4 LT |
476 | /* If the model name is still unset, do table lookup. */ |
477 | if ( !c->x86_model_id[0] ) { | |
478 | char *p; | |
479 | p = table_lookup_model(c); | |
480 | if ( p ) | |
481 | strcpy(c->x86_model_id, p); | |
482 | else | |
483 | /* Last resort... */ | |
484 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 485 | c->x86, c->x86_model); |
1da177e4 LT |
486 | } |
487 | ||
1da177e4 LT |
488 | /* |
489 | * On SMP, boot_cpu_data holds the common feature set between | |
490 | * all CPUs; so make sure that we indicate which features are | |
491 | * common between the CPUs. The first time this routine gets | |
492 | * executed, c == &boot_cpu_data. | |
493 | */ | |
494 | if ( c != &boot_cpu_data ) { | |
495 | /* AND the already accumulated flags with these */ | |
496 | for ( i = 0 ; i < NCAPINTS ; i++ ) | |
497 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; | |
498 | } | |
499 | ||
7d851c8d AK |
500 | /* Clear all flags overriden by options */ |
501 | for (i = 0; i < NCAPINTS; i++) | |
12c247a6 | 502 | c->x86_capability[i] &= ~cleared_cpu_caps[i]; |
7d851c8d | 503 | |
1da177e4 | 504 | /* Init Machine Check Exception if available. */ |
1da177e4 | 505 | mcheck_init(c); |
30d432df AK |
506 | |
507 | select_idle_routine(c); | |
a6c4e076 | 508 | } |
31ab269a | 509 | |
a6c4e076 JF |
510 | void __init identify_boot_cpu(void) |
511 | { | |
512 | identify_cpu(&boot_cpu_data); | |
513 | sysenter_setup(); | |
6fe940d6 | 514 | enable_sep_cpu(); |
a6c4e076 | 515 | } |
3b520b23 | 516 | |
a6c4e076 JF |
517 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) |
518 | { | |
519 | BUG_ON(c == &boot_cpu_data); | |
520 | identify_cpu(c); | |
521 | enable_sep_cpu(); | |
522 | mtrr_ap_init(); | |
1da177e4 LT |
523 | } |
524 | ||
525 | #ifdef CONFIG_X86_HT | |
3bc9b76b | 526 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 LT |
527 | { |
528 | u32 eax, ebx, ecx, edx; | |
94605eff | 529 | int index_msb, core_bits; |
1da177e4 | 530 | |
94605eff SS |
531 | cpuid(1, &eax, &ebx, &ecx, &edx); |
532 | ||
63518644 | 533 | if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
1da177e4 LT |
534 | return; |
535 | ||
1da177e4 LT |
536 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
537 | ||
538 | if (smp_num_siblings == 1) { | |
539 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
540 | } else if (smp_num_siblings > 1 ) { | |
1da177e4 LT |
541 | |
542 | if (smp_num_siblings > NR_CPUS) { | |
4b89aff9 RS |
543 | printk(KERN_WARNING "CPU: Unsupported number of the " |
544 | "siblings %d", smp_num_siblings); | |
1da177e4 LT |
545 | smp_num_siblings = 1; |
546 | return; | |
547 | } | |
94605eff SS |
548 | |
549 | index_msb = get_count_order(smp_num_siblings); | |
4b89aff9 | 550 | c->phys_proc_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb); |
1da177e4 LT |
551 | |
552 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
4b89aff9 | 553 | c->phys_proc_id); |
3dd9d514 | 554 | |
94605eff | 555 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
3dd9d514 | 556 | |
94605eff | 557 | index_msb = get_count_order(smp_num_siblings) ; |
3dd9d514 | 558 | |
94605eff | 559 | core_bits = get_count_order(c->x86_max_cores); |
3dd9d514 | 560 | |
4b89aff9 | 561 | c->cpu_core_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb) & |
94605eff | 562 | ((1 << core_bits) - 1); |
3dd9d514 | 563 | |
94605eff | 564 | if (c->x86_max_cores > 1) |
3dd9d514 | 565 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", |
4b89aff9 | 566 | c->cpu_core_id); |
1da177e4 LT |
567 | } |
568 | } | |
569 | #endif | |
570 | ||
191679fd AK |
571 | static __init int setup_noclflush(char *arg) |
572 | { | |
573 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
574 | return 1; | |
575 | } | |
576 | __setup("noclflush", setup_noclflush); | |
577 | ||
3bc9b76b | 578 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 LT |
579 | { |
580 | char *vendor = NULL; | |
581 | ||
582 | if (c->x86_vendor < X86_VENDOR_NUM) | |
583 | vendor = this_cpu->c_vendor; | |
584 | else if (c->cpuid_level >= 0) | |
585 | vendor = c->x86_vendor_id; | |
586 | ||
587 | if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor))) | |
588 | printk("%s ", vendor); | |
589 | ||
590 | if (!c->x86_model_id[0]) | |
591 | printk("%d86", c->x86); | |
592 | else | |
593 | printk("%s", c->x86_model_id); | |
594 | ||
595 | if (c->x86_mask || c->cpuid_level >= 0) | |
596 | printk(" stepping %02x\n", c->x86_mask); | |
597 | else | |
598 | printk("\n"); | |
599 | } | |
600 | ||
ac72e788 AK |
601 | static __init int setup_disablecpuid(char *arg) |
602 | { | |
603 | int bit; | |
604 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) | |
605 | setup_clear_cpu_cap(bit); | |
606 | else | |
607 | return 0; | |
608 | return 1; | |
609 | } | |
610 | __setup("clearcpuid=", setup_disablecpuid); | |
611 | ||
3bc9b76b | 612 | cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE; |
1da177e4 | 613 | |
1da177e4 LT |
614 | void __init early_cpu_init(void) |
615 | { | |
03ae5768 TP |
616 | struct cpu_vendor_dev *cvdev; |
617 | ||
618 | for (cvdev = __x86cpuvendor_start ; | |
619 | cvdev < __x86cpuvendor_end ; | |
620 | cvdev++) | |
621 | cpu_devs[cvdev->vendor] = cvdev->cpu_dev; | |
622 | ||
1da177e4 | 623 | early_cpu_detect(); |
1da177e4 | 624 | } |
62111195 | 625 | |
7c3576d2 | 626 | /* Make sure %fs is initialized properly in idle threads */ |
6b2fb3c6 | 627 | struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) |
f95d47ca JF |
628 | { |
629 | memset(regs, 0, sizeof(struct pt_regs)); | |
65ea5b03 | 630 | regs->fs = __KERNEL_PERCPU; |
f95d47ca JF |
631 | return regs; |
632 | } | |
633 | ||
c5413fbe JF |
634 | /* Current gdt points %fs at the "master" per-cpu area: after this, |
635 | * it's on the real one. */ | |
636 | void switch_to_new_gdt(void) | |
637 | { | |
6b68f01b | 638 | struct desc_ptr gdt_descr; |
c5413fbe JF |
639 | |
640 | gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id()); | |
641 | gdt_descr.size = GDT_SIZE - 1; | |
642 | load_gdt(&gdt_descr); | |
643 | asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory"); | |
644 | } | |
645 | ||
d2cbcc49 RR |
646 | /* |
647 | * cpu_init() initializes state that is per-CPU. Some data is already | |
648 | * initialized (naturally) in the bootstrap process, such as the GDT | |
649 | * and IDT. We reload them nevertheless, this function acts as a | |
650 | * 'CPU state barrier', nothing should get across. | |
651 | */ | |
652 | void __cpuinit cpu_init(void) | |
9ee79a3d | 653 | { |
d2cbcc49 RR |
654 | int cpu = smp_processor_id(); |
655 | struct task_struct *curr = current; | |
9ee79a3d JB |
656 | struct tss_struct * t = &per_cpu(init_tss, cpu); |
657 | struct thread_struct *thread = &curr->thread; | |
62111195 JF |
658 | |
659 | if (cpu_test_and_set(cpu, cpu_initialized)) { | |
660 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); | |
661 | for (;;) local_irq_enable(); | |
662 | } | |
663 | ||
664 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
665 | ||
666 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
667 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 668 | |
4d37e7e3 | 669 | load_idt(&idt_descr); |
c5413fbe | 670 | switch_to_new_gdt(); |
1da177e4 | 671 | |
1da177e4 LT |
672 | /* |
673 | * Set up and load the per-CPU TSS and LDT | |
674 | */ | |
675 | atomic_inc(&init_mm.mm_count); | |
62111195 JF |
676 | curr->active_mm = &init_mm; |
677 | if (curr->mm) | |
678 | BUG(); | |
679 | enter_lazy_tlb(&init_mm, curr); | |
1da177e4 | 680 | |
faca6227 | 681 | load_sp0(t, thread); |
1da177e4 LT |
682 | set_tss_desc(cpu,t); |
683 | load_TR_desc(); | |
684 | load_LDT(&init_mm.context); | |
685 | ||
22c4e308 | 686 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
687 | /* Set up doublefault TSS pointer in the GDT */ |
688 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 689 | #endif |
1da177e4 | 690 | |
464d1a78 JF |
691 | /* Clear %gs. */ |
692 | asm volatile ("mov %0, %%gs" : : "r" (0)); | |
1da177e4 LT |
693 | |
694 | /* Clear all 6 debug registers: */ | |
4bb0d3ec ZA |
695 | set_debugreg(0, 0); |
696 | set_debugreg(0, 1); | |
697 | set_debugreg(0, 2); | |
698 | set_debugreg(0, 3); | |
699 | set_debugreg(0, 6); | |
700 | set_debugreg(0, 7); | |
1da177e4 LT |
701 | |
702 | /* | |
703 | * Force FPU initialization: | |
704 | */ | |
705 | current_thread_info()->status = 0; | |
706 | clear_used_math(); | |
707 | mxcsr_feature_mask_init(); | |
708 | } | |
e1367daf LS |
709 | |
710 | #ifdef CONFIG_HOTPLUG_CPU | |
3bc9b76b | 711 | void __cpuinit cpu_uninit(void) |
e1367daf LS |
712 | { |
713 | int cpu = raw_smp_processor_id(); | |
714 | cpu_clear(cpu, cpu_initialized); | |
715 | ||
716 | /* lazy TLB state */ | |
717 | per_cpu(cpu_tlbstate, cpu).state = 0; | |
718 | per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm; | |
719 | } | |
720 | #endif |