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Commit | Line | Data |
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f0fc4aff | 1 | #include <linux/bootmem.h> |
9766cdbc | 2 | #include <linux/linkage.h> |
f0fc4aff | 3 | #include <linux/bitops.h> |
9766cdbc | 4 | #include <linux/kernel.h> |
186f4360 | 5 | #include <linux/export.h> |
9766cdbc JSR |
6 | #include <linux/percpu.h> |
7 | #include <linux/string.h> | |
ee098e1a | 8 | #include <linux/ctype.h> |
1da177e4 | 9 | #include <linux/delay.h> |
9766cdbc | 10 | #include <linux/sched.h> |
e6017571 | 11 | #include <linux/sched/clock.h> |
9164bb4a | 12 | #include <linux/sched/task.h> |
9766cdbc | 13 | #include <linux/init.h> |
0f46efeb | 14 | #include <linux/kprobes.h> |
9766cdbc | 15 | #include <linux/kgdb.h> |
1da177e4 | 16 | #include <linux/smp.h> |
9766cdbc | 17 | #include <linux/io.h> |
b51ef52d | 18 | #include <linux/syscore_ops.h> |
9766cdbc JSR |
19 | |
20 | #include <asm/stackprotector.h> | |
cdd6c482 | 21 | #include <asm/perf_event.h> |
1da177e4 | 22 | #include <asm/mmu_context.h> |
49d859d7 | 23 | #include <asm/archrandom.h> |
9766cdbc JSR |
24 | #include <asm/hypervisor.h> |
25 | #include <asm/processor.h> | |
1e02ce4c | 26 | #include <asm/tlbflush.h> |
f649e938 | 27 | #include <asm/debugreg.h> |
9766cdbc | 28 | #include <asm/sections.h> |
f40c3300 | 29 | #include <asm/vsyscall.h> |
8bdbd962 AC |
30 | #include <linux/topology.h> |
31 | #include <linux/cpumask.h> | |
9766cdbc | 32 | #include <asm/pgtable.h> |
60063497 | 33 | #include <linux/atomic.h> |
9766cdbc JSR |
34 | #include <asm/proto.h> |
35 | #include <asm/setup.h> | |
36 | #include <asm/apic.h> | |
37 | #include <asm/desc.h> | |
78f7f1e5 | 38 | #include <asm/fpu/internal.h> |
27b07da7 | 39 | #include <asm/mtrr.h> |
0274f955 | 40 | #include <asm/hwcap2.h> |
8bdbd962 | 41 | #include <linux/numa.h> |
9766cdbc | 42 | #include <asm/asm.h> |
0f6ff2bc | 43 | #include <asm/bugs.h> |
9766cdbc | 44 | #include <asm/cpu.h> |
a03a3e28 | 45 | #include <asm/mce.h> |
9766cdbc | 46 | #include <asm/msr.h> |
8d4a4300 | 47 | #include <asm/pat.h> |
d288e1cf FY |
48 | #include <asm/microcode.h> |
49 | #include <asm/microcode_intel.h> | |
e641f5f5 IM |
50 | |
51 | #ifdef CONFIG_X86_LOCAL_APIC | |
bdbcdd48 | 52 | #include <asm/uv/uv.h> |
1da177e4 LT |
53 | #endif |
54 | ||
55 | #include "cpu.h" | |
56 | ||
0274f955 GA |
57 | u32 elf_hwcap2 __read_mostly; |
58 | ||
c2d1cec1 | 59 | /* all of these masks are initialized in setup_cpu_local_masks() */ |
c2d1cec1 | 60 | cpumask_var_t cpu_initialized_mask; |
9766cdbc JSR |
61 | cpumask_var_t cpu_callout_mask; |
62 | cpumask_var_t cpu_callin_mask; | |
c2d1cec1 MT |
63 | |
64 | /* representing cpus for which sibling maps can be computed */ | |
65 | cpumask_var_t cpu_sibling_setup_mask; | |
66 | ||
2f2f52ba | 67 | /* correctly size the local cpu masks */ |
4369f1fb | 68 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
69 | { |
70 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
71 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
72 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
73 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
74 | } | |
75 | ||
148f9bb8 | 76 | static void default_init(struct cpuinfo_x86 *c) |
e8055139 OZ |
77 | { |
78 | #ifdef CONFIG_X86_64 | |
27c13ece | 79 | cpu_detect_cache_sizes(c); |
e8055139 OZ |
80 | #else |
81 | /* Not much we can do here... */ | |
82 | /* Check if at least it has cpuid */ | |
83 | if (c->cpuid_level == -1) { | |
84 | /* No cpuid. It must be an ancient CPU */ | |
85 | if (c->x86 == 4) | |
86 | strcpy(c->x86_model_id, "486"); | |
87 | else if (c->x86 == 3) | |
88 | strcpy(c->x86_model_id, "386"); | |
89 | } | |
90 | #endif | |
acb04058 | 91 | clear_sched_clock_stable(); |
e8055139 OZ |
92 | } |
93 | ||
148f9bb8 | 94 | static const struct cpu_dev default_cpu = { |
e8055139 OZ |
95 | .c_init = default_init, |
96 | .c_vendor = "Unknown", | |
97 | .c_x86_vendor = X86_VENDOR_UNKNOWN, | |
98 | }; | |
99 | ||
148f9bb8 | 100 | static const struct cpu_dev *this_cpu = &default_cpu; |
0a488a53 | 101 | |
06deef89 | 102 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 103 | #ifdef CONFIG_X86_64 |
06deef89 BG |
104 | /* |
105 | * We need valid kernel segments for data and code in long mode too | |
106 | * IRET will check the segment types kkeil 2000/10/28 | |
107 | * Also sysret mandates a special GDT layout | |
108 | * | |
9766cdbc | 109 | * TLS descriptors are currently at a different place compared to i386. |
06deef89 BG |
110 | * Hopefully nobody expects them at a fixed place (Wine?) |
111 | */ | |
1e5de182 AM |
112 | [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), |
113 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), | |
114 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), | |
115 | [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), | |
116 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), | |
117 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), | |
950ad7ff | 118 | #else |
1e5de182 AM |
119 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), |
120 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
121 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), | |
122 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), | |
bf504672 RR |
123 | /* |
124 | * Segments used for calling PnP BIOS have byte granularity. | |
125 | * They code segments and data segments have fixed 64k limits, | |
126 | * the transfer segment sizes are set at run time. | |
127 | */ | |
6842ef0e | 128 | /* 32-bit code */ |
1e5de182 | 129 | [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
6842ef0e | 130 | /* 16-bit code */ |
1e5de182 | 131 | [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 132 | /* 16-bit data */ |
1e5de182 | 133 | [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), |
6842ef0e | 134 | /* 16-bit data */ |
1e5de182 | 135 | [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), |
6842ef0e | 136 | /* 16-bit data */ |
1e5de182 | 137 | [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), |
bf504672 RR |
138 | /* |
139 | * The APM segments have byte granularity and their bases | |
140 | * are set at run time. All have 64k limits. | |
141 | */ | |
6842ef0e | 142 | /* 32-bit code */ |
1e5de182 | 143 | [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
bf504672 | 144 | /* 16-bit code */ |
1e5de182 | 145 | [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 146 | /* data */ |
72c4d853 | 147 | [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), |
bf504672 | 148 | |
1e5de182 AM |
149 | [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), |
150 | [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
60a5317f | 151 | GDT_STACK_CANARY_INIT |
950ad7ff | 152 | #endif |
06deef89 | 153 | } }; |
7a61d35d | 154 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 155 | |
8c3641e9 | 156 | static int __init x86_mpx_setup(char *s) |
0c752a93 | 157 | { |
8c3641e9 | 158 | /* require an exact match without trailing characters */ |
2cd3949f DH |
159 | if (strlen(s)) |
160 | return 0; | |
0c752a93 | 161 | |
8c3641e9 DH |
162 | /* do not emit a message if the feature is not present */ |
163 | if (!boot_cpu_has(X86_FEATURE_MPX)) | |
164 | return 1; | |
6bad06b7 | 165 | |
8c3641e9 DH |
166 | setup_clear_cpu_cap(X86_FEATURE_MPX); |
167 | pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); | |
b6f42a4a FY |
168 | return 1; |
169 | } | |
8c3641e9 | 170 | __setup("nompx", x86_mpx_setup); |
b6f42a4a | 171 | |
d12a72b8 AL |
172 | static int __init x86_noinvpcid_setup(char *s) |
173 | { | |
174 | /* noinvpcid doesn't accept parameters */ | |
175 | if (s) | |
176 | return -EINVAL; | |
177 | ||
178 | /* do not emit a message if the feature is not present */ | |
179 | if (!boot_cpu_has(X86_FEATURE_INVPCID)) | |
180 | return 0; | |
181 | ||
182 | setup_clear_cpu_cap(X86_FEATURE_INVPCID); | |
183 | pr_info("noinvpcid: INVPCID feature disabled\n"); | |
184 | return 0; | |
185 | } | |
186 | early_param("noinvpcid", x86_noinvpcid_setup); | |
187 | ||
ba51dced | 188 | #ifdef CONFIG_X86_32 |
148f9bb8 PG |
189 | static int cachesize_override = -1; |
190 | static int disable_x86_serial_nr = 1; | |
1da177e4 | 191 | |
0a488a53 YL |
192 | static int __init cachesize_setup(char *str) |
193 | { | |
194 | get_option(&str, &cachesize_override); | |
195 | return 1; | |
196 | } | |
197 | __setup("cachesize=", cachesize_setup); | |
198 | ||
0a488a53 YL |
199 | static int __init x86_sep_setup(char *s) |
200 | { | |
201 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
202 | return 1; | |
203 | } | |
204 | __setup("nosep", x86_sep_setup); | |
205 | ||
206 | /* Standard macro to see if a specific flag is changeable */ | |
207 | static inline int flag_is_changeable_p(u32 flag) | |
208 | { | |
209 | u32 f1, f2; | |
210 | ||
94f6bac1 KH |
211 | /* |
212 | * Cyrix and IDT cpus allow disabling of CPUID | |
213 | * so the code below may return different results | |
214 | * when it is executed before and after enabling | |
215 | * the CPUID. Add "volatile" to not allow gcc to | |
216 | * optimize the subsequent calls to this function. | |
217 | */ | |
0f3fa48a IM |
218 | asm volatile ("pushfl \n\t" |
219 | "pushfl \n\t" | |
220 | "popl %0 \n\t" | |
221 | "movl %0, %1 \n\t" | |
222 | "xorl %2, %0 \n\t" | |
223 | "pushl %0 \n\t" | |
224 | "popfl \n\t" | |
225 | "pushfl \n\t" | |
226 | "popl %0 \n\t" | |
227 | "popfl \n\t" | |
228 | ||
94f6bac1 KH |
229 | : "=&r" (f1), "=&r" (f2) |
230 | : "ir" (flag)); | |
0a488a53 YL |
231 | |
232 | return ((f1^f2) & flag) != 0; | |
233 | } | |
234 | ||
235 | /* Probe for the CPUID instruction */ | |
148f9bb8 | 236 | int have_cpuid_p(void) |
0a488a53 YL |
237 | { |
238 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
239 | } | |
240 | ||
148f9bb8 | 241 | static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
0a488a53 | 242 | { |
0f3fa48a IM |
243 | unsigned long lo, hi; |
244 | ||
245 | if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) | |
246 | return; | |
247 | ||
248 | /* Disable processor serial number: */ | |
249 | ||
250 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
251 | lo |= 0x200000; | |
252 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
253 | ||
1b74dde7 | 254 | pr_notice("CPU serial number disabled.\n"); |
0f3fa48a IM |
255 | clear_cpu_cap(c, X86_FEATURE_PN); |
256 | ||
257 | /* Disabling the serial number may affect the cpuid level */ | |
258 | c->cpuid_level = cpuid_eax(0); | |
0a488a53 YL |
259 | } |
260 | ||
261 | static int __init x86_serial_nr_setup(char *s) | |
262 | { | |
263 | disable_x86_serial_nr = 0; | |
264 | return 1; | |
265 | } | |
266 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 267 | #else |
102bbe3a YL |
268 | static inline int flag_is_changeable_p(u32 flag) |
269 | { | |
270 | return 1; | |
271 | } | |
102bbe3a YL |
272 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
273 | { | |
274 | } | |
ba51dced | 275 | #endif |
0a488a53 | 276 | |
de5397ad FY |
277 | static __init int setup_disable_smep(char *arg) |
278 | { | |
b2cc2a07 | 279 | setup_clear_cpu_cap(X86_FEATURE_SMEP); |
0f6ff2bc DH |
280 | /* Check for things that depend on SMEP being enabled: */ |
281 | check_mpx_erratum(&boot_cpu_data); | |
de5397ad FY |
282 | return 1; |
283 | } | |
284 | __setup("nosmep", setup_disable_smep); | |
285 | ||
b2cc2a07 | 286 | static __always_inline void setup_smep(struct cpuinfo_x86 *c) |
de5397ad | 287 | { |
b2cc2a07 | 288 | if (cpu_has(c, X86_FEATURE_SMEP)) |
375074cc | 289 | cr4_set_bits(X86_CR4_SMEP); |
de5397ad FY |
290 | } |
291 | ||
52b6179a PA |
292 | static __init int setup_disable_smap(char *arg) |
293 | { | |
b2cc2a07 | 294 | setup_clear_cpu_cap(X86_FEATURE_SMAP); |
52b6179a PA |
295 | return 1; |
296 | } | |
297 | __setup("nosmap", setup_disable_smap); | |
298 | ||
b2cc2a07 PA |
299 | static __always_inline void setup_smap(struct cpuinfo_x86 *c) |
300 | { | |
581b7f15 | 301 | unsigned long eflags = native_save_fl(); |
b2cc2a07 PA |
302 | |
303 | /* This should have been cleared long ago */ | |
b2cc2a07 PA |
304 | BUG_ON(eflags & X86_EFLAGS_AC); |
305 | ||
03bbd596 PA |
306 | if (cpu_has(c, X86_FEATURE_SMAP)) { |
307 | #ifdef CONFIG_X86_SMAP | |
375074cc | 308 | cr4_set_bits(X86_CR4_SMAP); |
03bbd596 | 309 | #else |
375074cc | 310 | cr4_clear_bits(X86_CR4_SMAP); |
03bbd596 PA |
311 | #endif |
312 | } | |
de5397ad FY |
313 | } |
314 | ||
06976945 DH |
315 | /* |
316 | * Protection Keys are not available in 32-bit mode. | |
317 | */ | |
318 | static bool pku_disabled; | |
319 | ||
320 | static __always_inline void setup_pku(struct cpuinfo_x86 *c) | |
321 | { | |
e8df1a95 DH |
322 | /* check the boot processor, plus compile options for PKU: */ |
323 | if (!cpu_feature_enabled(X86_FEATURE_PKU)) | |
324 | return; | |
325 | /* checks the actual processor's cpuid bits: */ | |
06976945 DH |
326 | if (!cpu_has(c, X86_FEATURE_PKU)) |
327 | return; | |
328 | if (pku_disabled) | |
329 | return; | |
330 | ||
331 | cr4_set_bits(X86_CR4_PKE); | |
332 | /* | |
333 | * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE | |
334 | * cpuid bit to be set. We need to ensure that we | |
335 | * update that bit in this CPU's "cpu_info". | |
336 | */ | |
337 | get_cpu_cap(c); | |
338 | } | |
339 | ||
340 | #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS | |
341 | static __init int setup_disable_pku(char *arg) | |
342 | { | |
343 | /* | |
344 | * Do not clear the X86_FEATURE_PKU bit. All of the | |
345 | * runtime checks are against OSPKE so clearing the | |
346 | * bit does nothing. | |
347 | * | |
348 | * This way, we will see "pku" in cpuinfo, but not | |
349 | * "ospke", which is exactly what we want. It shows | |
350 | * that the CPU has PKU, but the OS has not enabled it. | |
351 | * This happens to be exactly how a system would look | |
352 | * if we disabled the config option. | |
353 | */ | |
354 | pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); | |
355 | pku_disabled = true; | |
356 | return 1; | |
357 | } | |
358 | __setup("nopku", setup_disable_pku); | |
359 | #endif /* CONFIG_X86_64 */ | |
360 | ||
b38b0665 PA |
361 | /* |
362 | * Some CPU features depend on higher CPUID levels, which may not always | |
363 | * be available due to CPUID level capping or broken virtualization | |
364 | * software. Add those features to this table to auto-disable them. | |
365 | */ | |
366 | struct cpuid_dependent_feature { | |
367 | u32 feature; | |
368 | u32 level; | |
369 | }; | |
0f3fa48a | 370 | |
148f9bb8 | 371 | static const struct cpuid_dependent_feature |
b38b0665 PA |
372 | cpuid_dependent_features[] = { |
373 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
374 | { X86_FEATURE_DCA, 0x00000009 }, | |
375 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
376 | { 0, 0 } | |
377 | }; | |
378 | ||
148f9bb8 | 379 | static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) |
b38b0665 PA |
380 | { |
381 | const struct cpuid_dependent_feature *df; | |
9766cdbc | 382 | |
b38b0665 | 383 | for (df = cpuid_dependent_features; df->feature; df++) { |
0f3fa48a IM |
384 | |
385 | if (!cpu_has(c, df->feature)) | |
386 | continue; | |
b38b0665 PA |
387 | /* |
388 | * Note: cpuid_level is set to -1 if unavailable, but | |
389 | * extended_extended_level is set to 0 if unavailable | |
390 | * and the legitimate extended levels are all negative | |
391 | * when signed; hence the weird messing around with | |
392 | * signs here... | |
393 | */ | |
0f3fa48a | 394 | if (!((s32)df->level < 0 ? |
f6db44df | 395 | (u32)df->level > (u32)c->extended_cpuid_level : |
0f3fa48a IM |
396 | (s32)df->level > (s32)c->cpuid_level)) |
397 | continue; | |
398 | ||
399 | clear_cpu_cap(c, df->feature); | |
400 | if (!warn) | |
401 | continue; | |
402 | ||
1b74dde7 CY |
403 | pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", |
404 | x86_cap_flag(df->feature), df->level); | |
b38b0665 | 405 | } |
f6db44df | 406 | } |
b38b0665 | 407 | |
102bbe3a YL |
408 | /* |
409 | * Naming convention should be: <Name> [(<Codename>)] | |
410 | * This table only is used unless init_<vendor>() below doesn't set it; | |
0f3fa48a IM |
411 | * in particular, if CPUID levels 0x80000002..4 are supported, this |
412 | * isn't used | |
102bbe3a YL |
413 | */ |
414 | ||
415 | /* Look up CPU names by table lookup. */ | |
148f9bb8 | 416 | static const char *table_lookup_model(struct cpuinfo_x86 *c) |
102bbe3a | 417 | { |
09dc68d9 JB |
418 | #ifdef CONFIG_X86_32 |
419 | const struct legacy_cpu_model_info *info; | |
102bbe3a YL |
420 | |
421 | if (c->x86_model >= 16) | |
422 | return NULL; /* Range check */ | |
423 | ||
424 | if (!this_cpu) | |
425 | return NULL; | |
426 | ||
09dc68d9 | 427 | info = this_cpu->legacy_models; |
102bbe3a | 428 | |
09dc68d9 | 429 | while (info->family) { |
102bbe3a YL |
430 | if (info->family == c->x86) |
431 | return info->model_names[c->x86_model]; | |
432 | info++; | |
433 | } | |
09dc68d9 | 434 | #endif |
102bbe3a YL |
435 | return NULL; /* Not found */ |
436 | } | |
437 | ||
148f9bb8 PG |
438 | __u32 cpu_caps_cleared[NCAPINTS]; |
439 | __u32 cpu_caps_set[NCAPINTS]; | |
7d851c8d | 440 | |
11e3a840 JF |
441 | void load_percpu_segment(int cpu) |
442 | { | |
443 | #ifdef CONFIG_X86_32 | |
444 | loadsegment(fs, __KERNEL_PERCPU); | |
445 | #else | |
45e876f7 | 446 | __loadsegment_simple(gs, 0); |
11e3a840 JF |
447 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); |
448 | #endif | |
60a5317f | 449 | load_stack_canary_segment(); |
11e3a840 JF |
450 | } |
451 | ||
0f3fa48a IM |
452 | /* |
453 | * Current gdt points %fs at the "master" per-cpu area: after this, | |
454 | * it's on the real one. | |
455 | */ | |
552be871 | 456 | void switch_to_new_gdt(int cpu) |
9d31d35b YL |
457 | { |
458 | struct desc_ptr gdt_descr; | |
459 | ||
2697fbd5 | 460 | gdt_descr.address = (long)get_cpu_gdt_table(cpu); |
9d31d35b YL |
461 | gdt_descr.size = GDT_SIZE - 1; |
462 | load_gdt(&gdt_descr); | |
2697fbd5 | 463 | /* Reload the per-cpu base */ |
11e3a840 JF |
464 | |
465 | load_percpu_segment(cpu); | |
9d31d35b YL |
466 | } |
467 | ||
148f9bb8 | 468 | static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 469 | |
148f9bb8 | 470 | static void get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
471 | { |
472 | unsigned int *v; | |
ee098e1a | 473 | char *p, *q, *s; |
1da177e4 | 474 | |
3da99c97 | 475 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 476 | return; |
1da177e4 | 477 | |
0f3fa48a | 478 | v = (unsigned int *)c->x86_model_id; |
1da177e4 LT |
479 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); |
480 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
481 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
482 | c->x86_model_id[48] = 0; | |
483 | ||
ee098e1a BP |
484 | /* Trim whitespace */ |
485 | p = q = s = &c->x86_model_id[0]; | |
486 | ||
487 | while (*p == ' ') | |
488 | p++; | |
489 | ||
490 | while (*p) { | |
491 | /* Note the last non-whitespace index */ | |
492 | if (!isspace(*p)) | |
493 | s = q; | |
494 | ||
495 | *q++ = *p++; | |
496 | } | |
497 | ||
498 | *(s + 1) = '\0'; | |
1da177e4 LT |
499 | } |
500 | ||
148f9bb8 | 501 | void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) |
1da177e4 | 502 | { |
9d31d35b | 503 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 504 | |
3da99c97 | 505 | n = c->extended_cpuid_level; |
1da177e4 LT |
506 | |
507 | if (n >= 0x80000005) { | |
9d31d35b | 508 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
9d31d35b | 509 | c->x86_cache_size = (ecx>>24) + (edx>>24); |
140fc727 YL |
510 | #ifdef CONFIG_X86_64 |
511 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
512 | c->x86_tlbsize = 0; | |
513 | #endif | |
1da177e4 LT |
514 | } |
515 | ||
516 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
517 | return; | |
518 | ||
0a488a53 | 519 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 520 | l2size = ecx >> 16; |
34048c9e | 521 | |
140fc727 YL |
522 | #ifdef CONFIG_X86_64 |
523 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
524 | #else | |
1da177e4 | 525 | /* do processor-specific cache resizing */ |
09dc68d9 JB |
526 | if (this_cpu->legacy_cache_size) |
527 | l2size = this_cpu->legacy_cache_size(c, l2size); | |
1da177e4 LT |
528 | |
529 | /* Allow user to override all this if necessary. */ | |
530 | if (cachesize_override != -1) | |
531 | l2size = cachesize_override; | |
532 | ||
34048c9e | 533 | if (l2size == 0) |
1da177e4 | 534 | return; /* Again, no L2 cache is possible */ |
140fc727 | 535 | #endif |
1da177e4 LT |
536 | |
537 | c->x86_cache_size = l2size; | |
1da177e4 LT |
538 | } |
539 | ||
e0ba94f1 AS |
540 | u16 __read_mostly tlb_lli_4k[NR_INFO]; |
541 | u16 __read_mostly tlb_lli_2m[NR_INFO]; | |
542 | u16 __read_mostly tlb_lli_4m[NR_INFO]; | |
543 | u16 __read_mostly tlb_lld_4k[NR_INFO]; | |
544 | u16 __read_mostly tlb_lld_2m[NR_INFO]; | |
545 | u16 __read_mostly tlb_lld_4m[NR_INFO]; | |
dd360393 | 546 | u16 __read_mostly tlb_lld_1g[NR_INFO]; |
e0ba94f1 | 547 | |
f94fe119 | 548 | static void cpu_detect_tlb(struct cpuinfo_x86 *c) |
e0ba94f1 AS |
549 | { |
550 | if (this_cpu->c_detect_tlb) | |
551 | this_cpu->c_detect_tlb(c); | |
552 | ||
f94fe119 | 553 | pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", |
e0ba94f1 | 554 | tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], |
f94fe119 SH |
555 | tlb_lli_4m[ENTRIES]); |
556 | ||
557 | pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", | |
558 | tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], | |
559 | tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); | |
e0ba94f1 AS |
560 | } |
561 | ||
148f9bb8 | 562 | void detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 563 | { |
c8e56d20 | 564 | #ifdef CONFIG_SMP |
0a488a53 YL |
565 | u32 eax, ebx, ecx, edx; |
566 | int index_msb, core_bits; | |
2eaad1fd | 567 | static bool printed; |
1da177e4 | 568 | |
0a488a53 | 569 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 570 | return; |
1da177e4 | 571 | |
0a488a53 YL |
572 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
573 | goto out; | |
1da177e4 | 574 | |
1cd78776 YL |
575 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
576 | return; | |
1da177e4 | 577 | |
0a488a53 | 578 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 579 | |
9d31d35b YL |
580 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
581 | ||
582 | if (smp_num_siblings == 1) { | |
1b74dde7 | 583 | pr_info_once("CPU0: Hyper-Threading is disabled\n"); |
0f3fa48a IM |
584 | goto out; |
585 | } | |
9d31d35b | 586 | |
0f3fa48a IM |
587 | if (smp_num_siblings <= 1) |
588 | goto out; | |
9d31d35b | 589 | |
0f3fa48a IM |
590 | index_msb = get_count_order(smp_num_siblings); |
591 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); | |
9d31d35b | 592 | |
0f3fa48a | 593 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
9d31d35b | 594 | |
0f3fa48a | 595 | index_msb = get_count_order(smp_num_siblings); |
9d31d35b | 596 | |
0f3fa48a | 597 | core_bits = get_count_order(c->x86_max_cores); |
9d31d35b | 598 | |
0f3fa48a IM |
599 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & |
600 | ((1 << core_bits) - 1); | |
1da177e4 | 601 | |
0a488a53 | 602 | out: |
2eaad1fd | 603 | if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { |
1b74dde7 CY |
604 | pr_info("CPU: Physical Processor ID: %d\n", |
605 | c->phys_proc_id); | |
606 | pr_info("CPU: Processor Core ID: %d\n", | |
607 | c->cpu_core_id); | |
2eaad1fd | 608 | printed = 1; |
9d31d35b | 609 | } |
9d31d35b | 610 | #endif |
97e4db7c | 611 | } |
1da177e4 | 612 | |
148f9bb8 | 613 | static void get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
614 | { |
615 | char *v = c->x86_vendor_id; | |
0f3fa48a | 616 | int i; |
1da177e4 LT |
617 | |
618 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
619 | if (!cpu_devs[i]) |
620 | break; | |
621 | ||
622 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
623 | (cpu_devs[i]->c_ident[1] && | |
624 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
0f3fa48a | 625 | |
10a434fc YL |
626 | this_cpu = cpu_devs[i]; |
627 | c->x86_vendor = this_cpu->c_x86_vendor; | |
628 | return; | |
1da177e4 LT |
629 | } |
630 | } | |
10a434fc | 631 | |
1b74dde7 CY |
632 | pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ |
633 | "CPU: Your system may be unstable.\n", v); | |
10a434fc | 634 | |
fe38d855 CE |
635 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
636 | this_cpu = &default_cpu; | |
1da177e4 LT |
637 | } |
638 | ||
148f9bb8 | 639 | void cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 640 | { |
1da177e4 | 641 | /* Get vendor name */ |
4a148513 HH |
642 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
643 | (unsigned int *)&c->x86_vendor_id[0], | |
644 | (unsigned int *)&c->x86_vendor_id[8], | |
645 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 646 | |
1da177e4 | 647 | c->x86 = 4; |
9d31d35b | 648 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
649 | if (c->cpuid_level >= 0x00000001) { |
650 | u32 junk, tfms, cap0, misc; | |
0f3fa48a | 651 | |
1da177e4 | 652 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
99f925ce BP |
653 | c->x86 = x86_family(tfms); |
654 | c->x86_model = x86_model(tfms); | |
655 | c->x86_mask = x86_stepping(tfms); | |
0f3fa48a | 656 | |
d4387bd3 | 657 | if (cap0 & (1<<19)) { |
d4387bd3 | 658 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 659 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 660 | } |
1da177e4 | 661 | } |
1da177e4 | 662 | } |
3da99c97 | 663 | |
8bf1ebca AL |
664 | static void apply_forced_caps(struct cpuinfo_x86 *c) |
665 | { | |
666 | int i; | |
667 | ||
668 | for (i = 0; i < NCAPINTS; i++) { | |
669 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
670 | c->x86_capability[i] |= cpu_caps_set[i]; | |
671 | } | |
672 | } | |
673 | ||
148f9bb8 | 674 | void get_cpu_cap(struct cpuinfo_x86 *c) |
093af8d7 | 675 | { |
39c06df4 | 676 | u32 eax, ebx, ecx, edx; |
093af8d7 | 677 | |
3da99c97 YL |
678 | /* Intel-defined flags: level 0x00000001 */ |
679 | if (c->cpuid_level >= 0x00000001) { | |
39c06df4 | 680 | cpuid(0x00000001, &eax, &ebx, &ecx, &edx); |
0f3fa48a | 681 | |
39c06df4 BP |
682 | c->x86_capability[CPUID_1_ECX] = ecx; |
683 | c->x86_capability[CPUID_1_EDX] = edx; | |
3da99c97 | 684 | } |
093af8d7 | 685 | |
3df8d920 AL |
686 | /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ |
687 | if (c->cpuid_level >= 0x00000006) | |
688 | c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); | |
689 | ||
bdc802dc PA |
690 | /* Additional Intel-defined flags: level 0x00000007 */ |
691 | if (c->cpuid_level >= 0x00000007) { | |
bdc802dc | 692 | cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); |
39c06df4 | 693 | c->x86_capability[CPUID_7_0_EBX] = ebx; |
dfb4a70f | 694 | c->x86_capability[CPUID_7_ECX] = ecx; |
bdc802dc PA |
695 | } |
696 | ||
6229ad27 FY |
697 | /* Extended state features: level 0x0000000d */ |
698 | if (c->cpuid_level >= 0x0000000d) { | |
6229ad27 FY |
699 | cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); |
700 | ||
39c06df4 | 701 | c->x86_capability[CPUID_D_1_EAX] = eax; |
6229ad27 FY |
702 | } |
703 | ||
cbc82b17 PWJ |
704 | /* Additional Intel-defined flags: level 0x0000000F */ |
705 | if (c->cpuid_level >= 0x0000000F) { | |
cbc82b17 PWJ |
706 | |
707 | /* QoS sub-leaf, EAX=0Fh, ECX=0 */ | |
708 | cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx); | |
39c06df4 BP |
709 | c->x86_capability[CPUID_F_0_EDX] = edx; |
710 | ||
cbc82b17 PWJ |
711 | if (cpu_has(c, X86_FEATURE_CQM_LLC)) { |
712 | /* will be overridden if occupancy monitoring exists */ | |
713 | c->x86_cache_max_rmid = ebx; | |
714 | ||
715 | /* QoS sub-leaf, EAX=0Fh, ECX=1 */ | |
716 | cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx); | |
39c06df4 BP |
717 | c->x86_capability[CPUID_F_1_EDX] = edx; |
718 | ||
33c3cc7a VS |
719 | if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) || |
720 | ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) || | |
721 | (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) { | |
cbc82b17 PWJ |
722 | c->x86_cache_max_rmid = ecx; |
723 | c->x86_cache_occ_scale = ebx; | |
724 | } | |
725 | } else { | |
726 | c->x86_cache_max_rmid = -1; | |
727 | c->x86_cache_occ_scale = -1; | |
728 | } | |
729 | } | |
730 | ||
3da99c97 | 731 | /* AMD-defined flags: level 0x80000001 */ |
39c06df4 BP |
732 | eax = cpuid_eax(0x80000000); |
733 | c->extended_cpuid_level = eax; | |
734 | ||
735 | if ((eax & 0xffff0000) == 0x80000000) { | |
736 | if (eax >= 0x80000001) { | |
737 | cpuid(0x80000001, &eax, &ebx, &ecx, &edx); | |
0f3fa48a | 738 | |
39c06df4 BP |
739 | c->x86_capability[CPUID_8000_0001_ECX] = ecx; |
740 | c->x86_capability[CPUID_8000_0001_EDX] = edx; | |
093af8d7 | 741 | } |
093af8d7 | 742 | } |
093af8d7 | 743 | |
71faad43 YG |
744 | if (c->extended_cpuid_level >= 0x80000007) { |
745 | cpuid(0x80000007, &eax, &ebx, &ecx, &edx); | |
746 | ||
747 | c->x86_capability[CPUID_8000_0007_EBX] = ebx; | |
748 | c->x86_power = edx; | |
749 | } | |
750 | ||
5122c890 | 751 | if (c->extended_cpuid_level >= 0x80000008) { |
39c06df4 | 752 | cpuid(0x80000008, &eax, &ebx, &ecx, &edx); |
5122c890 YL |
753 | |
754 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
755 | c->x86_phys_bits = eax & 0xff; | |
39c06df4 | 756 | c->x86_capability[CPUID_8000_0008_EBX] = ebx; |
093af8d7 | 757 | } |
13c6c532 JB |
758 | #ifdef CONFIG_X86_32 |
759 | else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) | |
760 | c->x86_phys_bits = 36; | |
5122c890 | 761 | #endif |
e3224234 | 762 | |
2ccd71f1 | 763 | if (c->extended_cpuid_level >= 0x8000000a) |
39c06df4 | 764 | c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); |
093af8d7 | 765 | |
1dedefd1 | 766 | init_scattered_cpuid_features(c); |
60d34501 AL |
767 | |
768 | /* | |
769 | * Clear/Set all flags overridden by options, after probe. | |
770 | * This needs to happen each time we re-probe, which may happen | |
771 | * several times during CPU initialization. | |
772 | */ | |
773 | apply_forced_caps(c); | |
093af8d7 | 774 | } |
1da177e4 | 775 | |
148f9bb8 | 776 | static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
aef93c8b YL |
777 | { |
778 | #ifdef CONFIG_X86_32 | |
779 | int i; | |
780 | ||
781 | /* | |
782 | * First of all, decide if this is a 486 or higher | |
783 | * It's a 486 if we can modify the AC flag | |
784 | */ | |
785 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
786 | c->x86 = 4; | |
787 | else | |
788 | c->x86 = 3; | |
789 | ||
790 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
791 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
792 | c->x86_vendor_id[0] = 0; | |
793 | cpu_devs[i]->c_identify(c); | |
794 | if (c->x86_vendor_id[0]) { | |
795 | get_cpu_vendor(c); | |
796 | break; | |
797 | } | |
798 | } | |
799 | #endif | |
800 | } | |
801 | ||
34048c9e PC |
802 | /* |
803 | * Do minimum CPU detection early. | |
804 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
805 | * cache alignment. | |
806 | * The others are not touched to avoid unwanted side effects. | |
807 | * | |
808 | * WARNING: this function is only called on the BP. Don't add code here | |
809 | * that is supposed to run on all CPUs. | |
810 | */ | |
3da99c97 | 811 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 812 | { |
6627d242 YL |
813 | #ifdef CONFIG_X86_64 |
814 | c->x86_clflush_size = 64; | |
13c6c532 JB |
815 | c->x86_phys_bits = 36; |
816 | c->x86_virt_bits = 48; | |
6627d242 | 817 | #else |
d4387bd3 | 818 | c->x86_clflush_size = 32; |
13c6c532 JB |
819 | c->x86_phys_bits = 32; |
820 | c->x86_virt_bits = 32; | |
6627d242 | 821 | #endif |
0a488a53 | 822 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 823 | |
3da99c97 | 824 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 825 | c->extended_cpuid_level = 0; |
d7cd5611 | 826 | |
aef93c8b | 827 | /* cyrix could have cpuid enabled via c_identify()*/ |
05fb3c19 AL |
828 | if (have_cpuid_p()) { |
829 | cpu_detect(c); | |
830 | get_cpu_vendor(c); | |
831 | get_cpu_cap(c); | |
78d1b296 | 832 | setup_force_cpu_cap(X86_FEATURE_CPUID); |
d7cd5611 | 833 | |
05fb3c19 AL |
834 | if (this_cpu->c_early_init) |
835 | this_cpu->c_early_init(c); | |
12cf105c | 836 | |
05fb3c19 AL |
837 | c->cpu_index = 0; |
838 | filter_cpuid_features(c, false); | |
093af8d7 | 839 | |
05fb3c19 AL |
840 | if (this_cpu->c_bsp_init) |
841 | this_cpu->c_bsp_init(c); | |
78d1b296 BP |
842 | } else { |
843 | identify_cpu_without_cpuid(c); | |
844 | setup_clear_cpu_cap(X86_FEATURE_CPUID); | |
05fb3c19 | 845 | } |
c3b83598 BP |
846 | |
847 | setup_force_cpu_cap(X86_FEATURE_ALWAYS); | |
db52ef74 | 848 | fpu__init_system(c); |
d7cd5611 RR |
849 | } |
850 | ||
9d31d35b YL |
851 | void __init early_cpu_init(void) |
852 | { | |
02dde8b4 | 853 | const struct cpu_dev *const *cdev; |
10a434fc YL |
854 | int count = 0; |
855 | ||
ac23f253 | 856 | #ifdef CONFIG_PROCESSOR_SELECT |
1b74dde7 | 857 | pr_info("KERNEL supported cpus:\n"); |
31c997ca IM |
858 | #endif |
859 | ||
10a434fc | 860 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { |
02dde8b4 | 861 | const struct cpu_dev *cpudev = *cdev; |
9d31d35b | 862 | |
10a434fc YL |
863 | if (count >= X86_VENDOR_NUM) |
864 | break; | |
865 | cpu_devs[count] = cpudev; | |
866 | count++; | |
867 | ||
ac23f253 | 868 | #ifdef CONFIG_PROCESSOR_SELECT |
31c997ca IM |
869 | { |
870 | unsigned int j; | |
871 | ||
872 | for (j = 0; j < 2; j++) { | |
873 | if (!cpudev->c_ident[j]) | |
874 | continue; | |
1b74dde7 | 875 | pr_info(" %s %s\n", cpudev->c_vendor, |
31c997ca IM |
876 | cpudev->c_ident[j]); |
877 | } | |
10a434fc | 878 | } |
0388423d | 879 | #endif |
10a434fc | 880 | } |
9d31d35b | 881 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 882 | } |
093af8d7 | 883 | |
b6734c35 | 884 | /* |
366d4a43 BP |
885 | * The NOPL instruction is supposed to exist on all CPUs of family >= 6; |
886 | * unfortunately, that's not true in practice because of early VIA | |
887 | * chips and (more importantly) broken virtualizers that are not easy | |
888 | * to detect. In the latter case it doesn't even *fail* reliably, so | |
889 | * probing for it doesn't even work. Disable it completely on 32-bit | |
ba0593bf | 890 | * unless we can find a reliable way to detect all the broken cases. |
366d4a43 | 891 | * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). |
b6734c35 | 892 | */ |
148f9bb8 | 893 | static void detect_nopl(struct cpuinfo_x86 *c) |
b6734c35 | 894 | { |
366d4a43 | 895 | #ifdef CONFIG_X86_32 |
b6734c35 | 896 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
366d4a43 BP |
897 | #else |
898 | set_cpu_cap(c, X86_FEATURE_NOPL); | |
58a5aac5 | 899 | #endif |
d7cd5611 | 900 | } |
58a5aac5 | 901 | |
7a5d6704 AL |
902 | static void detect_null_seg_behavior(struct cpuinfo_x86 *c) |
903 | { | |
904 | #ifdef CONFIG_X86_64 | |
58a5aac5 | 905 | /* |
7a5d6704 AL |
906 | * Empirically, writing zero to a segment selector on AMD does |
907 | * not clear the base, whereas writing zero to a segment | |
908 | * selector on Intel does clear the base. Intel's behavior | |
909 | * allows slightly faster context switches in the common case | |
910 | * where GS is unused by the prev and next threads. | |
58a5aac5 | 911 | * |
7a5d6704 AL |
912 | * Since neither vendor documents this anywhere that I can see, |
913 | * detect it directly instead of hardcoding the choice by | |
914 | * vendor. | |
915 | * | |
916 | * I've designated AMD's behavior as the "bug" because it's | |
917 | * counterintuitive and less friendly. | |
58a5aac5 | 918 | */ |
7a5d6704 AL |
919 | |
920 | unsigned long old_base, tmp; | |
921 | rdmsrl(MSR_FS_BASE, old_base); | |
922 | wrmsrl(MSR_FS_BASE, 1); | |
923 | loadsegment(fs, 0); | |
924 | rdmsrl(MSR_FS_BASE, tmp); | |
925 | if (tmp != 0) | |
926 | set_cpu_bug(c, X86_BUG_NULL_SEG); | |
927 | wrmsrl(MSR_FS_BASE, old_base); | |
366d4a43 | 928 | #endif |
d7cd5611 RR |
929 | } |
930 | ||
148f9bb8 | 931 | static void generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 932 | { |
aef93c8b | 933 | c->extended_cpuid_level = 0; |
1da177e4 | 934 | |
3da99c97 | 935 | if (!have_cpuid_p()) |
aef93c8b | 936 | identify_cpu_without_cpuid(c); |
1d67953f | 937 | |
aef93c8b | 938 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 939 | if (!have_cpuid_p()) |
aef93c8b | 940 | return; |
1da177e4 | 941 | |
3da99c97 | 942 | cpu_detect(c); |
1da177e4 | 943 | |
3da99c97 | 944 | get_cpu_vendor(c); |
1da177e4 | 945 | |
3da99c97 | 946 | get_cpu_cap(c); |
1da177e4 | 947 | |
3da99c97 YL |
948 | if (c->cpuid_level >= 0x00000001) { |
949 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e | 950 | #ifdef CONFIG_X86_32 |
c8e56d20 | 951 | # ifdef CONFIG_SMP |
cb8cc442 | 952 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 953 | # else |
3da99c97 | 954 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
955 | # endif |
956 | #endif | |
b89d3b3e | 957 | c->phys_proc_id = c->initial_apicid; |
3da99c97 | 958 | } |
1da177e4 | 959 | |
1b05d60d | 960 | get_model_name(c); /* Default name */ |
1da177e4 | 961 | |
3da99c97 | 962 | detect_nopl(c); |
7a5d6704 AL |
963 | |
964 | detect_null_seg_behavior(c); | |
0230bb03 AL |
965 | |
966 | /* | |
967 | * ESPFIX is a strange bug. All real CPUs have it. Paravirt | |
968 | * systems that run Linux at CPL > 0 may or may not have the | |
969 | * issue, but, even if they have the issue, there's absolutely | |
970 | * nothing we can do about it because we can't use the real IRET | |
971 | * instruction. | |
972 | * | |
973 | * NB: For the time being, only 32-bit kernels support | |
974 | * X86_BUG_ESPFIX as such. 64-bit kernels directly choose | |
975 | * whether to apply espfix using paravirt hooks. If any | |
976 | * non-paravirt system ever shows up that does *not* have the | |
977 | * ESPFIX issue, we can change this. | |
978 | */ | |
979 | #ifdef CONFIG_X86_32 | |
980 | # ifdef CONFIG_PARAVIRT | |
981 | do { | |
982 | extern void native_iret(void); | |
983 | if (pv_cpu_ops.iret == native_iret) | |
984 | set_cpu_bug(c, X86_BUG_ESPFIX); | |
985 | } while (0); | |
986 | # else | |
987 | set_cpu_bug(c, X86_BUG_ESPFIX); | |
988 | # endif | |
989 | #endif | |
1da177e4 | 990 | } |
1da177e4 | 991 | |
cbc82b17 PWJ |
992 | static void x86_init_cache_qos(struct cpuinfo_x86 *c) |
993 | { | |
994 | /* | |
995 | * The heavy lifting of max_rmid and cache_occ_scale are handled | |
996 | * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu | |
997 | * in case CQM bits really aren't there in this CPU. | |
998 | */ | |
999 | if (c != &boot_cpu_data) { | |
1000 | boot_cpu_data.x86_cache_max_rmid = | |
1001 | min(boot_cpu_data.x86_cache_max_rmid, | |
1002 | c->x86_cache_max_rmid); | |
1003 | } | |
1004 | } | |
1005 | ||
d49597fd | 1006 | /* |
9d85eb91 TG |
1007 | * Validate that ACPI/mptables have the same information about the |
1008 | * effective APIC id and update the package map. | |
d49597fd | 1009 | */ |
9d85eb91 | 1010 | static void validate_apic_and_package_id(struct cpuinfo_x86 *c) |
d49597fd TG |
1011 | { |
1012 | #ifdef CONFIG_SMP | |
9d85eb91 | 1013 | unsigned int apicid, cpu = smp_processor_id(); |
d49597fd TG |
1014 | |
1015 | apicid = apic->cpu_present_to_apicid(cpu); | |
d49597fd | 1016 | |
9d85eb91 TG |
1017 | if (apicid != c->apicid) { |
1018 | pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", | |
d49597fd | 1019 | cpu, apicid, c->initial_apicid); |
d49597fd | 1020 | } |
9d85eb91 | 1021 | BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); |
d49597fd TG |
1022 | #else |
1023 | c->logical_proc_id = 0; | |
1024 | #endif | |
1025 | } | |
1026 | ||
1da177e4 LT |
1027 | /* |
1028 | * This does the hard work of actually picking apart the CPU stuff... | |
1029 | */ | |
148f9bb8 | 1030 | static void identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
1031 | { |
1032 | int i; | |
1033 | ||
1034 | c->loops_per_jiffy = loops_per_jiffy; | |
1035 | c->x86_cache_size = -1; | |
1036 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
1037 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
1038 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
1039 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 1040 | c->x86_max_cores = 1; |
102bbe3a | 1041 | c->x86_coreid_bits = 0; |
79a8b9aa | 1042 | c->cu_id = 0xff; |
11fdd252 | 1043 | #ifdef CONFIG_X86_64 |
102bbe3a | 1044 | c->x86_clflush_size = 64; |
13c6c532 JB |
1045 | c->x86_phys_bits = 36; |
1046 | c->x86_virt_bits = 48; | |
102bbe3a YL |
1047 | #else |
1048 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 1049 | c->x86_clflush_size = 32; |
13c6c532 JB |
1050 | c->x86_phys_bits = 32; |
1051 | c->x86_virt_bits = 32; | |
102bbe3a YL |
1052 | #endif |
1053 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
1054 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
1055 | ||
1da177e4 LT |
1056 | generic_identify(c); |
1057 | ||
3898534d | 1058 | if (this_cpu->c_identify) |
1da177e4 LT |
1059 | this_cpu->c_identify(c); |
1060 | ||
6a6256f9 | 1061 | /* Clear/Set all flags overridden by options, after probe */ |
8bf1ebca | 1062 | apply_forced_caps(c); |
2759c328 | 1063 | |
102bbe3a | 1064 | #ifdef CONFIG_X86_64 |
cb8cc442 | 1065 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
1066 | #endif |
1067 | ||
1da177e4 LT |
1068 | /* |
1069 | * Vendor-specific initialization. In this section we | |
1070 | * canonicalize the feature flags, meaning if there are | |
1071 | * features a certain CPU supports which CPUID doesn't | |
1072 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
1073 | * we handle them here. | |
1074 | * | |
1075 | * At the end of this section, c->x86_capability better | |
1076 | * indicate the features this CPU genuinely supports! | |
1077 | */ | |
1078 | if (this_cpu->c_init) | |
1079 | this_cpu->c_init(c); | |
acb04058 PZ |
1080 | else |
1081 | clear_sched_clock_stable(); | |
1da177e4 LT |
1082 | |
1083 | /* Disable the PN if appropriate */ | |
1084 | squash_the_stupid_serial_number(c); | |
1085 | ||
b2cc2a07 PA |
1086 | /* Set up SMEP/SMAP */ |
1087 | setup_smep(c); | |
1088 | setup_smap(c); | |
1089 | ||
1da177e4 | 1090 | /* |
0f3fa48a IM |
1091 | * The vendor-specific functions might have changed features. |
1092 | * Now we do "generic changes." | |
1da177e4 LT |
1093 | */ |
1094 | ||
b38b0665 PA |
1095 | /* Filter out anything that depends on CPUID levels we don't have */ |
1096 | filter_cpuid_features(c, true); | |
1097 | ||
1da177e4 | 1098 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 1099 | if (!c->x86_model_id[0]) { |
02dde8b4 | 1100 | const char *p; |
1da177e4 | 1101 | p = table_lookup_model(c); |
34048c9e | 1102 | if (p) |
1da177e4 LT |
1103 | strcpy(c->x86_model_id, p); |
1104 | else | |
1105 | /* Last resort... */ | |
1106 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 1107 | c->x86, c->x86_model); |
1da177e4 LT |
1108 | } |
1109 | ||
102bbe3a YL |
1110 | #ifdef CONFIG_X86_64 |
1111 | detect_ht(c); | |
1112 | #endif | |
1113 | ||
88b094fb | 1114 | init_hypervisor(c); |
49d859d7 | 1115 | x86_init_rdrand(c); |
cbc82b17 | 1116 | x86_init_cache_qos(c); |
06976945 | 1117 | setup_pku(c); |
3e0c3737 YL |
1118 | |
1119 | /* | |
6a6256f9 | 1120 | * Clear/Set all flags overridden by options, need do it |
3e0c3737 YL |
1121 | * before following smp all cpus cap AND. |
1122 | */ | |
8bf1ebca | 1123 | apply_forced_caps(c); |
3e0c3737 | 1124 | |
1da177e4 LT |
1125 | /* |
1126 | * On SMP, boot_cpu_data holds the common feature set between | |
1127 | * all CPUs; so make sure that we indicate which features are | |
1128 | * common between the CPUs. The first time this routine gets | |
1129 | * executed, c == &boot_cpu_data. | |
1130 | */ | |
34048c9e | 1131 | if (c != &boot_cpu_data) { |
1da177e4 | 1132 | /* AND the already accumulated flags with these */ |
9d31d35b | 1133 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 | 1134 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
65fc985b BP |
1135 | |
1136 | /* OR, i.e. replicate the bug flags */ | |
1137 | for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) | |
1138 | c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; | |
1da177e4 LT |
1139 | } |
1140 | ||
1141 | /* Init Machine Check Exception if available. */ | |
5e09954a | 1142 | mcheck_cpu_init(c); |
30d432df AK |
1143 | |
1144 | select_idle_routine(c); | |
102bbe3a | 1145 | |
de2d9445 | 1146 | #ifdef CONFIG_NUMA |
102bbe3a YL |
1147 | numa_add_cpu(smp_processor_id()); |
1148 | #endif | |
a6c4e076 | 1149 | } |
31ab269a | 1150 | |
8b6c0ab1 IM |
1151 | /* |
1152 | * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions | |
1153 | * on 32-bit kernels: | |
1154 | */ | |
cfda7bb9 AL |
1155 | #ifdef CONFIG_X86_32 |
1156 | void enable_sep_cpu(void) | |
1157 | { | |
8b6c0ab1 IM |
1158 | struct tss_struct *tss; |
1159 | int cpu; | |
cfda7bb9 | 1160 | |
b3edfda4 BP |
1161 | if (!boot_cpu_has(X86_FEATURE_SEP)) |
1162 | return; | |
1163 | ||
8b6c0ab1 IM |
1164 | cpu = get_cpu(); |
1165 | tss = &per_cpu(cpu_tss, cpu); | |
1166 | ||
8b6c0ab1 | 1167 | /* |
cf9328cc AL |
1168 | * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- |
1169 | * see the big comment in struct x86_hw_tss's definition. | |
8b6c0ab1 | 1170 | */ |
cfda7bb9 AL |
1171 | |
1172 | tss->x86_tss.ss1 = __KERNEL_CS; | |
8b6c0ab1 IM |
1173 | wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); |
1174 | ||
cf9328cc AL |
1175 | wrmsr(MSR_IA32_SYSENTER_ESP, |
1176 | (unsigned long)tss + offsetofend(struct tss_struct, SYSENTER_stack), | |
1177 | 0); | |
8b6c0ab1 | 1178 | |
4c8cd0c5 | 1179 | wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); |
8b6c0ab1 | 1180 | |
cfda7bb9 AL |
1181 | put_cpu(); |
1182 | } | |
e04d645f GC |
1183 | #endif |
1184 | ||
a6c4e076 JF |
1185 | void __init identify_boot_cpu(void) |
1186 | { | |
1187 | identify_cpu(&boot_cpu_data); | |
102bbe3a | 1188 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1189 | sysenter_setup(); |
6fe940d6 | 1190 | enable_sep_cpu(); |
102bbe3a | 1191 | #endif |
5b556332 | 1192 | cpu_detect_tlb(&boot_cpu_data); |
a6c4e076 | 1193 | } |
3b520b23 | 1194 | |
148f9bb8 | 1195 | void identify_secondary_cpu(struct cpuinfo_x86 *c) |
a6c4e076 JF |
1196 | { |
1197 | BUG_ON(c == &boot_cpu_data); | |
1198 | identify_cpu(c); | |
102bbe3a | 1199 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1200 | enable_sep_cpu(); |
102bbe3a | 1201 | #endif |
a6c4e076 | 1202 | mtrr_ap_init(); |
9d85eb91 | 1203 | validate_apic_and_package_id(c); |
1da177e4 LT |
1204 | } |
1205 | ||
191679fd AK |
1206 | static __init int setup_noclflush(char *arg) |
1207 | { | |
840d2830 | 1208 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); |
da4aaa7d | 1209 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); |
191679fd AK |
1210 | return 1; |
1211 | } | |
1212 | __setup("noclflush", setup_noclflush); | |
1213 | ||
148f9bb8 | 1214 | void print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 | 1215 | { |
02dde8b4 | 1216 | const char *vendor = NULL; |
1da177e4 | 1217 | |
0f3fa48a | 1218 | if (c->x86_vendor < X86_VENDOR_NUM) { |
1da177e4 | 1219 | vendor = this_cpu->c_vendor; |
0f3fa48a IM |
1220 | } else { |
1221 | if (c->cpuid_level >= 0) | |
1222 | vendor = c->x86_vendor_id; | |
1223 | } | |
1da177e4 | 1224 | |
bd32a8cf | 1225 | if (vendor && !strstr(c->x86_model_id, vendor)) |
1b74dde7 | 1226 | pr_cont("%s ", vendor); |
1da177e4 | 1227 | |
9d31d35b | 1228 | if (c->x86_model_id[0]) |
1b74dde7 | 1229 | pr_cont("%s", c->x86_model_id); |
1da177e4 | 1230 | else |
1b74dde7 | 1231 | pr_cont("%d86", c->x86); |
1da177e4 | 1232 | |
1b74dde7 | 1233 | pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); |
924e101a | 1234 | |
34048c9e | 1235 | if (c->x86_mask || c->cpuid_level >= 0) |
1b74dde7 | 1236 | pr_cont(", stepping: 0x%x)\n", c->x86_mask); |
1da177e4 | 1237 | else |
1b74dde7 | 1238 | pr_cont(")\n"); |
1da177e4 LT |
1239 | } |
1240 | ||
ac72e788 AK |
1241 | static __init int setup_disablecpuid(char *arg) |
1242 | { | |
1243 | int bit; | |
0f3fa48a | 1244 | |
dd853fd2 | 1245 | if (get_option(&arg, &bit) && bit >= 0 && bit < NCAPINTS * 32) |
ac72e788 AK |
1246 | setup_clear_cpu_cap(bit); |
1247 | else | |
1248 | return 0; | |
0f3fa48a | 1249 | |
ac72e788 AK |
1250 | return 1; |
1251 | } | |
1252 | __setup("clearcpuid=", setup_disablecpuid); | |
1253 | ||
d5494d4f | 1254 | #ifdef CONFIG_X86_64 |
404f6aac KC |
1255 | struct desc_ptr idt_descr __ro_after_init = { |
1256 | .size = NR_VECTORS * 16 - 1, | |
1257 | .address = (unsigned long) idt_table, | |
1258 | }; | |
1259 | const struct desc_ptr debug_idt_descr = { | |
1260 | .size = NR_VECTORS * 16 - 1, | |
1261 | .address = (unsigned long) debug_idt_table, | |
1262 | }; | |
d5494d4f | 1263 | |
947e76cd | 1264 | DEFINE_PER_CPU_FIRST(union irq_stack_union, |
277d5b40 | 1265 | irq_stack_union) __aligned(PAGE_SIZE) __visible; |
0f3fa48a | 1266 | |
bdf977b3 | 1267 | /* |
a7fcf28d AL |
1268 | * The following percpu variables are hot. Align current_task to |
1269 | * cacheline size such that they fall in the same cacheline. | |
bdf977b3 TH |
1270 | */ |
1271 | DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = | |
1272 | &init_task; | |
1273 | EXPORT_PER_CPU_SYMBOL(current_task); | |
d5494d4f | 1274 | |
bdf977b3 | 1275 | DEFINE_PER_CPU(char *, irq_stack_ptr) = |
4950d6d4 | 1276 | init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE; |
bdf977b3 | 1277 | |
277d5b40 | 1278 | DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; |
d5494d4f | 1279 | |
c2daa3be PZ |
1280 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1281 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
1282 | ||
0f3fa48a IM |
1283 | /* |
1284 | * Special IST stacks which the CPU switches to when it calls | |
1285 | * an IST-marked descriptor entry. Up to 7 stacks (hardware | |
1286 | * limit), all of them are 4K, except the debug stack which | |
1287 | * is 8K. | |
1288 | */ | |
1289 | static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { | |
1290 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
1291 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
1292 | }; | |
1293 | ||
92d65b23 | 1294 | static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks |
3e352aa8 | 1295 | [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); |
d5494d4f | 1296 | |
d5494d4f YL |
1297 | /* May not be marked __init: used by software suspend */ |
1298 | void syscall_init(void) | |
1da177e4 | 1299 | { |
31ac34ca | 1300 | wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); |
47edb651 | 1301 | wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); |
d56fe4bf IM |
1302 | |
1303 | #ifdef CONFIG_IA32_EMULATION | |
47edb651 | 1304 | wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); |
a76c7f46 | 1305 | /* |
487d1edb DV |
1306 | * This only works on Intel CPUs. |
1307 | * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. | |
1308 | * This does not cause SYSENTER to jump to the wrong location, because | |
1309 | * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). | |
a76c7f46 DV |
1310 | */ |
1311 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); | |
1312 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); | |
4c8cd0c5 | 1313 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); |
d56fe4bf | 1314 | #else |
47edb651 | 1315 | wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); |
6b51311c | 1316 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); |
d56fe4bf IM |
1317 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); |
1318 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); | |
d5494d4f | 1319 | #endif |
03ae5768 | 1320 | |
d5494d4f YL |
1321 | /* Flags to clear on syscall */ |
1322 | wrmsrl(MSR_SYSCALL_MASK, | |
63bcff2a | 1323 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| |
8c7aa698 | 1324 | X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); |
1da177e4 | 1325 | } |
62111195 | 1326 | |
d5494d4f YL |
1327 | /* |
1328 | * Copies of the original ist values from the tss are only accessed during | |
1329 | * debugging, no special alignment required. | |
1330 | */ | |
1331 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
1332 | ||
228bdaa9 | 1333 | static DEFINE_PER_CPU(unsigned long, debug_stack_addr); |
42181186 | 1334 | DEFINE_PER_CPU(int, debug_stack_usage); |
228bdaa9 SR |
1335 | |
1336 | int is_debug_stack(unsigned long addr) | |
1337 | { | |
89cbc767 CL |
1338 | return __this_cpu_read(debug_stack_usage) || |
1339 | (addr <= __this_cpu_read(debug_stack_addr) && | |
1340 | addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ)); | |
228bdaa9 | 1341 | } |
0f46efeb | 1342 | NOKPROBE_SYMBOL(is_debug_stack); |
228bdaa9 | 1343 | |
629f4f9d | 1344 | DEFINE_PER_CPU(u32, debug_idt_ctr); |
f8988175 | 1345 | |
228bdaa9 SR |
1346 | void debug_stack_set_zero(void) |
1347 | { | |
629f4f9d SA |
1348 | this_cpu_inc(debug_idt_ctr); |
1349 | load_current_idt(); | |
228bdaa9 | 1350 | } |
0f46efeb | 1351 | NOKPROBE_SYMBOL(debug_stack_set_zero); |
228bdaa9 SR |
1352 | |
1353 | void debug_stack_reset(void) | |
1354 | { | |
629f4f9d | 1355 | if (WARN_ON(!this_cpu_read(debug_idt_ctr))) |
f8988175 | 1356 | return; |
629f4f9d SA |
1357 | if (this_cpu_dec_return(debug_idt_ctr) == 0) |
1358 | load_current_idt(); | |
228bdaa9 | 1359 | } |
0f46efeb | 1360 | NOKPROBE_SYMBOL(debug_stack_reset); |
228bdaa9 | 1361 | |
0f3fa48a | 1362 | #else /* CONFIG_X86_64 */ |
d5494d4f | 1363 | |
bdf977b3 TH |
1364 | DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; |
1365 | EXPORT_PER_CPU_SYMBOL(current_task); | |
c2daa3be PZ |
1366 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1367 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
bdf977b3 | 1368 | |
a7fcf28d AL |
1369 | /* |
1370 | * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find | |
1371 | * the top of the kernel stack. Use an extra percpu variable to track the | |
1372 | * top of the kernel stack directly. | |
1373 | */ | |
1374 | DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = | |
1375 | (unsigned long)&init_thread_union + THREAD_SIZE; | |
1376 | EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); | |
1377 | ||
60a5317f | 1378 | #ifdef CONFIG_CC_STACKPROTECTOR |
53f82452 | 1379 | DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); |
60a5317f | 1380 | #endif |
d5494d4f | 1381 | |
0f3fa48a | 1382 | #endif /* CONFIG_X86_64 */ |
c5413fbe | 1383 | |
9766cdbc JSR |
1384 | /* |
1385 | * Clear all 6 debug registers: | |
1386 | */ | |
1387 | static void clear_all_debug_regs(void) | |
1388 | { | |
1389 | int i; | |
1390 | ||
1391 | for (i = 0; i < 8; i++) { | |
1392 | /* Ignore db4, db5 */ | |
1393 | if ((i == 4) || (i == 5)) | |
1394 | continue; | |
1395 | ||
1396 | set_debugreg(0, i); | |
1397 | } | |
1398 | } | |
c5413fbe | 1399 | |
0bb9fef9 JW |
1400 | #ifdef CONFIG_KGDB |
1401 | /* | |
1402 | * Restore debug regs if using kgdbwait and you have a kernel debugger | |
1403 | * connection established. | |
1404 | */ | |
1405 | static void dbg_restore_debug_regs(void) | |
1406 | { | |
1407 | if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) | |
1408 | arch_kgdb_ops.correct_hw_break(); | |
1409 | } | |
1410 | #else /* ! CONFIG_KGDB */ | |
1411 | #define dbg_restore_debug_regs() | |
1412 | #endif /* ! CONFIG_KGDB */ | |
1413 | ||
ce4b1b16 IM |
1414 | static void wait_for_master_cpu(int cpu) |
1415 | { | |
1416 | #ifdef CONFIG_SMP | |
1417 | /* | |
1418 | * wait for ACK from master CPU before continuing | |
1419 | * with AP initialization | |
1420 | */ | |
1421 | WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); | |
1422 | while (!cpumask_test_cpu(cpu, cpu_callout_mask)) | |
1423 | cpu_relax(); | |
1424 | #endif | |
1425 | } | |
1426 | ||
d2cbcc49 RR |
1427 | /* |
1428 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1429 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1430 | * and IDT. We reload them nevertheless, this function acts as a | |
1431 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 1432 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 1433 | */ |
1ba76586 | 1434 | #ifdef CONFIG_X86_64 |
0f3fa48a | 1435 | |
148f9bb8 | 1436 | void cpu_init(void) |
1ba76586 | 1437 | { |
0fe1e009 | 1438 | struct orig_ist *oist; |
1ba76586 | 1439 | struct task_struct *me; |
0f3fa48a IM |
1440 | struct tss_struct *t; |
1441 | unsigned long v; | |
fb59831b | 1442 | int cpu = raw_smp_processor_id(); |
1ba76586 YL |
1443 | int i; |
1444 | ||
ce4b1b16 IM |
1445 | wait_for_master_cpu(cpu); |
1446 | ||
1e02ce4c AL |
1447 | /* |
1448 | * Initialize the CR4 shadow before doing anything that could | |
1449 | * try to read it. | |
1450 | */ | |
1451 | cr4_init_shadow(); | |
1452 | ||
777284b6 BP |
1453 | if (cpu) |
1454 | load_ucode_ap(); | |
e6ebf5de | 1455 | |
24933b82 | 1456 | t = &per_cpu(cpu_tss, cpu); |
0fe1e009 | 1457 | oist = &per_cpu(orig_ist, cpu); |
0f3fa48a | 1458 | |
e7a22c1e | 1459 | #ifdef CONFIG_NUMA |
27fd185f | 1460 | if (this_cpu_read(numa_node) == 0 && |
e534c7c5 LS |
1461 | early_cpu_to_node(cpu) != NUMA_NO_NODE) |
1462 | set_numa_node(early_cpu_to_node(cpu)); | |
e7a22c1e | 1463 | #endif |
1ba76586 YL |
1464 | |
1465 | me = current; | |
1466 | ||
2eaad1fd | 1467 | pr_debug("Initializing CPU#%d\n", cpu); |
1ba76586 | 1468 | |
375074cc | 1469 | cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); |
1ba76586 YL |
1470 | |
1471 | /* | |
1472 | * Initialize the per-CPU GDT with the boot GDT, | |
1473 | * and set up the GDT descriptor: | |
1474 | */ | |
1475 | ||
552be871 | 1476 | switch_to_new_gdt(cpu); |
2697fbd5 BG |
1477 | loadsegment(fs, 0); |
1478 | ||
cf910e83 | 1479 | load_current_idt(); |
1ba76586 YL |
1480 | |
1481 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1482 | syscall_init(); | |
1483 | ||
1484 | wrmsrl(MSR_FS_BASE, 0); | |
1485 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1486 | barrier(); | |
1487 | ||
4763ed4d | 1488 | x86_configure_nx(); |
659006bf | 1489 | x2apic_setup(); |
1ba76586 YL |
1490 | |
1491 | /* | |
1492 | * set up and load the per-CPU TSS | |
1493 | */ | |
0fe1e009 | 1494 | if (!oist->ist[0]) { |
92d65b23 | 1495 | char *estacks = per_cpu(exception_stacks, cpu); |
0f3fa48a | 1496 | |
1ba76586 | 1497 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
0f3fa48a | 1498 | estacks += exception_stack_sizes[v]; |
0fe1e009 | 1499 | oist->ist[v] = t->x86_tss.ist[v] = |
1ba76586 | 1500 | (unsigned long)estacks; |
228bdaa9 SR |
1501 | if (v == DEBUG_STACK-1) |
1502 | per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; | |
1ba76586 YL |
1503 | } |
1504 | } | |
1505 | ||
1506 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
0f3fa48a | 1507 | |
1ba76586 YL |
1508 | /* |
1509 | * <= is required because the CPU will access up to | |
1510 | * 8 bits beyond the end of the IO permission bitmap. | |
1511 | */ | |
1512 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1513 | t->io_bitmap[i] = ~0UL; | |
1514 | ||
f1f10076 | 1515 | mmgrab(&init_mm); |
1ba76586 | 1516 | me->active_mm = &init_mm; |
8c5dfd25 | 1517 | BUG_ON(me->mm); |
1ba76586 YL |
1518 | enter_lazy_tlb(&init_mm, me); |
1519 | ||
1520 | load_sp0(t, ¤t->thread); | |
1521 | set_tss_desc(cpu, t); | |
1522 | load_TR_desc(); | |
37868fe1 | 1523 | load_mm_ldt(&init_mm); |
1ba76586 | 1524 | |
0bb9fef9 JW |
1525 | clear_all_debug_regs(); |
1526 | dbg_restore_debug_regs(); | |
1ba76586 | 1527 | |
21c4cd10 | 1528 | fpu__init_cpu(); |
1ba76586 | 1529 | |
1ba76586 YL |
1530 | if (is_uv_system()) |
1531 | uv_cpu_init(); | |
1532 | } | |
1533 | ||
1534 | #else | |
1535 | ||
148f9bb8 | 1536 | void cpu_init(void) |
9ee79a3d | 1537 | { |
d2cbcc49 RR |
1538 | int cpu = smp_processor_id(); |
1539 | struct task_struct *curr = current; | |
24933b82 | 1540 | struct tss_struct *t = &per_cpu(cpu_tss, cpu); |
9ee79a3d | 1541 | struct thread_struct *thread = &curr->thread; |
62111195 | 1542 | |
ce4b1b16 | 1543 | wait_for_master_cpu(cpu); |
e6ebf5de | 1544 | |
5b2bdbc8 SR |
1545 | /* |
1546 | * Initialize the CR4 shadow before doing anything that could | |
1547 | * try to read it. | |
1548 | */ | |
1549 | cr4_init_shadow(); | |
1550 | ||
ce4b1b16 | 1551 | show_ucode_info_early(); |
62111195 | 1552 | |
1b74dde7 | 1553 | pr_info("Initializing CPU#%d\n", cpu); |
62111195 | 1554 | |
362f924b | 1555 | if (cpu_feature_enabled(X86_FEATURE_VME) || |
59e21e3d | 1556 | boot_cpu_has(X86_FEATURE_TSC) || |
362f924b | 1557 | boot_cpu_has(X86_FEATURE_DE)) |
375074cc | 1558 | cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); |
62111195 | 1559 | |
cf910e83 | 1560 | load_current_idt(); |
552be871 | 1561 | switch_to_new_gdt(cpu); |
1da177e4 | 1562 | |
1da177e4 LT |
1563 | /* |
1564 | * Set up and load the per-CPU TSS and LDT | |
1565 | */ | |
f1f10076 | 1566 | mmgrab(&init_mm); |
62111195 | 1567 | curr->active_mm = &init_mm; |
8c5dfd25 | 1568 | BUG_ON(curr->mm); |
62111195 | 1569 | enter_lazy_tlb(&init_mm, curr); |
1da177e4 | 1570 | |
faca6227 | 1571 | load_sp0(t, thread); |
34048c9e | 1572 | set_tss_desc(cpu, t); |
1da177e4 | 1573 | load_TR_desc(); |
37868fe1 | 1574 | load_mm_ldt(&init_mm); |
1da177e4 | 1575 | |
f9a196b8 TG |
1576 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); |
1577 | ||
22c4e308 | 1578 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1579 | /* Set up doublefault TSS pointer in the GDT */ |
1580 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1581 | #endif |
1da177e4 | 1582 | |
9766cdbc | 1583 | clear_all_debug_regs(); |
0bb9fef9 | 1584 | dbg_restore_debug_regs(); |
1da177e4 | 1585 | |
21c4cd10 | 1586 | fpu__init_cpu(); |
1da177e4 | 1587 | } |
1ba76586 | 1588 | #endif |
5700f743 | 1589 | |
b51ef52d LA |
1590 | static void bsp_resume(void) |
1591 | { | |
1592 | if (this_cpu->c_bsp_resume) | |
1593 | this_cpu->c_bsp_resume(&boot_cpu_data); | |
1594 | } | |
1595 | ||
1596 | static struct syscore_ops cpu_syscore_ops = { | |
1597 | .resume = bsp_resume, | |
1598 | }; | |
1599 | ||
1600 | static int __init init_cpu_syscore(void) | |
1601 | { | |
1602 | register_syscore_ops(&cpu_syscore_ops); | |
1603 | return 0; | |
1604 | } | |
1605 | core_initcall(init_cpu_syscore); |