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1da177e4 | 1 | #include <linux/init.h> |
f0fc4aff YL |
2 | #include <linux/kernel.h> |
3 | #include <linux/sched.h> | |
1da177e4 | 4 | #include <linux/string.h> |
f0fc4aff YL |
5 | #include <linux/bootmem.h> |
6 | #include <linux/bitops.h> | |
7 | #include <linux/module.h> | |
8 | #include <linux/kgdb.h> | |
9 | #include <linux/topology.h> | |
1da177e4 LT |
10 | #include <linux/delay.h> |
11 | #include <linux/smp.h> | |
1da177e4 | 12 | #include <linux/percpu.h> |
1da177e4 LT |
13 | #include <asm/i387.h> |
14 | #include <asm/msr.h> | |
15 | #include <asm/io.h> | |
f0fc4aff | 16 | #include <asm/linkage.h> |
1da177e4 | 17 | #include <asm/mmu_context.h> |
27b07da7 | 18 | #include <asm/mtrr.h> |
a03a3e28 | 19 | #include <asm/mce.h> |
8d4a4300 | 20 | #include <asm/pat.h> |
7e00df58 | 21 | #include <asm/asm.h> |
f0fc4aff | 22 | #include <asm/numa.h> |
1da177e4 LT |
23 | #ifdef CONFIG_X86_LOCAL_APIC |
24 | #include <asm/mpspec.h> | |
25 | #include <asm/apic.h> | |
26 | #include <mach_apic.h> | |
f0fc4aff | 27 | #include <asm/genapic.h> |
1da177e4 LT |
28 | #endif |
29 | ||
f0fc4aff YL |
30 | #include <asm/pda.h> |
31 | #include <asm/pgtable.h> | |
32 | #include <asm/processor.h> | |
33 | #include <asm/desc.h> | |
34 | #include <asm/atomic.h> | |
35 | #include <asm/proto.h> | |
36 | #include <asm/sections.h> | |
37 | #include <asm/setup.h> | |
38 | ||
1da177e4 LT |
39 | #include "cpu.h" |
40 | ||
0a488a53 YL |
41 | static struct cpu_dev *this_cpu __cpuinitdata; |
42 | ||
950ad7ff YL |
43 | #ifdef CONFIG_X86_64 |
44 | /* We need valid kernel segments for data and code in long mode too | |
45 | * IRET will check the segment types kkeil 2000/10/28 | |
46 | * Also sysret mandates a special GDT layout | |
47 | */ | |
48 | /* The TLS descriptors are currently at a different place compared to i386. | |
49 | Hopefully nobody expects them at a fixed place (Wine?) */ | |
50 | DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = { | |
51 | [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } }, | |
52 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } }, | |
53 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } }, | |
54 | [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } }, | |
55 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } }, | |
56 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } }, | |
57 | } }; | |
58 | #else | |
63cc8c75 | 59 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
6842ef0e GOC |
60 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, |
61 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, | |
62 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, | |
63 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, | |
bf504672 RR |
64 | /* |
65 | * Segments used for calling PnP BIOS have byte granularity. | |
66 | * They code segments and data segments have fixed 64k limits, | |
67 | * the transfer segment sizes are set at run time. | |
68 | */ | |
6842ef0e GOC |
69 | /* 32-bit code */ |
70 | [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, | |
71 | /* 16-bit code */ | |
72 | [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, | |
73 | /* 16-bit data */ | |
74 | [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, | |
75 | /* 16-bit data */ | |
76 | [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, | |
77 | /* 16-bit data */ | |
78 | [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, | |
bf504672 RR |
79 | /* |
80 | * The APM segments have byte granularity and their bases | |
81 | * are set at run time. All have 64k limits. | |
82 | */ | |
6842ef0e GOC |
83 | /* 32-bit code */ |
84 | [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, | |
bf504672 | 85 | /* 16-bit code */ |
6842ef0e GOC |
86 | [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, |
87 | /* data */ | |
88 | [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, | |
bf504672 | 89 | |
6842ef0e GOC |
90 | [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, |
91 | [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } }, | |
7a61d35d | 92 | } }; |
950ad7ff | 93 | #endif |
7a61d35d | 94 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 95 | |
ba51dced | 96 | #ifdef CONFIG_X86_32 |
3bc9b76b | 97 | static int cachesize_override __cpuinitdata = -1; |
3bc9b76b | 98 | static int disable_x86_serial_nr __cpuinitdata = 1; |
1da177e4 | 99 | |
0a488a53 YL |
100 | static int __init cachesize_setup(char *str) |
101 | { | |
102 | get_option(&str, &cachesize_override); | |
103 | return 1; | |
104 | } | |
105 | __setup("cachesize=", cachesize_setup); | |
106 | ||
0a488a53 YL |
107 | static int __init x86_fxsr_setup(char *s) |
108 | { | |
109 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
110 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
111 | return 1; | |
112 | } | |
113 | __setup("nofxsr", x86_fxsr_setup); | |
114 | ||
115 | static int __init x86_sep_setup(char *s) | |
116 | { | |
117 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
118 | return 1; | |
119 | } | |
120 | __setup("nosep", x86_sep_setup); | |
121 | ||
122 | /* Standard macro to see if a specific flag is changeable */ | |
123 | static inline int flag_is_changeable_p(u32 flag) | |
124 | { | |
125 | u32 f1, f2; | |
126 | ||
127 | asm("pushfl\n\t" | |
128 | "pushfl\n\t" | |
129 | "popl %0\n\t" | |
130 | "movl %0,%1\n\t" | |
131 | "xorl %2,%0\n\t" | |
132 | "pushl %0\n\t" | |
133 | "popfl\n\t" | |
134 | "pushfl\n\t" | |
135 | "popl %0\n\t" | |
136 | "popfl\n\t" | |
137 | : "=&r" (f1), "=&r" (f2) | |
138 | : "ir" (flag)); | |
139 | ||
140 | return ((f1^f2) & flag) != 0; | |
141 | } | |
142 | ||
143 | /* Probe for the CPUID instruction */ | |
144 | static int __cpuinit have_cpuid_p(void) | |
145 | { | |
146 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
147 | } | |
148 | ||
149 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
150 | { | |
151 | if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) { | |
152 | /* Disable processor serial number */ | |
153 | unsigned long lo, hi; | |
154 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
155 | lo |= 0x200000; | |
156 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
157 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
158 | clear_cpu_cap(c, X86_FEATURE_PN); | |
159 | ||
160 | /* Disabling the serial number may affect the cpuid level */ | |
161 | c->cpuid_level = cpuid_eax(0); | |
162 | } | |
163 | } | |
164 | ||
165 | static int __init x86_serial_nr_setup(char *s) | |
166 | { | |
167 | disable_x86_serial_nr = 0; | |
168 | return 1; | |
169 | } | |
170 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 171 | #else |
102bbe3a YL |
172 | static inline int flag_is_changeable_p(u32 flag) |
173 | { | |
174 | return 1; | |
175 | } | |
ba51dced YL |
176 | /* Probe for the CPUID instruction */ |
177 | static inline int have_cpuid_p(void) | |
178 | { | |
179 | return 1; | |
180 | } | |
102bbe3a YL |
181 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
182 | { | |
183 | } | |
ba51dced | 184 | #endif |
0a488a53 | 185 | |
102bbe3a YL |
186 | /* |
187 | * Naming convention should be: <Name> [(<Codename>)] | |
188 | * This table only is used unless init_<vendor>() below doesn't set it; | |
189 | * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used | |
190 | * | |
191 | */ | |
192 | ||
193 | /* Look up CPU names by table lookup. */ | |
194 | static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c) | |
195 | { | |
196 | struct cpu_model_info *info; | |
197 | ||
198 | if (c->x86_model >= 16) | |
199 | return NULL; /* Range check */ | |
200 | ||
201 | if (!this_cpu) | |
202 | return NULL; | |
203 | ||
204 | info = this_cpu->c_models; | |
205 | ||
206 | while (info && info->family) { | |
207 | if (info->family == c->x86) | |
208 | return info->model_names[c->x86_model]; | |
209 | info++; | |
210 | } | |
211 | return NULL; /* Not found */ | |
212 | } | |
213 | ||
7d851c8d AK |
214 | __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; |
215 | ||
9d31d35b YL |
216 | /* Current gdt points %fs at the "master" per-cpu area: after this, |
217 | * it's on the real one. */ | |
218 | void switch_to_new_gdt(void) | |
219 | { | |
220 | struct desc_ptr gdt_descr; | |
221 | ||
222 | gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id()); | |
223 | gdt_descr.size = GDT_SIZE - 1; | |
224 | load_gdt(&gdt_descr); | |
fab334c1 | 225 | #ifdef CONFIG_X86_32 |
9d31d35b | 226 | asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory"); |
fab334c1 | 227 | #endif |
9d31d35b YL |
228 | } |
229 | ||
10a434fc | 230 | static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 231 | |
34048c9e | 232 | static void __cpuinit default_init(struct cpuinfo_x86 *c) |
1da177e4 | 233 | { |
b9e67f00 YL |
234 | #ifdef CONFIG_X86_64 |
235 | display_cacheinfo(c); | |
236 | #else | |
1da177e4 LT |
237 | /* Not much we can do here... */ |
238 | /* Check if at least it has cpuid */ | |
239 | if (c->cpuid_level == -1) { | |
240 | /* No cpuid. It must be an ancient CPU */ | |
241 | if (c->x86 == 4) | |
242 | strcpy(c->x86_model_id, "486"); | |
243 | else if (c->x86 == 3) | |
244 | strcpy(c->x86_model_id, "386"); | |
245 | } | |
b9e67f00 | 246 | #endif |
1da177e4 LT |
247 | } |
248 | ||
95414930 | 249 | static struct cpu_dev __cpuinitdata default_cpu = { |
1da177e4 | 250 | .c_init = default_init, |
fe38d855 | 251 | .c_vendor = "Unknown", |
10a434fc | 252 | .c_x86_vendor = X86_VENDOR_UNKNOWN, |
1da177e4 | 253 | }; |
1da177e4 | 254 | |
3bc9b76b | 255 | int __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
256 | { |
257 | unsigned int *v; | |
258 | char *p, *q; | |
259 | ||
3da99c97 | 260 | if (c->extended_cpuid_level < 0x80000004) |
1da177e4 LT |
261 | return 0; |
262 | ||
263 | v = (unsigned int *) c->x86_model_id; | |
264 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
265 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
266 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
267 | c->x86_model_id[48] = 0; | |
268 | ||
269 | /* Intel chips right-justify this string for some dumb reason; | |
270 | undo that brain damage */ | |
271 | p = q = &c->x86_model_id[0]; | |
34048c9e | 272 | while (*p == ' ') |
1da177e4 | 273 | p++; |
34048c9e PC |
274 | if (p != q) { |
275 | while (*p) | |
1da177e4 | 276 | *q++ = *p++; |
34048c9e | 277 | while (q <= &c->x86_model_id[48]) |
1da177e4 LT |
278 | *q++ = '\0'; /* Zero-pad the rest */ |
279 | } | |
280 | ||
281 | return 1; | |
282 | } | |
283 | ||
3bc9b76b | 284 | void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) |
1da177e4 | 285 | { |
9d31d35b | 286 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 287 | |
3da99c97 | 288 | n = c->extended_cpuid_level; |
1da177e4 LT |
289 | |
290 | if (n >= 0x80000005) { | |
9d31d35b | 291 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 292 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", |
9d31d35b YL |
293 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); |
294 | c->x86_cache_size = (ecx>>24) + (edx>>24); | |
140fc727 YL |
295 | #ifdef CONFIG_X86_64 |
296 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
297 | c->x86_tlbsize = 0; | |
298 | #endif | |
1da177e4 LT |
299 | } |
300 | ||
301 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
302 | return; | |
303 | ||
0a488a53 | 304 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 305 | l2size = ecx >> 16; |
34048c9e | 306 | |
140fc727 YL |
307 | #ifdef CONFIG_X86_64 |
308 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
309 | #else | |
1da177e4 LT |
310 | /* do processor-specific cache resizing */ |
311 | if (this_cpu->c_size_cache) | |
34048c9e | 312 | l2size = this_cpu->c_size_cache(c, l2size); |
1da177e4 LT |
313 | |
314 | /* Allow user to override all this if necessary. */ | |
315 | if (cachesize_override != -1) | |
316 | l2size = cachesize_override; | |
317 | ||
34048c9e | 318 | if (l2size == 0) |
1da177e4 | 319 | return; /* Again, no L2 cache is possible */ |
140fc727 | 320 | #endif |
1da177e4 LT |
321 | |
322 | c->x86_cache_size = l2size; | |
323 | ||
324 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
0a488a53 | 325 | l2size, ecx & 0xFF); |
1da177e4 LT |
326 | } |
327 | ||
9d31d35b | 328 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 329 | { |
97e4db7c | 330 | #ifdef CONFIG_X86_HT |
0a488a53 YL |
331 | u32 eax, ebx, ecx, edx; |
332 | int index_msb, core_bits; | |
1da177e4 | 333 | |
0a488a53 | 334 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 335 | return; |
1da177e4 | 336 | |
0a488a53 YL |
337 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
338 | goto out; | |
1da177e4 | 339 | |
1cd78776 YL |
340 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
341 | return; | |
342 | ||
0a488a53 | 343 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 344 | |
9d31d35b YL |
345 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
346 | ||
347 | if (smp_num_siblings == 1) { | |
348 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
349 | } else if (smp_num_siblings > 1) { | |
350 | ||
351 | if (smp_num_siblings > NR_CPUS) { | |
352 | printk(KERN_WARNING "CPU: Unsupported number of siblings %d", | |
353 | smp_num_siblings); | |
354 | smp_num_siblings = 1; | |
355 | return; | |
356 | } | |
357 | ||
358 | index_msb = get_count_order(smp_num_siblings); | |
1cd78776 YL |
359 | #ifdef CONFIG_X86_64 |
360 | c->phys_proc_id = phys_pkg_id(index_msb); | |
361 | #else | |
9d31d35b | 362 | c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb); |
1cd78776 | 363 | #endif |
9d31d35b YL |
364 | |
365 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; | |
366 | ||
367 | index_msb = get_count_order(smp_num_siblings); | |
368 | ||
369 | core_bits = get_count_order(c->x86_max_cores); | |
370 | ||
1cd78776 YL |
371 | #ifdef CONFIG_X86_64 |
372 | c->cpu_core_id = phys_pkg_id(index_msb) & | |
373 | ((1 << core_bits) - 1); | |
374 | #else | |
9d31d35b YL |
375 | c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) & |
376 | ((1 << core_bits) - 1); | |
1cd78776 | 377 | #endif |
1da177e4 | 378 | } |
1da177e4 | 379 | |
0a488a53 YL |
380 | out: |
381 | if ((c->x86_max_cores * smp_num_siblings) > 1) { | |
382 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
383 | c->phys_proc_id); | |
384 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
385 | c->cpu_core_id); | |
9d31d35b | 386 | } |
9d31d35b | 387 | #endif |
97e4db7c | 388 | } |
1da177e4 | 389 | |
3da99c97 | 390 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
391 | { |
392 | char *v = c->x86_vendor_id; | |
393 | int i; | |
fe38d855 | 394 | static int printed; |
1da177e4 LT |
395 | |
396 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
397 | if (!cpu_devs[i]) |
398 | break; | |
399 | ||
400 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
401 | (cpu_devs[i]->c_ident[1] && | |
402 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
403 | this_cpu = cpu_devs[i]; | |
404 | c->x86_vendor = this_cpu->c_x86_vendor; | |
405 | return; | |
1da177e4 LT |
406 | } |
407 | } | |
10a434fc | 408 | |
fe38d855 CE |
409 | if (!printed) { |
410 | printed++; | |
411 | printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n"); | |
412 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); | |
413 | } | |
10a434fc | 414 | |
fe38d855 CE |
415 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
416 | this_cpu = &default_cpu; | |
1da177e4 LT |
417 | } |
418 | ||
9d31d35b | 419 | void __cpuinit cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 420 | { |
1da177e4 | 421 | /* Get vendor name */ |
4a148513 HH |
422 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
423 | (unsigned int *)&c->x86_vendor_id[0], | |
424 | (unsigned int *)&c->x86_vendor_id[8], | |
425 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 426 | |
1da177e4 | 427 | c->x86 = 4; |
9d31d35b | 428 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
429 | if (c->cpuid_level >= 0x00000001) { |
430 | u32 junk, tfms, cap0, misc; | |
431 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
9d31d35b YL |
432 | c->x86 = (tfms >> 8) & 0xf; |
433 | c->x86_model = (tfms >> 4) & 0xf; | |
434 | c->x86_mask = tfms & 0xf; | |
f5f786d0 | 435 | if (c->x86 == 0xf) |
1da177e4 | 436 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 437 | if (c->x86 >= 0x6) |
9d31d35b | 438 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
d4387bd3 | 439 | if (cap0 & (1<<19)) { |
d4387bd3 | 440 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 441 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 442 | } |
1da177e4 | 443 | } |
1da177e4 | 444 | } |
3da99c97 YL |
445 | |
446 | static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) | |
093af8d7 YL |
447 | { |
448 | u32 tfms, xlvl; | |
3da99c97 | 449 | u32 ebx; |
093af8d7 | 450 | |
3da99c97 YL |
451 | /* Intel-defined flags: level 0x00000001 */ |
452 | if (c->cpuid_level >= 0x00000001) { | |
453 | u32 capability, excap; | |
454 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); | |
455 | c->x86_capability[0] = capability; | |
456 | c->x86_capability[4] = excap; | |
457 | } | |
093af8d7 | 458 | |
3da99c97 YL |
459 | /* AMD-defined flags: level 0x80000001 */ |
460 | xlvl = cpuid_eax(0x80000000); | |
461 | c->extended_cpuid_level = xlvl; | |
462 | if ((xlvl & 0xffff0000) == 0x80000000) { | |
463 | if (xlvl >= 0x80000001) { | |
464 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
465 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 466 | } |
093af8d7 | 467 | } |
5122c890 YL |
468 | |
469 | #ifdef CONFIG_X86_64 | |
470 | /* Transmeta-defined flags: level 0x80860001 */ | |
471 | xlvl = cpuid_eax(0x80860000); | |
472 | if ((xlvl & 0xffff0000) == 0x80860000) { | |
473 | /* Don't set x86_cpuid_level here for now to not confuse. */ | |
474 | if (xlvl >= 0x80860001) | |
475 | c->x86_capability[2] = cpuid_edx(0x80860001); | |
476 | } | |
477 | ||
478 | if (c->extended_cpuid_level >= 0x80000007) | |
479 | c->x86_power = cpuid_edx(0x80000007); | |
480 | ||
481 | if (c->extended_cpuid_level >= 0x80000008) { | |
482 | u32 eax = cpuid_eax(0x80000008); | |
483 | ||
484 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
485 | c->x86_phys_bits = eax & 0xff; | |
486 | } | |
487 | #endif | |
093af8d7 | 488 | } |
34048c9e PC |
489 | /* |
490 | * Do minimum CPU detection early. | |
491 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
492 | * cache alignment. | |
493 | * The others are not touched to avoid unwanted side effects. | |
494 | * | |
495 | * WARNING: this function is only called on the BP. Don't add code here | |
496 | * that is supposed to run on all CPUs. | |
497 | */ | |
3da99c97 | 498 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 499 | { |
6627d242 YL |
500 | #ifdef CONFIG_X86_64 |
501 | c->x86_clflush_size = 64; | |
502 | #else | |
d4387bd3 | 503 | c->x86_clflush_size = 32; |
6627d242 | 504 | #endif |
0a488a53 | 505 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 RR |
506 | |
507 | if (!have_cpuid_p()) | |
508 | return; | |
509 | ||
3da99c97 YL |
510 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
511 | ||
0a488a53 YL |
512 | c->extended_cpuid_level = 0; |
513 | ||
d7cd5611 RR |
514 | cpu_detect(c); |
515 | ||
3da99c97 | 516 | get_cpu_vendor(c); |
2b16a235 | 517 | |
3da99c97 | 518 | get_cpu_cap(c); |
2b16a235 | 519 | |
10a434fc YL |
520 | if (this_cpu->c_early_init) |
521 | this_cpu->c_early_init(c); | |
093af8d7 | 522 | |
3da99c97 | 523 | validate_pat_support(c); |
d7cd5611 RR |
524 | } |
525 | ||
9d31d35b YL |
526 | void __init early_cpu_init(void) |
527 | { | |
10a434fc YL |
528 | struct cpu_dev **cdev; |
529 | int count = 0; | |
530 | ||
531 | printk("KERNEL supported cpus:\n"); | |
532 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { | |
533 | struct cpu_dev *cpudev = *cdev; | |
534 | unsigned int j; | |
9d31d35b | 535 | |
10a434fc YL |
536 | if (count >= X86_VENDOR_NUM) |
537 | break; | |
538 | cpu_devs[count] = cpudev; | |
539 | count++; | |
540 | ||
541 | for (j = 0; j < 2; j++) { | |
542 | if (!cpudev->c_ident[j]) | |
543 | continue; | |
544 | printk(" %s %s\n", cpudev->c_vendor, | |
545 | cpudev->c_ident[j]); | |
546 | } | |
547 | } | |
9d31d35b | 548 | |
9d31d35b | 549 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 RR |
550 | } |
551 | ||
7e00df58 PA |
552 | /* |
553 | * The NOPL instruction is supposed to exist on all CPUs with | |
554 | * family >= 6, unfortunately, that's not true in practice because | |
555 | * of early VIA chips and (more importantly) broken virtualizers that | |
556 | * are not easy to detect. Hence, probe for it based on first | |
557 | * principles. | |
b89d3b3e YL |
558 | * |
559 | * Note: no 64-bit chip is known to lack these, but put the code here | |
560 | * for consistency with 32 bits, and to make it utterly trivial to | |
561 | * diagnose the problem should it ever surface. | |
7e00df58 PA |
562 | */ |
563 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
564 | { | |
565 | const u32 nopl_signature = 0x888c53b1; /* Random number */ | |
566 | u32 has_nopl = nopl_signature; | |
567 | ||
568 | clear_cpu_cap(c, X86_FEATURE_NOPL); | |
569 | if (c->x86 >= 6) { | |
570 | asm volatile("\n" | |
571 | "1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */ | |
572 | "2:\n" | |
573 | " .section .fixup,\"ax\"\n" | |
574 | "3: xor %0,%0\n" | |
575 | " jmp 2b\n" | |
576 | " .previous\n" | |
577 | _ASM_EXTABLE(1b,3b) | |
578 | : "+a" (has_nopl)); | |
579 | ||
580 | if (has_nopl == nopl_signature) | |
581 | set_cpu_cap(c, X86_FEATURE_NOPL); | |
582 | } | |
583 | } | |
584 | ||
34048c9e | 585 | static void __cpuinit generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 586 | { |
3da99c97 YL |
587 | if (!have_cpuid_p()) |
588 | return; | |
1da177e4 | 589 | |
3da99c97 | 590 | c->extended_cpuid_level = 0; |
1d67953f | 591 | |
3da99c97 | 592 | cpu_detect(c); |
1da177e4 | 593 | |
3da99c97 | 594 | get_cpu_vendor(c); |
1da177e4 | 595 | |
3da99c97 | 596 | get_cpu_cap(c); |
1da177e4 | 597 | |
3da99c97 YL |
598 | if (c->cpuid_level >= 0x00000001) { |
599 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e YL |
600 | #ifdef CONFIG_X86_32 |
601 | # ifdef CONFIG_X86_HT | |
3da99c97 | 602 | c->apicid = phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 603 | # else |
3da99c97 | 604 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
605 | # endif |
606 | #endif | |
607 | ||
608 | #ifdef CONFIG_X86_HT | |
609 | c->phys_proc_id = c->initial_apicid; | |
1e9f28fa | 610 | #endif |
3da99c97 | 611 | } |
1da177e4 | 612 | |
3da99c97 YL |
613 | if (c->extended_cpuid_level >= 0x80000004) |
614 | get_model_name(c); /* Default name */ | |
1da177e4 | 615 | |
3da99c97 YL |
616 | init_scattered_cpuid_features(c); |
617 | detect_nopl(c); | |
1da177e4 | 618 | } |
1da177e4 LT |
619 | |
620 | /* | |
621 | * This does the hard work of actually picking apart the CPU stuff... | |
622 | */ | |
9a250347 | 623 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
624 | { |
625 | int i; | |
626 | ||
627 | c->loops_per_jiffy = loops_per_jiffy; | |
628 | c->x86_cache_size = -1; | |
629 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
630 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
631 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
632 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 633 | c->x86_max_cores = 1; |
102bbe3a YL |
634 | #ifdef CONFIG_X86_64 |
635 | c->x86_coreid_bits = 0; | |
636 | c->x86_clflush_size = 64; | |
637 | #else | |
638 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 639 | c->x86_clflush_size = 32; |
102bbe3a YL |
640 | #endif |
641 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
642 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
643 | ||
644 | if (!have_cpuid_p()) { | |
34048c9e PC |
645 | /* |
646 | * First of all, decide if this is a 486 or higher | |
647 | * It's a 486 if we can modify the AC flag | |
648 | */ | |
649 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
1da177e4 LT |
650 | c->x86 = 4; |
651 | else | |
652 | c->x86 = 3; | |
653 | } | |
654 | ||
655 | generic_identify(c); | |
656 | ||
3898534d | 657 | if (this_cpu->c_identify) |
1da177e4 LT |
658 | this_cpu->c_identify(c); |
659 | ||
102bbe3a YL |
660 | #ifdef CONFIG_X86_64 |
661 | c->apicid = phys_pkg_id(0); | |
662 | #endif | |
663 | ||
1da177e4 LT |
664 | /* |
665 | * Vendor-specific initialization. In this section we | |
666 | * canonicalize the feature flags, meaning if there are | |
667 | * features a certain CPU supports which CPUID doesn't | |
668 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
669 | * we handle them here. | |
670 | * | |
671 | * At the end of this section, c->x86_capability better | |
672 | * indicate the features this CPU genuinely supports! | |
673 | */ | |
674 | if (this_cpu->c_init) | |
675 | this_cpu->c_init(c); | |
676 | ||
677 | /* Disable the PN if appropriate */ | |
678 | squash_the_stupid_serial_number(c); | |
679 | ||
680 | /* | |
681 | * The vendor-specific functions might have changed features. Now | |
682 | * we do "generic changes." | |
683 | */ | |
684 | ||
1da177e4 | 685 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 686 | if (!c->x86_model_id[0]) { |
1da177e4 LT |
687 | char *p; |
688 | p = table_lookup_model(c); | |
34048c9e | 689 | if (p) |
1da177e4 LT |
690 | strcpy(c->x86_model_id, p); |
691 | else | |
692 | /* Last resort... */ | |
693 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 694 | c->x86, c->x86_model); |
1da177e4 LT |
695 | } |
696 | ||
102bbe3a YL |
697 | #ifdef CONFIG_X86_64 |
698 | detect_ht(c); | |
699 | #endif | |
700 | ||
1da177e4 LT |
701 | /* |
702 | * On SMP, boot_cpu_data holds the common feature set between | |
703 | * all CPUs; so make sure that we indicate which features are | |
704 | * common between the CPUs. The first time this routine gets | |
705 | * executed, c == &boot_cpu_data. | |
706 | */ | |
34048c9e | 707 | if (c != &boot_cpu_data) { |
1da177e4 | 708 | /* AND the already accumulated flags with these */ |
9d31d35b | 709 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 LT |
710 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
711 | } | |
712 | ||
7d851c8d AK |
713 | /* Clear all flags overriden by options */ |
714 | for (i = 0; i < NCAPINTS; i++) | |
12c247a6 | 715 | c->x86_capability[i] &= ~cleared_cpu_caps[i]; |
7d851c8d | 716 | |
102bbe3a | 717 | #ifdef CONFIG_X86_MCE |
1da177e4 | 718 | /* Init Machine Check Exception if available. */ |
1da177e4 | 719 | mcheck_init(c); |
102bbe3a | 720 | #endif |
30d432df AK |
721 | |
722 | select_idle_routine(c); | |
102bbe3a YL |
723 | |
724 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) | |
725 | numa_add_cpu(smp_processor_id()); | |
726 | #endif | |
a6c4e076 | 727 | } |
31ab269a | 728 | |
a6c4e076 JF |
729 | void __init identify_boot_cpu(void) |
730 | { | |
731 | identify_cpu(&boot_cpu_data); | |
102bbe3a | 732 | #ifdef CONFIG_X86_32 |
a6c4e076 | 733 | sysenter_setup(); |
6fe940d6 | 734 | enable_sep_cpu(); |
102bbe3a | 735 | #endif |
a6c4e076 | 736 | } |
3b520b23 | 737 | |
a6c4e076 JF |
738 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) |
739 | { | |
740 | BUG_ON(c == &boot_cpu_data); | |
741 | identify_cpu(c); | |
102bbe3a | 742 | #ifdef CONFIG_X86_32 |
a6c4e076 | 743 | enable_sep_cpu(); |
102bbe3a | 744 | #endif |
a6c4e076 | 745 | mtrr_ap_init(); |
1da177e4 LT |
746 | } |
747 | ||
a0854a46 YL |
748 | struct msr_range { |
749 | unsigned min; | |
750 | unsigned max; | |
751 | }; | |
1da177e4 | 752 | |
a0854a46 YL |
753 | static struct msr_range msr_range_array[] __cpuinitdata = { |
754 | { 0x00000000, 0x00000418}, | |
755 | { 0xc0000000, 0xc000040b}, | |
756 | { 0xc0010000, 0xc0010142}, | |
757 | { 0xc0011000, 0xc001103b}, | |
758 | }; | |
1da177e4 | 759 | |
a0854a46 YL |
760 | static void __cpuinit print_cpu_msr(void) |
761 | { | |
762 | unsigned index; | |
763 | u64 val; | |
764 | int i; | |
765 | unsigned index_min, index_max; | |
766 | ||
767 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
768 | index_min = msr_range_array[i].min; | |
769 | index_max = msr_range_array[i].max; | |
770 | for (index = index_min; index < index_max; index++) { | |
771 | if (rdmsrl_amd_safe(index, &val)) | |
772 | continue; | |
773 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1da177e4 | 774 | } |
a0854a46 YL |
775 | } |
776 | } | |
94605eff | 777 | |
a0854a46 YL |
778 | static int show_msr __cpuinitdata; |
779 | static __init int setup_show_msr(char *arg) | |
780 | { | |
781 | int num; | |
3dd9d514 | 782 | |
a0854a46 | 783 | get_option(&arg, &num); |
3dd9d514 | 784 | |
a0854a46 YL |
785 | if (num > 0) |
786 | show_msr = num; | |
787 | return 1; | |
1da177e4 | 788 | } |
a0854a46 | 789 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 790 | |
191679fd AK |
791 | static __init int setup_noclflush(char *arg) |
792 | { | |
793 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
794 | return 1; | |
795 | } | |
796 | __setup("noclflush", setup_noclflush); | |
797 | ||
3bc9b76b | 798 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 LT |
799 | { |
800 | char *vendor = NULL; | |
801 | ||
802 | if (c->x86_vendor < X86_VENDOR_NUM) | |
803 | vendor = this_cpu->c_vendor; | |
804 | else if (c->cpuid_level >= 0) | |
805 | vendor = c->x86_vendor_id; | |
806 | ||
807 | if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor))) | |
9d31d35b | 808 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 809 | |
9d31d35b YL |
810 | if (c->x86_model_id[0]) |
811 | printk(KERN_CONT "%s", c->x86_model_id); | |
1da177e4 | 812 | else |
9d31d35b | 813 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 814 | |
34048c9e | 815 | if (c->x86_mask || c->cpuid_level >= 0) |
9d31d35b | 816 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); |
1da177e4 | 817 | else |
9d31d35b | 818 | printk(KERN_CONT "\n"); |
a0854a46 YL |
819 | |
820 | #ifdef CONFIG_SMP | |
821 | if (c->cpu_index < show_msr) | |
822 | print_cpu_msr(); | |
823 | #else | |
824 | if (show_msr) | |
825 | print_cpu_msr(); | |
826 | #endif | |
1da177e4 LT |
827 | } |
828 | ||
ac72e788 AK |
829 | static __init int setup_disablecpuid(char *arg) |
830 | { | |
831 | int bit; | |
832 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) | |
833 | setup_clear_cpu_cap(bit); | |
834 | else | |
835 | return 0; | |
836 | return 1; | |
837 | } | |
838 | __setup("clearcpuid=", setup_disablecpuid); | |
839 | ||
3bc9b76b | 840 | cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE; |
1da177e4 | 841 | |
d5494d4f YL |
842 | #ifdef CONFIG_X86_64 |
843 | struct x8664_pda **_cpu_pda __read_mostly; | |
844 | EXPORT_SYMBOL(_cpu_pda); | |
845 | ||
846 | struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; | |
847 | ||
848 | char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss; | |
849 | ||
d5494d4f YL |
850 | void pda_init(int cpu) |
851 | { | |
852 | struct x8664_pda *pda = cpu_pda(cpu); | |
853 | ||
854 | /* Setup up data that may be needed in __get_free_pages early */ | |
855 | loadsegment(fs, 0); | |
856 | loadsegment(gs, 0); | |
857 | /* Memory clobbers used to order PDA accessed */ | |
858 | mb(); | |
859 | wrmsrl(MSR_GS_BASE, pda); | |
860 | mb(); | |
861 | ||
862 | pda->cpunumber = cpu; | |
863 | pda->irqcount = -1; | |
864 | pda->kernelstack = (unsigned long)stack_thread_info() - | |
865 | PDA_STACKOFFSET + THREAD_SIZE; | |
866 | pda->active_mm = &init_mm; | |
867 | pda->mmu_state = 0; | |
868 | ||
869 | if (cpu == 0) { | |
870 | /* others are initialized in smpboot.c */ | |
871 | pda->pcurrent = &init_task; | |
872 | pda->irqstackptr = boot_cpu_stack; | |
873 | pda->irqstackptr += IRQSTACKSIZE - 64; | |
874 | } else { | |
875 | if (!pda->irqstackptr) { | |
876 | pda->irqstackptr = (char *) | |
877 | __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER); | |
878 | if (!pda->irqstackptr) | |
879 | panic("cannot allocate irqstack for cpu %d", | |
880 | cpu); | |
881 | pda->irqstackptr += IRQSTACKSIZE - 64; | |
882 | } | |
883 | ||
884 | if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE) | |
885 | pda->nodenumber = cpu_to_node(cpu); | |
886 | } | |
887 | } | |
888 | ||
889 | char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + | |
890 | DEBUG_STKSZ] __page_aligned_bss; | |
891 | ||
892 | extern asmlinkage void ignore_sysret(void); | |
893 | ||
894 | /* May not be marked __init: used by software suspend */ | |
895 | void syscall_init(void) | |
896 | { | |
897 | /* | |
898 | * LSTAR and STAR live in a bit strange symbiosis. | |
899 | * They both write to the same internal register. STAR allows to | |
900 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
901 | */ | |
902 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
903 | wrmsrl(MSR_LSTAR, system_call); | |
904 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
905 | ||
906 | #ifdef CONFIG_IA32_EMULATION | |
907 | syscall32_cpu_init(); | |
908 | #endif | |
909 | ||
910 | /* Flags to clear on syscall */ | |
911 | wrmsrl(MSR_SYSCALL_MASK, | |
912 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); | |
913 | } | |
914 | ||
d5494d4f YL |
915 | unsigned long kernel_eflags; |
916 | ||
917 | /* | |
918 | * Copies of the original ist values from the tss are only accessed during | |
919 | * debugging, no special alignment required. | |
920 | */ | |
921 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
922 | ||
923 | #else | |
924 | ||
7c3576d2 | 925 | /* Make sure %fs is initialized properly in idle threads */ |
6b2fb3c6 | 926 | struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) |
f95d47ca JF |
927 | { |
928 | memset(regs, 0, sizeof(struct pt_regs)); | |
65ea5b03 | 929 | regs->fs = __KERNEL_PERCPU; |
f95d47ca JF |
930 | return regs; |
931 | } | |
d5494d4f | 932 | #endif |
f95d47ca | 933 | |
d2cbcc49 RR |
934 | /* |
935 | * cpu_init() initializes state that is per-CPU. Some data is already | |
936 | * initialized (naturally) in the bootstrap process, such as the GDT | |
937 | * and IDT. We reload them nevertheless, this function acts as a | |
938 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 939 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 940 | */ |
1ba76586 YL |
941 | #ifdef CONFIG_X86_64 |
942 | void __cpuinit cpu_init(void) | |
943 | { | |
944 | int cpu = stack_smp_processor_id(); | |
945 | struct tss_struct *t = &per_cpu(init_tss, cpu); | |
946 | struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu); | |
947 | unsigned long v; | |
948 | char *estacks = NULL; | |
949 | struct task_struct *me; | |
950 | int i; | |
951 | ||
952 | /* CPU 0 is initialised in head64.c */ | |
953 | if (cpu != 0) | |
954 | pda_init(cpu); | |
955 | else | |
956 | estacks = boot_exception_stacks; | |
957 | ||
958 | me = current; | |
959 | ||
960 | if (cpu_test_and_set(cpu, cpu_initialized)) | |
961 | panic("CPU#%d already initialized!\n", cpu); | |
962 | ||
963 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
964 | ||
965 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
966 | ||
967 | /* | |
968 | * Initialize the per-CPU GDT with the boot GDT, | |
969 | * and set up the GDT descriptor: | |
970 | */ | |
971 | ||
972 | switch_to_new_gdt(); | |
973 | load_idt((const struct desc_ptr *)&idt_descr); | |
974 | ||
975 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
976 | syscall_init(); | |
977 | ||
978 | wrmsrl(MSR_FS_BASE, 0); | |
979 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
980 | barrier(); | |
981 | ||
982 | check_efer(); | |
983 | if (cpu != 0 && x2apic) | |
984 | enable_x2apic(); | |
985 | ||
986 | /* | |
987 | * set up and load the per-CPU TSS | |
988 | */ | |
989 | if (!orig_ist->ist[0]) { | |
990 | static const unsigned int order[N_EXCEPTION_STACKS] = { | |
991 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER, | |
992 | [DEBUG_STACK - 1] = DEBUG_STACK_ORDER | |
993 | }; | |
994 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { | |
995 | if (cpu) { | |
996 | estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]); | |
997 | if (!estacks) | |
998 | panic("Cannot allocate exception " | |
999 | "stack %ld %d\n", v, cpu); | |
1000 | } | |
1001 | estacks += PAGE_SIZE << order[v]; | |
1002 | orig_ist->ist[v] = t->x86_tss.ist[v] = | |
1003 | (unsigned long)estacks; | |
1004 | } | |
1005 | } | |
1006 | ||
1007 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
1008 | /* | |
1009 | * <= is required because the CPU will access up to | |
1010 | * 8 bits beyond the end of the IO permission bitmap. | |
1011 | */ | |
1012 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1013 | t->io_bitmap[i] = ~0UL; | |
1014 | ||
1015 | atomic_inc(&init_mm.mm_count); | |
1016 | me->active_mm = &init_mm; | |
1017 | if (me->mm) | |
1018 | BUG(); | |
1019 | enter_lazy_tlb(&init_mm, me); | |
1020 | ||
1021 | load_sp0(t, ¤t->thread); | |
1022 | set_tss_desc(cpu, t); | |
1023 | load_TR_desc(); | |
1024 | load_LDT(&init_mm.context); | |
1025 | ||
1026 | #ifdef CONFIG_KGDB | |
1027 | /* | |
1028 | * If the kgdb is connected no debug regs should be altered. This | |
1029 | * is only applicable when KGDB and a KGDB I/O module are built | |
1030 | * into the kernel and you are using early debugging with | |
1031 | * kgdbwait. KGDB will control the kernel HW breakpoint registers. | |
1032 | */ | |
1033 | if (kgdb_connected && arch_kgdb_ops.correct_hw_break) | |
1034 | arch_kgdb_ops.correct_hw_break(); | |
1035 | else { | |
1036 | #endif | |
1037 | /* | |
1038 | * Clear all 6 debug registers: | |
1039 | */ | |
1040 | ||
1041 | set_debugreg(0UL, 0); | |
1042 | set_debugreg(0UL, 1); | |
1043 | set_debugreg(0UL, 2); | |
1044 | set_debugreg(0UL, 3); | |
1045 | set_debugreg(0UL, 6); | |
1046 | set_debugreg(0UL, 7); | |
1047 | #ifdef CONFIG_KGDB | |
1048 | /* If the kgdb is connected no debug regs should be altered. */ | |
1049 | } | |
1050 | #endif | |
1051 | ||
1052 | fpu_init(); | |
1053 | ||
1054 | raw_local_save_flags(kernel_eflags); | |
1055 | ||
1056 | if (is_uv_system()) | |
1057 | uv_cpu_init(); | |
1058 | } | |
1059 | ||
1060 | #else | |
1061 | ||
d2cbcc49 | 1062 | void __cpuinit cpu_init(void) |
9ee79a3d | 1063 | { |
d2cbcc49 RR |
1064 | int cpu = smp_processor_id(); |
1065 | struct task_struct *curr = current; | |
34048c9e | 1066 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 1067 | struct thread_struct *thread = &curr->thread; |
62111195 JF |
1068 | |
1069 | if (cpu_test_and_set(cpu, cpu_initialized)) { | |
1070 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); | |
1071 | for (;;) local_irq_enable(); | |
1072 | } | |
1073 | ||
1074 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1075 | ||
1076 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
1077 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 1078 | |
4d37e7e3 | 1079 | load_idt(&idt_descr); |
c5413fbe | 1080 | switch_to_new_gdt(); |
1da177e4 | 1081 | |
1da177e4 LT |
1082 | /* |
1083 | * Set up and load the per-CPU TSS and LDT | |
1084 | */ | |
1085 | atomic_inc(&init_mm.mm_count); | |
62111195 JF |
1086 | curr->active_mm = &init_mm; |
1087 | if (curr->mm) | |
1088 | BUG(); | |
1089 | enter_lazy_tlb(&init_mm, curr); | |
1da177e4 | 1090 | |
faca6227 | 1091 | load_sp0(t, thread); |
34048c9e | 1092 | set_tss_desc(cpu, t); |
1da177e4 LT |
1093 | load_TR_desc(); |
1094 | load_LDT(&init_mm.context); | |
1095 | ||
22c4e308 | 1096 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1097 | /* Set up doublefault TSS pointer in the GDT */ |
1098 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1099 | #endif |
1da177e4 | 1100 | |
464d1a78 JF |
1101 | /* Clear %gs. */ |
1102 | asm volatile ("mov %0, %%gs" : : "r" (0)); | |
1da177e4 LT |
1103 | |
1104 | /* Clear all 6 debug registers: */ | |
4bb0d3ec ZA |
1105 | set_debugreg(0, 0); |
1106 | set_debugreg(0, 1); | |
1107 | set_debugreg(0, 2); | |
1108 | set_debugreg(0, 3); | |
1109 | set_debugreg(0, 6); | |
1110 | set_debugreg(0, 7); | |
1da177e4 LT |
1111 | |
1112 | /* | |
1113 | * Force FPU initialization: | |
1114 | */ | |
b359e8a4 SS |
1115 | if (cpu_has_xsave) |
1116 | current_thread_info()->status = TS_XSAVE; | |
1117 | else | |
1118 | current_thread_info()->status = 0; | |
1da177e4 LT |
1119 | clear_used_math(); |
1120 | mxcsr_feature_mask_init(); | |
dc1e35c6 SS |
1121 | |
1122 | /* | |
1123 | * Boot processor to setup the FP and extended state context info. | |
1124 | */ | |
1125 | if (!smp_processor_id()) | |
1126 | init_thread_xstate(); | |
1127 | ||
1128 | xsave_init(); | |
1da177e4 | 1129 | } |
e1367daf LS |
1130 | |
1131 | #ifdef CONFIG_HOTPLUG_CPU | |
3bc9b76b | 1132 | void __cpuinit cpu_uninit(void) |
e1367daf LS |
1133 | { |
1134 | int cpu = raw_smp_processor_id(); | |
1135 | cpu_clear(cpu, cpu_initialized); | |
1136 | ||
1137 | /* lazy TLB state */ | |
1138 | per_cpu(cpu_tlbstate, cpu).state = 0; | |
1139 | per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm; | |
1140 | } | |
1141 | #endif | |
1ba76586 YL |
1142 | |
1143 | #endif |