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1da177e4 | 1 | #include <linux/init.h> |
f0fc4aff YL |
2 | #include <linux/kernel.h> |
3 | #include <linux/sched.h> | |
1da177e4 | 4 | #include <linux/string.h> |
f0fc4aff YL |
5 | #include <linux/bootmem.h> |
6 | #include <linux/bitops.h> | |
7 | #include <linux/module.h> | |
8 | #include <linux/kgdb.h> | |
9 | #include <linux/topology.h> | |
1da177e4 LT |
10 | #include <linux/delay.h> |
11 | #include <linux/smp.h> | |
1da177e4 | 12 | #include <linux/percpu.h> |
1da177e4 LT |
13 | #include <asm/i387.h> |
14 | #include <asm/msr.h> | |
15 | #include <asm/io.h> | |
f0fc4aff | 16 | #include <asm/linkage.h> |
1da177e4 | 17 | #include <asm/mmu_context.h> |
27b07da7 | 18 | #include <asm/mtrr.h> |
a03a3e28 | 19 | #include <asm/mce.h> |
5c167b85 | 20 | #include <asm/perf_counter.h> |
8d4a4300 | 21 | #include <asm/pat.h> |
b6734c35 | 22 | #include <asm/asm.h> |
f0fc4aff | 23 | #include <asm/numa.h> |
b342797c | 24 | #include <asm/smp.h> |
f472cdba | 25 | #include <asm/cpu.h> |
06879033 | 26 | #include <asm/cpumask.h> |
1da177e4 | 27 | #include <asm/apic.h> |
e641f5f5 IM |
28 | |
29 | #ifdef CONFIG_X86_LOCAL_APIC | |
bdbcdd48 | 30 | #include <asm/uv/uv.h> |
1da177e4 LT |
31 | #endif |
32 | ||
f0fc4aff YL |
33 | #include <asm/pgtable.h> |
34 | #include <asm/processor.h> | |
35 | #include <asm/desc.h> | |
36 | #include <asm/atomic.h> | |
37 | #include <asm/proto.h> | |
38 | #include <asm/sections.h> | |
39 | #include <asm/setup.h> | |
88b094fb | 40 | #include <asm/hypervisor.h> |
60a5317f | 41 | #include <asm/stackprotector.h> |
f0fc4aff | 42 | |
1da177e4 LT |
43 | #include "cpu.h" |
44 | ||
c2d1cec1 MT |
45 | #ifdef CONFIG_X86_64 |
46 | ||
47 | /* all of these masks are initialized in setup_cpu_local_masks() */ | |
48 | cpumask_var_t cpu_callin_mask; | |
49 | cpumask_var_t cpu_callout_mask; | |
50 | cpumask_var_t cpu_initialized_mask; | |
51 | ||
52 | /* representing cpus for which sibling maps can be computed */ | |
53 | cpumask_var_t cpu_sibling_setup_mask; | |
54 | ||
2f2f52ba | 55 | /* correctly size the local cpu masks */ |
4369f1fb | 56 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
57 | { |
58 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
59 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
60 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
61 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
62 | } | |
63 | ||
c2d1cec1 MT |
64 | #else /* CONFIG_X86_32 */ |
65 | ||
66 | cpumask_t cpu_callin_map; | |
67 | cpumask_t cpu_callout_map; | |
68 | cpumask_t cpu_initialized; | |
69 | cpumask_t cpu_sibling_setup_map; | |
70 | ||
71 | #endif /* CONFIG_X86_32 */ | |
72 | ||
73 | ||
0a488a53 YL |
74 | static struct cpu_dev *this_cpu __cpuinitdata; |
75 | ||
06deef89 | 76 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 77 | #ifdef CONFIG_X86_64 |
06deef89 BG |
78 | /* |
79 | * We need valid kernel segments for data and code in long mode too | |
80 | * IRET will check the segment types kkeil 2000/10/28 | |
81 | * Also sysret mandates a special GDT layout | |
82 | * | |
83 | * The TLS descriptors are currently at a different place compared to i386. | |
84 | * Hopefully nobody expects them at a fixed place (Wine?) | |
85 | */ | |
950ad7ff YL |
86 | [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } }, |
87 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } }, | |
88 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } }, | |
89 | [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } }, | |
90 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } }, | |
91 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } }, | |
950ad7ff | 92 | #else |
6842ef0e GOC |
93 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, |
94 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, | |
95 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, | |
96 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, | |
bf504672 RR |
97 | /* |
98 | * Segments used for calling PnP BIOS have byte granularity. | |
99 | * They code segments and data segments have fixed 64k limits, | |
100 | * the transfer segment sizes are set at run time. | |
101 | */ | |
6842ef0e GOC |
102 | /* 32-bit code */ |
103 | [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, | |
104 | /* 16-bit code */ | |
105 | [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, | |
106 | /* 16-bit data */ | |
107 | [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, | |
108 | /* 16-bit data */ | |
109 | [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, | |
110 | /* 16-bit data */ | |
111 | [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, | |
bf504672 RR |
112 | /* |
113 | * The APM segments have byte granularity and their bases | |
114 | * are set at run time. All have 64k limits. | |
115 | */ | |
6842ef0e GOC |
116 | /* 32-bit code */ |
117 | [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, | |
bf504672 | 118 | /* 16-bit code */ |
6842ef0e GOC |
119 | [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, |
120 | /* data */ | |
121 | [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, | |
bf504672 | 122 | |
6842ef0e | 123 | [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, |
0dd76d73 | 124 | [GDT_ENTRY_PERCPU] = { { { 0x0000ffff, 0x00cf9200 } } }, |
60a5317f | 125 | GDT_STACK_CANARY_INIT |
950ad7ff | 126 | #endif |
06deef89 | 127 | } }; |
7a61d35d | 128 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 129 | |
ba51dced | 130 | #ifdef CONFIG_X86_32 |
3bc9b76b | 131 | static int cachesize_override __cpuinitdata = -1; |
3bc9b76b | 132 | static int disable_x86_serial_nr __cpuinitdata = 1; |
1da177e4 | 133 | |
0a488a53 YL |
134 | static int __init cachesize_setup(char *str) |
135 | { | |
136 | get_option(&str, &cachesize_override); | |
137 | return 1; | |
138 | } | |
139 | __setup("cachesize=", cachesize_setup); | |
140 | ||
0a488a53 YL |
141 | static int __init x86_fxsr_setup(char *s) |
142 | { | |
143 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
144 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
145 | return 1; | |
146 | } | |
147 | __setup("nofxsr", x86_fxsr_setup); | |
148 | ||
149 | static int __init x86_sep_setup(char *s) | |
150 | { | |
151 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
152 | return 1; | |
153 | } | |
154 | __setup("nosep", x86_sep_setup); | |
155 | ||
156 | /* Standard macro to see if a specific flag is changeable */ | |
157 | static inline int flag_is_changeable_p(u32 flag) | |
158 | { | |
159 | u32 f1, f2; | |
160 | ||
94f6bac1 KH |
161 | /* |
162 | * Cyrix and IDT cpus allow disabling of CPUID | |
163 | * so the code below may return different results | |
164 | * when it is executed before and after enabling | |
165 | * the CPUID. Add "volatile" to not allow gcc to | |
166 | * optimize the subsequent calls to this function. | |
167 | */ | |
168 | asm volatile ("pushfl\n\t" | |
169 | "pushfl\n\t" | |
170 | "popl %0\n\t" | |
171 | "movl %0,%1\n\t" | |
172 | "xorl %2,%0\n\t" | |
173 | "pushl %0\n\t" | |
174 | "popfl\n\t" | |
175 | "pushfl\n\t" | |
176 | "popl %0\n\t" | |
177 | "popfl\n\t" | |
178 | : "=&r" (f1), "=&r" (f2) | |
179 | : "ir" (flag)); | |
0a488a53 YL |
180 | |
181 | return ((f1^f2) & flag) != 0; | |
182 | } | |
183 | ||
184 | /* Probe for the CPUID instruction */ | |
185 | static int __cpuinit have_cpuid_p(void) | |
186 | { | |
187 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
188 | } | |
189 | ||
190 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
191 | { | |
192 | if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) { | |
193 | /* Disable processor serial number */ | |
194 | unsigned long lo, hi; | |
195 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
196 | lo |= 0x200000; | |
197 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
198 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
199 | clear_cpu_cap(c, X86_FEATURE_PN); | |
200 | ||
201 | /* Disabling the serial number may affect the cpuid level */ | |
202 | c->cpuid_level = cpuid_eax(0); | |
203 | } | |
204 | } | |
205 | ||
206 | static int __init x86_serial_nr_setup(char *s) | |
207 | { | |
208 | disable_x86_serial_nr = 0; | |
209 | return 1; | |
210 | } | |
211 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 212 | #else |
102bbe3a YL |
213 | static inline int flag_is_changeable_p(u32 flag) |
214 | { | |
215 | return 1; | |
216 | } | |
ba51dced YL |
217 | /* Probe for the CPUID instruction */ |
218 | static inline int have_cpuid_p(void) | |
219 | { | |
220 | return 1; | |
221 | } | |
102bbe3a YL |
222 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
223 | { | |
224 | } | |
ba51dced | 225 | #endif |
0a488a53 | 226 | |
b38b0665 PA |
227 | /* |
228 | * Some CPU features depend on higher CPUID levels, which may not always | |
229 | * be available due to CPUID level capping or broken virtualization | |
230 | * software. Add those features to this table to auto-disable them. | |
231 | */ | |
232 | struct cpuid_dependent_feature { | |
233 | u32 feature; | |
234 | u32 level; | |
235 | }; | |
236 | static const struct cpuid_dependent_feature __cpuinitconst | |
237 | cpuid_dependent_features[] = { | |
238 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
239 | { X86_FEATURE_DCA, 0x00000009 }, | |
240 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
241 | { 0, 0 } | |
242 | }; | |
243 | ||
244 | static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) | |
245 | { | |
246 | const struct cpuid_dependent_feature *df; | |
247 | for (df = cpuid_dependent_features; df->feature; df++) { | |
248 | /* | |
249 | * Note: cpuid_level is set to -1 if unavailable, but | |
250 | * extended_extended_level is set to 0 if unavailable | |
251 | * and the legitimate extended levels are all negative | |
252 | * when signed; hence the weird messing around with | |
253 | * signs here... | |
254 | */ | |
255 | if (cpu_has(c, df->feature) && | |
f6db44df YL |
256 | ((s32)df->level < 0 ? |
257 | (u32)df->level > (u32)c->extended_cpuid_level : | |
258 | (s32)df->level > (s32)c->cpuid_level)) { | |
b38b0665 PA |
259 | clear_cpu_cap(c, df->feature); |
260 | if (warn) | |
261 | printk(KERN_WARNING | |
262 | "CPU: CPU feature %s disabled " | |
263 | "due to lack of CPUID level 0x%x\n", | |
264 | x86_cap_flags[df->feature], | |
265 | df->level); | |
266 | } | |
267 | } | |
f6db44df | 268 | } |
b38b0665 | 269 | |
102bbe3a YL |
270 | /* |
271 | * Naming convention should be: <Name> [(<Codename>)] | |
272 | * This table only is used unless init_<vendor>() below doesn't set it; | |
273 | * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used | |
274 | * | |
275 | */ | |
276 | ||
277 | /* Look up CPU names by table lookup. */ | |
278 | static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c) | |
279 | { | |
280 | struct cpu_model_info *info; | |
281 | ||
282 | if (c->x86_model >= 16) | |
283 | return NULL; /* Range check */ | |
284 | ||
285 | if (!this_cpu) | |
286 | return NULL; | |
287 | ||
288 | info = this_cpu->c_models; | |
289 | ||
290 | while (info && info->family) { | |
291 | if (info->family == c->x86) | |
292 | return info->model_names[c->x86_model]; | |
293 | info++; | |
294 | } | |
295 | return NULL; /* Not found */ | |
296 | } | |
297 | ||
7d851c8d AK |
298 | __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; |
299 | ||
11e3a840 JF |
300 | void load_percpu_segment(int cpu) |
301 | { | |
302 | #ifdef CONFIG_X86_32 | |
303 | loadsegment(fs, __KERNEL_PERCPU); | |
304 | #else | |
305 | loadsegment(gs, 0); | |
306 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); | |
307 | #endif | |
60a5317f | 308 | load_stack_canary_segment(); |
11e3a840 JF |
309 | } |
310 | ||
9d31d35b YL |
311 | /* Current gdt points %fs at the "master" per-cpu area: after this, |
312 | * it's on the real one. */ | |
552be871 | 313 | void switch_to_new_gdt(int cpu) |
9d31d35b YL |
314 | { |
315 | struct desc_ptr gdt_descr; | |
316 | ||
2697fbd5 | 317 | gdt_descr.address = (long)get_cpu_gdt_table(cpu); |
9d31d35b YL |
318 | gdt_descr.size = GDT_SIZE - 1; |
319 | load_gdt(&gdt_descr); | |
2697fbd5 | 320 | /* Reload the per-cpu base */ |
11e3a840 JF |
321 | |
322 | load_percpu_segment(cpu); | |
9d31d35b YL |
323 | } |
324 | ||
10a434fc | 325 | static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 326 | |
34048c9e | 327 | static void __cpuinit default_init(struct cpuinfo_x86 *c) |
1da177e4 | 328 | { |
b9e67f00 YL |
329 | #ifdef CONFIG_X86_64 |
330 | display_cacheinfo(c); | |
331 | #else | |
1da177e4 LT |
332 | /* Not much we can do here... */ |
333 | /* Check if at least it has cpuid */ | |
334 | if (c->cpuid_level == -1) { | |
335 | /* No cpuid. It must be an ancient CPU */ | |
336 | if (c->x86 == 4) | |
337 | strcpy(c->x86_model_id, "486"); | |
338 | else if (c->x86 == 3) | |
339 | strcpy(c->x86_model_id, "386"); | |
340 | } | |
b9e67f00 | 341 | #endif |
1da177e4 LT |
342 | } |
343 | ||
95414930 | 344 | static struct cpu_dev __cpuinitdata default_cpu = { |
1da177e4 | 345 | .c_init = default_init, |
fe38d855 | 346 | .c_vendor = "Unknown", |
10a434fc | 347 | .c_x86_vendor = X86_VENDOR_UNKNOWN, |
1da177e4 | 348 | }; |
1da177e4 | 349 | |
1b05d60d | 350 | static void __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
351 | { |
352 | unsigned int *v; | |
353 | char *p, *q; | |
354 | ||
3da99c97 | 355 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 356 | return; |
1da177e4 LT |
357 | |
358 | v = (unsigned int *) c->x86_model_id; | |
359 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
360 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
361 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
362 | c->x86_model_id[48] = 0; | |
363 | ||
364 | /* Intel chips right-justify this string for some dumb reason; | |
365 | undo that brain damage */ | |
366 | p = q = &c->x86_model_id[0]; | |
34048c9e | 367 | while (*p == ' ') |
1da177e4 | 368 | p++; |
34048c9e PC |
369 | if (p != q) { |
370 | while (*p) | |
1da177e4 | 371 | *q++ = *p++; |
34048c9e | 372 | while (q <= &c->x86_model_id[48]) |
1da177e4 LT |
373 | *q++ = '\0'; /* Zero-pad the rest */ |
374 | } | |
1da177e4 LT |
375 | } |
376 | ||
3bc9b76b | 377 | void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) |
1da177e4 | 378 | { |
9d31d35b | 379 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 380 | |
3da99c97 | 381 | n = c->extended_cpuid_level; |
1da177e4 LT |
382 | |
383 | if (n >= 0x80000005) { | |
9d31d35b | 384 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 385 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", |
9d31d35b YL |
386 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); |
387 | c->x86_cache_size = (ecx>>24) + (edx>>24); | |
140fc727 YL |
388 | #ifdef CONFIG_X86_64 |
389 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
390 | c->x86_tlbsize = 0; | |
391 | #endif | |
1da177e4 LT |
392 | } |
393 | ||
394 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
395 | return; | |
396 | ||
0a488a53 | 397 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 398 | l2size = ecx >> 16; |
34048c9e | 399 | |
140fc727 YL |
400 | #ifdef CONFIG_X86_64 |
401 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
402 | #else | |
1da177e4 LT |
403 | /* do processor-specific cache resizing */ |
404 | if (this_cpu->c_size_cache) | |
34048c9e | 405 | l2size = this_cpu->c_size_cache(c, l2size); |
1da177e4 LT |
406 | |
407 | /* Allow user to override all this if necessary. */ | |
408 | if (cachesize_override != -1) | |
409 | l2size = cachesize_override; | |
410 | ||
34048c9e | 411 | if (l2size == 0) |
1da177e4 | 412 | return; /* Again, no L2 cache is possible */ |
140fc727 | 413 | #endif |
1da177e4 LT |
414 | |
415 | c->x86_cache_size = l2size; | |
416 | ||
417 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
0a488a53 | 418 | l2size, ecx & 0xFF); |
1da177e4 LT |
419 | } |
420 | ||
9d31d35b | 421 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 422 | { |
97e4db7c | 423 | #ifdef CONFIG_X86_HT |
0a488a53 YL |
424 | u32 eax, ebx, ecx, edx; |
425 | int index_msb, core_bits; | |
1da177e4 | 426 | |
0a488a53 | 427 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 428 | return; |
1da177e4 | 429 | |
0a488a53 YL |
430 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
431 | goto out; | |
1da177e4 | 432 | |
1cd78776 YL |
433 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
434 | return; | |
1da177e4 | 435 | |
0a488a53 | 436 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 437 | |
9d31d35b YL |
438 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
439 | ||
440 | if (smp_num_siblings == 1) { | |
441 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
442 | } else if (smp_num_siblings > 1) { | |
443 | ||
9628937d | 444 | if (smp_num_siblings > nr_cpu_ids) { |
9d31d35b YL |
445 | printk(KERN_WARNING "CPU: Unsupported number of siblings %d", |
446 | smp_num_siblings); | |
447 | smp_num_siblings = 1; | |
448 | return; | |
449 | } | |
450 | ||
451 | index_msb = get_count_order(smp_num_siblings); | |
cb8cc442 | 452 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); |
9d31d35b YL |
453 | |
454 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; | |
455 | ||
456 | index_msb = get_count_order(smp_num_siblings); | |
457 | ||
458 | core_bits = get_count_order(c->x86_max_cores); | |
459 | ||
cb8cc442 | 460 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & |
9d31d35b | 461 | ((1 << core_bits) - 1); |
1da177e4 | 462 | } |
1da177e4 | 463 | |
0a488a53 YL |
464 | out: |
465 | if ((c->x86_max_cores * smp_num_siblings) > 1) { | |
466 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
467 | c->phys_proc_id); | |
468 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
469 | c->cpu_core_id); | |
9d31d35b | 470 | } |
9d31d35b | 471 | #endif |
97e4db7c | 472 | } |
1da177e4 | 473 | |
3da99c97 | 474 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
475 | { |
476 | char *v = c->x86_vendor_id; | |
477 | int i; | |
fe38d855 | 478 | static int printed; |
1da177e4 LT |
479 | |
480 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
481 | if (!cpu_devs[i]) |
482 | break; | |
483 | ||
484 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
485 | (cpu_devs[i]->c_ident[1] && | |
486 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
487 | this_cpu = cpu_devs[i]; | |
488 | c->x86_vendor = this_cpu->c_x86_vendor; | |
489 | return; | |
1da177e4 LT |
490 | } |
491 | } | |
10a434fc | 492 | |
fe38d855 CE |
493 | if (!printed) { |
494 | printed++; | |
43603c8d | 495 | printk(KERN_ERR "CPU: vendor_id '%s' unknown, using generic init.\n", v); |
fe38d855 CE |
496 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); |
497 | } | |
10a434fc | 498 | |
fe38d855 CE |
499 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
500 | this_cpu = &default_cpu; | |
1da177e4 LT |
501 | } |
502 | ||
9d31d35b | 503 | void __cpuinit cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 504 | { |
1da177e4 | 505 | /* Get vendor name */ |
4a148513 HH |
506 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
507 | (unsigned int *)&c->x86_vendor_id[0], | |
508 | (unsigned int *)&c->x86_vendor_id[8], | |
509 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 510 | |
1da177e4 | 511 | c->x86 = 4; |
9d31d35b | 512 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
513 | if (c->cpuid_level >= 0x00000001) { |
514 | u32 junk, tfms, cap0, misc; | |
515 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
9d31d35b YL |
516 | c->x86 = (tfms >> 8) & 0xf; |
517 | c->x86_model = (tfms >> 4) & 0xf; | |
518 | c->x86_mask = tfms & 0xf; | |
f5f786d0 | 519 | if (c->x86 == 0xf) |
1da177e4 | 520 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 521 | if (c->x86 >= 0x6) |
9d31d35b | 522 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
d4387bd3 | 523 | if (cap0 & (1<<19)) { |
d4387bd3 | 524 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 525 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 526 | } |
1da177e4 | 527 | } |
1da177e4 | 528 | } |
3da99c97 YL |
529 | |
530 | static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) | |
093af8d7 YL |
531 | { |
532 | u32 tfms, xlvl; | |
3da99c97 | 533 | u32 ebx; |
093af8d7 | 534 | |
3da99c97 YL |
535 | /* Intel-defined flags: level 0x00000001 */ |
536 | if (c->cpuid_level >= 0x00000001) { | |
537 | u32 capability, excap; | |
538 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); | |
539 | c->x86_capability[0] = capability; | |
540 | c->x86_capability[4] = excap; | |
541 | } | |
093af8d7 | 542 | |
3da99c97 YL |
543 | /* AMD-defined flags: level 0x80000001 */ |
544 | xlvl = cpuid_eax(0x80000000); | |
545 | c->extended_cpuid_level = xlvl; | |
546 | if ((xlvl & 0xffff0000) == 0x80000000) { | |
547 | if (xlvl >= 0x80000001) { | |
548 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
549 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 550 | } |
093af8d7 | 551 | } |
093af8d7 | 552 | |
5122c890 | 553 | #ifdef CONFIG_X86_64 |
5122c890 YL |
554 | if (c->extended_cpuid_level >= 0x80000008) { |
555 | u32 eax = cpuid_eax(0x80000008); | |
556 | ||
557 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
558 | c->x86_phys_bits = eax & 0xff; | |
093af8d7 | 559 | } |
5122c890 | 560 | #endif |
e3224234 YL |
561 | |
562 | if (c->extended_cpuid_level >= 0x80000007) | |
563 | c->x86_power = cpuid_edx(0x80000007); | |
093af8d7 YL |
564 | |
565 | } | |
1da177e4 | 566 | |
aef93c8b YL |
567 | static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
568 | { | |
569 | #ifdef CONFIG_X86_32 | |
570 | int i; | |
571 | ||
572 | /* | |
573 | * First of all, decide if this is a 486 or higher | |
574 | * It's a 486 if we can modify the AC flag | |
575 | */ | |
576 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
577 | c->x86 = 4; | |
578 | else | |
579 | c->x86 = 3; | |
580 | ||
581 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
582 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
583 | c->x86_vendor_id[0] = 0; | |
584 | cpu_devs[i]->c_identify(c); | |
585 | if (c->x86_vendor_id[0]) { | |
586 | get_cpu_vendor(c); | |
587 | break; | |
588 | } | |
589 | } | |
590 | #endif | |
591 | } | |
592 | ||
34048c9e PC |
593 | /* |
594 | * Do minimum CPU detection early. | |
595 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
596 | * cache alignment. | |
597 | * The others are not touched to avoid unwanted side effects. | |
598 | * | |
599 | * WARNING: this function is only called on the BP. Don't add code here | |
600 | * that is supposed to run on all CPUs. | |
601 | */ | |
3da99c97 | 602 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 603 | { |
6627d242 YL |
604 | #ifdef CONFIG_X86_64 |
605 | c->x86_clflush_size = 64; | |
606 | #else | |
d4387bd3 | 607 | c->x86_clflush_size = 32; |
6627d242 | 608 | #endif |
0a488a53 | 609 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 610 | |
3da99c97 | 611 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 612 | c->extended_cpuid_level = 0; |
d7cd5611 | 613 | |
aef93c8b YL |
614 | if (!have_cpuid_p()) |
615 | identify_cpu_without_cpuid(c); | |
616 | ||
617 | /* cyrix could have cpuid enabled via c_identify()*/ | |
d7cd5611 RR |
618 | if (!have_cpuid_p()) |
619 | return; | |
620 | ||
621 | cpu_detect(c); | |
622 | ||
3da99c97 | 623 | get_cpu_vendor(c); |
2b16a235 | 624 | |
3da99c97 | 625 | get_cpu_cap(c); |
12cf105c | 626 | |
10a434fc YL |
627 | if (this_cpu->c_early_init) |
628 | this_cpu->c_early_init(c); | |
093af8d7 | 629 | |
1c4acdb4 | 630 | #ifdef CONFIG_SMP |
bfcb4c1b | 631 | c->cpu_index = boot_cpu_id; |
1c4acdb4 | 632 | #endif |
b38b0665 | 633 | filter_cpuid_features(c, false); |
d7cd5611 RR |
634 | } |
635 | ||
9d31d35b YL |
636 | void __init early_cpu_init(void) |
637 | { | |
10a434fc YL |
638 | struct cpu_dev **cdev; |
639 | int count = 0; | |
640 | ||
641 | printk("KERNEL supported cpus:\n"); | |
642 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { | |
643 | struct cpu_dev *cpudev = *cdev; | |
644 | unsigned int j; | |
9d31d35b | 645 | |
10a434fc YL |
646 | if (count >= X86_VENDOR_NUM) |
647 | break; | |
648 | cpu_devs[count] = cpudev; | |
649 | count++; | |
650 | ||
651 | for (j = 0; j < 2; j++) { | |
652 | if (!cpudev->c_ident[j]) | |
653 | continue; | |
654 | printk(" %s %s\n", cpudev->c_vendor, | |
655 | cpudev->c_ident[j]); | |
656 | } | |
657 | } | |
9d31d35b | 658 | |
9d31d35b | 659 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 660 | } |
093af8d7 | 661 | |
b6734c35 PA |
662 | /* |
663 | * The NOPL instruction is supposed to exist on all CPUs with | |
ba0593bf | 664 | * family >= 6; unfortunately, that's not true in practice because |
b6734c35 | 665 | * of early VIA chips and (more importantly) broken virtualizers that |
ba0593bf PA |
666 | * are not easy to detect. In the latter case it doesn't even *fail* |
667 | * reliably, so probing for it doesn't even work. Disable it completely | |
668 | * unless we can find a reliable way to detect all the broken cases. | |
b6734c35 PA |
669 | */ |
670 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
671 | { | |
b6734c35 | 672 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
d7cd5611 RR |
673 | } |
674 | ||
34048c9e | 675 | static void __cpuinit generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 676 | { |
aef93c8b | 677 | c->extended_cpuid_level = 0; |
1da177e4 | 678 | |
3da99c97 | 679 | if (!have_cpuid_p()) |
aef93c8b | 680 | identify_cpu_without_cpuid(c); |
1d67953f | 681 | |
aef93c8b | 682 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 683 | if (!have_cpuid_p()) |
aef93c8b | 684 | return; |
1da177e4 | 685 | |
3da99c97 | 686 | cpu_detect(c); |
1da177e4 | 687 | |
3da99c97 | 688 | get_cpu_vendor(c); |
1da177e4 | 689 | |
3da99c97 | 690 | get_cpu_cap(c); |
1da177e4 | 691 | |
3da99c97 YL |
692 | if (c->cpuid_level >= 0x00000001) { |
693 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e YL |
694 | #ifdef CONFIG_X86_32 |
695 | # ifdef CONFIG_X86_HT | |
cb8cc442 | 696 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 697 | # else |
3da99c97 | 698 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
699 | # endif |
700 | #endif | |
1da177e4 | 701 | |
b89d3b3e YL |
702 | #ifdef CONFIG_X86_HT |
703 | c->phys_proc_id = c->initial_apicid; | |
1e9f28fa | 704 | #endif |
3da99c97 | 705 | } |
1da177e4 | 706 | |
1b05d60d | 707 | get_model_name(c); /* Default name */ |
1da177e4 | 708 | |
3da99c97 YL |
709 | init_scattered_cpuid_features(c); |
710 | detect_nopl(c); | |
1da177e4 | 711 | } |
1da177e4 LT |
712 | |
713 | /* | |
714 | * This does the hard work of actually picking apart the CPU stuff... | |
715 | */ | |
9a250347 | 716 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
717 | { |
718 | int i; | |
719 | ||
720 | c->loops_per_jiffy = loops_per_jiffy; | |
721 | c->x86_cache_size = -1; | |
722 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
723 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
724 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
725 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 726 | c->x86_max_cores = 1; |
102bbe3a | 727 | c->x86_coreid_bits = 0; |
11fdd252 | 728 | #ifdef CONFIG_X86_64 |
102bbe3a YL |
729 | c->x86_clflush_size = 64; |
730 | #else | |
731 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 732 | c->x86_clflush_size = 32; |
102bbe3a YL |
733 | #endif |
734 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
735 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
736 | ||
1da177e4 LT |
737 | generic_identify(c); |
738 | ||
3898534d | 739 | if (this_cpu->c_identify) |
1da177e4 LT |
740 | this_cpu->c_identify(c); |
741 | ||
102bbe3a | 742 | #ifdef CONFIG_X86_64 |
cb8cc442 | 743 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
744 | #endif |
745 | ||
1da177e4 LT |
746 | /* |
747 | * Vendor-specific initialization. In this section we | |
748 | * canonicalize the feature flags, meaning if there are | |
749 | * features a certain CPU supports which CPUID doesn't | |
750 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
751 | * we handle them here. | |
752 | * | |
753 | * At the end of this section, c->x86_capability better | |
754 | * indicate the features this CPU genuinely supports! | |
755 | */ | |
756 | if (this_cpu->c_init) | |
757 | this_cpu->c_init(c); | |
758 | ||
759 | /* Disable the PN if appropriate */ | |
760 | squash_the_stupid_serial_number(c); | |
761 | ||
762 | /* | |
763 | * The vendor-specific functions might have changed features. Now | |
764 | * we do "generic changes." | |
765 | */ | |
766 | ||
b38b0665 PA |
767 | /* Filter out anything that depends on CPUID levels we don't have */ |
768 | filter_cpuid_features(c, true); | |
769 | ||
1da177e4 | 770 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 771 | if (!c->x86_model_id[0]) { |
1da177e4 LT |
772 | char *p; |
773 | p = table_lookup_model(c); | |
34048c9e | 774 | if (p) |
1da177e4 LT |
775 | strcpy(c->x86_model_id, p); |
776 | else | |
777 | /* Last resort... */ | |
778 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 779 | c->x86, c->x86_model); |
1da177e4 LT |
780 | } |
781 | ||
102bbe3a YL |
782 | #ifdef CONFIG_X86_64 |
783 | detect_ht(c); | |
784 | #endif | |
785 | ||
88b094fb | 786 | init_hypervisor(c); |
1da177e4 LT |
787 | /* |
788 | * On SMP, boot_cpu_data holds the common feature set between | |
789 | * all CPUs; so make sure that we indicate which features are | |
790 | * common between the CPUs. The first time this routine gets | |
791 | * executed, c == &boot_cpu_data. | |
792 | */ | |
34048c9e | 793 | if (c != &boot_cpu_data) { |
1da177e4 | 794 | /* AND the already accumulated flags with these */ |
9d31d35b | 795 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 LT |
796 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
797 | } | |
798 | ||
7d851c8d AK |
799 | /* Clear all flags overriden by options */ |
800 | for (i = 0; i < NCAPINTS; i++) | |
12c247a6 | 801 | c->x86_capability[i] &= ~cleared_cpu_caps[i]; |
7d851c8d | 802 | |
102bbe3a | 803 | #ifdef CONFIG_X86_MCE |
1da177e4 | 804 | /* Init Machine Check Exception if available. */ |
1da177e4 | 805 | mcheck_init(c); |
102bbe3a | 806 | #endif |
30d432df AK |
807 | |
808 | select_idle_routine(c); | |
102bbe3a YL |
809 | |
810 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) | |
811 | numa_add_cpu(smp_processor_id()); | |
812 | #endif | |
a6c4e076 | 813 | } |
31ab269a | 814 | |
e04d645f GC |
815 | #ifdef CONFIG_X86_64 |
816 | static void vgetcpu_set_mode(void) | |
817 | { | |
818 | if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) | |
819 | vgetcpu_mode = VGETCPU_RDTSCP; | |
820 | else | |
821 | vgetcpu_mode = VGETCPU_LSL; | |
822 | } | |
823 | #endif | |
824 | ||
a6c4e076 JF |
825 | void __init identify_boot_cpu(void) |
826 | { | |
827 | identify_cpu(&boot_cpu_data); | |
102bbe3a | 828 | #ifdef CONFIG_X86_32 |
a6c4e076 | 829 | sysenter_setup(); |
6fe940d6 | 830 | enable_sep_cpu(); |
e04d645f GC |
831 | #else |
832 | vgetcpu_set_mode(); | |
102bbe3a | 833 | #endif |
241771ef | 834 | init_hw_perf_counters(); |
a6c4e076 | 835 | } |
3b520b23 | 836 | |
a6c4e076 JF |
837 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) |
838 | { | |
839 | BUG_ON(c == &boot_cpu_data); | |
840 | identify_cpu(c); | |
102bbe3a | 841 | #ifdef CONFIG_X86_32 |
a6c4e076 | 842 | enable_sep_cpu(); |
102bbe3a | 843 | #endif |
a6c4e076 | 844 | mtrr_ap_init(); |
1da177e4 LT |
845 | } |
846 | ||
a0854a46 YL |
847 | struct msr_range { |
848 | unsigned min; | |
849 | unsigned max; | |
850 | }; | |
1da177e4 | 851 | |
a0854a46 YL |
852 | static struct msr_range msr_range_array[] __cpuinitdata = { |
853 | { 0x00000000, 0x00000418}, | |
854 | { 0xc0000000, 0xc000040b}, | |
855 | { 0xc0010000, 0xc0010142}, | |
856 | { 0xc0011000, 0xc001103b}, | |
857 | }; | |
1da177e4 | 858 | |
a0854a46 YL |
859 | static void __cpuinit print_cpu_msr(void) |
860 | { | |
861 | unsigned index; | |
862 | u64 val; | |
863 | int i; | |
864 | unsigned index_min, index_max; | |
865 | ||
866 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
867 | index_min = msr_range_array[i].min; | |
868 | index_max = msr_range_array[i].max; | |
869 | for (index = index_min; index < index_max; index++) { | |
870 | if (rdmsrl_amd_safe(index, &val)) | |
871 | continue; | |
872 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1da177e4 | 873 | } |
a0854a46 YL |
874 | } |
875 | } | |
94605eff | 876 | |
a0854a46 YL |
877 | static int show_msr __cpuinitdata; |
878 | static __init int setup_show_msr(char *arg) | |
879 | { | |
880 | int num; | |
3dd9d514 | 881 | |
a0854a46 | 882 | get_option(&arg, &num); |
3dd9d514 | 883 | |
a0854a46 YL |
884 | if (num > 0) |
885 | show_msr = num; | |
886 | return 1; | |
1da177e4 | 887 | } |
a0854a46 | 888 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 889 | |
191679fd AK |
890 | static __init int setup_noclflush(char *arg) |
891 | { | |
892 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
893 | return 1; | |
894 | } | |
895 | __setup("noclflush", setup_noclflush); | |
896 | ||
3bc9b76b | 897 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 LT |
898 | { |
899 | char *vendor = NULL; | |
900 | ||
901 | if (c->x86_vendor < X86_VENDOR_NUM) | |
902 | vendor = this_cpu->c_vendor; | |
903 | else if (c->cpuid_level >= 0) | |
904 | vendor = c->x86_vendor_id; | |
905 | ||
bd32a8cf | 906 | if (vendor && !strstr(c->x86_model_id, vendor)) |
9d31d35b | 907 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 908 | |
9d31d35b YL |
909 | if (c->x86_model_id[0]) |
910 | printk(KERN_CONT "%s", c->x86_model_id); | |
1da177e4 | 911 | else |
9d31d35b | 912 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 913 | |
34048c9e | 914 | if (c->x86_mask || c->cpuid_level >= 0) |
9d31d35b | 915 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); |
1da177e4 | 916 | else |
9d31d35b | 917 | printk(KERN_CONT "\n"); |
a0854a46 YL |
918 | |
919 | #ifdef CONFIG_SMP | |
920 | if (c->cpu_index < show_msr) | |
921 | print_cpu_msr(); | |
922 | #else | |
923 | if (show_msr) | |
924 | print_cpu_msr(); | |
925 | #endif | |
1da177e4 LT |
926 | } |
927 | ||
ac72e788 AK |
928 | static __init int setup_disablecpuid(char *arg) |
929 | { | |
930 | int bit; | |
931 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) | |
932 | setup_clear_cpu_cap(bit); | |
933 | else | |
934 | return 0; | |
935 | return 1; | |
936 | } | |
937 | __setup("clearcpuid=", setup_disablecpuid); | |
938 | ||
d5494d4f | 939 | #ifdef CONFIG_X86_64 |
d5494d4f YL |
940 | struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; |
941 | ||
947e76cd BG |
942 | DEFINE_PER_CPU_FIRST(union irq_stack_union, |
943 | irq_stack_union) __aligned(PAGE_SIZE); | |
26f80bd6 | 944 | DEFINE_PER_CPU(char *, irq_stack_ptr) = |
2add8e23 | 945 | init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; |
d5494d4f | 946 | |
9af45651 BG |
947 | DEFINE_PER_CPU(unsigned long, kernel_stack) = |
948 | (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; | |
949 | EXPORT_PER_CPU_SYMBOL(kernel_stack); | |
950 | ||
56895530 | 951 | DEFINE_PER_CPU(unsigned int, irq_count) = -1; |
d5494d4f | 952 | |
92d65b23 BG |
953 | static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks |
954 | [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]) | |
955 | __aligned(PAGE_SIZE); | |
d5494d4f YL |
956 | |
957 | extern asmlinkage void ignore_sysret(void); | |
958 | ||
959 | /* May not be marked __init: used by software suspend */ | |
960 | void syscall_init(void) | |
1da177e4 | 961 | { |
d5494d4f YL |
962 | /* |
963 | * LSTAR and STAR live in a bit strange symbiosis. | |
964 | * They both write to the same internal register. STAR allows to | |
965 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
966 | */ | |
967 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
968 | wrmsrl(MSR_LSTAR, system_call); | |
969 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
03ae5768 | 970 | |
d5494d4f YL |
971 | #ifdef CONFIG_IA32_EMULATION |
972 | syscall32_cpu_init(); | |
973 | #endif | |
03ae5768 | 974 | |
d5494d4f YL |
975 | /* Flags to clear on syscall */ |
976 | wrmsrl(MSR_SYSCALL_MASK, | |
977 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); | |
1da177e4 | 978 | } |
62111195 | 979 | |
d5494d4f YL |
980 | unsigned long kernel_eflags; |
981 | ||
982 | /* | |
983 | * Copies of the original ist values from the tss are only accessed during | |
984 | * debugging, no special alignment required. | |
985 | */ | |
986 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
987 | ||
60a5317f | 988 | #else /* x86_64 */ |
d5494d4f | 989 | |
60a5317f TH |
990 | #ifdef CONFIG_CC_STACKPROTECTOR |
991 | DEFINE_PER_CPU(unsigned long, stack_canary); | |
992 | #endif | |
d5494d4f | 993 | |
60a5317f | 994 | /* Make sure %fs and %gs are initialized properly in idle threads */ |
6b2fb3c6 | 995 | struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) |
f95d47ca JF |
996 | { |
997 | memset(regs, 0, sizeof(struct pt_regs)); | |
65ea5b03 | 998 | regs->fs = __KERNEL_PERCPU; |
60a5317f | 999 | regs->gs = __KERNEL_STACK_CANARY; |
f95d47ca JF |
1000 | return regs; |
1001 | } | |
60a5317f | 1002 | #endif /* x86_64 */ |
c5413fbe | 1003 | |
d2cbcc49 RR |
1004 | /* |
1005 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1006 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1007 | * and IDT. We reload them nevertheless, this function acts as a | |
1008 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 1009 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 1010 | */ |
1ba76586 YL |
1011 | #ifdef CONFIG_X86_64 |
1012 | void __cpuinit cpu_init(void) | |
1013 | { | |
1014 | int cpu = stack_smp_processor_id(); | |
1015 | struct tss_struct *t = &per_cpu(init_tss, cpu); | |
1016 | struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu); | |
1017 | unsigned long v; | |
1ba76586 YL |
1018 | struct task_struct *me; |
1019 | int i; | |
1020 | ||
e7a22c1e BG |
1021 | #ifdef CONFIG_NUMA |
1022 | if (cpu != 0 && percpu_read(node_number) == 0 && | |
1023 | cpu_to_node(cpu) != NUMA_NO_NODE) | |
1024 | percpu_write(node_number, cpu_to_node(cpu)); | |
1025 | #endif | |
1ba76586 YL |
1026 | |
1027 | me = current; | |
1028 | ||
c2d1cec1 | 1029 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) |
1ba76586 YL |
1030 | panic("CPU#%d already initialized!\n", cpu); |
1031 | ||
1032 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1033 | ||
1034 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
1035 | ||
1036 | /* | |
1037 | * Initialize the per-CPU GDT with the boot GDT, | |
1038 | * and set up the GDT descriptor: | |
1039 | */ | |
1040 | ||
552be871 | 1041 | switch_to_new_gdt(cpu); |
2697fbd5 BG |
1042 | loadsegment(fs, 0); |
1043 | ||
1ba76586 YL |
1044 | load_idt((const struct desc_ptr *)&idt_descr); |
1045 | ||
1046 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1047 | syscall_init(); | |
1048 | ||
1049 | wrmsrl(MSR_FS_BASE, 0); | |
1050 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1051 | barrier(); | |
1052 | ||
1053 | check_efer(); | |
06cd9a7d | 1054 | if (cpu != 0) |
1ba76586 YL |
1055 | enable_x2apic(); |
1056 | ||
1057 | /* | |
1058 | * set up and load the per-CPU TSS | |
1059 | */ | |
1060 | if (!orig_ist->ist[0]) { | |
92d65b23 BG |
1061 | static const unsigned int sizes[N_EXCEPTION_STACKS] = { |
1062 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
1063 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
1ba76586 | 1064 | }; |
92d65b23 | 1065 | char *estacks = per_cpu(exception_stacks, cpu); |
1ba76586 | 1066 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
92d65b23 | 1067 | estacks += sizes[v]; |
1ba76586 YL |
1068 | orig_ist->ist[v] = t->x86_tss.ist[v] = |
1069 | (unsigned long)estacks; | |
1070 | } | |
1071 | } | |
1072 | ||
1073 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
1074 | /* | |
1075 | * <= is required because the CPU will access up to | |
1076 | * 8 bits beyond the end of the IO permission bitmap. | |
1077 | */ | |
1078 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1079 | t->io_bitmap[i] = ~0UL; | |
1080 | ||
1081 | atomic_inc(&init_mm.mm_count); | |
1082 | me->active_mm = &init_mm; | |
1083 | if (me->mm) | |
1084 | BUG(); | |
1085 | enter_lazy_tlb(&init_mm, me); | |
1086 | ||
1087 | load_sp0(t, ¤t->thread); | |
1088 | set_tss_desc(cpu, t); | |
1089 | load_TR_desc(); | |
1090 | load_LDT(&init_mm.context); | |
1091 | ||
1092 | #ifdef CONFIG_KGDB | |
1093 | /* | |
1094 | * If the kgdb is connected no debug regs should be altered. This | |
1095 | * is only applicable when KGDB and a KGDB I/O module are built | |
1096 | * into the kernel and you are using early debugging with | |
1097 | * kgdbwait. KGDB will control the kernel HW breakpoint registers. | |
1098 | */ | |
1099 | if (kgdb_connected && arch_kgdb_ops.correct_hw_break) | |
1100 | arch_kgdb_ops.correct_hw_break(); | |
8f6d86dc | 1101 | else |
1ba76586 | 1102 | #endif |
8f6d86dc PZ |
1103 | { |
1104 | /* | |
1105 | * Clear all 6 debug registers: | |
1106 | */ | |
1107 | set_debugreg(0UL, 0); | |
1108 | set_debugreg(0UL, 1); | |
1109 | set_debugreg(0UL, 2); | |
1110 | set_debugreg(0UL, 3); | |
1111 | set_debugreg(0UL, 6); | |
1112 | set_debugreg(0UL, 7); | |
1ba76586 | 1113 | } |
1ba76586 YL |
1114 | |
1115 | fpu_init(); | |
1116 | ||
1117 | raw_local_save_flags(kernel_eflags); | |
1118 | ||
1119 | if (is_uv_system()) | |
1120 | uv_cpu_init(); | |
1121 | } | |
1122 | ||
1123 | #else | |
1124 | ||
d2cbcc49 | 1125 | void __cpuinit cpu_init(void) |
9ee79a3d | 1126 | { |
d2cbcc49 RR |
1127 | int cpu = smp_processor_id(); |
1128 | struct task_struct *curr = current; | |
34048c9e | 1129 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 1130 | struct thread_struct *thread = &curr->thread; |
62111195 | 1131 | |
c2d1cec1 | 1132 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { |
62111195 JF |
1133 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); |
1134 | for (;;) local_irq_enable(); | |
1135 | } | |
1136 | ||
1137 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1138 | ||
1139 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
1140 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 1141 | |
4d37e7e3 | 1142 | load_idt(&idt_descr); |
552be871 | 1143 | switch_to_new_gdt(cpu); |
1da177e4 | 1144 | |
1da177e4 LT |
1145 | /* |
1146 | * Set up and load the per-CPU TSS and LDT | |
1147 | */ | |
1148 | atomic_inc(&init_mm.mm_count); | |
62111195 JF |
1149 | curr->active_mm = &init_mm; |
1150 | if (curr->mm) | |
1151 | BUG(); | |
1152 | enter_lazy_tlb(&init_mm, curr); | |
1da177e4 | 1153 | |
faca6227 | 1154 | load_sp0(t, thread); |
34048c9e | 1155 | set_tss_desc(cpu, t); |
1da177e4 LT |
1156 | load_TR_desc(); |
1157 | load_LDT(&init_mm.context); | |
1158 | ||
22c4e308 | 1159 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1160 | /* Set up doublefault TSS pointer in the GDT */ |
1161 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1162 | #endif |
1da177e4 | 1163 | |
1da177e4 | 1164 | /* Clear all 6 debug registers: */ |
4bb0d3ec ZA |
1165 | set_debugreg(0, 0); |
1166 | set_debugreg(0, 1); | |
1167 | set_debugreg(0, 2); | |
1168 | set_debugreg(0, 3); | |
1169 | set_debugreg(0, 6); | |
1170 | set_debugreg(0, 7); | |
1da177e4 LT |
1171 | |
1172 | /* | |
1173 | * Force FPU initialization: | |
1174 | */ | |
b359e8a4 SS |
1175 | if (cpu_has_xsave) |
1176 | current_thread_info()->status = TS_XSAVE; | |
1177 | else | |
1178 | current_thread_info()->status = 0; | |
1da177e4 LT |
1179 | clear_used_math(); |
1180 | mxcsr_feature_mask_init(); | |
dc1e35c6 SS |
1181 | |
1182 | /* | |
1183 | * Boot processor to setup the FP and extended state context info. | |
1184 | */ | |
b3572e36 | 1185 | if (smp_processor_id() == boot_cpu_id) |
dc1e35c6 SS |
1186 | init_thread_xstate(); |
1187 | ||
1188 | xsave_init(); | |
1da177e4 | 1189 | } |
e1367daf | 1190 | |
1ba76586 YL |
1191 | |
1192 | #endif |