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f580366f | 1 | #include <linux/init.h> |
0f0124fa YL |
2 | #include <linux/kernel.h> |
3 | #include <linux/sched.h> | |
4 | #include <linux/string.h> | |
5 | #include <linux/bootmem.h> | |
6 | #include <linux/bitops.h> | |
7 | #include <linux/module.h> | |
8 | #include <linux/kgdb.h> | |
9 | #include <linux/topology.h> | |
f580366f YL |
10 | #include <linux/delay.h> |
11 | #include <linux/smp.h> | |
f580366f | 12 | #include <linux/percpu.h> |
f580366f YL |
13 | #include <asm/i387.h> |
14 | #include <asm/msr.h> | |
15 | #include <asm/io.h> | |
cbcd79c2 | 16 | #include <asm/linkage.h> |
f580366f YL |
17 | #include <asm/mmu_context.h> |
18 | #include <asm/mtrr.h> | |
19 | #include <asm/mce.h> | |
20 | #include <asm/pat.h> | |
21 | #include <asm/numa.h> | |
22 | #ifdef CONFIG_X86_LOCAL_APIC | |
23 | #include <asm/mpspec.h> | |
24 | #include <asm/apic.h> | |
25 | #include <mach_apic.h> | |
26 | #endif | |
0f0124fa YL |
27 | #include <asm/pda.h> |
28 | #include <asm/pgtable.h> | |
29 | #include <asm/processor.h> | |
30 | #include <asm/desc.h> | |
31 | #include <asm/atomic.h> | |
32 | #include <asm/proto.h> | |
33 | #include <asm/sections.h> | |
34 | #include <asm/setup.h> | |
35 | #include <asm/genapic.h> | |
f580366f YL |
36 | |
37 | #include "cpu.h" | |
38 | ||
39 | /* We need valid kernel segments for data and code in long mode too | |
40 | * IRET will check the segment types kkeil 2000/10/28 | |
41 | * Also sysret mandates a special GDT layout | |
42 | */ | |
43 | /* The TLS descriptors are currently at a different place compared to i386. | |
44 | Hopefully nobody expects them at a fixed place (Wine?) */ | |
45 | DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = { | |
46 | [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } }, | |
47 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } }, | |
48 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } }, | |
49 | [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } }, | |
50 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } }, | |
51 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } }, | |
52 | } }; | |
53 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); | |
54 | ||
55 | __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; | |
56 | ||
57 | /* Current gdt points %fs at the "master" per-cpu area: after this, | |
58 | * it's on the real one. */ | |
59 | void switch_to_new_gdt(void) | |
60 | { | |
61 | struct desc_ptr gdt_descr; | |
62 | ||
63 | gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id()); | |
64 | gdt_descr.size = GDT_SIZE - 1; | |
65 | load_gdt(&gdt_descr); | |
66 | } | |
67 | ||
68 | struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; | |
69 | ||
70 | static void __cpuinit default_init(struct cpuinfo_x86 *c) | |
71 | { | |
72 | display_cacheinfo(c); | |
73 | } | |
74 | ||
75 | static struct cpu_dev __cpuinitdata default_cpu = { | |
76 | .c_init = default_init, | |
77 | .c_vendor = "Unknown", | |
78 | }; | |
79 | static struct cpu_dev *this_cpu __cpuinitdata = &default_cpu; | |
80 | ||
81 | int __cpuinit get_model_name(struct cpuinfo_x86 *c) | |
82 | { | |
83 | unsigned int *v; | |
84 | ||
85 | if (c->extended_cpuid_level < 0x80000004) | |
86 | return 0; | |
87 | ||
88 | v = (unsigned int *) c->x86_model_id; | |
89 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
90 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
91 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
92 | c->x86_model_id[48] = 0; | |
93 | return 1; | |
94 | } | |
95 | ||
96 | ||
97 | void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) | |
98 | { | |
87a1c441 | 99 | unsigned int n, dummy, ebx, ecx, edx; |
f580366f YL |
100 | |
101 | n = c->extended_cpuid_level; | |
102 | ||
103 | if (n >= 0x80000005) { | |
104 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); | |
105 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), " | |
106 | "D cache %dK (%d bytes/line)\n", | |
107 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); | |
108 | c->x86_cache_size = (ecx>>24) + (edx>>24); | |
109 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
110 | c->x86_tlbsize = 0; | |
111 | } | |
112 | ||
113 | if (n >= 0x80000006) { | |
114 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); | |
115 | ecx = cpuid_ecx(0x80000006); | |
116 | c->x86_cache_size = ecx >> 16; | |
117 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
118 | ||
119 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
120 | c->x86_cache_size, ecx & 0xFF); | |
121 | } | |
f580366f YL |
122 | } |
123 | ||
124 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) | |
125 | { | |
126 | #ifdef CONFIG_SMP | |
127 | u32 eax, ebx, ecx, edx; | |
128 | int index_msb, core_bits; | |
129 | ||
130 | cpuid(1, &eax, &ebx, &ecx, &edx); | |
131 | ||
132 | ||
133 | if (!cpu_has(c, X86_FEATURE_HT)) | |
134 | return; | |
135 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) | |
136 | goto out; | |
137 | ||
138 | smp_num_siblings = (ebx & 0xff0000) >> 16; | |
139 | ||
140 | if (smp_num_siblings == 1) { | |
141 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
142 | } else if (smp_num_siblings > 1) { | |
143 | ||
144 | if (smp_num_siblings > NR_CPUS) { | |
145 | printk(KERN_WARNING "CPU: Unsupported number of " | |
146 | "siblings %d", smp_num_siblings); | |
147 | smp_num_siblings = 1; | |
148 | return; | |
149 | } | |
150 | ||
151 | index_msb = get_count_order(smp_num_siblings); | |
152 | c->phys_proc_id = phys_pkg_id(index_msb); | |
153 | ||
154 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; | |
155 | ||
156 | index_msb = get_count_order(smp_num_siblings); | |
157 | ||
158 | core_bits = get_count_order(c->x86_max_cores); | |
159 | ||
160 | c->cpu_core_id = phys_pkg_id(index_msb) & | |
161 | ((1 << core_bits) - 1); | |
162 | } | |
163 | out: | |
164 | if ((c->x86_max_cores * smp_num_siblings) > 1) { | |
165 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
166 | c->phys_proc_id); | |
167 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
168 | c->cpu_core_id); | |
169 | } | |
170 | ||
171 | #endif | |
172 | } | |
173 | ||
174 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) | |
175 | { | |
176 | char *v = c->x86_vendor_id; | |
177 | int i; | |
178 | static int printed; | |
179 | ||
180 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
181 | if (cpu_devs[i]) { | |
182 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
183 | (cpu_devs[i]->c_ident[1] && | |
184 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
185 | c->x86_vendor = i; | |
186 | this_cpu = cpu_devs[i]; | |
187 | return; | |
188 | } | |
189 | } | |
190 | } | |
191 | if (!printed) { | |
192 | printed++; | |
193 | printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n"); | |
194 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); | |
195 | } | |
196 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
197 | } | |
198 | ||
199 | static void __init early_cpu_support_print(void) | |
200 | { | |
201 | int i,j; | |
202 | struct cpu_dev *cpu_devx; | |
203 | ||
204 | printk("KERNEL supported cpus:\n"); | |
205 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
206 | cpu_devx = cpu_devs[i]; | |
207 | if (!cpu_devx) | |
208 | continue; | |
209 | for (j = 0; j < 2; j++) { | |
210 | if (!cpu_devx->c_ident[j]) | |
211 | continue; | |
212 | printk(" %s %s\n", cpu_devx->c_vendor, | |
213 | cpu_devx->c_ident[j]); | |
214 | } | |
215 | } | |
216 | } | |
217 | ||
218 | static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c); | |
219 | ||
220 | void __init early_cpu_init(void) | |
221 | { | |
222 | struct cpu_vendor_dev *cvdev; | |
223 | ||
224 | for (cvdev = __x86cpuvendor_start ; | |
225 | cvdev < __x86cpuvendor_end ; | |
226 | cvdev++) | |
227 | cpu_devs[cvdev->vendor] = cvdev->cpu_dev; | |
228 | early_cpu_support_print(); | |
229 | early_identify_cpu(&boot_cpu_data); | |
230 | } | |
231 | ||
232 | /* Do some early cpuid on the boot CPU to get some parameter that are | |
233 | needed before check_bugs. Everything advanced is in identify_cpu | |
234 | below. */ | |
235 | static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c) | |
236 | { | |
237 | u32 tfms, xlvl; | |
238 | ||
239 | c->loops_per_jiffy = loops_per_jiffy; | |
240 | c->x86_cache_size = -1; | |
241 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
242 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ | |
243 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
244 | c->x86_model_id[0] = '\0'; /* Unset */ | |
245 | c->x86_clflush_size = 64; | |
246 | c->x86_cache_alignment = c->x86_clflush_size; | |
247 | c->x86_max_cores = 1; | |
248 | c->x86_coreid_bits = 0; | |
249 | c->extended_cpuid_level = 0; | |
250 | memset(&c->x86_capability, 0, sizeof c->x86_capability); | |
251 | ||
252 | /* Get vendor name */ | |
253 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, | |
254 | (unsigned int *)&c->x86_vendor_id[0], | |
255 | (unsigned int *)&c->x86_vendor_id[8], | |
256 | (unsigned int *)&c->x86_vendor_id[4]); | |
257 | ||
258 | get_cpu_vendor(c); | |
259 | ||
260 | /* Initialize the standard set of capabilities */ | |
261 | /* Note that the vendor-specific code below might override */ | |
262 | ||
263 | /* Intel-defined flags: level 0x00000001 */ | |
264 | if (c->cpuid_level >= 0x00000001) { | |
265 | __u32 misc; | |
266 | cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4], | |
267 | &c->x86_capability[0]); | |
268 | c->x86 = (tfms >> 8) & 0xf; | |
269 | c->x86_model = (tfms >> 4) & 0xf; | |
270 | c->x86_mask = tfms & 0xf; | |
271 | if (c->x86 == 0xf) | |
272 | c->x86 += (tfms >> 20) & 0xff; | |
273 | if (c->x86 >= 0x6) | |
274 | c->x86_model += ((tfms >> 16) & 0xF) << 4; | |
275 | if (test_cpu_cap(c, X86_FEATURE_CLFLSH)) | |
276 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; | |
277 | } else { | |
278 | /* Have CPUID level 0 only - unheard of */ | |
279 | c->x86 = 4; | |
280 | } | |
281 | ||
282 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xff; | |
283 | #ifdef CONFIG_SMP | |
284 | c->phys_proc_id = c->initial_apicid; | |
285 | #endif | |
286 | /* AMD-defined flags: level 0x80000001 */ | |
287 | xlvl = cpuid_eax(0x80000000); | |
288 | c->extended_cpuid_level = xlvl; | |
289 | if ((xlvl & 0xffff0000) == 0x80000000) { | |
290 | if (xlvl >= 0x80000001) { | |
291 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
292 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
293 | } | |
294 | if (xlvl >= 0x80000004) | |
295 | get_model_name(c); /* Default name */ | |
296 | } | |
297 | ||
298 | /* Transmeta-defined flags: level 0x80860001 */ | |
299 | xlvl = cpuid_eax(0x80860000); | |
300 | if ((xlvl & 0xffff0000) == 0x80860000) { | |
301 | /* Don't set x86_cpuid_level here for now to not confuse. */ | |
302 | if (xlvl >= 0x80860001) | |
303 | c->x86_capability[2] = cpuid_edx(0x80860001); | |
304 | } | |
305 | ||
f580366f YL |
306 | if (c->extended_cpuid_level >= 0x80000007) |
307 | c->x86_power = cpuid_edx(0x80000007); | |
308 | ||
87a1c441 YL |
309 | if (c->extended_cpuid_level >= 0x80000008) { |
310 | u32 eax = cpuid_eax(0x80000008); | |
311 | ||
312 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
313 | c->x86_phys_bits = eax & 0xff; | |
314 | } | |
315 | ||
f580366f YL |
316 | if (c->x86_vendor != X86_VENDOR_UNKNOWN && |
317 | cpu_devs[c->x86_vendor]->c_early_init) | |
318 | cpu_devs[c->x86_vendor]->c_early_init(c); | |
319 | ||
320 | validate_pat_support(c); | |
f580366f YL |
321 | } |
322 | ||
323 | /* | |
324 | * This does the hard work of actually picking apart the CPU stuff... | |
325 | */ | |
9a250347 | 326 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
f580366f YL |
327 | { |
328 | int i; | |
329 | ||
330 | early_identify_cpu(c); | |
331 | ||
332 | init_scattered_cpuid_features(c); | |
333 | ||
334 | c->apicid = phys_pkg_id(0); | |
335 | ||
336 | /* | |
337 | * Vendor-specific initialization. In this section we | |
338 | * canonicalize the feature flags, meaning if there are | |
339 | * features a certain CPU supports which CPUID doesn't | |
340 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
341 | * we handle them here. | |
342 | * | |
343 | * At the end of this section, c->x86_capability better | |
344 | * indicate the features this CPU genuinely supports! | |
345 | */ | |
346 | if (this_cpu->c_init) | |
347 | this_cpu->c_init(c); | |
348 | ||
349 | detect_ht(c); | |
350 | ||
351 | /* | |
352 | * On SMP, boot_cpu_data holds the common feature set between | |
353 | * all CPUs; so make sure that we indicate which features are | |
354 | * common between the CPUs. The first time this routine gets | |
355 | * executed, c == &boot_cpu_data. | |
356 | */ | |
357 | if (c != &boot_cpu_data) { | |
358 | /* AND the already accumulated flags with these */ | |
359 | for (i = 0; i < NCAPINTS; i++) | |
360 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; | |
361 | } | |
362 | ||
363 | /* Clear all flags overriden by options */ | |
364 | for (i = 0; i < NCAPINTS; i++) | |
365 | c->x86_capability[i] &= ~cleared_cpu_caps[i]; | |
366 | ||
367 | #ifdef CONFIG_X86_MCE | |
368 | mcheck_init(c); | |
369 | #endif | |
370 | select_idle_routine(c); | |
371 | ||
372 | #ifdef CONFIG_NUMA | |
373 | numa_add_cpu(smp_processor_id()); | |
374 | #endif | |
375 | ||
376 | } | |
377 | ||
378 | void __cpuinit identify_boot_cpu(void) | |
379 | { | |
380 | identify_cpu(&boot_cpu_data); | |
381 | } | |
382 | ||
383 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) | |
384 | { | |
385 | BUG_ON(c == &boot_cpu_data); | |
386 | identify_cpu(c); | |
387 | mtrr_ap_init(); | |
388 | } | |
389 | ||
390 | static __init int setup_noclflush(char *arg) | |
391 | { | |
392 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
393 | return 1; | |
394 | } | |
395 | __setup("noclflush", setup_noclflush); | |
396 | ||
397 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) | |
398 | { | |
399 | if (c->x86_model_id[0]) | |
400 | printk(KERN_CONT "%s", c->x86_model_id); | |
401 | ||
402 | if (c->x86_mask || c->cpuid_level >= 0) | |
403 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); | |
404 | else | |
405 | printk(KERN_CONT "\n"); | |
406 | } | |
407 | ||
408 | static __init int setup_disablecpuid(char *arg) | |
409 | { | |
410 | int bit; | |
411 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) | |
412 | setup_clear_cpu_cap(bit); | |
413 | else | |
414 | return 0; | |
415 | return 1; | |
416 | } | |
417 | __setup("clearcpuid=", setup_disablecpuid); | |
0f0124fa | 418 | |
0f0124fa YL |
419 | cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE; |
420 | ||
421 | struct x8664_pda **_cpu_pda __read_mostly; | |
422 | EXPORT_SYMBOL(_cpu_pda); | |
423 | ||
424 | struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; | |
425 | ||
426 | char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss; | |
427 | ||
428 | unsigned long __supported_pte_mask __read_mostly = ~0UL; | |
429 | EXPORT_SYMBOL_GPL(__supported_pte_mask); | |
430 | ||
431 | static int do_not_nx __cpuinitdata; | |
432 | ||
433 | /* noexec=on|off | |
434 | Control non executable mappings for 64bit processes. | |
435 | ||
436 | on Enable(default) | |
437 | off Disable | |
438 | */ | |
439 | static int __init nonx_setup(char *str) | |
440 | { | |
441 | if (!str) | |
442 | return -EINVAL; | |
443 | if (!strncmp(str, "on", 2)) { | |
444 | __supported_pte_mask |= _PAGE_NX; | |
445 | do_not_nx = 0; | |
446 | } else if (!strncmp(str, "off", 3)) { | |
447 | do_not_nx = 1; | |
448 | __supported_pte_mask &= ~_PAGE_NX; | |
449 | } | |
450 | return 0; | |
451 | } | |
452 | early_param("noexec", nonx_setup); | |
453 | ||
454 | int force_personality32; | |
455 | ||
456 | /* noexec32=on|off | |
457 | Control non executable heap for 32bit processes. | |
458 | To control the stack too use noexec=off | |
459 | ||
460 | on PROT_READ does not imply PROT_EXEC for 32bit processes (default) | |
461 | off PROT_READ implies PROT_EXEC | |
462 | */ | |
463 | static int __init nonx32_setup(char *str) | |
464 | { | |
465 | if (!strcmp(str, "on")) | |
466 | force_personality32 &= ~READ_IMPLIES_EXEC; | |
467 | else if (!strcmp(str, "off")) | |
468 | force_personality32 |= READ_IMPLIES_EXEC; | |
469 | return 1; | |
470 | } | |
471 | __setup("noexec32=", nonx32_setup); | |
472 | ||
473 | void pda_init(int cpu) | |
474 | { | |
475 | struct x8664_pda *pda = cpu_pda(cpu); | |
476 | ||
477 | /* Setup up data that may be needed in __get_free_pages early */ | |
ada85708 JF |
478 | loadsegment(fs, 0); |
479 | loadsegment(gs, 0); | |
0f0124fa YL |
480 | /* Memory clobbers used to order PDA accessed */ |
481 | mb(); | |
482 | wrmsrl(MSR_GS_BASE, pda); | |
483 | mb(); | |
484 | ||
485 | pda->cpunumber = cpu; | |
486 | pda->irqcount = -1; | |
487 | pda->kernelstack = (unsigned long)stack_thread_info() - | |
488 | PDA_STACKOFFSET + THREAD_SIZE; | |
489 | pda->active_mm = &init_mm; | |
490 | pda->mmu_state = 0; | |
491 | ||
492 | if (cpu == 0) { | |
493 | /* others are initialized in smpboot.c */ | |
494 | pda->pcurrent = &init_task; | |
495 | pda->irqstackptr = boot_cpu_stack; | |
496 | } else { | |
497 | pda->irqstackptr = (char *) | |
498 | __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER); | |
499 | if (!pda->irqstackptr) | |
500 | panic("cannot allocate irqstack for cpu %d", cpu); | |
501 | ||
502 | if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE) | |
503 | pda->nodenumber = cpu_to_node(cpu); | |
504 | } | |
505 | ||
506 | pda->irqstackptr += IRQSTACKSIZE-64; | |
507 | } | |
508 | ||
509 | char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + | |
cbcd79c2 | 510 | DEBUG_STKSZ] __page_aligned_bss; |
0f0124fa YL |
511 | |
512 | extern asmlinkage void ignore_sysret(void); | |
513 | ||
514 | /* May not be marked __init: used by software suspend */ | |
515 | void syscall_init(void) | |
516 | { | |
517 | /* | |
518 | * LSTAR and STAR live in a bit strange symbiosis. | |
519 | * They both write to the same internal register. STAR allows to | |
520 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
521 | */ | |
522 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
523 | wrmsrl(MSR_LSTAR, system_call); | |
524 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
525 | ||
526 | #ifdef CONFIG_IA32_EMULATION | |
527 | syscall32_cpu_init(); | |
528 | #endif | |
529 | ||
530 | /* Flags to clear on syscall */ | |
531 | wrmsrl(MSR_SYSCALL_MASK, | |
532 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); | |
533 | } | |
534 | ||
535 | void __cpuinit check_efer(void) | |
536 | { | |
537 | unsigned long efer; | |
538 | ||
539 | rdmsrl(MSR_EFER, efer); | |
540 | if (!(efer & EFER_NX) || do_not_nx) | |
541 | __supported_pte_mask &= ~_PAGE_NX; | |
542 | } | |
543 | ||
544 | unsigned long kernel_eflags; | |
545 | ||
546 | /* | |
547 | * Copies of the original ist values from the tss are only accessed during | |
548 | * debugging, no special alignment required. | |
549 | */ | |
550 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
551 | ||
552 | /* | |
553 | * cpu_init() initializes state that is per-CPU. Some data is already | |
554 | * initialized (naturally) in the bootstrap process, such as the GDT | |
555 | * and IDT. We reload them nevertheless, this function acts as a | |
556 | * 'CPU state barrier', nothing should get across. | |
557 | * A lot of state is already set up in PDA init. | |
558 | */ | |
559 | void __cpuinit cpu_init(void) | |
560 | { | |
561 | int cpu = stack_smp_processor_id(); | |
562 | struct tss_struct *t = &per_cpu(init_tss, cpu); | |
563 | struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu); | |
564 | unsigned long v; | |
565 | char *estacks = NULL; | |
566 | struct task_struct *me; | |
567 | int i; | |
568 | ||
569 | /* CPU 0 is initialised in head64.c */ | |
570 | if (cpu != 0) | |
571 | pda_init(cpu); | |
572 | else | |
573 | estacks = boot_exception_stacks; | |
574 | ||
575 | me = current; | |
576 | ||
577 | if (cpu_test_and_set(cpu, cpu_initialized)) | |
578 | panic("CPU#%d already initialized!\n", cpu); | |
579 | ||
580 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
581 | ||
582 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
583 | ||
584 | /* | |
585 | * Initialize the per-CPU GDT with the boot GDT, | |
586 | * and set up the GDT descriptor: | |
587 | */ | |
588 | ||
589 | switch_to_new_gdt(); | |
590 | load_idt((const struct desc_ptr *)&idt_descr); | |
591 | ||
592 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
593 | syscall_init(); | |
594 | ||
595 | wrmsrl(MSR_FS_BASE, 0); | |
596 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
597 | barrier(); | |
598 | ||
599 | check_efer(); | |
6e1cb38a SS |
600 | if (cpu != 0 && x2apic) |
601 | enable_x2apic(); | |
0f0124fa YL |
602 | |
603 | /* | |
604 | * set up and load the per-CPU TSS | |
605 | */ | |
606 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { | |
607 | static const unsigned int order[N_EXCEPTION_STACKS] = { | |
608 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER, | |
609 | [DEBUG_STACK - 1] = DEBUG_STACK_ORDER | |
610 | }; | |
611 | if (cpu) { | |
612 | estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]); | |
613 | if (!estacks) | |
614 | panic("Cannot allocate exception stack %ld %d\n", | |
615 | v, cpu); | |
616 | } | |
617 | estacks += PAGE_SIZE << order[v]; | |
618 | orig_ist->ist[v] = t->x86_tss.ist[v] = (unsigned long)estacks; | |
619 | } | |
620 | ||
621 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
622 | /* | |
623 | * <= is required because the CPU will access up to | |
624 | * 8 bits beyond the end of the IO permission bitmap. | |
625 | */ | |
626 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
627 | t->io_bitmap[i] = ~0UL; | |
628 | ||
629 | atomic_inc(&init_mm.mm_count); | |
630 | me->active_mm = &init_mm; | |
631 | if (me->mm) | |
632 | BUG(); | |
633 | enter_lazy_tlb(&init_mm, me); | |
634 | ||
635 | load_sp0(t, ¤t->thread); | |
636 | set_tss_desc(cpu, t); | |
637 | load_TR_desc(); | |
638 | load_LDT(&init_mm.context); | |
639 | ||
640 | #ifdef CONFIG_KGDB | |
641 | /* | |
642 | * If the kgdb is connected no debug regs should be altered. This | |
643 | * is only applicable when KGDB and a KGDB I/O module are built | |
644 | * into the kernel and you are using early debugging with | |
645 | * kgdbwait. KGDB will control the kernel HW breakpoint registers. | |
646 | */ | |
647 | if (kgdb_connected && arch_kgdb_ops.correct_hw_break) | |
648 | arch_kgdb_ops.correct_hw_break(); | |
649 | else { | |
650 | #endif | |
651 | /* | |
652 | * Clear all 6 debug registers: | |
653 | */ | |
654 | ||
655 | set_debugreg(0UL, 0); | |
656 | set_debugreg(0UL, 1); | |
657 | set_debugreg(0UL, 2); | |
658 | set_debugreg(0UL, 3); | |
659 | set_debugreg(0UL, 6); | |
660 | set_debugreg(0UL, 7); | |
661 | #ifdef CONFIG_KGDB | |
662 | /* If the kgdb is connected no debug regs should be altered. */ | |
663 | } | |
664 | #endif | |
665 | ||
666 | fpu_init(); | |
667 | ||
668 | raw_local_save_flags(kernel_eflags); | |
669 | ||
670 | if (is_uv_system()) | |
671 | uv_cpu_init(); | |
672 | } |