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f580366f | 1 | #include <linux/init.h> |
0f0124fa YL |
2 | #include <linux/kernel.h> |
3 | #include <linux/sched.h> | |
4 | #include <linux/string.h> | |
5 | #include <linux/bootmem.h> | |
6 | #include <linux/bitops.h> | |
7 | #include <linux/module.h> | |
8 | #include <linux/kgdb.h> | |
9 | #include <linux/topology.h> | |
f580366f YL |
10 | #include <linux/delay.h> |
11 | #include <linux/smp.h> | |
f580366f | 12 | #include <linux/percpu.h> |
f580366f YL |
13 | #include <asm/i387.h> |
14 | #include <asm/msr.h> | |
15 | #include <asm/io.h> | |
cbcd79c2 | 16 | #include <asm/linkage.h> |
f580366f YL |
17 | #include <asm/mmu_context.h> |
18 | #include <asm/mtrr.h> | |
19 | #include <asm/mce.h> | |
20 | #include <asm/pat.h> | |
7e00df58 | 21 | #include <asm/asm.h> |
f580366f YL |
22 | #include <asm/numa.h> |
23 | #ifdef CONFIG_X86_LOCAL_APIC | |
24 | #include <asm/mpspec.h> | |
25 | #include <asm/apic.h> | |
26 | #include <mach_apic.h> | |
f0fc4aff | 27 | #include <asm/genapic.h> |
f580366f | 28 | #endif |
0f0124fa YL |
29 | #include <asm/pda.h> |
30 | #include <asm/pgtable.h> | |
31 | #include <asm/processor.h> | |
32 | #include <asm/desc.h> | |
33 | #include <asm/atomic.h> | |
34 | #include <asm/proto.h> | |
35 | #include <asm/sections.h> | |
36 | #include <asm/setup.h> | |
f580366f YL |
37 | |
38 | #include "cpu.h" | |
39 | ||
0a488a53 YL |
40 | static struct cpu_dev *this_cpu __cpuinitdata; |
41 | ||
950ad7ff | 42 | #ifdef CONFIG_X86_64 |
f580366f YL |
43 | /* We need valid kernel segments for data and code in long mode too |
44 | * IRET will check the segment types kkeil 2000/10/28 | |
45 | * Also sysret mandates a special GDT layout | |
46 | */ | |
47 | /* The TLS descriptors are currently at a different place compared to i386. | |
48 | Hopefully nobody expects them at a fixed place (Wine?) */ | |
49 | DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = { | |
50 | [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } }, | |
51 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } }, | |
52 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } }, | |
53 | [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } }, | |
54 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } }, | |
55 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } }, | |
56 | } }; | |
950ad7ff YL |
57 | #else |
58 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { | |
59 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, | |
60 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, | |
61 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, | |
62 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, | |
63 | /* | |
64 | * Segments used for calling PnP BIOS have byte granularity. | |
65 | * They code segments and data segments have fixed 64k limits, | |
66 | * the transfer segment sizes are set at run time. | |
67 | */ | |
68 | /* 32-bit code */ | |
69 | [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, | |
70 | /* 16-bit code */ | |
71 | [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, | |
72 | /* 16-bit data */ | |
73 | [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, | |
74 | /* 16-bit data */ | |
75 | [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, | |
76 | /* 16-bit data */ | |
77 | [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, | |
78 | /* | |
79 | * The APM segments have byte granularity and their bases | |
80 | * are set at run time. All have 64k limits. | |
81 | */ | |
82 | /* 32-bit code */ | |
83 | [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, | |
84 | /* 16-bit code */ | |
85 | [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, | |
86 | /* data */ | |
87 | [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, | |
88 | ||
89 | [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, | |
90 | [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } }, | |
91 | } }; | |
92 | #endif | |
f580366f YL |
93 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
94 | ||
ba51dced YL |
95 | #ifdef CONFIG_X86_32 |
96 | static int cachesize_override __cpuinitdata = -1; | |
97 | static int disable_x86_serial_nr __cpuinitdata = 1; | |
98 | ||
99 | static int __init cachesize_setup(char *str) | |
100 | { | |
101 | get_option(&str, &cachesize_override); | |
102 | return 1; | |
103 | } | |
104 | __setup("cachesize=", cachesize_setup); | |
105 | ||
106 | /* | |
107 | * Naming convention should be: <Name> [(<Codename>)] | |
108 | * This table only is used unless init_<vendor>() below doesn't set it; | |
109 | * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used | |
110 | * | |
111 | */ | |
112 | ||
113 | /* Look up CPU names by table lookup. */ | |
114 | static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c) | |
115 | { | |
116 | struct cpu_model_info *info; | |
117 | ||
118 | if (c->x86_model >= 16) | |
119 | return NULL; /* Range check */ | |
120 | ||
121 | if (!this_cpu) | |
122 | return NULL; | |
123 | ||
124 | info = this_cpu->c_models; | |
125 | ||
126 | while (info && info->family) { | |
127 | if (info->family == c->x86) | |
128 | return info->model_names[c->x86_model]; | |
129 | info++; | |
130 | } | |
131 | return NULL; /* Not found */ | |
132 | } | |
133 | ||
134 | static int __init x86_fxsr_setup(char *s) | |
135 | { | |
136 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
137 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
138 | return 1; | |
139 | } | |
140 | __setup("nofxsr", x86_fxsr_setup); | |
141 | ||
142 | static int __init x86_sep_setup(char *s) | |
143 | { | |
144 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
145 | return 1; | |
146 | } | |
147 | __setup("nosep", x86_sep_setup); | |
148 | ||
149 | /* Standard macro to see if a specific flag is changeable */ | |
150 | static inline int flag_is_changeable_p(u32 flag) | |
151 | { | |
152 | u32 f1, f2; | |
153 | ||
154 | asm("pushfl\n\t" | |
155 | "pushfl\n\t" | |
156 | "popl %0\n\t" | |
157 | "movl %0,%1\n\t" | |
158 | "xorl %2,%0\n\t" | |
159 | "pushl %0\n\t" | |
160 | "popfl\n\t" | |
161 | "pushfl\n\t" | |
162 | "popl %0\n\t" | |
163 | "popfl\n\t" | |
164 | : "=&r" (f1), "=&r" (f2) | |
165 | : "ir" (flag)); | |
166 | ||
167 | return ((f1^f2) & flag) != 0; | |
168 | } | |
169 | ||
170 | /* Probe for the CPUID instruction */ | |
171 | static int __cpuinit have_cpuid_p(void) | |
172 | { | |
173 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
174 | } | |
175 | ||
176 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
177 | { | |
178 | if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) { | |
179 | /* Disable processor serial number */ | |
180 | unsigned long lo, hi; | |
181 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
182 | lo |= 0x200000; | |
183 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
184 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
185 | clear_cpu_cap(c, X86_FEATURE_PN); | |
186 | ||
187 | /* Disabling the serial number may affect the cpuid level */ | |
188 | c->cpuid_level = cpuid_eax(0); | |
189 | } | |
190 | } | |
191 | ||
192 | static int __init x86_serial_nr_setup(char *s) | |
193 | { | |
194 | disable_x86_serial_nr = 0; | |
195 | return 1; | |
196 | } | |
197 | __setup("serialnumber", x86_serial_nr_setup); | |
198 | #else | |
199 | /* Probe for the CPUID instruction */ | |
200 | static inline int have_cpuid_p(void) | |
201 | { | |
202 | return 1; | |
203 | } | |
204 | #endif | |
205 | ||
f580366f YL |
206 | __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; |
207 | ||
208 | /* Current gdt points %fs at the "master" per-cpu area: after this, | |
209 | * it's on the real one. */ | |
210 | void switch_to_new_gdt(void) | |
211 | { | |
212 | struct desc_ptr gdt_descr; | |
213 | ||
214 | gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id()); | |
215 | gdt_descr.size = GDT_SIZE - 1; | |
216 | load_gdt(&gdt_descr); | |
fab334c1 YL |
217 | #ifdef CONFIG_X86_32 |
218 | asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory"); | |
219 | #endif | |
f580366f YL |
220 | } |
221 | ||
10a434fc | 222 | static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
f580366f YL |
223 | |
224 | static void __cpuinit default_init(struct cpuinfo_x86 *c) | |
225 | { | |
226 | display_cacheinfo(c); | |
227 | } | |
228 | ||
229 | static struct cpu_dev __cpuinitdata default_cpu = { | |
230 | .c_init = default_init, | |
231 | .c_vendor = "Unknown", | |
10a434fc | 232 | .c_x86_vendor = X86_VENDOR_UNKNOWN, |
f580366f | 233 | }; |
f580366f YL |
234 | |
235 | int __cpuinit get_model_name(struct cpuinfo_x86 *c) | |
236 | { | |
237 | unsigned int *v; | |
01b2e16a | 238 | char *p, *q; |
f580366f YL |
239 | |
240 | if (c->extended_cpuid_level < 0x80000004) | |
241 | return 0; | |
242 | ||
243 | v = (unsigned int *) c->x86_model_id; | |
244 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
245 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
246 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
247 | c->x86_model_id[48] = 0; | |
01b2e16a YL |
248 | |
249 | /* Intel chips right-justify this string for some dumb reason; | |
250 | undo that brain damage */ | |
251 | p = q = &c->x86_model_id[0]; | |
252 | while (*p == ' ') | |
253 | p++; | |
254 | if (p != q) { | |
255 | while (*p) | |
256 | *q++ = *p++; | |
257 | while (q <= &c->x86_model_id[48]) | |
258 | *q++ = '\0'; /* Zero-pad the rest */ | |
259 | } | |
260 | ||
f580366f YL |
261 | return 1; |
262 | } | |
263 | ||
264 | ||
265 | void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) | |
266 | { | |
0a488a53 | 267 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
f580366f YL |
268 | |
269 | n = c->extended_cpuid_level; | |
270 | ||
271 | if (n >= 0x80000005) { | |
272 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); | |
9d31d35b YL |
273 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", |
274 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); | |
f580366f YL |
275 | c->x86_cache_size = (ecx>>24) + (edx>>24); |
276 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
277 | c->x86_tlbsize = 0; | |
278 | } | |
279 | ||
0a488a53 YL |
280 | if (n < 0x80000006) /* Some chips just has a large L1. */ |
281 | return; | |
f580366f | 282 | |
0a488a53 YL |
283 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
284 | l2size = ecx >> 16; | |
285 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
286 | ||
287 | c->x86_cache_size = l2size; | |
288 | ||
289 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
290 | l2size, ecx & 0xFF); | |
f580366f YL |
291 | } |
292 | ||
293 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) | |
294 | { | |
97e4db7c | 295 | #ifdef CONFIG_X86_HT |
f580366f YL |
296 | u32 eax, ebx, ecx, edx; |
297 | int index_msb, core_bits; | |
298 | ||
f580366f YL |
299 | if (!cpu_has(c, X86_FEATURE_HT)) |
300 | return; | |
301 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) | |
302 | goto out; | |
303 | ||
90427638 IM |
304 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
305 | return; | |
306 | ||
0a488a53 YL |
307 | cpuid(1, &eax, &ebx, &ecx, &edx); |
308 | ||
f580366f YL |
309 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
310 | ||
311 | if (smp_num_siblings == 1) { | |
312 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
313 | } else if (smp_num_siblings > 1) { | |
314 | ||
315 | if (smp_num_siblings > NR_CPUS) { | |
9d31d35b YL |
316 | printk(KERN_WARNING "CPU: Unsupported number of siblings %d", |
317 | smp_num_siblings); | |
f580366f YL |
318 | smp_num_siblings = 1; |
319 | return; | |
320 | } | |
321 | ||
322 | index_msb = get_count_order(smp_num_siblings); | |
323 | c->phys_proc_id = phys_pkg_id(index_msb); | |
324 | ||
325 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; | |
326 | ||
327 | index_msb = get_count_order(smp_num_siblings); | |
328 | ||
329 | core_bits = get_count_order(c->x86_max_cores); | |
330 | ||
331 | c->cpu_core_id = phys_pkg_id(index_msb) & | |
332 | ((1 << core_bits) - 1); | |
333 | } | |
0a488a53 | 334 | |
f580366f YL |
335 | out: |
336 | if ((c->x86_max_cores * smp_num_siblings) > 1) { | |
337 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
338 | c->phys_proc_id); | |
339 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
340 | c->cpu_core_id); | |
341 | } | |
f580366f YL |
342 | #endif |
343 | } | |
344 | ||
345 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) | |
346 | { | |
347 | char *v = c->x86_vendor_id; | |
348 | int i; | |
349 | static int printed; | |
350 | ||
351 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
352 | if (!cpu_devs[i]) |
353 | break; | |
354 | ||
355 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
356 | (cpu_devs[i]->c_ident[1] && | |
357 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
358 | this_cpu = cpu_devs[i]; | |
359 | c->x86_vendor = this_cpu->c_x86_vendor; | |
360 | return; | |
f580366f YL |
361 | } |
362 | } | |
10a434fc | 363 | |
f580366f YL |
364 | if (!printed) { |
365 | printed++; | |
366 | printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n"); | |
367 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); | |
368 | } | |
10a434fc | 369 | |
f580366f | 370 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
3da99c97 | 371 | this_cpu = &default_cpu; |
f580366f YL |
372 | } |
373 | ||
3da99c97 | 374 | void __cpuinit cpu_detect(struct cpuinfo_x86 *c) |
f580366f | 375 | { |
f580366f YL |
376 | /* Get vendor name */ |
377 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, | |
378 | (unsigned int *)&c->x86_vendor_id[0], | |
379 | (unsigned int *)&c->x86_vendor_id[8], | |
380 | (unsigned int *)&c->x86_vendor_id[4]); | |
381 | ||
9d31d35b | 382 | c->x86 = 4; |
f580366f YL |
383 | /* Intel-defined flags: level 0x00000001 */ |
384 | if (c->cpuid_level >= 0x00000001) { | |
3da99c97 YL |
385 | u32 junk, tfms, cap0, misc; |
386 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
f580366f YL |
387 | c->x86 = (tfms >> 8) & 0xf; |
388 | c->x86_model = (tfms >> 4) & 0xf; | |
389 | c->x86_mask = tfms & 0xf; | |
390 | if (c->x86 == 0xf) | |
391 | c->x86 += (tfms >> 20) & 0xff; | |
392 | if (c->x86 >= 0x6) | |
9d31d35b YL |
393 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
394 | if (cap0 & (1<<19)) { | |
f580366f | 395 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b YL |
396 | c->x86_cache_alignment = c->x86_clflush_size; |
397 | } | |
f580366f | 398 | } |
3da99c97 YL |
399 | } |
400 | ||
401 | ||
402 | static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) | |
403 | { | |
404 | u32 tfms, xlvl; | |
405 | u32 ebx; | |
406 | ||
3da99c97 YL |
407 | /* Intel-defined flags: level 0x00000001 */ |
408 | if (c->cpuid_level >= 0x00000001) { | |
409 | u32 capability, excap; | |
410 | ||
411 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); | |
412 | c->x86_capability[0] = capability; | |
413 | c->x86_capability[4] = excap; | |
414 | } | |
f580366f | 415 | |
f580366f YL |
416 | /* AMD-defined flags: level 0x80000001 */ |
417 | xlvl = cpuid_eax(0x80000000); | |
418 | c->extended_cpuid_level = xlvl; | |
419 | if ((xlvl & 0xffff0000) == 0x80000000) { | |
420 | if (xlvl >= 0x80000001) { | |
421 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
422 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
423 | } | |
f580366f YL |
424 | } |
425 | ||
426 | /* Transmeta-defined flags: level 0x80860001 */ | |
427 | xlvl = cpuid_eax(0x80860000); | |
428 | if ((xlvl & 0xffff0000) == 0x80860000) { | |
429 | /* Don't set x86_cpuid_level here for now to not confuse. */ | |
430 | if (xlvl >= 0x80860001) | |
431 | c->x86_capability[2] = cpuid_edx(0x80860001); | |
432 | } | |
433 | ||
f580366f YL |
434 | if (c->extended_cpuid_level >= 0x80000007) |
435 | c->x86_power = cpuid_edx(0x80000007); | |
436 | ||
87a1c441 YL |
437 | if (c->extended_cpuid_level >= 0x80000008) { |
438 | u32 eax = cpuid_eax(0x80000008); | |
439 | ||
440 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
441 | c->x86_phys_bits = eax & 0xff; | |
442 | } | |
f580366f YL |
443 | } |
444 | ||
3da99c97 YL |
445 | /* Do some early cpuid on the boot CPU to get some parameter that are |
446 | needed before check_bugs. Everything advanced is in identify_cpu | |
447 | below. */ | |
448 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) | |
f580366f | 449 | { |
3da99c97 YL |
450 | |
451 | c->x86_clflush_size = 64; | |
452 | c->x86_cache_alignment = c->x86_clflush_size; | |
453 | ||
454 | memset(&c->x86_capability, 0, sizeof c->x86_capability); | |
455 | ||
456 | c->extended_cpuid_level = 0; | |
457 | ||
458 | cpu_detect(c); | |
459 | ||
460 | get_cpu_vendor(c); | |
461 | ||
462 | get_cpu_cap(c); | |
7e00df58 | 463 | |
10a434fc YL |
464 | if (this_cpu->c_early_init) |
465 | this_cpu->c_early_init(c); | |
f580366f YL |
466 | |
467 | validate_pat_support(c); | |
f580366f YL |
468 | } |
469 | ||
3da99c97 YL |
470 | void __init early_cpu_init(void) |
471 | { | |
10a434fc YL |
472 | struct cpu_dev **cdev; |
473 | int count = 0; | |
f580366f YL |
474 | |
475 | printk("KERNEL supported cpus:\n"); | |
10a434fc YL |
476 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { |
477 | struct cpu_dev *cpudev = *cdev; | |
478 | unsigned int j; | |
3da99c97 | 479 | |
10a434fc YL |
480 | if (count >= X86_VENDOR_NUM) |
481 | break; | |
482 | cpu_devs[count] = cpudev; | |
483 | count++; | |
484 | ||
f580366f | 485 | for (j = 0; j < 2; j++) { |
10a434fc | 486 | if (!cpudev->c_ident[j]) |
f580366f | 487 | continue; |
10a434fc YL |
488 | printk(" %s %s\n", cpudev->c_vendor, |
489 | cpudev->c_ident[j]); | |
f580366f YL |
490 | } |
491 | } | |
3da99c97 | 492 | |
3da99c97 | 493 | early_identify_cpu(&boot_cpu_data); |
f580366f YL |
494 | } |
495 | ||
7e00df58 PA |
496 | /* |
497 | * The NOPL instruction is supposed to exist on all CPUs with | |
498 | * family >= 6, unfortunately, that's not true in practice because | |
499 | * of early VIA chips and (more importantly) broken virtualizers that | |
500 | * are not easy to detect. Hence, probe for it based on first | |
501 | * principles. | |
502 | * | |
503 | * Note: no 64-bit chip is known to lack these, but put the code here | |
504 | * for consistency with 32 bits, and to make it utterly trivial to | |
505 | * diagnose the problem should it ever surface. | |
506 | */ | |
507 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
508 | { | |
509 | const u32 nopl_signature = 0x888c53b1; /* Random number */ | |
510 | u32 has_nopl = nopl_signature; | |
511 | ||
512 | clear_cpu_cap(c, X86_FEATURE_NOPL); | |
513 | if (c->x86 >= 6) { | |
514 | asm volatile("\n" | |
515 | "1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */ | |
516 | "2:\n" | |
517 | " .section .fixup,\"ax\"\n" | |
518 | "3: xor %0,%0\n" | |
519 | " jmp 2b\n" | |
520 | " .previous\n" | |
521 | _ASM_EXTABLE(1b,3b) | |
522 | : "+a" (has_nopl)); | |
523 | ||
524 | if (has_nopl == nopl_signature) | |
525 | set_cpu_cap(c, X86_FEATURE_NOPL); | |
526 | } | |
527 | } | |
528 | ||
3da99c97 | 529 | static void __cpuinit generic_identify(struct cpuinfo_x86 *c) |
f580366f | 530 | { |
f580366f | 531 | c->extended_cpuid_level = 0; |
f580366f | 532 | |
3da99c97 | 533 | cpu_detect(c); |
f580366f YL |
534 | |
535 | get_cpu_vendor(c); | |
536 | ||
3da99c97 | 537 | get_cpu_cap(c); |
f580366f YL |
538 | |
539 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xff; | |
540 | #ifdef CONFIG_SMP | |
541 | c->phys_proc_id = c->initial_apicid; | |
542 | #endif | |
f580366f | 543 | |
3da99c97 YL |
544 | if (c->extended_cpuid_level >= 0x80000004) |
545 | get_model_name(c); /* Default name */ | |
87a1c441 | 546 | |
3da99c97 | 547 | init_scattered_cpuid_features(c); |
7e00df58 | 548 | detect_nopl(c); |
f580366f YL |
549 | } |
550 | ||
551 | /* | |
552 | * This does the hard work of actually picking apart the CPU stuff... | |
553 | */ | |
9a250347 | 554 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
f580366f YL |
555 | { |
556 | int i; | |
557 | ||
3da99c97 YL |
558 | c->loops_per_jiffy = loops_per_jiffy; |
559 | c->x86_cache_size = -1; | |
560 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
561 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ | |
562 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
563 | c->x86_model_id[0] = '\0'; /* Unset */ | |
3da99c97 YL |
564 | c->x86_max_cores = 1; |
565 | c->x86_coreid_bits = 0; | |
0a488a53 YL |
566 | c->x86_clflush_size = 64; |
567 | c->x86_cache_alignment = c->x86_clflush_size; | |
3da99c97 | 568 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
f580366f | 569 | |
3da99c97 | 570 | generic_identify(c); |
f580366f YL |
571 | |
572 | c->apicid = phys_pkg_id(0); | |
573 | ||
574 | /* | |
575 | * Vendor-specific initialization. In this section we | |
576 | * canonicalize the feature flags, meaning if there are | |
577 | * features a certain CPU supports which CPUID doesn't | |
578 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
579 | * we handle them here. | |
580 | * | |
581 | * At the end of this section, c->x86_capability better | |
582 | * indicate the features this CPU genuinely supports! | |
583 | */ | |
584 | if (this_cpu->c_init) | |
585 | this_cpu->c_init(c); | |
586 | ||
587 | detect_ht(c); | |
588 | ||
589 | /* | |
590 | * On SMP, boot_cpu_data holds the common feature set between | |
591 | * all CPUs; so make sure that we indicate which features are | |
592 | * common between the CPUs. The first time this routine gets | |
593 | * executed, c == &boot_cpu_data. | |
594 | */ | |
595 | if (c != &boot_cpu_data) { | |
596 | /* AND the already accumulated flags with these */ | |
597 | for (i = 0; i < NCAPINTS; i++) | |
598 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; | |
599 | } | |
600 | ||
601 | /* Clear all flags overriden by options */ | |
602 | for (i = 0; i < NCAPINTS; i++) | |
603 | c->x86_capability[i] &= ~cleared_cpu_caps[i]; | |
604 | ||
605 | #ifdef CONFIG_X86_MCE | |
606 | mcheck_init(c); | |
607 | #endif | |
608 | select_idle_routine(c); | |
609 | ||
610 | #ifdef CONFIG_NUMA | |
611 | numa_add_cpu(smp_processor_id()); | |
612 | #endif | |
613 | ||
614 | } | |
615 | ||
9d31d35b | 616 | void __init identify_boot_cpu(void) |
f580366f YL |
617 | { |
618 | identify_cpu(&boot_cpu_data); | |
619 | } | |
620 | ||
621 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) | |
622 | { | |
623 | BUG_ON(c == &boot_cpu_data); | |
624 | identify_cpu(c); | |
625 | mtrr_ap_init(); | |
626 | } | |
627 | ||
b05f78f5 YL |
628 | struct msr_range { |
629 | unsigned min; | |
630 | unsigned max; | |
631 | }; | |
632 | ||
633 | static struct msr_range msr_range_array[] __cpuinitdata = { | |
634 | { 0x00000000, 0x00000418}, | |
635 | { 0xc0000000, 0xc000040b}, | |
636 | { 0xc0010000, 0xc0010142}, | |
637 | { 0xc0011000, 0xc001103b}, | |
638 | }; | |
639 | ||
640 | static void __cpuinit print_cpu_msr(void) | |
641 | { | |
642 | unsigned index; | |
643 | u64 val; | |
644 | int i; | |
645 | unsigned index_min, index_max; | |
646 | ||
647 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
648 | index_min = msr_range_array[i].min; | |
649 | index_max = msr_range_array[i].max; | |
650 | for (index = index_min; index < index_max; index++) { | |
651 | if (rdmsrl_amd_safe(index, &val)) | |
652 | continue; | |
653 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
654 | } | |
655 | } | |
656 | } | |
657 | ||
658 | static int show_msr __cpuinitdata; | |
659 | static __init int setup_show_msr(char *arg) | |
660 | { | |
661 | int num; | |
662 | ||
663 | get_option(&arg, &num); | |
664 | ||
665 | if (num > 0) | |
666 | show_msr = num; | |
667 | return 1; | |
668 | } | |
669 | __setup("show_msr=", setup_show_msr); | |
670 | ||
f580366f YL |
671 | static __init int setup_noclflush(char *arg) |
672 | { | |
673 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
674 | return 1; | |
675 | } | |
676 | __setup("noclflush", setup_noclflush); | |
677 | ||
678 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) | |
679 | { | |
680 | if (c->x86_model_id[0]) | |
681 | printk(KERN_CONT "%s", c->x86_model_id); | |
682 | ||
683 | if (c->x86_mask || c->cpuid_level >= 0) | |
684 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); | |
685 | else | |
686 | printk(KERN_CONT "\n"); | |
b05f78f5 YL |
687 | |
688 | #ifdef CONFIG_SMP | |
689 | if (c->cpu_index < show_msr) | |
690 | print_cpu_msr(); | |
691 | #else | |
692 | if (show_msr) | |
693 | print_cpu_msr(); | |
694 | #endif | |
f580366f YL |
695 | } |
696 | ||
697 | static __init int setup_disablecpuid(char *arg) | |
698 | { | |
699 | int bit; | |
700 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) | |
701 | setup_clear_cpu_cap(bit); | |
702 | else | |
703 | return 0; | |
704 | return 1; | |
705 | } | |
706 | __setup("clearcpuid=", setup_disablecpuid); | |
0f0124fa | 707 | |
0f0124fa YL |
708 | cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE; |
709 | ||
d5494d4f | 710 | #ifdef CONFIG_X86_64 |
0f0124fa YL |
711 | struct x8664_pda **_cpu_pda __read_mostly; |
712 | EXPORT_SYMBOL(_cpu_pda); | |
713 | ||
714 | struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; | |
715 | ||
716 | char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss; | |
717 | ||
718 | unsigned long __supported_pte_mask __read_mostly = ~0UL; | |
719 | EXPORT_SYMBOL_GPL(__supported_pte_mask); | |
720 | ||
721 | static int do_not_nx __cpuinitdata; | |
722 | ||
723 | /* noexec=on|off | |
724 | Control non executable mappings for 64bit processes. | |
725 | ||
726 | on Enable(default) | |
727 | off Disable | |
728 | */ | |
729 | static int __init nonx_setup(char *str) | |
730 | { | |
731 | if (!str) | |
732 | return -EINVAL; | |
733 | if (!strncmp(str, "on", 2)) { | |
734 | __supported_pte_mask |= _PAGE_NX; | |
735 | do_not_nx = 0; | |
736 | } else if (!strncmp(str, "off", 3)) { | |
737 | do_not_nx = 1; | |
738 | __supported_pte_mask &= ~_PAGE_NX; | |
739 | } | |
740 | return 0; | |
741 | } | |
742 | early_param("noexec", nonx_setup); | |
743 | ||
744 | int force_personality32; | |
745 | ||
746 | /* noexec32=on|off | |
747 | Control non executable heap for 32bit processes. | |
748 | To control the stack too use noexec=off | |
749 | ||
750 | on PROT_READ does not imply PROT_EXEC for 32bit processes (default) | |
751 | off PROT_READ implies PROT_EXEC | |
752 | */ | |
753 | static int __init nonx32_setup(char *str) | |
754 | { | |
755 | if (!strcmp(str, "on")) | |
756 | force_personality32 &= ~READ_IMPLIES_EXEC; | |
757 | else if (!strcmp(str, "off")) | |
758 | force_personality32 |= READ_IMPLIES_EXEC; | |
759 | return 1; | |
760 | } | |
761 | __setup("noexec32=", nonx32_setup); | |
762 | ||
763 | void pda_init(int cpu) | |
764 | { | |
765 | struct x8664_pda *pda = cpu_pda(cpu); | |
766 | ||
767 | /* Setup up data that may be needed in __get_free_pages early */ | |
ada85708 JF |
768 | loadsegment(fs, 0); |
769 | loadsegment(gs, 0); | |
0f0124fa YL |
770 | /* Memory clobbers used to order PDA accessed */ |
771 | mb(); | |
772 | wrmsrl(MSR_GS_BASE, pda); | |
773 | mb(); | |
774 | ||
775 | pda->cpunumber = cpu; | |
776 | pda->irqcount = -1; | |
777 | pda->kernelstack = (unsigned long)stack_thread_info() - | |
778 | PDA_STACKOFFSET + THREAD_SIZE; | |
779 | pda->active_mm = &init_mm; | |
780 | pda->mmu_state = 0; | |
781 | ||
782 | if (cpu == 0) { | |
783 | /* others are initialized in smpboot.c */ | |
784 | pda->pcurrent = &init_task; | |
785 | pda->irqstackptr = boot_cpu_stack; | |
49800efc | 786 | pda->irqstackptr += IRQSTACKSIZE - 64; |
0f0124fa | 787 | } else { |
49800efc AH |
788 | if (!pda->irqstackptr) { |
789 | pda->irqstackptr = (char *) | |
790 | __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER); | |
791 | if (!pda->irqstackptr) | |
792 | panic("cannot allocate irqstack for cpu %d", | |
793 | cpu); | |
794 | pda->irqstackptr += IRQSTACKSIZE - 64; | |
795 | } | |
0f0124fa YL |
796 | |
797 | if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE) | |
798 | pda->nodenumber = cpu_to_node(cpu); | |
799 | } | |
0f0124fa YL |
800 | } |
801 | ||
802 | char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + | |
cbcd79c2 | 803 | DEBUG_STKSZ] __page_aligned_bss; |
0f0124fa YL |
804 | |
805 | extern asmlinkage void ignore_sysret(void); | |
806 | ||
807 | /* May not be marked __init: used by software suspend */ | |
808 | void syscall_init(void) | |
809 | { | |
810 | /* | |
811 | * LSTAR and STAR live in a bit strange symbiosis. | |
812 | * They both write to the same internal register. STAR allows to | |
813 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
814 | */ | |
815 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
816 | wrmsrl(MSR_LSTAR, system_call); | |
817 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
818 | ||
819 | #ifdef CONFIG_IA32_EMULATION | |
820 | syscall32_cpu_init(); | |
821 | #endif | |
822 | ||
823 | /* Flags to clear on syscall */ | |
824 | wrmsrl(MSR_SYSCALL_MASK, | |
825 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); | |
826 | } | |
827 | ||
828 | void __cpuinit check_efer(void) | |
829 | { | |
830 | unsigned long efer; | |
831 | ||
832 | rdmsrl(MSR_EFER, efer); | |
833 | if (!(efer & EFER_NX) || do_not_nx) | |
834 | __supported_pte_mask &= ~_PAGE_NX; | |
835 | } | |
836 | ||
837 | unsigned long kernel_eflags; | |
838 | ||
839 | /* | |
840 | * Copies of the original ist values from the tss are only accessed during | |
841 | * debugging, no special alignment required. | |
842 | */ | |
843 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
844 | ||
d5494d4f YL |
845 | #else |
846 | ||
847 | /* Make sure %fs is initialized properly in idle threads */ | |
848 | struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) | |
849 | { | |
850 | memset(regs, 0, sizeof(struct pt_regs)); | |
851 | regs->fs = __KERNEL_PERCPU; | |
852 | return regs; | |
853 | } | |
854 | #endif | |
855 | ||
0f0124fa YL |
856 | /* |
857 | * cpu_init() initializes state that is per-CPU. Some data is already | |
858 | * initialized (naturally) in the bootstrap process, such as the GDT | |
859 | * and IDT. We reload them nevertheless, this function acts as a | |
860 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 861 | * A lot of state is already set up in PDA init for 64 bit |
0f0124fa | 862 | */ |
1ba76586 | 863 | #ifdef CONFIG_X86_64 |
0f0124fa YL |
864 | void __cpuinit cpu_init(void) |
865 | { | |
866 | int cpu = stack_smp_processor_id(); | |
867 | struct tss_struct *t = &per_cpu(init_tss, cpu); | |
868 | struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu); | |
869 | unsigned long v; | |
870 | char *estacks = NULL; | |
871 | struct task_struct *me; | |
872 | int i; | |
873 | ||
874 | /* CPU 0 is initialised in head64.c */ | |
875 | if (cpu != 0) | |
876 | pda_init(cpu); | |
877 | else | |
878 | estacks = boot_exception_stacks; | |
879 | ||
880 | me = current; | |
881 | ||
882 | if (cpu_test_and_set(cpu, cpu_initialized)) | |
883 | panic("CPU#%d already initialized!\n", cpu); | |
884 | ||
885 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
886 | ||
887 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
888 | ||
889 | /* | |
890 | * Initialize the per-CPU GDT with the boot GDT, | |
891 | * and set up the GDT descriptor: | |
892 | */ | |
893 | ||
894 | switch_to_new_gdt(); | |
895 | load_idt((const struct desc_ptr *)&idt_descr); | |
896 | ||
897 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
898 | syscall_init(); | |
899 | ||
900 | wrmsrl(MSR_FS_BASE, 0); | |
901 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
902 | barrier(); | |
903 | ||
904 | check_efer(); | |
6e1cb38a SS |
905 | if (cpu != 0 && x2apic) |
906 | enable_x2apic(); | |
0f0124fa YL |
907 | |
908 | /* | |
909 | * set up and load the per-CPU TSS | |
910 | */ | |
b55793f7 | 911 | if (!orig_ist->ist[0]) { |
0f0124fa | 912 | static const unsigned int order[N_EXCEPTION_STACKS] = { |
b55793f7 AH |
913 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER, |
914 | [DEBUG_STACK - 1] = DEBUG_STACK_ORDER | |
0f0124fa | 915 | }; |
b55793f7 AH |
916 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
917 | if (cpu) { | |
918 | estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]); | |
919 | if (!estacks) | |
920 | panic("Cannot allocate exception " | |
921 | "stack %ld %d\n", v, cpu); | |
922 | } | |
923 | estacks += PAGE_SIZE << order[v]; | |
924 | orig_ist->ist[v] = t->x86_tss.ist[v] = | |
925 | (unsigned long)estacks; | |
0f0124fa | 926 | } |
0f0124fa YL |
927 | } |
928 | ||
929 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
930 | /* | |
931 | * <= is required because the CPU will access up to | |
932 | * 8 bits beyond the end of the IO permission bitmap. | |
933 | */ | |
934 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
935 | t->io_bitmap[i] = ~0UL; | |
936 | ||
937 | atomic_inc(&init_mm.mm_count); | |
938 | me->active_mm = &init_mm; | |
939 | if (me->mm) | |
940 | BUG(); | |
941 | enter_lazy_tlb(&init_mm, me); | |
942 | ||
943 | load_sp0(t, ¤t->thread); | |
944 | set_tss_desc(cpu, t); | |
945 | load_TR_desc(); | |
946 | load_LDT(&init_mm.context); | |
947 | ||
948 | #ifdef CONFIG_KGDB | |
949 | /* | |
950 | * If the kgdb is connected no debug regs should be altered. This | |
951 | * is only applicable when KGDB and a KGDB I/O module are built | |
952 | * into the kernel and you are using early debugging with | |
953 | * kgdbwait. KGDB will control the kernel HW breakpoint registers. | |
954 | */ | |
955 | if (kgdb_connected && arch_kgdb_ops.correct_hw_break) | |
956 | arch_kgdb_ops.correct_hw_break(); | |
957 | else { | |
958 | #endif | |
959 | /* | |
960 | * Clear all 6 debug registers: | |
961 | */ | |
962 | ||
963 | set_debugreg(0UL, 0); | |
964 | set_debugreg(0UL, 1); | |
965 | set_debugreg(0UL, 2); | |
966 | set_debugreg(0UL, 3); | |
967 | set_debugreg(0UL, 6); | |
968 | set_debugreg(0UL, 7); | |
969 | #ifdef CONFIG_KGDB | |
970 | /* If the kgdb is connected no debug regs should be altered. */ | |
971 | } | |
972 | #endif | |
973 | ||
974 | fpu_init(); | |
975 | ||
976 | raw_local_save_flags(kernel_eflags); | |
977 | ||
978 | if (is_uv_system()) | |
979 | uv_cpu_init(); | |
980 | } | |
1ba76586 YL |
981 | |
982 | #else | |
983 | ||
984 | void __cpuinit cpu_init(void) | |
985 | { | |
986 | int cpu = smp_processor_id(); | |
987 | struct task_struct *curr = current; | |
988 | struct tss_struct *t = &per_cpu(init_tss, cpu); | |
989 | struct thread_struct *thread = &curr->thread; | |
990 | ||
991 | if (cpu_test_and_set(cpu, cpu_initialized)) { | |
992 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); | |
993 | for (;;) local_irq_enable(); | |
994 | } | |
995 | ||
996 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
997 | ||
998 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
999 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
1000 | ||
1001 | load_idt(&idt_descr); | |
1002 | switch_to_new_gdt(); | |
1003 | ||
1004 | /* | |
1005 | * Set up and load the per-CPU TSS and LDT | |
1006 | */ | |
1007 | atomic_inc(&init_mm.mm_count); | |
1008 | curr->active_mm = &init_mm; | |
1009 | if (curr->mm) | |
1010 | BUG(); | |
1011 | enter_lazy_tlb(&init_mm, curr); | |
1012 | ||
1013 | load_sp0(t, thread); | |
1014 | set_tss_desc(cpu, t); | |
1015 | load_TR_desc(); | |
1016 | load_LDT(&init_mm.context); | |
1017 | ||
1018 | #ifdef CONFIG_DOUBLEFAULT | |
1019 | /* Set up doublefault TSS pointer in the GDT */ | |
1020 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
1021 | #endif | |
1022 | ||
1023 | /* Clear %gs. */ | |
1024 | asm volatile ("mov %0, %%gs" : : "r" (0)); | |
1025 | ||
1026 | /* Clear all 6 debug registers: */ | |
1027 | set_debugreg(0, 0); | |
1028 | set_debugreg(0, 1); | |
1029 | set_debugreg(0, 2); | |
1030 | set_debugreg(0, 3); | |
1031 | set_debugreg(0, 6); | |
1032 | set_debugreg(0, 7); | |
1033 | ||
1034 | /* | |
1035 | * Force FPU initialization: | |
1036 | */ | |
1037 | if (cpu_has_xsave) | |
1038 | current_thread_info()->status = TS_XSAVE; | |
1039 | else | |
1040 | current_thread_info()->status = 0; | |
1041 | clear_used_math(); | |
1042 | mxcsr_feature_mask_init(); | |
1043 | ||
1044 | /* | |
1045 | * Boot processor to setup the FP and extended state context info. | |
1046 | */ | |
1047 | if (!smp_processor_id()) | |
1048 | init_thread_xstate(); | |
1049 | ||
1050 | xsave_init(); | |
1051 | } | |
1052 | ||
1053 | #ifdef CONFIG_HOTPLUG_CPU | |
1054 | void __cpuinit cpu_uninit(void) | |
1055 | { | |
1056 | int cpu = raw_smp_processor_id(); | |
1057 | cpu_clear(cpu, cpu_initialized); | |
1058 | ||
1059 | /* lazy TLB state */ | |
1060 | per_cpu(cpu_tlbstate, cpu).state = 0; | |
1061 | per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm; | |
1062 | } | |
1063 | #endif | |
1064 | ||
1065 | #endif |