[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kernel / cpu / cpufreq / p4-clockmod.c

/*
 *	Pentium 4/Xeon CPU on demand clock modulation/speed scaling
 *	(C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
 *	(C) 2002 Zwane Mwaikambo <zwane@commfireservices.com>
 *	(C) 2002 Arjan van de Ven <arjanv@redhat.com>
 *	(C) 2002 Tora T. Engstad
 *	All Rights Reserved
 *
 *	This program is free software; you can redistribute it and/or
 *      modify it under the terms of the GNU General Public License
 *      as published by the Free Software Foundation; either version
 *      2 of the License, or (at your option) any later version.
 *
 *      The author(s) of this software shall not be held liable for damages
 *      of any nature resulting due to the use of this software. This
 *      software is provided AS-IS with no warranties.
 *
 *	Date		Errata			Description
 *	20020525	N44, O17	12.5% or 25% DC causes lockup
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/cpufreq.h>
#include <linux/slab.h>
#include <linux/cpumask.h>
#include <linux/timex.h>

#include <asm/processor.h>
#include <asm/msr.h>
#include <asm/timer.h>

#include "speedstep-lib.h"

#define PFX	"p4-clockmod: "
#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, \
		"p4-clockmod", msg)

/*
 * Duty Cycle (3bits), note DC_DISABLE is not specified in
 * intel docs i just use it to mean disable
 */
enum {
	DC_RESV, DC_DFLT, DC_25PT, DC_38PT, DC_50PT,
	DC_64PT, DC_75PT, DC_88PT, DC_DISABLE
};

#define DC_ENTRIES	8


static int has_N44_O17_errata[NR_CPUS];
static unsigned int stock_freq;
static struct cpufreq_driver p4clockmod_driver;
static unsigned int cpufreq_p4_get(unsigned int cpu);

static int cpufreq_p4_setdc(unsigned int cpu, unsigned int newstate)
{
	u32 l, h;

	if (!cpu_online(cpu) ||
	    (newstate > DC_DISABLE) || (newstate == DC_RESV))
		return -EINVAL;

	rdmsr_on_cpu(cpu, MSR_IA32_THERM_STATUS, &l, &h);

	if (l & 0x01)
		dprintk("CPU#%d currently thermal throttled\n", cpu);

	if (has_N44_O17_errata[cpu] &&
	    (newstate == DC_25PT || newstate == DC_DFLT))
		newstate = DC_38PT;

	rdmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &l, &h);
	if (newstate == DC_DISABLE) {
		dprintk("CPU#%d disabling modulation\n", cpu);
		wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, l & ~(1<<4), h);
	} else {
		dprintk("CPU#%d setting duty cycle to %d%%\n",
			cpu, ((125 * newstate) / 10));
		/* bits 63 - 5	: reserved
		 * bit  4	: enable/disable
		 * bits 3-1	: duty cycle
		 * bit  0	: reserved
		 */
		l = (l & ~14);
		l = l | (1<<4) | ((newstate & 0x7)<<1);
		wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, l, h);
	}

	return 0;
}


static struct cpufreq_frequency_table p4clockmod_table[] = {
	{DC_RESV, CPUFREQ_ENTRY_INVALID},
	{DC_DFLT, 0},
	{DC_25PT, 0},
	{DC_38PT, 0},
	{DC_50PT, 0},
	{DC_64PT, 0},
	{DC_75PT, 0},
	{DC_88PT, 0},
	{DC_DISABLE, 0},
	{DC_RESV, CPUFREQ_TABLE_END},
};


static int cpufreq_p4_target(struct cpufreq_policy *policy,
			     unsigned int target_freq,
			     unsigned int relation)
{
	unsigned int    newstate = DC_RESV;
	struct cpufreq_freqs freqs;
	int i;

	if (cpufreq_frequency_table_target(policy, &p4clockmod_table[0],
				target_freq, relation, &newstate))
		return -EINVAL;

	freqs.old = cpufreq_p4_get(policy->cpu);
	freqs.new = stock_freq * p4clockmod_table[newstate].index / 8;

	if (freqs.new == freqs.old)
		return 0;

	/* notifiers */
	for_each_cpu(i, policy->cpus) {
		freqs.cpu = i;
		cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
	}

	/* run on each logical CPU,
	 * see section 13.15.3 of IA32 Intel Architecture Software
	 * Developer's Manual, Volume 3
	 */
	for_each_cpu(i, policy->cpus)
		cpufreq_p4_setdc(i, p4clockmod_table[newstate].index);

	/* notifiers */
	for_each_cpu(i, policy->cpus) {
		freqs.cpu = i;
		cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
	}

	return 0;
}


static int cpufreq_p4_verify(struct cpufreq_policy *policy)
{
	return cpufreq_frequency_table_verify(policy, &p4clockmod_table[0]);
}


static unsigned int cpufreq_p4_get_frequency(struct cpuinfo_x86 *c)
{
	if (c->x86 == 0x06) {
		if (cpu_has(c, X86_FEATURE_EST))
			printk(KERN_WARNING PFX "Warning: EST-capable CPU "
			       "detected. The acpi-cpufreq module offers "
			       "voltage scaling in addition of frequency "
			       "scaling. You should use that instead of "
			       "p4-clockmod, if possible.\n");
		switch (c->x86_model) {
		case 0x0E: /* Core */
		case 0x0F: /* Core Duo */
		case 0x16: /* Celeron Core */
		case 0x1C: /* Atom */
			p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS;
			return speedstep_get_frequency(SPEEDSTEP_CPU_PCORE);
		case 0x0D: /* Pentium M (Dothan) */
			p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS;
			/* fall through */
		case 0x09: /* Pentium M (Banias) */
			return speedstep_get_frequency(SPEEDSTEP_CPU_PM);
		}
	}

	if (c->x86 != 0xF) {
		if (!cpu_has(c, X86_FEATURE_EST))
			printk(KERN_WARNING PFX "Unknown CPU. "
				"Please send an e-mail to "
				"<cpufreq@vger.kernel.org>\n");
		return 0;
	}

	/* on P-4s, the TSC runs with constant frequency independent whether
	 * throttling is active or not. */
	p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS;

	if (speedstep_detect_processor() == SPEEDSTEP_CPU_P4M) {
		printk(KERN_WARNING PFX "Warning: Pentium 4-M detected. "
		       "The speedstep-ich or acpi cpufreq modules offer "
		       "voltage scaling in addition of frequency scaling. "
		       "You should use either one instead of p4-clockmod, "
		       "if possible.\n");
		return speedstep_get_frequency(SPEEDSTEP_CPU_P4M);
	}

	return speedstep_get_frequency(SPEEDSTEP_CPU_P4D);
}


static int cpufreq_p4_cpu_init(struct cpufreq_policy *policy)
{
	struct cpuinfo_x86 *c = &cpu_data(policy->cpu);
	int cpuid = 0;
	unsigned int i;

#ifdef CONFIG_SMP
	cpumask_copy(policy->cpus, cpu_sibling_mask(policy->cpu));
#endif

	/* Errata workaround */
	cpuid = (c->x86 << 8) | (c->x86_model << 4) | c->x86_mask;
	switch (cpuid) {
	case 0x0f07:
	case 0x0f0a:
	case 0x0f11:
	case 0x0f12:
		has_N44_O17_errata[policy->cpu] = 1;
		dprintk("has errata -- disabling low frequencies\n");
	}

	if (speedstep_detect_processor() == SPEEDSTEP_CPU_P4D &&
	    c->x86_model < 2) {
		/* switch to maximum frequency and measure result */
		cpufreq_p4_setdc(policy->cpu, DC_DISABLE);
		recalibrate_cpu_khz();
	}
	/* get max frequency */
	stock_freq = cpufreq_p4_get_frequency(c);
	if (!stock_freq)
		return -EINVAL;

	/* table init */
	for (i = 1; (p4clockmod_table[i].frequency != CPUFREQ_TABLE_END); i++) {
		if ((i < 2) && (has_N44_O17_errata[policy->cpu]))
			p4clockmod_table[i].frequency = CPUFREQ_ENTRY_INVALID;
		else
			p4clockmod_table[i].frequency = (stock_freq * i)/8;
	}
	cpufreq_frequency_table_get_attr(p4clockmod_table, policy->cpu);

	/* cpuinfo and default policy values */

	/* the transition latency is set to be 1 higher than the maximum
	 * transition latency of the ondemand governor */
	policy->cpuinfo.transition_latency = 10000001;
	policy->cur = stock_freq;

	return cpufreq_frequency_table_cpuinfo(policy, &p4clockmod_table[0]);
}


static int cpufreq_p4_cpu_exit(struct cpufreq_policy *policy)
{
	cpufreq_frequency_table_put_attr(policy->cpu);
	return 0;
}

static unsigned int cpufreq_p4_get(unsigned int cpu)
{
	u32 l, h;

	rdmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &l, &h);

	if (l & 0x10) {
		l = l >> 1;
		l &= 0x7;
	} else
		l = DC_DISABLE;

	if (l != DC_DISABLE)
		return stock_freq * l / 8;

	return stock_freq;
}

static struct freq_attr *p4clockmod_attr[] = {
	&cpufreq_freq_attr_scaling_available_freqs,
	NULL,
};

static struct cpufreq_driver p4clockmod_driver = {
	.verify		= cpufreq_p4_verify,
	.target		= cpufreq_p4_target,
	.init		= cpufreq_p4_cpu_init,
	.exit		= cpufreq_p4_cpu_exit,
	.get		= cpufreq_p4_get,
	.name		= "p4-clockmod",
	.owner		= THIS_MODULE,
	.attr		= p4clockmod_attr,
};


static int __init cpufreq_p4_init(void)
{
	struct cpuinfo_x86 *c = &cpu_data(0);
	int ret;

	/*
	 * THERM_CONTROL is architectural for IA32 now, so
	 * we can rely on the capability checks
	 */
	if (c->x86_vendor != X86_VENDOR_INTEL)
		return -ENODEV;

	if (!test_cpu_cap(c, X86_FEATURE_ACPI) ||
				!test_cpu_cap(c, X86_FEATURE_ACC))
		return -ENODEV;

	ret = cpufreq_register_driver(&p4clockmod_driver);
	if (!ret)
		printk(KERN_INFO PFX "P4/Xeon(TM) CPU On-Demand Clock "
				"Modulation available\n");

	return ret;
}


static void __exit cpufreq_p4_exit(void)
{
	cpufreq_unregister_driver(&p4clockmod_driver);
}


MODULE_AUTHOR("Zwane Mwaikambo <zwane@commfireservices.com>");
MODULE_DESCRIPTION("cpufreq driver for Pentium(TM) 4/Xeon(TM)");
MODULE_LICENSE("GPL");

late_initcall(cpufreq_p4_init);
module_exit(cpufreq_p4_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Pentium 4/Xeon CPU on demand clock modulation/speed scaling
	3	* (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
	4	* (C) 2002 Zwane Mwaikambo <zwane@commfireservices.com>
	5	* (C) 2002 Arjan van de Ven <arjanv@redhat.com>
	6	* (C) 2002 Tora T. Engstad
	7	* All Rights Reserved
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; either version
	12	* 2 of the License, or (at your option) any later version.
	13	*
	14	* The author(s) of this software shall not be held liable for damages
	15	* of any nature resulting due to the use of this software. This
	16	* software is provided AS-IS with no warranties.
32ee8c3e	17	*
1da177e4 LT	18	* Date Errata Description
	19	* 20020525 N44, O17 12.5% or 25% DC causes lockup
	20	*
	21	*/
	22
1da177e4	23	#include <linux/kernel.h>
32ee8c3e	24	#include <linux/module.h>
1da177e4 LT	25	#include <linux/init.h>
	26	#include <linux/smp.h>
	27	#include <linux/cpufreq.h>
	28	#include <linux/slab.h>
	29	#include <linux/cpumask.h>
bbfebd66	30	#include <linux/timex.h>
1da177e4	31
32ee8c3e	32	#include <asm/processor.h>
1da177e4	33	#include <asm/msr.h>
199785ea	34	#include <asm/timer.h>
1da177e4 LT	35
	36	#include "speedstep-lib.h"
	37
	38	#define PFX "p4-clockmod: "
bbfebd66 DJ	39	#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, \
bbfebd66 DJ	40	"p4-clockmod", msg)
1da177e4 LT	41
	42	/*
	43	* Duty Cycle (3bits), note DC_DISABLE is not specified in
	44	* intel docs i just use it to mean disable
	45	*/
	46	enum {
	47	DC_RESV, DC_DFLT, DC_25PT, DC_38PT, DC_50PT,
	48	DC_64PT, DC_75PT, DC_88PT, DC_DISABLE
	49	};
	50
	51	#define DC_ENTRIES 8
	52
	53
	54	static int has_N44_O17_errata[NR_CPUS];
	55	static unsigned int stock_freq;
	56	static struct cpufreq_driver p4clockmod_driver;
	57	static unsigned int cpufreq_p4_get(unsigned int cpu);
	58
	59	static int cpufreq_p4_setdc(unsigned int cpu, unsigned int newstate)
	60	{
	61	u32 l, h;
	62
bbfebd66 DJ	63	if (!cpu_online(cpu) \|\|
bbfebd66 DJ	64	(newstate > DC_DISABLE) \|\| (newstate == DC_RESV))
1da177e4 LT	65	return -EINVAL;
1da177e4 LT	66
551948bc	67	rdmsr_on_cpu(cpu, MSR_IA32_THERM_STATUS, &l, &h);
1da177e4 LT	68
	69	if (l & 0x01)
	70	dprintk("CPU#%d currently thermal throttled\n", cpu);
	71
bbfebd66 DJ	72	if (has_N44_O17_errata[cpu] &&
bbfebd66 DJ	73	(newstate == DC_25PT \|\| newstate == DC_DFLT))
1da177e4 LT	74	newstate = DC_38PT;
1da177e4 LT	75
551948bc	76	rdmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &l, &h);
1da177e4 LT	77	if (newstate == DC_DISABLE) {
1da177e4 LT	78	dprintk("CPU#%d disabling modulation\n", cpu);
551948bc	79	wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, l & ~(1<<4), h);
1da177e4 LT	80	} else {
	81	dprintk("CPU#%d setting duty cycle to %d%%\n",
	82	cpu, ((125 * newstate) / 10));
32ee8c3e	83	/* bits 63 - 5 : reserved
1da177e4 LT	84	* bit 4 : enable/disable
	85	* bits 3-1 : duty cycle
	86	* bit 0 : reserved
	87	*/
	88	l = (l & ~14);
	89	l = l \| (1<<4) \| ((newstate & 0x7)<<1);
551948bc	90	wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, l, h);
1da177e4 LT	91	}
	92
	93	return 0;
	94	}
	95
	96
	97	static struct cpufreq_frequency_table p4clockmod_table[] = {
	98	{DC_RESV, CPUFREQ_ENTRY_INVALID},
	99	{DC_DFLT, 0},
	100	{DC_25PT, 0},
	101	{DC_38PT, 0},
	102	{DC_50PT, 0},
	103	{DC_64PT, 0},
	104	{DC_75PT, 0},
	105	{DC_88PT, 0},
	106	{DC_DISABLE, 0},
	107	{DC_RESV, CPUFREQ_TABLE_END},
	108	};
	109
	110
	111	static int cpufreq_p4_target(struct cpufreq_policy *policy,
	112	unsigned int target_freq,
	113	unsigned int relation)
	114	{
	115	unsigned int newstate = DC_RESV;
	116	struct cpufreq_freqs freqs;
1da177e4 LT	117	int i;
1da177e4 LT	118
bbfebd66 DJ	119	if (cpufreq_frequency_table_target(policy, &p4clockmod_table[0],
bbfebd66 DJ	120	target_freq, relation, &newstate))
1da177e4 LT	121	return -EINVAL;
	122
	123	freqs.old = cpufreq_p4_get(policy->cpu);
	124	freqs.new = stock_freq * p4clockmod_table[newstate].index / 8;
	125
	126	if (freqs.new == freqs.old)
	127	return 0;
	128
	129	/* notifiers */
835481d9	130	for_each_cpu(i, policy->cpus) {
1da177e4 LT	131	freqs.cpu = i;
	132	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
	133	}
	134
bbfebd66 DJ	135	/* run on each logical CPU,
bbfebd66 DJ	136	* see section 13.15.3 of IA32 Intel Architecture Software
32ee8c3e	137	* Developer's Manual, Volume 3
1da177e4	138	*/
835481d9	139	for_each_cpu(i, policy->cpus)
1da177e4	140	cpufreq_p4_setdc(i, p4clockmod_table[newstate].index);
1da177e4 LT	141
1da177e4 LT	142	/* notifiers */
835481d9	143	for_each_cpu(i, policy->cpus) {
1da177e4 LT	144	freqs.cpu = i;
	145	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
	146	}
	147
	148	return 0;
	149	}
	150
	151
	152	static int cpufreq_p4_verify(struct cpufreq_policy *policy)
	153	{
	154	return cpufreq_frequency_table_verify(policy, &p4clockmod_table[0]);
	155	}
	156
	157
	158	static unsigned int cpufreq_p4_get_frequency(struct cpuinfo_x86 *c)
	159	{
4e74663c DB	160	if (c->x86 == 0x06) {
4e74663c DB	161	if (cpu_has(c, X86_FEATURE_EST))
bbfebd66 DJ	162	printk(KERN_WARNING PFX "Warning: EST-capable CPU "
	163	"detected. The acpi-cpufreq module offers "
	164	"voltage scaling in addition of frequency "
	165	"scaling. You should use that instead of "
	166	"p4-clockmod, if possible.\n");
4e74663c DB	167	switch (c->x86_model) {
	168	case 0x0E: /* Core */
	169	case 0x0F: /* Core Duo */
8529154e	170	case 0x16: /* Celeron Core */
43195037	171	case 0x1C: /* Atom */
4e74663c	172	p4clockmod_driver.flags \|= CPUFREQ_CONST_LOOPS;
bbfebd66	173	return speedstep_get_frequency(SPEEDSTEP_CPU_PCORE);
4e74663c DB	174	case 0x0D: /* Pentium M (Dothan) */
	175	p4clockmod_driver.flags \|= CPUFREQ_CONST_LOOPS;
	176	/* fall through */
	177	case 0x09: /* Pentium M (Banias) */
bbfebd66	178	return speedstep_get_frequency(SPEEDSTEP_CPU_PM);
4e74663c	179	}
1da177e4 LT	180	}
	181
	182	if (c->x86 != 0xF) {
10db2e5c	183	if (!cpu_has(c, X86_FEATURE_EST))
bbfebd66 DJ	184	printk(KERN_WARNING PFX "Unknown CPU. "
	185	"Please send an e-mail to "
	186	"<cpufreq@vger.kernel.org>\n");
1da177e4 LT	187	return 0;
	188	}
	189
	190	/* on P-4s, the TSC runs with constant frequency independent whether
	191	* throttling is active or not. */
	192	p4clockmod_driver.flags \|= CPUFREQ_CONST_LOOPS;
	193
bbfebd66	194	if (speedstep_detect_processor() == SPEEDSTEP_CPU_P4M) {
1da177e4 LT	195	printk(KERN_WARNING PFX "Warning: Pentium 4-M detected. "
	196	"The speedstep-ich or acpi cpufreq modules offer "
	197	"voltage scaling in addition of frequency scaling. "
	198	"You should use either one instead of p4-clockmod, "
	199	"if possible.\n");
bbfebd66	200	return speedstep_get_frequency(SPEEDSTEP_CPU_P4M);
1da177e4 LT	201	}
1da177e4 LT	202
bbfebd66	203	return speedstep_get_frequency(SPEEDSTEP_CPU_P4D);
1da177e4 LT	204	}
1da177e4 LT	205
32ee8c3e	206
1da177e4 LT	207
	208	static int cpufreq_p4_cpu_init(struct cpufreq_policy *policy)
	209	{
92cb7612	210	struct cpuinfo_x86 *c = &cpu_data(policy->cpu);
1da177e4 LT	211	int cpuid = 0;
	212	unsigned int i;
	213
	214	#ifdef CONFIG_SMP
7ad728f9	215	cpumask_copy(policy->cpus, cpu_sibling_mask(policy->cpu));
1da177e4 LT	216	#endif
	217
	218	/* Errata workaround */
	219	cpuid = (c->x86 << 8) \| (c->x86_model << 4) \| c->x86_mask;
	220	switch (cpuid) {
	221	case 0x0f07:
	222	case 0x0f0a:
	223	case 0x0f11:
	224	case 0x0f12:
	225	has_N44_O17_errata[policy->cpu] = 1;
	226	dprintk("has errata -- disabling low frequencies\n");
	227	}
32ee8c3e	228
199785ea MCO	229	if (speedstep_detect_processor() == SPEEDSTEP_CPU_P4D &&
	230	c->x86_model < 2) {
	231	/* switch to maximum frequency and measure result */
	232	cpufreq_p4_setdc(policy->cpu, DC_DISABLE);
	233	recalibrate_cpu_khz();
	234	}
1da177e4 LT	235	/* get max frequency */
	236	stock_freq = cpufreq_p4_get_frequency(c);
	237	if (!stock_freq)
	238	return -EINVAL;
	239
	240	/* table init */
bbfebd66 DJ	241	for (i = 1; (p4clockmod_table[i].frequency != CPUFREQ_TABLE_END); i++) {
bbfebd66 DJ	242	if ((i < 2) && (has_N44_O17_errata[policy->cpu]))
1da177e4 LT	243	p4clockmod_table[i].frequency = CPUFREQ_ENTRY_INVALID;
	244	else
	245	p4clockmod_table[i].frequency = (stock_freq * i)/8;
	246	}
	247	cpufreq_frequency_table_get_attr(p4clockmod_table, policy->cpu);
32ee8c3e	248
1da177e4	249	/* cpuinfo and default policy values */
36e8abf3 DJ	250
	251	/* the transition latency is set to be 1 higher than the maximum
	252	* transition latency of the ondemand governor */
	253	policy->cpuinfo.transition_latency = 10000001;
1da177e4 LT	254	policy->cur = stock_freq;
	255
	256	return cpufreq_frequency_table_cpuinfo(policy, &p4clockmod_table[0]);
	257	}
	258
	259
	260	static int cpufreq_p4_cpu_exit(struct cpufreq_policy *policy)
	261	{
32ee8c3e	262	cpufreq_frequency_table_put_attr(policy->cpu);
1da177e4 LT	263	return 0;
	264	}
	265
	266	static unsigned int cpufreq_p4_get(unsigned int cpu)
	267	{
1da177e4 LT	268	u32 l, h;
1da177e4 LT	269
551948bc	270	rdmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &l, &h);
1da177e4 LT	271
	272	if (l & 0x10) {
	273	l = l >> 1;
	274	l &= 0x7;
	275	} else
	276	l = DC_DISABLE;
	277
	278	if (l != DC_DISABLE)
bbfebd66	279	return stock_freq * l / 8;
1da177e4 LT	280
	281	return stock_freq;
	282	}
	283
bbfebd66	284	static struct freq_attr *p4clockmod_attr[] = {
1da177e4 LT	285	&cpufreq_freq_attr_scaling_available_freqs,
	286	NULL,
	287	};
	288
	289	static struct cpufreq_driver p4clockmod_driver = {
32ee8c3e	290	.verify = cpufreq_p4_verify,
1da177e4 LT	291	.target = cpufreq_p4_target,
	292	.init = cpufreq_p4_cpu_init,
	293	.exit = cpufreq_p4_cpu_exit,
	294	.get = cpufreq_p4_get,
	295	.name = "p4-clockmod",
	296	.owner = THIS_MODULE,
	297	.attr = p4clockmod_attr,
	298	};
	299
	300
	301	static int __init cpufreq_p4_init(void)
32ee8c3e	302	{
92cb7612	303	struct cpuinfo_x86 *c = &cpu_data(0);
1da177e4 LT	304	int ret;
	305
	306	/*
32ee8c3e	307	* THERM_CONTROL is architectural for IA32 now, so
1da177e4 LT	308	* we can rely on the capability checks
	309	*/
	310	if (c->x86_vendor != X86_VENDOR_INTEL)
	311	return -ENODEV;
	312
8ce116e5 IM	313	if (!test_cpu_cap(c, X86_FEATURE_ACPI) \|\|
8ce116e5 IM	314	!test_cpu_cap(c, X86_FEATURE_ACC))
1da177e4 LT	315	return -ENODEV;
	316
	317	ret = cpufreq_register_driver(&p4clockmod_driver);
	318	if (!ret)
bbfebd66 DJ	319	printk(KERN_INFO PFX "P4/Xeon(TM) CPU On-Demand Clock "
bbfebd66 DJ	320	"Modulation available\n");
1da177e4	321
bbfebd66	322	return ret;
1da177e4 LT	323	}
	324
	325
	326	static void __exit cpufreq_p4_exit(void)
	327	{
	328	cpufreq_unregister_driver(&p4clockmod_driver);
	329	}
	330
	331
bbfebd66 DJ	332	MODULE_AUTHOR("Zwane Mwaikambo <zwane@commfireservices.com>");
	333	MODULE_DESCRIPTION("cpufreq driver for Pentium(TM) 4/Xeon(TM)");
	334	MODULE_LICENSE("GPL");
1da177e4 LT	335
	336	late_initcall(cpufreq_p4_init);
	337	module_exit(cpufreq_p4_exit);