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Commit | Line | Data |
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1da177e4 | 1 | /* |
1f729e06 | 2 | * (c) 2003-2006 Advanced Micro Devices, Inc. |
1da177e4 LT |
3 | * Your use of this code is subject to the terms and conditions of the |
4 | * GNU general public license version 2. See "COPYING" or | |
5 | * http://www.gnu.org/licenses/gpl.html | |
6 | * | |
065b807c | 7 | * Support : mark.langsdorf@amd.com |
1da177e4 LT |
8 | * |
9 | * Based on the powernow-k7.c module written by Dave Jones. | |
f4432c5c | 10 | * (C) 2003 Dave Jones on behalf of SuSE Labs |
1da177e4 LT |
11 | * (C) 2004 Dominik Brodowski <linux@brodo.de> |
12 | * (C) 2004 Pavel Machek <pavel@suse.cz> | |
13 | * Licensed under the terms of the GNU GPL License version 2. | |
14 | * Based upon datasheets & sample CPUs kindly provided by AMD. | |
15 | * | |
16 | * Valuable input gratefully received from Dave Jones, Pavel Machek, | |
1f729e06 | 17 | * Dominik Brodowski, Jacob Shin, and others. |
065b807c | 18 | * Originally developed by Paul Devriendt. |
1da177e4 LT |
19 | * Processor information obtained from Chapter 9 (Power and Thermal Management) |
20 | * of the "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD | |
21 | * Opteron Processors" available for download from www.amd.com | |
22 | * | |
2e3f8faa | 23 | * Tables for specific CPUs can be inferred from |
065b807c | 24 | * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/30430.pdf |
1da177e4 LT |
25 | */ |
26 | ||
27 | #include <linux/kernel.h> | |
28 | #include <linux/smp.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/cpufreq.h> | |
32 | #include <linux/slab.h> | |
33 | #include <linux/string.h> | |
065b807c | 34 | #include <linux/cpumask.h> |
4e57b681 | 35 | #include <linux/sched.h> /* for current / set_cpus_allowed() */ |
0e64a0c9 DJ |
36 | #include <linux/io.h> |
37 | #include <linux/delay.h> | |
1da177e4 LT |
38 | |
39 | #include <asm/msr.h> | |
1da177e4 | 40 | |
1da177e4 | 41 | #include <linux/acpi.h> |
14cc3e2b | 42 | #include <linux/mutex.h> |
1da177e4 | 43 | #include <acpi/processor.h> |
1da177e4 LT |
44 | |
45 | #define PFX "powernow-k8: " | |
c5829cd0 | 46 | #define VERSION "version 2.20.00" |
1da177e4 LT |
47 | #include "powernow-k8.h" |
48 | ||
49 | /* serialize freq changes */ | |
14cc3e2b | 50 | static DEFINE_MUTEX(fidvid_mutex); |
1da177e4 | 51 | |
2c6b8c03 | 52 | static DEFINE_PER_CPU(struct powernow_k8_data *, powernow_data); |
1da177e4 | 53 | |
1f729e06 DJ |
54 | static int cpu_family = CPU_OPTERON; |
55 | ||
065b807c | 56 | #ifndef CONFIG_SMP |
7ad728f9 RR |
57 | static inline const struct cpumask *cpu_core_mask(int cpu) |
58 | { | |
59 | return cpumask_of(0); | |
60 | } | |
065b807c DJ |
61 | #endif |
62 | ||
1da177e4 LT |
63 | /* Return a frequency in MHz, given an input fid */ |
64 | static u32 find_freq_from_fid(u32 fid) | |
65 | { | |
66 | return 800 + (fid * 100); | |
67 | } | |
68 | ||
69 | /* Return a frequency in KHz, given an input fid */ | |
70 | static u32 find_khz_freq_from_fid(u32 fid) | |
71 | { | |
72 | return 1000 * find_freq_from_fid(fid); | |
73 | } | |
74 | ||
0e64a0c9 DJ |
75 | static u32 find_khz_freq_from_pstate(struct cpufreq_frequency_table *data, |
76 | u32 pstate) | |
1f729e06 | 77 | { |
c5829cd0 | 78 | return data[pstate].frequency; |
1f729e06 DJ |
79 | } |
80 | ||
1da177e4 LT |
81 | /* Return the vco fid for an input fid |
82 | * | |
83 | * Each "low" fid has corresponding "high" fid, and you can get to "low" fids | |
84 | * only from corresponding high fids. This returns "high" fid corresponding to | |
85 | * "low" one. | |
86 | */ | |
87 | static u32 convert_fid_to_vco_fid(u32 fid) | |
88 | { | |
32ee8c3e | 89 | if (fid < HI_FID_TABLE_BOTTOM) |
1da177e4 | 90 | return 8 + (2 * fid); |
32ee8c3e | 91 | else |
1da177e4 | 92 | return fid; |
1da177e4 LT |
93 | } |
94 | ||
95 | /* | |
96 | * Return 1 if the pending bit is set. Unless we just instructed the processor | |
97 | * to transition to a new state, seeing this bit set is really bad news. | |
98 | */ | |
99 | static int pending_bit_stuck(void) | |
100 | { | |
101 | u32 lo, hi; | |
102 | ||
e7bdd7a5 | 103 | if (cpu_family == CPU_HW_PSTATE) |
1f729e06 DJ |
104 | return 0; |
105 | ||
1da177e4 LT |
106 | rdmsr(MSR_FIDVID_STATUS, lo, hi); |
107 | return lo & MSR_S_LO_CHANGE_PENDING ? 1 : 0; | |
108 | } | |
109 | ||
110 | /* | |
111 | * Update the global current fid / vid values from the status msr. | |
112 | * Returns 1 on error. | |
113 | */ | |
114 | static int query_current_values_with_pending_wait(struct powernow_k8_data *data) | |
115 | { | |
116 | u32 lo, hi; | |
117 | u32 i = 0; | |
118 | ||
e7bdd7a5 | 119 | if (cpu_family == CPU_HW_PSTATE) { |
a266d9f1 AH |
120 | if (data->currpstate == HW_PSTATE_INVALID) { |
121 | /* read (initial) hw pstate if not yet set */ | |
122 | rdmsr(MSR_PSTATE_STATUS, lo, hi); | |
123 | i = lo & HW_PSTATE_MASK; | |
124 | ||
125 | /* | |
126 | * a workaround for family 11h erratum 311 might cause | |
127 | * an "out-of-range Pstate if the core is in Pstate-0 | |
128 | */ | |
129 | if (i >= data->numps) | |
130 | data->currpstate = HW_PSTATE_0; | |
131 | else | |
132 | data->currpstate = i; | |
133 | } | |
1f729e06 DJ |
134 | return 0; |
135 | } | |
7153d961 | 136 | do { |
0213df74 DJ |
137 | if (i++ > 10000) { |
138 | dprintk("detected change pending stuck\n"); | |
1da177e4 LT |
139 | return 1; |
140 | } | |
141 | rdmsr(MSR_FIDVID_STATUS, lo, hi); | |
7153d961 | 142 | } while (lo & MSR_S_LO_CHANGE_PENDING); |
1da177e4 LT |
143 | |
144 | data->currvid = hi & MSR_S_HI_CURRENT_VID; | |
145 | data->currfid = lo & MSR_S_LO_CURRENT_FID; | |
146 | ||
147 | return 0; | |
148 | } | |
149 | ||
150 | /* the isochronous relief time */ | |
151 | static void count_off_irt(struct powernow_k8_data *data) | |
152 | { | |
153 | udelay((1 << data->irt) * 10); | |
154 | return; | |
155 | } | |
156 | ||
27b46d76 | 157 | /* the voltage stabilization time */ |
1da177e4 LT |
158 | static void count_off_vst(struct powernow_k8_data *data) |
159 | { | |
160 | udelay(data->vstable * VST_UNITS_20US); | |
161 | return; | |
162 | } | |
163 | ||
164 | /* need to init the control msr to a safe value (for each cpu) */ | |
165 | static void fidvid_msr_init(void) | |
166 | { | |
167 | u32 lo, hi; | |
168 | u8 fid, vid; | |
169 | ||
170 | rdmsr(MSR_FIDVID_STATUS, lo, hi); | |
171 | vid = hi & MSR_S_HI_CURRENT_VID; | |
172 | fid = lo & MSR_S_LO_CURRENT_FID; | |
173 | lo = fid | (vid << MSR_C_LO_VID_SHIFT); | |
174 | hi = MSR_C_HI_STP_GNT_BENIGN; | |
175 | dprintk("cpu%d, init lo 0x%x, hi 0x%x\n", smp_processor_id(), lo, hi); | |
176 | wrmsr(MSR_FIDVID_CTL, lo, hi); | |
177 | } | |
178 | ||
1da177e4 LT |
179 | /* write the new fid value along with the other control fields to the msr */ |
180 | static int write_new_fid(struct powernow_k8_data *data, u32 fid) | |
181 | { | |
182 | u32 lo; | |
183 | u32 savevid = data->currvid; | |
0213df74 | 184 | u32 i = 0; |
1da177e4 LT |
185 | |
186 | if ((fid & INVALID_FID_MASK) || (data->currvid & INVALID_VID_MASK)) { | |
187 | printk(KERN_ERR PFX "internal error - overflow on fid write\n"); | |
188 | return 1; | |
189 | } | |
190 | ||
0e64a0c9 DJ |
191 | lo = fid; |
192 | lo |= (data->currvid << MSR_C_LO_VID_SHIFT); | |
193 | lo |= MSR_C_LO_INIT_FID_VID; | |
1da177e4 LT |
194 | |
195 | dprintk("writing fid 0x%x, lo 0x%x, hi 0x%x\n", | |
196 | fid, lo, data->plllock * PLL_LOCK_CONVERSION); | |
197 | ||
0213df74 DJ |
198 | do { |
199 | wrmsr(MSR_FIDVID_CTL, lo, data->plllock * PLL_LOCK_CONVERSION); | |
200 | if (i++ > 100) { | |
0e64a0c9 DJ |
201 | printk(KERN_ERR PFX |
202 | "Hardware error - pending bit very stuck - " | |
203 | "no further pstate changes possible\n"); | |
63172cb3 | 204 | return 1; |
32ee8c3e | 205 | } |
0213df74 | 206 | } while (query_current_values_with_pending_wait(data)); |
1da177e4 LT |
207 | |
208 | count_off_irt(data); | |
209 | ||
210 | if (savevid != data->currvid) { | |
0e64a0c9 DJ |
211 | printk(KERN_ERR PFX |
212 | "vid change on fid trans, old 0x%x, new 0x%x\n", | |
213 | savevid, data->currvid); | |
1da177e4 LT |
214 | return 1; |
215 | } | |
216 | ||
217 | if (fid != data->currfid) { | |
0e64a0c9 DJ |
218 | printk(KERN_ERR PFX |
219 | "fid trans failed, fid 0x%x, curr 0x%x\n", fid, | |
220 | data->currfid); | |
1da177e4 LT |
221 | return 1; |
222 | } | |
223 | ||
224 | return 0; | |
225 | } | |
226 | ||
227 | /* Write a new vid to the hardware */ | |
228 | static int write_new_vid(struct powernow_k8_data *data, u32 vid) | |
229 | { | |
230 | u32 lo; | |
231 | u32 savefid = data->currfid; | |
0213df74 | 232 | int i = 0; |
1da177e4 LT |
233 | |
234 | if ((data->currfid & INVALID_FID_MASK) || (vid & INVALID_VID_MASK)) { | |
235 | printk(KERN_ERR PFX "internal error - overflow on vid write\n"); | |
236 | return 1; | |
237 | } | |
238 | ||
0e64a0c9 DJ |
239 | lo = data->currfid; |
240 | lo |= (vid << MSR_C_LO_VID_SHIFT); | |
241 | lo |= MSR_C_LO_INIT_FID_VID; | |
1da177e4 LT |
242 | |
243 | dprintk("writing vid 0x%x, lo 0x%x, hi 0x%x\n", | |
244 | vid, lo, STOP_GRANT_5NS); | |
245 | ||
0213df74 DJ |
246 | do { |
247 | wrmsr(MSR_FIDVID_CTL, lo, STOP_GRANT_5NS); | |
6df89006 | 248 | if (i++ > 100) { |
0e64a0c9 DJ |
249 | printk(KERN_ERR PFX "internal error - pending bit " |
250 | "very stuck - no further pstate " | |
251 | "changes possible\n"); | |
6df89006 DJ |
252 | return 1; |
253 | } | |
0213df74 | 254 | } while (query_current_values_with_pending_wait(data)); |
1da177e4 LT |
255 | |
256 | if (savefid != data->currfid) { | |
0e64a0c9 DJ |
257 | printk(KERN_ERR PFX "fid changed on vid trans, old " |
258 | "0x%x new 0x%x\n", | |
1da177e4 LT |
259 | savefid, data->currfid); |
260 | return 1; | |
261 | } | |
262 | ||
263 | if (vid != data->currvid) { | |
0e64a0c9 DJ |
264 | printk(KERN_ERR PFX "vid trans failed, vid 0x%x, " |
265 | "curr 0x%x\n", | |
266 | vid, data->currvid); | |
1da177e4 LT |
267 | return 1; |
268 | } | |
269 | ||
270 | return 0; | |
271 | } | |
272 | ||
273 | /* | |
274 | * Reduce the vid by the max of step or reqvid. | |
275 | * Decreasing vid codes represent increasing voltages: | |
841e40b3 | 276 | * vid of 0 is 1.550V, vid of 0x1e is 0.800V, vid of VID_OFF is off. |
1da177e4 | 277 | */ |
0e64a0c9 DJ |
278 | static int decrease_vid_code_by_step(struct powernow_k8_data *data, |
279 | u32 reqvid, u32 step) | |
1da177e4 LT |
280 | { |
281 | if ((data->currvid - reqvid) > step) | |
282 | reqvid = data->currvid - step; | |
283 | ||
284 | if (write_new_vid(data, reqvid)) | |
285 | return 1; | |
286 | ||
287 | count_off_vst(data); | |
288 | ||
289 | return 0; | |
290 | } | |
291 | ||
1f729e06 DJ |
292 | /* Change hardware pstate by single MSR write */ |
293 | static int transition_pstate(struct powernow_k8_data *data, u32 pstate) | |
294 | { | |
295 | wrmsr(MSR_PSTATE_CTRL, pstate, 0); | |
c5829cd0 | 296 | data->currpstate = pstate; |
1f729e06 DJ |
297 | return 0; |
298 | } | |
299 | ||
300 | /* Change Opteron/Athlon64 fid and vid, by the 3 phases. */ | |
0e64a0c9 DJ |
301 | static int transition_fid_vid(struct powernow_k8_data *data, |
302 | u32 reqfid, u32 reqvid) | |
1da177e4 LT |
303 | { |
304 | if (core_voltage_pre_transition(data, reqvid)) | |
305 | return 1; | |
306 | ||
307 | if (core_frequency_transition(data, reqfid)) | |
308 | return 1; | |
309 | ||
310 | if (core_voltage_post_transition(data, reqvid)) | |
311 | return 1; | |
312 | ||
313 | if (query_current_values_with_pending_wait(data)) | |
314 | return 1; | |
315 | ||
316 | if ((reqfid != data->currfid) || (reqvid != data->currvid)) { | |
0e64a0c9 DJ |
317 | printk(KERN_ERR PFX "failed (cpu%d): req 0x%x 0x%x, " |
318 | "curr 0x%x 0x%x\n", | |
1da177e4 LT |
319 | smp_processor_id(), |
320 | reqfid, reqvid, data->currfid, data->currvid); | |
321 | return 1; | |
322 | } | |
323 | ||
324 | dprintk("transitioned (cpu%d): new fid 0x%x, vid 0x%x\n", | |
325 | smp_processor_id(), data->currfid, data->currvid); | |
326 | ||
327 | return 0; | |
328 | } | |
329 | ||
330 | /* Phase 1 - core voltage transition ... setup voltage */ | |
0e64a0c9 DJ |
331 | static int core_voltage_pre_transition(struct powernow_k8_data *data, |
332 | u32 reqvid) | |
1da177e4 LT |
333 | { |
334 | u32 rvosteps = data->rvo; | |
335 | u32 savefid = data->currfid; | |
065b807c | 336 | u32 maxvid, lo; |
1da177e4 | 337 | |
0e64a0c9 DJ |
338 | dprintk("ph1 (cpu%d): start, currfid 0x%x, currvid 0x%x, " |
339 | "reqvid 0x%x, rvo 0x%x\n", | |
1da177e4 LT |
340 | smp_processor_id(), |
341 | data->currfid, data->currvid, reqvid, data->rvo); | |
342 | ||
065b807c DJ |
343 | rdmsr(MSR_FIDVID_STATUS, lo, maxvid); |
344 | maxvid = 0x1f & (maxvid >> 16); | |
345 | dprintk("ph1 maxvid=0x%x\n", maxvid); | |
346 | if (reqvid < maxvid) /* lower numbers are higher voltages */ | |
347 | reqvid = maxvid; | |
348 | ||
1da177e4 LT |
349 | while (data->currvid > reqvid) { |
350 | dprintk("ph1: curr 0x%x, req vid 0x%x\n", | |
351 | data->currvid, reqvid); | |
352 | if (decrease_vid_code_by_step(data, reqvid, data->vidmvs)) | |
353 | return 1; | |
354 | } | |
355 | ||
065b807c DJ |
356 | while ((rvosteps > 0) && ((data->rvo + data->currvid) > reqvid)) { |
357 | if (data->currvid == maxvid) { | |
1da177e4 LT |
358 | rvosteps = 0; |
359 | } else { | |
360 | dprintk("ph1: changing vid for rvo, req 0x%x\n", | |
361 | data->currvid - 1); | |
0e64a0c9 | 362 | if (decrease_vid_code_by_step(data, data->currvid-1, 1)) |
1da177e4 LT |
363 | return 1; |
364 | rvosteps--; | |
365 | } | |
366 | } | |
367 | ||
368 | if (query_current_values_with_pending_wait(data)) | |
369 | return 1; | |
370 | ||
371 | if (savefid != data->currfid) { | |
0e64a0c9 DJ |
372 | printk(KERN_ERR PFX "ph1 err, currfid changed 0x%x\n", |
373 | data->currfid); | |
1da177e4 LT |
374 | return 1; |
375 | } | |
376 | ||
377 | dprintk("ph1 complete, currfid 0x%x, currvid 0x%x\n", | |
378 | data->currfid, data->currvid); | |
379 | ||
380 | return 0; | |
381 | } | |
382 | ||
383 | /* Phase 2 - core frequency transition */ | |
384 | static int core_frequency_transition(struct powernow_k8_data *data, u32 reqfid) | |
385 | { | |
0e64a0c9 DJ |
386 | u32 vcoreqfid, vcocurrfid, vcofiddiff; |
387 | u32 fid_interval, savevid = data->currvid; | |
1da177e4 | 388 | |
0e64a0c9 DJ |
389 | if ((reqfid < HI_FID_TABLE_BOTTOM) && |
390 | (data->currfid < HI_FID_TABLE_BOTTOM)) { | |
391 | printk(KERN_ERR PFX "ph2: illegal lo-lo transition " | |
392 | "0x%x 0x%x\n", reqfid, data->currfid); | |
1da177e4 LT |
393 | return 1; |
394 | } | |
395 | ||
396 | if (data->currfid == reqfid) { | |
0e64a0c9 DJ |
397 | printk(KERN_ERR PFX "ph2 null fid transition 0x%x\n", |
398 | data->currfid); | |
1da177e4 LT |
399 | return 0; |
400 | } | |
401 | ||
0e64a0c9 DJ |
402 | dprintk("ph2 (cpu%d): starting, currfid 0x%x, currvid 0x%x, " |
403 | "reqfid 0x%x\n", | |
1da177e4 LT |
404 | smp_processor_id(), |
405 | data->currfid, data->currvid, reqfid); | |
406 | ||
407 | vcoreqfid = convert_fid_to_vco_fid(reqfid); | |
408 | vcocurrfid = convert_fid_to_vco_fid(data->currfid); | |
409 | vcofiddiff = vcocurrfid > vcoreqfid ? vcocurrfid - vcoreqfid | |
410 | : vcoreqfid - vcocurrfid; | |
411 | ||
412 | while (vcofiddiff > 2) { | |
019a61b9 LM |
413 | (data->currfid & 1) ? (fid_interval = 1) : (fid_interval = 2); |
414 | ||
1da177e4 LT |
415 | if (reqfid > data->currfid) { |
416 | if (data->currfid > LO_FID_TABLE_TOP) { | |
0e64a0c9 DJ |
417 | if (write_new_fid(data, |
418 | data->currfid + fid_interval)) | |
1da177e4 | 419 | return 1; |
1da177e4 LT |
420 | } else { |
421 | if (write_new_fid | |
0e64a0c9 DJ |
422 | (data, |
423 | 2 + convert_fid_to_vco_fid(data->currfid))) | |
1da177e4 | 424 | return 1; |
1da177e4 LT |
425 | } |
426 | } else { | |
019a61b9 | 427 | if (write_new_fid(data, data->currfid - fid_interval)) |
1da177e4 LT |
428 | return 1; |
429 | } | |
430 | ||
431 | vcocurrfid = convert_fid_to_vco_fid(data->currfid); | |
432 | vcofiddiff = vcocurrfid > vcoreqfid ? vcocurrfid - vcoreqfid | |
433 | : vcoreqfid - vcocurrfid; | |
434 | } | |
435 | ||
436 | if (write_new_fid(data, reqfid)) | |
437 | return 1; | |
438 | ||
439 | if (query_current_values_with_pending_wait(data)) | |
440 | return 1; | |
441 | ||
442 | if (data->currfid != reqfid) { | |
443 | printk(KERN_ERR PFX | |
0e64a0c9 DJ |
444 | "ph2: mismatch, failed fid transition, " |
445 | "curr 0x%x, req 0x%x\n", | |
1da177e4 LT |
446 | data->currfid, reqfid); |
447 | return 1; | |
448 | } | |
449 | ||
450 | if (savevid != data->currvid) { | |
451 | printk(KERN_ERR PFX "ph2: vid changed, save 0x%x, curr 0x%x\n", | |
452 | savevid, data->currvid); | |
453 | return 1; | |
454 | } | |
455 | ||
456 | dprintk("ph2 complete, currfid 0x%x, currvid 0x%x\n", | |
457 | data->currfid, data->currvid); | |
458 | ||
459 | return 0; | |
460 | } | |
461 | ||
462 | /* Phase 3 - core voltage transition flow ... jump to the final vid. */ | |
0e64a0c9 DJ |
463 | static int core_voltage_post_transition(struct powernow_k8_data *data, |
464 | u32 reqvid) | |
1da177e4 LT |
465 | { |
466 | u32 savefid = data->currfid; | |
467 | u32 savereqvid = reqvid; | |
468 | ||
469 | dprintk("ph3 (cpu%d): starting, currfid 0x%x, currvid 0x%x\n", | |
470 | smp_processor_id(), | |
471 | data->currfid, data->currvid); | |
472 | ||
473 | if (reqvid != data->currvid) { | |
474 | if (write_new_vid(data, reqvid)) | |
475 | return 1; | |
476 | ||
477 | if (savefid != data->currfid) { | |
478 | printk(KERN_ERR PFX | |
479 | "ph3: bad fid change, save 0x%x, curr 0x%x\n", | |
480 | savefid, data->currfid); | |
481 | return 1; | |
482 | } | |
483 | ||
484 | if (data->currvid != reqvid) { | |
485 | printk(KERN_ERR PFX | |
0e64a0c9 DJ |
486 | "ph3: failed vid transition\n, " |
487 | "req 0x%x, curr 0x%x", | |
1da177e4 LT |
488 | reqvid, data->currvid); |
489 | return 1; | |
490 | } | |
491 | } | |
492 | ||
493 | if (query_current_values_with_pending_wait(data)) | |
494 | return 1; | |
495 | ||
496 | if (savereqvid != data->currvid) { | |
497 | dprintk("ph3 failed, currvid 0x%x\n", data->currvid); | |
498 | return 1; | |
499 | } | |
500 | ||
501 | if (savefid != data->currfid) { | |
502 | dprintk("ph3 failed, currfid changed 0x%x\n", | |
503 | data->currfid); | |
504 | return 1; | |
505 | } | |
506 | ||
507 | dprintk("ph3 complete, currfid 0x%x, currvid 0x%x\n", | |
508 | data->currfid, data->currvid); | |
509 | ||
510 | return 0; | |
511 | } | |
512 | ||
513 | static int check_supported_cpu(unsigned int cpu) | |
514 | { | |
fc0e4748 | 515 | cpumask_t oldmask; |
1da177e4 LT |
516 | u32 eax, ebx, ecx, edx; |
517 | unsigned int rc = 0; | |
518 | ||
519 | oldmask = current->cpus_allowed; | |
0bc3cc03 | 520 | set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu)); |
1da177e4 LT |
521 | |
522 | if (smp_processor_id() != cpu) { | |
8aae8284 | 523 | printk(KERN_ERR PFX "limiting to cpu %u failed\n", cpu); |
1da177e4 LT |
524 | goto out; |
525 | } | |
526 | ||
527 | if (current_cpu_data.x86_vendor != X86_VENDOR_AMD) | |
528 | goto out; | |
529 | ||
530 | eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE); | |
1f729e06 DJ |
531 | if (((eax & CPUID_XFAM) != CPUID_XFAM_K8) && |
532 | ((eax & CPUID_XFAM) < CPUID_XFAM_10H)) | |
2c906ae6 DJ |
533 | goto out; |
534 | ||
1f729e06 DJ |
535 | if ((eax & CPUID_XFAM) == CPUID_XFAM_K8) { |
536 | if (((eax & CPUID_USE_XFAM_XMOD) != CPUID_USE_XFAM_XMOD) || | |
99fbe1ac | 537 | ((eax & CPUID_XMOD) > CPUID_XMOD_REV_MASK)) { |
0e64a0c9 DJ |
538 | printk(KERN_INFO PFX |
539 | "Processor cpuid %x not supported\n", eax); | |
1f729e06 DJ |
540 | goto out; |
541 | } | |
1da177e4 | 542 | |
1f729e06 DJ |
543 | eax = cpuid_eax(CPUID_GET_MAX_CAPABILITIES); |
544 | if (eax < CPUID_FREQ_VOLT_CAPABILITIES) { | |
545 | printk(KERN_INFO PFX | |
546 | "No frequency change capabilities detected\n"); | |
547 | goto out; | |
548 | } | |
1da177e4 | 549 | |
1f729e06 | 550 | cpuid(CPUID_FREQ_VOLT_CAPABILITIES, &eax, &ebx, &ecx, &edx); |
0e64a0c9 DJ |
551 | if ((edx & P_STATE_TRANSITION_CAPABLE) |
552 | != P_STATE_TRANSITION_CAPABLE) { | |
553 | printk(KERN_INFO PFX | |
554 | "Power state transitions not supported\n"); | |
1f729e06 DJ |
555 | goto out; |
556 | } | |
557 | } else { /* must be a HW Pstate capable processor */ | |
558 | cpuid(CPUID_FREQ_VOLT_CAPABILITIES, &eax, &ebx, &ecx, &edx); | |
559 | if ((edx & USE_HW_PSTATE) == USE_HW_PSTATE) | |
560 | cpu_family = CPU_HW_PSTATE; | |
561 | else | |
562 | goto out; | |
1da177e4 LT |
563 | } |
564 | ||
565 | rc = 1; | |
566 | ||
567 | out: | |
fc0e4748 | 568 | set_cpus_allowed_ptr(current, &oldmask); |
1da177e4 | 569 | return rc; |
1da177e4 LT |
570 | } |
571 | ||
0e64a0c9 DJ |
572 | static int check_pst_table(struct powernow_k8_data *data, struct pst_s *pst, |
573 | u8 maxvid) | |
1da177e4 LT |
574 | { |
575 | unsigned int j; | |
576 | u8 lastfid = 0xff; | |
577 | ||
578 | for (j = 0; j < data->numps; j++) { | |
579 | if (pst[j].vid > LEAST_VID) { | |
2fd47094 TR |
580 | printk(KERN_ERR FW_BUG PFX "vid %d invalid : 0x%x\n", |
581 | j, pst[j].vid); | |
1da177e4 LT |
582 | return -EINVAL; |
583 | } | |
0e64a0c9 DJ |
584 | if (pst[j].vid < data->rvo) { |
585 | /* vid + rvo >= 0 */ | |
2fd47094 TR |
586 | printk(KERN_ERR FW_BUG PFX "0 vid exceeded with pstate" |
587 | " %d\n", j); | |
1da177e4 LT |
588 | return -ENODEV; |
589 | } | |
0e64a0c9 DJ |
590 | if (pst[j].vid < maxvid + data->rvo) { |
591 | /* vid + rvo >= maxvid */ | |
2fd47094 TR |
592 | printk(KERN_ERR FW_BUG PFX "maxvid exceeded with pstate" |
593 | " %d\n", j); | |
1da177e4 LT |
594 | return -ENODEV; |
595 | } | |
8aae8284 | 596 | if (pst[j].fid > MAX_FID) { |
2fd47094 TR |
597 | printk(KERN_ERR FW_BUG PFX "maxfid exceeded with pstate" |
598 | " %d\n", j); | |
8aae8284 JS |
599 | return -ENODEV; |
600 | } | |
8aae8284 | 601 | if (j && (pst[j].fid < HI_FID_TABLE_BOTTOM)) { |
1da177e4 | 602 | /* Only first fid is allowed to be in "low" range */ |
2fd47094 TR |
603 | printk(KERN_ERR FW_BUG PFX "two low fids - %d : " |
604 | "0x%x\n", j, pst[j].fid); | |
1da177e4 LT |
605 | return -EINVAL; |
606 | } | |
607 | if (pst[j].fid < lastfid) | |
608 | lastfid = pst[j].fid; | |
609 | } | |
610 | if (lastfid & 1) { | |
2fd47094 | 611 | printk(KERN_ERR FW_BUG PFX "lastfid invalid\n"); |
1da177e4 LT |
612 | return -EINVAL; |
613 | } | |
614 | if (lastfid > LO_FID_TABLE_TOP) | |
0e64a0c9 DJ |
615 | printk(KERN_INFO FW_BUG PFX |
616 | "first fid not from lo freq table\n"); | |
1da177e4 LT |
617 | |
618 | return 0; | |
619 | } | |
620 | ||
0e64a0c9 DJ |
621 | static void invalidate_entry(struct powernow_k8_data *data, unsigned int entry) |
622 | { | |
623 | data->powernow_table[entry].frequency = CPUFREQ_ENTRY_INVALID; | |
624 | } | |
625 | ||
1da177e4 LT |
626 | static void print_basics(struct powernow_k8_data *data) |
627 | { | |
628 | int j; | |
629 | for (j = 0; j < data->numps; j++) { | |
0e64a0c9 DJ |
630 | if (data->powernow_table[j].frequency != |
631 | CPUFREQ_ENTRY_INVALID) { | |
e7bdd7a5 | 632 | if (cpu_family == CPU_HW_PSTATE) { |
0e64a0c9 DJ |
633 | printk(KERN_INFO PFX |
634 | " %d : pstate %d (%d MHz)\n", j, | |
4ae5c49f | 635 | data->powernow_table[j].index, |
9a60ddbc | 636 | data->powernow_table[j].frequency/1000); |
1f729e06 | 637 | } else { |
0e64a0c9 DJ |
638 | printk(KERN_INFO PFX |
639 | " %d : fid 0x%x (%d MHz), vid 0x%x\n", | |
9a60ddbc DJ |
640 | j, |
641 | data->powernow_table[j].index & 0xff, | |
642 | data->powernow_table[j].frequency/1000, | |
643 | data->powernow_table[j].index >> 8); | |
1f729e06 DJ |
644 | } |
645 | } | |
1da177e4 LT |
646 | } |
647 | if (data->batps) | |
0e64a0c9 DJ |
648 | printk(KERN_INFO PFX "Only %d pstates on battery\n", |
649 | data->batps); | |
1da177e4 LT |
650 | } |
651 | ||
ca446d06 AH |
652 | static u32 freq_from_fid_did(u32 fid, u32 did) |
653 | { | |
654 | u32 mhz = 0; | |
655 | ||
656 | if (boot_cpu_data.x86 == 0x10) | |
657 | mhz = (100 * (fid + 0x10)) >> did; | |
658 | else if (boot_cpu_data.x86 == 0x11) | |
659 | mhz = (100 * (fid + 8)) >> did; | |
660 | else | |
661 | BUG(); | |
662 | ||
663 | return mhz * 1000; | |
664 | } | |
665 | ||
0e64a0c9 DJ |
666 | static int fill_powernow_table(struct powernow_k8_data *data, |
667 | struct pst_s *pst, u8 maxvid) | |
1da177e4 LT |
668 | { |
669 | struct cpufreq_frequency_table *powernow_table; | |
670 | unsigned int j; | |
671 | ||
0e64a0c9 DJ |
672 | if (data->batps) { |
673 | /* use ACPI support to get full speed on mains power */ | |
674 | printk(KERN_WARNING PFX | |
675 | "Only %d pstates usable (use ACPI driver for full " | |
676 | "range\n", data->batps); | |
1da177e4 LT |
677 | data->numps = data->batps; |
678 | } | |
679 | ||
0e64a0c9 | 680 | for (j = 1; j < data->numps; j++) { |
1da177e4 LT |
681 | if (pst[j-1].fid >= pst[j].fid) { |
682 | printk(KERN_ERR PFX "PST out of sequence\n"); | |
683 | return -EINVAL; | |
684 | } | |
685 | } | |
686 | ||
687 | if (data->numps < 2) { | |
688 | printk(KERN_ERR PFX "no p states to transition\n"); | |
689 | return -ENODEV; | |
690 | } | |
691 | ||
692 | if (check_pst_table(data, pst, maxvid)) | |
693 | return -EINVAL; | |
694 | ||
695 | powernow_table = kmalloc((sizeof(struct cpufreq_frequency_table) | |
696 | * (data->numps + 1)), GFP_KERNEL); | |
697 | if (!powernow_table) { | |
698 | printk(KERN_ERR PFX "powernow_table memory alloc failure\n"); | |
699 | return -ENOMEM; | |
700 | } | |
701 | ||
702 | for (j = 0; j < data->numps; j++) { | |
0e64a0c9 | 703 | int freq; |
1da177e4 LT |
704 | powernow_table[j].index = pst[j].fid; /* lower 8 bits */ |
705 | powernow_table[j].index |= (pst[j].vid << 8); /* upper 8 bits */ | |
0e64a0c9 DJ |
706 | freq = find_khz_freq_from_fid(pst[j].fid); |
707 | powernow_table[j].frequency = freq; | |
1da177e4 LT |
708 | } |
709 | powernow_table[data->numps].frequency = CPUFREQ_TABLE_END; | |
710 | powernow_table[data->numps].index = 0; | |
711 | ||
712 | if (query_current_values_with_pending_wait(data)) { | |
713 | kfree(powernow_table); | |
714 | return -EIO; | |
715 | } | |
716 | ||
717 | dprintk("cfid 0x%x, cvid 0x%x\n", data->currfid, data->currvid); | |
718 | data->powernow_table = powernow_table; | |
7ad728f9 | 719 | if (cpumask_first(cpu_core_mask(data->cpu)) == data->cpu) |
2e497620 | 720 | print_basics(data); |
1da177e4 LT |
721 | |
722 | for (j = 0; j < data->numps; j++) | |
0e64a0c9 DJ |
723 | if ((pst[j].fid == data->currfid) && |
724 | (pst[j].vid == data->currvid)) | |
1da177e4 LT |
725 | return 0; |
726 | ||
727 | dprintk("currfid/vid do not match PST, ignoring\n"); | |
728 | return 0; | |
729 | } | |
730 | ||
731 | /* Find and validate the PSB/PST table in BIOS. */ | |
732 | static int find_psb_table(struct powernow_k8_data *data) | |
733 | { | |
734 | struct psb_s *psb; | |
735 | unsigned int i; | |
736 | u32 mvs; | |
737 | u8 maxvid; | |
738 | u32 cpst = 0; | |
739 | u32 thiscpuid; | |
740 | ||
741 | for (i = 0xc0000; i < 0xffff0; i += 0x10) { | |
742 | /* Scan BIOS looking for the signature. */ | |
743 | /* It can not be at ffff0 - it is too big. */ | |
744 | ||
745 | psb = phys_to_virt(i); | |
746 | if (memcmp(psb, PSB_ID_STRING, PSB_ID_STRING_LEN) != 0) | |
747 | continue; | |
748 | ||
749 | dprintk("found PSB header at 0x%p\n", psb); | |
750 | ||
751 | dprintk("table vers: 0x%x\n", psb->tableversion); | |
752 | if (psb->tableversion != PSB_VERSION_1_4) { | |
2fd47094 | 753 | printk(KERN_ERR FW_BUG PFX "PSB table is not v1.4\n"); |
1da177e4 LT |
754 | return -ENODEV; |
755 | } | |
756 | ||
757 | dprintk("flags: 0x%x\n", psb->flags1); | |
758 | if (psb->flags1) { | |
2fd47094 | 759 | printk(KERN_ERR FW_BUG PFX "unknown flags\n"); |
1da177e4 LT |
760 | return -ENODEV; |
761 | } | |
762 | ||
763 | data->vstable = psb->vstable; | |
0e64a0c9 DJ |
764 | dprintk("voltage stabilization time: %d(*20us)\n", |
765 | data->vstable); | |
1da177e4 LT |
766 | |
767 | dprintk("flags2: 0x%x\n", psb->flags2); | |
768 | data->rvo = psb->flags2 & 3; | |
769 | data->irt = ((psb->flags2) >> 2) & 3; | |
770 | mvs = ((psb->flags2) >> 4) & 3; | |
771 | data->vidmvs = 1 << mvs; | |
772 | data->batps = ((psb->flags2) >> 6) & 3; | |
773 | ||
774 | dprintk("ramp voltage offset: %d\n", data->rvo); | |
775 | dprintk("isochronous relief time: %d\n", data->irt); | |
776 | dprintk("maximum voltage step: %d - 0x%x\n", mvs, data->vidmvs); | |
777 | ||
778 | dprintk("numpst: 0x%x\n", psb->num_tables); | |
779 | cpst = psb->num_tables; | |
0e64a0c9 DJ |
780 | if ((psb->cpuid == 0x00000fc0) || |
781 | (psb->cpuid == 0x00000fe0)) { | |
1da177e4 | 782 | thiscpuid = cpuid_eax(CPUID_PROCESSOR_SIGNATURE); |
0e64a0c9 DJ |
783 | if ((thiscpuid == 0x00000fc0) || |
784 | (thiscpuid == 0x00000fe0)) | |
1da177e4 | 785 | cpst = 1; |
1da177e4 LT |
786 | } |
787 | if (cpst != 1) { | |
2fd47094 | 788 | printk(KERN_ERR FW_BUG PFX "numpst must be 1\n"); |
1da177e4 LT |
789 | return -ENODEV; |
790 | } | |
791 | ||
792 | data->plllock = psb->plllocktime; | |
793 | dprintk("plllocktime: 0x%x (units 1us)\n", psb->plllocktime); | |
794 | dprintk("maxfid: 0x%x\n", psb->maxfid); | |
795 | dprintk("maxvid: 0x%x\n", psb->maxvid); | |
796 | maxvid = psb->maxvid; | |
797 | ||
798 | data->numps = psb->numps; | |
799 | dprintk("numpstates: 0x%x\n", data->numps); | |
0e64a0c9 DJ |
800 | return fill_powernow_table(data, |
801 | (struct pst_s *)(psb+1), maxvid); | |
1da177e4 LT |
802 | } |
803 | /* | |
804 | * If you see this message, complain to BIOS manufacturer. If | |
805 | * he tells you "we do not support Linux" or some similar | |
806 | * nonsense, remember that Windows 2000 uses the same legacy | |
807 | * mechanism that the old Linux PSB driver uses. Tell them it | |
808 | * is broken with Windows 2000. | |
809 | * | |
810 | * The reference to the AMD documentation is chapter 9 in the | |
811 | * BIOS and Kernel Developer's Guide, which is available on | |
812 | * www.amd.com | |
813 | */ | |
79cc56af | 814 | printk(KERN_ERR FW_BUG PFX "No PSB or ACPI _PSS objects\n"); |
1da177e4 LT |
815 | return -ENODEV; |
816 | } | |
817 | ||
0e64a0c9 DJ |
818 | static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, |
819 | unsigned int index) | |
1da177e4 | 820 | { |
0e64a0c9 DJ |
821 | acpi_integer control; |
822 | ||
f607e3a0 | 823 | if (!data->acpi_data.state_count || (cpu_family == CPU_HW_PSTATE)) |
1da177e4 LT |
824 | return; |
825 | ||
0e64a0c9 DJ |
826 | control = data->acpi_data.states[index].control; data->irt = (control |
827 | >> IRT_SHIFT) & IRT_MASK; data->rvo = (control >> | |
828 | RVO_SHIFT) & RVO_MASK; data->exttype = (control | |
829 | >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK; | |
830 | data->plllock = (control >> PLL_L_SHIFT) & PLL_L_MASK; data->vidmvs = 1 | |
831 | << ((control >> MVS_SHIFT) & MVS_MASK); data->vstable = | |
832 | (control >> VST_SHIFT) & VST_MASK; } | |
1da177e4 LT |
833 | |
834 | static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data) | |
835 | { | |
1da177e4 | 836 | struct cpufreq_frequency_table *powernow_table; |
2fdf66b4 | 837 | int ret_val = -ENODEV; |
0e64a0c9 | 838 | acpi_integer space_id; |
1da177e4 | 839 | |
f607e3a0 | 840 | if (acpi_processor_register_performance(&data->acpi_data, data->cpu)) { |
065b807c | 841 | dprintk("register performance failed: bad ACPI data\n"); |
1da177e4 LT |
842 | return -EIO; |
843 | } | |
844 | ||
845 | /* verify the data contained in the ACPI structures */ | |
f607e3a0 | 846 | if (data->acpi_data.state_count <= 1) { |
1da177e4 LT |
847 | dprintk("No ACPI P-States\n"); |
848 | goto err_out; | |
849 | } | |
850 | ||
0e64a0c9 DJ |
851 | space_id = data->acpi_data.control_register.space_id; |
852 | if ((space_id != ACPI_ADR_SPACE_FIXED_HARDWARE) || | |
853 | (space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) { | |
1da177e4 | 854 | dprintk("Invalid control/status registers (%x - %x)\n", |
f607e3a0 | 855 | data->acpi_data.control_register.space_id, |
0e64a0c9 | 856 | space_id); |
1da177e4 LT |
857 | goto err_out; |
858 | } | |
859 | ||
860 | /* fill in data->powernow_table */ | |
861 | powernow_table = kmalloc((sizeof(struct cpufreq_frequency_table) | |
f607e3a0 | 862 | * (data->acpi_data.state_count + 1)), GFP_KERNEL); |
1da177e4 LT |
863 | if (!powernow_table) { |
864 | dprintk("powernow_table memory alloc failure\n"); | |
865 | goto err_out; | |
866 | } | |
867 | ||
e7bdd7a5 | 868 | if (cpu_family == CPU_HW_PSTATE) |
1f729e06 DJ |
869 | ret_val = fill_powernow_table_pstate(data, powernow_table); |
870 | else | |
871 | ret_val = fill_powernow_table_fidvid(data, powernow_table); | |
872 | if (ret_val) | |
873 | goto err_out_mem; | |
874 | ||
0e64a0c9 DJ |
875 | powernow_table[data->acpi_data.state_count].frequency = |
876 | CPUFREQ_TABLE_END; | |
f607e3a0 | 877 | powernow_table[data->acpi_data.state_count].index = 0; |
1f729e06 DJ |
878 | data->powernow_table = powernow_table; |
879 | ||
880 | /* fill in data */ | |
f607e3a0 | 881 | data->numps = data->acpi_data.state_count; |
7ad728f9 | 882 | if (cpumask_first(cpu_core_mask(data->cpu)) == data->cpu) |
2e497620 | 883 | print_basics(data); |
1f729e06 DJ |
884 | powernow_k8_acpi_pst_values(data, 0); |
885 | ||
886 | /* notify BIOS that we exist */ | |
887 | acpi_processor_notify_smm(THIS_MODULE); | |
888 | ||
2fdf66b4 RR |
889 | if (!alloc_cpumask_var(&data->acpi_data.shared_cpu_map, GFP_KERNEL)) { |
890 | printk(KERN_ERR PFX | |
891 | "unable to alloc powernow_k8_data cpumask\n"); | |
892 | ret_val = -ENOMEM; | |
893 | goto err_out_mem; | |
894 | } | |
895 | ||
1f729e06 DJ |
896 | return 0; |
897 | ||
898 | err_out_mem: | |
899 | kfree(powernow_table); | |
900 | ||
901 | err_out: | |
f607e3a0 | 902 | acpi_processor_unregister_performance(&data->acpi_data, data->cpu); |
1f729e06 | 903 | |
0e64a0c9 DJ |
904 | /* data->acpi_data.state_count informs us at ->exit() |
905 | * whether ACPI was used */ | |
f607e3a0 | 906 | data->acpi_data.state_count = 0; |
1f729e06 | 907 | |
2fdf66b4 | 908 | return ret_val; |
1f729e06 DJ |
909 | } |
910 | ||
0e64a0c9 DJ |
911 | static int fill_powernow_table_pstate(struct powernow_k8_data *data, |
912 | struct cpufreq_frequency_table *powernow_table) | |
1f729e06 DJ |
913 | { |
914 | int i; | |
c5829cd0 ML |
915 | u32 hi = 0, lo = 0; |
916 | rdmsr(MSR_PSTATE_CUR_LIMIT, hi, lo); | |
917 | data->max_hw_pstate = (hi & HW_PSTATE_MAX_MASK) >> HW_PSTATE_MAX_SHIFT; | |
1f729e06 | 918 | |
f607e3a0 | 919 | for (i = 0; i < data->acpi_data.state_count; i++) { |
1f729e06 | 920 | u32 index; |
1f729e06 | 921 | |
f607e3a0 | 922 | index = data->acpi_data.states[i].control & HW_PSTATE_MASK; |
c5829cd0 | 923 | if (index > data->max_hw_pstate) { |
0e64a0c9 DJ |
924 | printk(KERN_ERR PFX "invalid pstate %d - " |
925 | "bad value %d.\n", i, index); | |
926 | printk(KERN_ERR PFX "Please report to BIOS " | |
927 | "manufacturer\n"); | |
928 | invalidate_entry(data, i); | |
c5829cd0 | 929 | continue; |
1f729e06 DJ |
930 | } |
931 | rdmsr(MSR_PSTATE_DEF_BASE + index, lo, hi); | |
932 | if (!(hi & HW_PSTATE_VALID_MASK)) { | |
933 | dprintk("invalid pstate %d, ignoring\n", index); | |
0e64a0c9 | 934 | invalidate_entry(data, i); |
1f729e06 DJ |
935 | continue; |
936 | } | |
937 | ||
c5829cd0 | 938 | powernow_table[i].index = index; |
1f729e06 | 939 | |
ca446d06 AH |
940 | /* Frequency may be rounded for these */ |
941 | if (boot_cpu_data.x86 == 0x10 || boot_cpu_data.x86 == 0x11) { | |
942 | powernow_table[i].frequency = | |
943 | freq_from_fid_did(lo & 0x3f, (lo >> 6) & 7); | |
944 | } else | |
945 | powernow_table[i].frequency = | |
946 | data->acpi_data.states[i].core_frequency * 1000; | |
1f729e06 DJ |
947 | } |
948 | return 0; | |
949 | } | |
950 | ||
0e64a0c9 DJ |
951 | static int fill_powernow_table_fidvid(struct powernow_k8_data *data, |
952 | struct cpufreq_frequency_table *powernow_table) | |
1f729e06 DJ |
953 | { |
954 | int i; | |
955 | int cntlofreq = 0; | |
0e64a0c9 | 956 | |
f607e3a0 | 957 | for (i = 0; i < data->acpi_data.state_count; i++) { |
094ce7fd DJ |
958 | u32 fid; |
959 | u32 vid; | |
0e64a0c9 DJ |
960 | u32 freq, index; |
961 | acpi_integer status, control; | |
094ce7fd DJ |
962 | |
963 | if (data->exttype) { | |
0e64a0c9 DJ |
964 | status = data->acpi_data.states[i].status; |
965 | fid = status & EXT_FID_MASK; | |
966 | vid = (status >> VID_SHIFT) & EXT_VID_MASK; | |
841e40b3 | 967 | } else { |
0e64a0c9 DJ |
968 | control = data->acpi_data.states[i].control; |
969 | fid = control & FID_MASK; | |
970 | vid = (control >> VID_SHIFT) & VID_MASK; | |
841e40b3 | 971 | } |
1da177e4 LT |
972 | |
973 | dprintk(" %d : fid 0x%x, vid 0x%x\n", i, fid, vid); | |
974 | ||
0e64a0c9 DJ |
975 | index = fid | (vid<<8); |
976 | powernow_table[i].index = index; | |
977 | ||
978 | freq = find_khz_freq_from_fid(fid); | |
979 | powernow_table[i].frequency = freq; | |
1da177e4 LT |
980 | |
981 | /* verify frequency is OK */ | |
0e64a0c9 DJ |
982 | if ((freq > (MAX_FREQ * 1000)) || (freq < (MIN_FREQ * 1000))) { |
983 | dprintk("invalid freq %u kHz, ignoring\n", freq); | |
984 | invalidate_entry(data, i); | |
1da177e4 LT |
985 | continue; |
986 | } | |
987 | ||
0e64a0c9 DJ |
988 | /* verify voltage is OK - |
989 | * BIOSs are using "off" to indicate invalid */ | |
841e40b3 | 990 | if (vid == VID_OFF) { |
1da177e4 | 991 | dprintk("invalid vid %u, ignoring\n", vid); |
0e64a0c9 | 992 | invalidate_entry(data, i); |
1da177e4 LT |
993 | continue; |
994 | } | |
995 | ||
065b807c DJ |
996 | /* verify only 1 entry from the lo frequency table */ |
997 | if (fid < HI_FID_TABLE_BOTTOM) { | |
998 | if (cntlofreq) { | |
0e64a0c9 DJ |
999 | /* if both entries are the same, |
1000 | * ignore this one ... */ | |
1001 | if ((freq != powernow_table[cntlofreq].frequency) || | |
1002 | (index != powernow_table[cntlofreq].index)) { | |
1003 | printk(KERN_ERR PFX | |
1004 | "Too many lo freq table " | |
1005 | "entries\n"); | |
1f729e06 | 1006 | return 1; |
065b807c DJ |
1007 | } |
1008 | ||
0e64a0c9 DJ |
1009 | dprintk("double low frequency table entry, " |
1010 | "ignoring it.\n"); | |
1011 | invalidate_entry(data, i); | |
065b807c DJ |
1012 | continue; |
1013 | } else | |
1014 | cntlofreq = i; | |
1da177e4 LT |
1015 | } |
1016 | ||
0e64a0c9 DJ |
1017 | if (freq != (data->acpi_data.states[i].core_frequency * 1000)) { |
1018 | printk(KERN_INFO PFX "invalid freq entries " | |
1019 | "%u kHz vs. %u kHz\n", freq, | |
1020 | (unsigned int) | |
1021 | (data->acpi_data.states[i].core_frequency | |
1022 | * 1000)); | |
1023 | invalidate_entry(data, i); | |
1da177e4 LT |
1024 | continue; |
1025 | } | |
1026 | } | |
1da177e4 | 1027 | return 0; |
1da177e4 LT |
1028 | } |
1029 | ||
1030 | static void powernow_k8_cpu_exit_acpi(struct powernow_k8_data *data) | |
1031 | { | |
f607e3a0 | 1032 | if (data->acpi_data.state_count) |
0e64a0c9 DJ |
1033 | acpi_processor_unregister_performance(&data->acpi_data, |
1034 | data->cpu); | |
2fdf66b4 | 1035 | free_cpumask_var(data->acpi_data.shared_cpu_map); |
1da177e4 LT |
1036 | } |
1037 | ||
732553e5 ML |
1038 | static int get_transition_latency(struct powernow_k8_data *data) |
1039 | { | |
1040 | int max_latency = 0; | |
1041 | int i; | |
1042 | for (i = 0; i < data->acpi_data.state_count; i++) { | |
1043 | int cur_latency = data->acpi_data.states[i].transition_latency | |
1044 | + data->acpi_data.states[i].bus_master_latency; | |
1045 | if (cur_latency > max_latency) | |
1046 | max_latency = cur_latency; | |
1047 | } | |
1048 | /* value in usecs, needs to be in nanoseconds */ | |
1049 | return 1000 * max_latency; | |
1050 | } | |
1051 | ||
1da177e4 | 1052 | /* Take a frequency, and issue the fid/vid transition command */ |
0e64a0c9 DJ |
1053 | static int transition_frequency_fidvid(struct powernow_k8_data *data, |
1054 | unsigned int index) | |
1da177e4 | 1055 | { |
1f729e06 DJ |
1056 | u32 fid = 0; |
1057 | u32 vid = 0; | |
065b807c | 1058 | int res, i; |
1da177e4 LT |
1059 | struct cpufreq_freqs freqs; |
1060 | ||
1061 | dprintk("cpu %d transition to index %u\n", smp_processor_id(), index); | |
1062 | ||
1f729e06 | 1063 | /* fid/vid correctness check for k8 */ |
1da177e4 | 1064 | /* fid are the lower 8 bits of the index we stored into |
1f729e06 DJ |
1065 | * the cpufreq frequency table in find_psb_table, vid |
1066 | * are the upper 8 bits. | |
1da177e4 | 1067 | */ |
1da177e4 LT |
1068 | fid = data->powernow_table[index].index & 0xFF; |
1069 | vid = (data->powernow_table[index].index & 0xFF00) >> 8; | |
1070 | ||
1071 | dprintk("table matched fid 0x%x, giving vid 0x%x\n", fid, vid); | |
1072 | ||
1073 | if (query_current_values_with_pending_wait(data)) | |
1074 | return 1; | |
1075 | ||
1076 | if ((data->currvid == vid) && (data->currfid == fid)) { | |
1077 | dprintk("target matches current values (fid 0x%x, vid 0x%x)\n", | |
1078 | fid, vid); | |
1079 | return 0; | |
1080 | } | |
1081 | ||
0e64a0c9 DJ |
1082 | if ((fid < HI_FID_TABLE_BOTTOM) && |
1083 | (data->currfid < HI_FID_TABLE_BOTTOM)) { | |
065b807c DJ |
1084 | printk(KERN_ERR PFX |
1085 | "ignoring illegal change in lo freq table-%x to 0x%x\n", | |
1da177e4 LT |
1086 | data->currfid, fid); |
1087 | return 1; | |
1088 | } | |
1089 | ||
1090 | dprintk("cpu %d, changing to fid 0x%x, vid 0x%x\n", | |
1091 | smp_processor_id(), fid, vid); | |
1da177e4 LT |
1092 | freqs.old = find_khz_freq_from_fid(data->currfid); |
1093 | freqs.new = find_khz_freq_from_fid(fid); | |
1f729e06 | 1094 | |
334ef7a7 | 1095 | for_each_cpu_mask_nr(i, *(data->available_cores)) { |
065b807c DJ |
1096 | freqs.cpu = i; |
1097 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); | |
1098 | } | |
1da177e4 | 1099 | |
1da177e4 | 1100 | res = transition_fid_vid(data, fid, vid); |
1da177e4 | 1101 | freqs.new = find_khz_freq_from_fid(data->currfid); |
1f729e06 | 1102 | |
334ef7a7 | 1103 | for_each_cpu_mask_nr(i, *(data->available_cores)) { |
1f729e06 DJ |
1104 | freqs.cpu = i; |
1105 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | |
1106 | } | |
1107 | return res; | |
1108 | } | |
1109 | ||
1110 | /* Take a frequency, and issue the hardware pstate transition command */ | |
0e64a0c9 DJ |
1111 | static int transition_frequency_pstate(struct powernow_k8_data *data, |
1112 | unsigned int index) | |
1f729e06 | 1113 | { |
1f729e06 DJ |
1114 | u32 pstate = 0; |
1115 | int res, i; | |
1116 | struct cpufreq_freqs freqs; | |
1117 | ||
1118 | dprintk("cpu %d transition to index %u\n", smp_processor_id(), index); | |
1119 | ||
c5829cd0 | 1120 | /* get MSR index for hardware pstate transition */ |
1f729e06 | 1121 | pstate = index & HW_PSTATE_MASK; |
c5829cd0 | 1122 | if (pstate > data->max_hw_pstate) |
1f729e06 | 1123 | return 0; |
0e64a0c9 DJ |
1124 | freqs.old = find_khz_freq_from_pstate(data->powernow_table, |
1125 | data->currpstate); | |
c5829cd0 | 1126 | freqs.new = find_khz_freq_from_pstate(data->powernow_table, pstate); |
1f729e06 | 1127 | |
334ef7a7 | 1128 | for_each_cpu_mask_nr(i, *(data->available_cores)) { |
1f729e06 DJ |
1129 | freqs.cpu = i; |
1130 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); | |
1131 | } | |
1132 | ||
1133 | res = transition_pstate(data, pstate); | |
c5829cd0 | 1134 | freqs.new = find_khz_freq_from_pstate(data->powernow_table, pstate); |
1f729e06 | 1135 | |
334ef7a7 | 1136 | for_each_cpu_mask_nr(i, *(data->available_cores)) { |
065b807c DJ |
1137 | freqs.cpu = i; |
1138 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | |
2e3f8faa | 1139 | } |
1da177e4 LT |
1140 | return res; |
1141 | } | |
1142 | ||
1143 | /* Driver entry point to switch to the target frequency */ | |
0e64a0c9 DJ |
1144 | static int powernowk8_target(struct cpufreq_policy *pol, |
1145 | unsigned targfreq, unsigned relation) | |
1da177e4 | 1146 | { |
fc0e4748 | 1147 | cpumask_t oldmask; |
2c6b8c03 | 1148 | struct powernow_k8_data *data = per_cpu(powernow_data, pol->cpu); |
9180053c AB |
1149 | u32 checkfid; |
1150 | u32 checkvid; | |
1da177e4 LT |
1151 | unsigned int newstate; |
1152 | int ret = -EIO; | |
1153 | ||
4211a303 JS |
1154 | if (!data) |
1155 | return -EINVAL; | |
1156 | ||
9180053c AB |
1157 | checkfid = data->currfid; |
1158 | checkvid = data->currvid; | |
1159 | ||
1da177e4 LT |
1160 | /* only run on specific CPU from here on */ |
1161 | oldmask = current->cpus_allowed; | |
0bc3cc03 | 1162 | set_cpus_allowed_ptr(current, &cpumask_of_cpu(pol->cpu)); |
1da177e4 LT |
1163 | |
1164 | if (smp_processor_id() != pol->cpu) { | |
8aae8284 | 1165 | printk(KERN_ERR PFX "limiting to cpu %u failed\n", pol->cpu); |
1da177e4 LT |
1166 | goto err_out; |
1167 | } | |
1168 | ||
1169 | if (pending_bit_stuck()) { | |
1170 | printk(KERN_ERR PFX "failing targ, change pending bit set\n"); | |
1171 | goto err_out; | |
1172 | } | |
1173 | ||
1174 | dprintk("targ: cpu %d, %d kHz, min %d, max %d, relation %d\n", | |
1175 | pol->cpu, targfreq, pol->min, pol->max, relation); | |
1176 | ||
83844510 | 1177 | if (query_current_values_with_pending_wait(data)) |
1da177e4 | 1178 | goto err_out; |
1da177e4 | 1179 | |
c5829cd0 | 1180 | if (cpu_family != CPU_HW_PSTATE) { |
1f729e06 | 1181 | dprintk("targ: curr fid 0x%x, vid 0x%x\n", |
1da177e4 LT |
1182 | data->currfid, data->currvid); |
1183 | ||
0e64a0c9 DJ |
1184 | if ((checkvid != data->currvid) || |
1185 | (checkfid != data->currfid)) { | |
1f729e06 | 1186 | printk(KERN_INFO PFX |
0e64a0c9 DJ |
1187 | "error - out of sync, fix 0x%x 0x%x, " |
1188 | "vid 0x%x 0x%x\n", | |
1189 | checkfid, data->currfid, | |
1190 | checkvid, data->currvid); | |
1f729e06 | 1191 | } |
1da177e4 LT |
1192 | } |
1193 | ||
0e64a0c9 DJ |
1194 | if (cpufreq_frequency_table_target(pol, data->powernow_table, |
1195 | targfreq, relation, &newstate)) | |
1da177e4 LT |
1196 | goto err_out; |
1197 | ||
14cc3e2b | 1198 | mutex_lock(&fidvid_mutex); |
065b807c | 1199 | |
1da177e4 LT |
1200 | powernow_k8_acpi_pst_values(data, newstate); |
1201 | ||
e7bdd7a5 | 1202 | if (cpu_family == CPU_HW_PSTATE) |
1f729e06 DJ |
1203 | ret = transition_frequency_pstate(data, newstate); |
1204 | else | |
1205 | ret = transition_frequency_fidvid(data, newstate); | |
1206 | if (ret) { | |
1da177e4 LT |
1207 | printk(KERN_ERR PFX "transition frequency failed\n"); |
1208 | ret = 1; | |
14cc3e2b | 1209 | mutex_unlock(&fidvid_mutex); |
1da177e4 LT |
1210 | goto err_out; |
1211 | } | |
14cc3e2b | 1212 | mutex_unlock(&fidvid_mutex); |
065b807c | 1213 | |
e7bdd7a5 | 1214 | if (cpu_family == CPU_HW_PSTATE) |
0e64a0c9 DJ |
1215 | pol->cur = find_khz_freq_from_pstate(data->powernow_table, |
1216 | newstate); | |
1f729e06 DJ |
1217 | else |
1218 | pol->cur = find_khz_freq_from_fid(data->currfid); | |
1da177e4 LT |
1219 | ret = 0; |
1220 | ||
1221 | err_out: | |
fc0e4748 | 1222 | set_cpus_allowed_ptr(current, &oldmask); |
1da177e4 LT |
1223 | return ret; |
1224 | } | |
1225 | ||
1226 | /* Driver entry point to verify the policy and range of frequencies */ | |
1227 | static int powernowk8_verify(struct cpufreq_policy *pol) | |
1228 | { | |
2c6b8c03 | 1229 | struct powernow_k8_data *data = per_cpu(powernow_data, pol->cpu); |
1da177e4 | 1230 | |
4211a303 JS |
1231 | if (!data) |
1232 | return -EINVAL; | |
1233 | ||
1da177e4 LT |
1234 | return cpufreq_frequency_table_verify(pol, data->powernow_table); |
1235 | } | |
1236 | ||
df182977 TR |
1237 | static const char ACPI_PSS_BIOS_BUG_MSG[] = |
1238 | KERN_ERR FW_BUG PFX "No compatible ACPI _PSS objects found.\n" | |
1239 | KERN_ERR FW_BUG PFX "Try again with latest BIOS.\n"; | |
1240 | ||
1da177e4 | 1241 | /* per CPU init entry point to the driver */ |
aa41eb99 | 1242 | static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol) |
1da177e4 LT |
1243 | { |
1244 | struct powernow_k8_data *data; | |
f607e3a0 | 1245 | cpumask_t oldmask; |
d7fa706c | 1246 | int rc; |
1da177e4 | 1247 | |
8aae8284 JS |
1248 | if (!cpu_online(pol->cpu)) |
1249 | return -ENODEV; | |
1250 | ||
1da177e4 LT |
1251 | if (!check_supported_cpu(pol->cpu)) |
1252 | return -ENODEV; | |
1253 | ||
bfdc708d | 1254 | data = kzalloc(sizeof(struct powernow_k8_data), GFP_KERNEL); |
1da177e4 LT |
1255 | if (!data) { |
1256 | printk(KERN_ERR PFX "unable to alloc powernow_k8_data"); | |
1257 | return -ENOMEM; | |
1258 | } | |
1da177e4 LT |
1259 | |
1260 | data->cpu = pol->cpu; | |
a266d9f1 | 1261 | data->currpstate = HW_PSTATE_INVALID; |
1da177e4 | 1262 | |
a0abd520 | 1263 | if (powernow_k8_cpu_init_acpi(data)) { |
1da177e4 LT |
1264 | /* |
1265 | * Use the PSB BIOS structure. This is only availabe on | |
1266 | * an UP version, and is deprecated by AMD. | |
1267 | */ | |
9ed059e1 | 1268 | if (num_online_cpus() != 1) { |
df182977 | 1269 | printk_once(ACPI_PSS_BIOS_BUG_MSG); |
0cb8bc25 | 1270 | goto err_out; |
1da177e4 LT |
1271 | } |
1272 | if (pol->cpu != 0) { | |
2fd47094 TR |
1273 | printk(KERN_ERR FW_BUG PFX "No ACPI _PSS objects for " |
1274 | "CPU other than CPU0. Complain to your BIOS " | |
1275 | "vendor.\n"); | |
0cb8bc25 | 1276 | goto err_out; |
1da177e4 LT |
1277 | } |
1278 | rc = find_psb_table(data); | |
0cb8bc25 DJ |
1279 | if (rc) |
1280 | goto err_out; | |
1281 | ||
732553e5 ML |
1282 | /* Take a crude guess here. |
1283 | * That guess was in microseconds, so multiply with 1000 */ | |
1284 | pol->cpuinfo.transition_latency = ( | |
1285 | ((data->rvo + 8) * data->vstable * VST_UNITS_20US) + | |
1286 | ((1 << data->irt) * 30)) * 1000; | |
1287 | } else /* ACPI _PSS objects available */ | |
1288 | pol->cpuinfo.transition_latency = get_transition_latency(data); | |
1da177e4 LT |
1289 | |
1290 | /* only run on specific CPU from here on */ | |
1291 | oldmask = current->cpus_allowed; | |
0bc3cc03 | 1292 | set_cpus_allowed_ptr(current, &cpumask_of_cpu(pol->cpu)); |
1da177e4 LT |
1293 | |
1294 | if (smp_processor_id() != pol->cpu) { | |
8aae8284 | 1295 | printk(KERN_ERR PFX "limiting to cpu %u failed\n", pol->cpu); |
0cb8bc25 | 1296 | goto err_out_unmask; |
1da177e4 LT |
1297 | } |
1298 | ||
1299 | if (pending_bit_stuck()) { | |
1300 | printk(KERN_ERR PFX "failing init, change pending bit set\n"); | |
0cb8bc25 | 1301 | goto err_out_unmask; |
1da177e4 LT |
1302 | } |
1303 | ||
1304 | if (query_current_values_with_pending_wait(data)) | |
0cb8bc25 | 1305 | goto err_out_unmask; |
1da177e4 | 1306 | |
e7bdd7a5 | 1307 | if (cpu_family == CPU_OPTERON) |
1f729e06 | 1308 | fidvid_msr_init(); |
1da177e4 LT |
1309 | |
1310 | /* run on any CPU again */ | |
fc0e4748 | 1311 | set_cpus_allowed_ptr(current, &oldmask); |
1da177e4 | 1312 | |
f607e3a0 | 1313 | if (cpu_family == CPU_HW_PSTATE) |
835481d9 | 1314 | cpumask_copy(pol->cpus, cpumask_of(pol->cpu)); |
f607e3a0 | 1315 | else |
7ad728f9 | 1316 | cpumask_copy(pol->cpus, cpu_core_mask(pol->cpu)); |
835481d9 | 1317 | data->available_cores = pol->cpus; |
1da177e4 | 1318 | |
e7bdd7a5 | 1319 | if (cpu_family == CPU_HW_PSTATE) |
0e64a0c9 DJ |
1320 | pol->cur = find_khz_freq_from_pstate(data->powernow_table, |
1321 | data->currpstate); | |
1f729e06 DJ |
1322 | else |
1323 | pol->cur = find_khz_freq_from_fid(data->currfid); | |
1da177e4 LT |
1324 | dprintk("policy current frequency %d kHz\n", pol->cur); |
1325 | ||
1326 | /* min/max the cpu is capable of */ | |
1327 | if (cpufreq_frequency_table_cpuinfo(pol, data->powernow_table)) { | |
2fd47094 | 1328 | printk(KERN_ERR FW_BUG PFX "invalid powernow_table\n"); |
1da177e4 LT |
1329 | powernow_k8_cpu_exit_acpi(data); |
1330 | kfree(data->powernow_table); | |
1331 | kfree(data); | |
1332 | return -EINVAL; | |
1333 | } | |
1334 | ||
1335 | cpufreq_frequency_table_get_attr(data->powernow_table, pol->cpu); | |
1336 | ||
e7bdd7a5 | 1337 | if (cpu_family == CPU_HW_PSTATE) |
0e64a0c9 DJ |
1338 | dprintk("cpu_init done, current pstate 0x%x\n", |
1339 | data->currpstate); | |
1f729e06 DJ |
1340 | else |
1341 | dprintk("cpu_init done, current fid 0x%x, vid 0x%x\n", | |
1342 | data->currfid, data->currvid); | |
1da177e4 | 1343 | |
2c6b8c03 | 1344 | per_cpu(powernow_data, pol->cpu) = data; |
1da177e4 LT |
1345 | |
1346 | return 0; | |
1347 | ||
0cb8bc25 | 1348 | err_out_unmask: |
fc0e4748 | 1349 | set_cpus_allowed_ptr(current, &oldmask); |
1da177e4 LT |
1350 | powernow_k8_cpu_exit_acpi(data); |
1351 | ||
0cb8bc25 | 1352 | err_out: |
1da177e4 LT |
1353 | kfree(data); |
1354 | return -ENODEV; | |
1355 | } | |
1356 | ||
0e64a0c9 | 1357 | static int __devexit powernowk8_cpu_exit(struct cpufreq_policy *pol) |
1da177e4 | 1358 | { |
2c6b8c03 | 1359 | struct powernow_k8_data *data = per_cpu(powernow_data, pol->cpu); |
1da177e4 LT |
1360 | |
1361 | if (!data) | |
1362 | return -EINVAL; | |
1363 | ||
1364 | powernow_k8_cpu_exit_acpi(data); | |
1365 | ||
1366 | cpufreq_frequency_table_put_attr(pol->cpu); | |
1367 | ||
1368 | kfree(data->powernow_table); | |
1369 | kfree(data); | |
1370 | ||
1371 | return 0; | |
1372 | } | |
1373 | ||
0e64a0c9 | 1374 | static unsigned int powernowk8_get(unsigned int cpu) |
1da177e4 | 1375 | { |
eef5167e | 1376 | struct powernow_k8_data *data; |
1da177e4 LT |
1377 | cpumask_t oldmask = current->cpus_allowed; |
1378 | unsigned int khz = 0; | |
89c04849 | 1379 | unsigned int first; |
1da177e4 | 1380 | |
7ad728f9 | 1381 | first = cpumask_first(cpu_core_mask(cpu)); |
89c04849 | 1382 | data = per_cpu(powernow_data, first); |
eef5167e JS |
1383 | |
1384 | if (!data) | |
1385 | return -EINVAL; | |
1386 | ||
0bc3cc03 | 1387 | set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu)); |
1da177e4 | 1388 | if (smp_processor_id() != cpu) { |
fc0e4748 MT |
1389 | printk(KERN_ERR PFX |
1390 | "limiting to CPU %d failed in powernowk8_get\n", cpu); | |
1391 | set_cpus_allowed_ptr(current, &oldmask); | |
1da177e4 LT |
1392 | return 0; |
1393 | } | |
b9111b7b | 1394 | |
1da177e4 LT |
1395 | if (query_current_values_with_pending_wait(data)) |
1396 | goto out; | |
1397 | ||
58389a86 | 1398 | if (cpu_family == CPU_HW_PSTATE) |
fc0e4748 MT |
1399 | khz = find_khz_freq_from_pstate(data->powernow_table, |
1400 | data->currpstate); | |
58389a86 JD |
1401 | else |
1402 | khz = find_khz_freq_from_fid(data->currfid); | |
1403 | ||
1da177e4 | 1404 | |
b9111b7b | 1405 | out: |
fc0e4748 | 1406 | set_cpus_allowed_ptr(current, &oldmask); |
1da177e4 LT |
1407 | return khz; |
1408 | } | |
1409 | ||
0e64a0c9 | 1410 | static struct freq_attr *powernow_k8_attr[] = { |
1da177e4 LT |
1411 | &cpufreq_freq_attr_scaling_available_freqs, |
1412 | NULL, | |
1413 | }; | |
1414 | ||
221dee28 | 1415 | static struct cpufreq_driver cpufreq_amd64_driver = { |
1da177e4 LT |
1416 | .verify = powernowk8_verify, |
1417 | .target = powernowk8_target, | |
1418 | .init = powernowk8_cpu_init, | |
1419 | .exit = __devexit_p(powernowk8_cpu_exit), | |
1420 | .get = powernowk8_get, | |
1421 | .name = "powernow-k8", | |
1422 | .owner = THIS_MODULE, | |
1423 | .attr = powernow_k8_attr, | |
1424 | }; | |
1425 | ||
1426 | /* driver entry point for init */ | |
aa41eb99 | 1427 | static int __cpuinit powernowk8_init(void) |
1da177e4 LT |
1428 | { |
1429 | unsigned int i, supported_cpus = 0; | |
1430 | ||
a7201156 | 1431 | for_each_online_cpu(i) { |
1da177e4 LT |
1432 | if (check_supported_cpu(i)) |
1433 | supported_cpus++; | |
1434 | } | |
1435 | ||
1436 | if (supported_cpus == num_online_cpus()) { | |
1f729e06 | 1437 | printk(KERN_INFO PFX "Found %d %s " |
904f7a3f | 1438 | "processors (%d cpu cores) (" VERSION ")\n", |
c925401b | 1439 | num_online_nodes(), |
904f7a3f | 1440 | boot_cpu_data.x86_model_id, supported_cpus); |
1da177e4 LT |
1441 | return cpufreq_register_driver(&cpufreq_amd64_driver); |
1442 | } | |
1443 | ||
1444 | return -ENODEV; | |
1445 | } | |
1446 | ||
1447 | /* driver entry point for term */ | |
1448 | static void __exit powernowk8_exit(void) | |
1449 | { | |
1450 | dprintk("exit\n"); | |
1451 | ||
1452 | cpufreq_unregister_driver(&cpufreq_amd64_driver); | |
1453 | } | |
1454 | ||
0e64a0c9 DJ |
1455 | MODULE_AUTHOR("Paul Devriendt <paul.devriendt@amd.com> and " |
1456 | "Mark Langsdorf <mark.langsdorf@amd.com>"); | |
1da177e4 LT |
1457 | MODULE_DESCRIPTION("AMD Athlon 64 and Opteron processor frequency driver."); |
1458 | MODULE_LICENSE("GPL"); | |
1459 | ||
1460 | late_initcall(powernowk8_init); | |
1461 | module_exit(powernowk8_exit); |