[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kernel / cpu / cpufreq / speedstep-centrino.c

/*
 * cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium
 * M (part of the Centrino chipset).
 *
 * Since the original Pentium M, most new Intel CPUs support Enhanced
 * SpeedStep.
 *
 * Despite the "SpeedStep" in the name, this is almost entirely unlike
 * traditional SpeedStep.
 *
 * Modelled on speedstep.c
 *
 * Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org>
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/cpufreq.h>
#include <linux/sched.h>	/* current */
#include <linux/delay.h>
#include <linux/compiler.h>

#include <asm/msr.h>
#include <asm/processor.h>
#include <asm/cpufeature.h>

#define PFX		"speedstep-centrino: "
#define MAINTAINER	"cpufreq@lists.linux.org.uk"

#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-centrino", msg)

#define INTEL_MSR_RANGE	(0xffff)

struct cpu_id
{
	__u8	x86;            /* CPU family */
	__u8	x86_model;	/* model */
	__u8	x86_mask;	/* stepping */
};

enum {
	CPU_BANIAS,
	CPU_DOTHAN_A1,
	CPU_DOTHAN_A2,
	CPU_DOTHAN_B0,
	CPU_MP4HT_D0,
	CPU_MP4HT_E0,
};

static const struct cpu_id cpu_ids[] = {
	[CPU_BANIAS]	= { 6,  9, 5 },
	[CPU_DOTHAN_A1]	= { 6, 13, 1 },
	[CPU_DOTHAN_A2]	= { 6, 13, 2 },
	[CPU_DOTHAN_B0]	= { 6, 13, 6 },
	[CPU_MP4HT_D0]	= {15,  3, 4 },
	[CPU_MP4HT_E0]	= {15,  4, 1 },
};
#define N_IDS	ARRAY_SIZE(cpu_ids)

struct cpu_model
{
	const struct cpu_id *cpu_id;
	const char	*model_name;
	unsigned	max_freq; /* max clock in kHz */

	struct cpufreq_frequency_table *op_points; /* clock/voltage pairs */
};
static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x);

/* Operating points for current CPU */
static struct cpu_model *centrino_model[NR_CPUS];
static const struct cpu_id *centrino_cpu[NR_CPUS];

static struct cpufreq_driver centrino_driver;

#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE

/* Computes the correct form for IA32_PERF_CTL MSR for a particular
   frequency/voltage operating point; frequency in MHz, volts in mV.
   This is stored as "index" in the structure. */
#define OP(mhz, mv)							\
	{								\
		.frequency = (mhz) * 1000,				\
		.index = (((mhz)/100) << 8) | ((mv - 700) / 16)		\
	}

/*
 * These voltage tables were derived from the Intel Pentium M
 * datasheet, document 25261202.pdf, Table 5.  I have verified they
 * are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium
 * M.
 */

/* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
static struct cpufreq_frequency_table banias_900[] =
{
	OP(600,  844),
	OP(800,  988),
	OP(900, 1004),
	{ .frequency = CPUFREQ_TABLE_END }
};

/* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
static struct cpufreq_frequency_table banias_1000[] =
{
	OP(600,   844),
	OP(800,   972),
	OP(900,   988),
	OP(1000, 1004),
	{ .frequency = CPUFREQ_TABLE_END }
};

/* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */
static struct cpufreq_frequency_table banias_1100[] =
{
	OP( 600,  956),
	OP( 800, 1020),
	OP( 900, 1100),
	OP(1000, 1164),
	OP(1100, 1180),
	{ .frequency = CPUFREQ_TABLE_END }
};


/* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */
static struct cpufreq_frequency_table banias_1200[] =
{
	OP( 600,  956),
	OP( 800, 1004),
	OP( 900, 1020),
	OP(1000, 1100),
	OP(1100, 1164),
	OP(1200, 1180),
	{ .frequency = CPUFREQ_TABLE_END }
};

/* Intel Pentium M processor 1.30GHz (Banias) */
static struct cpufreq_frequency_table banias_1300[] =
{
	OP( 600,  956),
	OP( 800, 1260),
	OP(1000, 1292),
	OP(1200, 1356),
	OP(1300, 1388),
	{ .frequency = CPUFREQ_TABLE_END }
};

/* Intel Pentium M processor 1.40GHz (Banias) */
static struct cpufreq_frequency_table banias_1400[] =
{
	OP( 600,  956),
	OP( 800, 1180),
	OP(1000, 1308),
	OP(1200, 1436),
	OP(1400, 1484),
	{ .frequency = CPUFREQ_TABLE_END }
};

/* Intel Pentium M processor 1.50GHz (Banias) */
static struct cpufreq_frequency_table banias_1500[] =
{
	OP( 600,  956),
	OP( 800, 1116),
	OP(1000, 1228),
	OP(1200, 1356),
	OP(1400, 1452),
	OP(1500, 1484),
	{ .frequency = CPUFREQ_TABLE_END }
};

/* Intel Pentium M processor 1.60GHz (Banias) */
static struct cpufreq_frequency_table banias_1600[] =
{
	OP( 600,  956),
	OP( 800, 1036),
	OP(1000, 1164),
	OP(1200, 1276),
	OP(1400, 1420),
	OP(1600, 1484),
	{ .frequency = CPUFREQ_TABLE_END }
};

/* Intel Pentium M processor 1.70GHz (Banias) */
static struct cpufreq_frequency_table banias_1700[] =
{
	OP( 600,  956),
	OP( 800, 1004),
	OP(1000, 1116),
	OP(1200, 1228),
	OP(1400, 1308),
	OP(1700, 1484),
	{ .frequency = CPUFREQ_TABLE_END }
};
#undef OP

#define _BANIAS(cpuid, max, name)	\
{	.cpu_id		= cpuid,	\
	.model_name	= "Intel(R) Pentium(R) M processor " name "MHz", \
	.max_freq	= (max)*1000,	\
	.op_points	= banias_##max,	\
}
#define BANIAS(max)	_BANIAS(&cpu_ids[CPU_BANIAS], max, #max)

/* CPU models, their operating frequency range, and freq/voltage
   operating points */
static struct cpu_model models[] =
{
	_BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"),
	BANIAS(1000),
	BANIAS(1100),
	BANIAS(1200),
	BANIAS(1300),
	BANIAS(1400),
	BANIAS(1500),
	BANIAS(1600),
	BANIAS(1700),

	/* NULL model_name is a wildcard */
	{ &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL },
	{ &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL },
	{ &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL },
	{ &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL },
	{ &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL },

	{ NULL, }
};
#undef _BANIAS
#undef BANIAS

static int centrino_cpu_init_table(struct cpufreq_policy *policy)
{
	struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
	struct cpu_model *model;

	for(model = models; model->cpu_id != NULL; model++)
		if (centrino_verify_cpu_id(cpu, model->cpu_id) &&
		    (model->model_name == NULL ||
		     strcmp(cpu->x86_model_id, model->model_name) == 0))
			break;

	if (model->cpu_id == NULL) {
		/* No match at all */
		dprintk("no support for CPU model \"%s\": "
		       "send /proc/cpuinfo to " MAINTAINER "\n",
		       cpu->x86_model_id);
		return -ENOENT;
	}

	if (model->op_points == NULL) {
		/* Matched a non-match */
		dprintk("no table support for CPU model \"%s\"\n",
		       cpu->x86_model_id);
		dprintk("try using the acpi-cpufreq driver\n");
		return -ENOENT;
	}

	centrino_model[policy->cpu] = model;

	dprintk("found \"%s\": max frequency: %dkHz\n",
	       model->model_name, model->max_freq);

	return 0;
}

#else
static inline int centrino_cpu_init_table(struct cpufreq_policy *policy) { return -ENODEV; }
#endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */

static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x)
{
	if ((c->x86 == x->x86) &&
	    (c->x86_model == x->x86_model) &&
	    (c->x86_mask == x->x86_mask))
		return 1;
	return 0;
}

/* To be called only after centrino_model is initialized */
static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe)
{
	int i;

	/*
	 * Extract clock in kHz from PERF_CTL value
	 * for centrino, as some DSDTs are buggy.
	 * Ideally, this can be done using the acpi_data structure.
	 */
	if ((centrino_cpu[cpu] == &cpu_ids[CPU_BANIAS]) ||
	    (centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_A1]) ||
	    (centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_B0])) {
		msr = (msr >> 8) & 0xff;
		return msr * 100000;
	}

	if ((!centrino_model[cpu]) || (!centrino_model[cpu]->op_points))
		return 0;

	msr &= 0xffff;
	for (i=0;centrino_model[cpu]->op_points[i].frequency != CPUFREQ_TABLE_END; i++) {
		if (msr == centrino_model[cpu]->op_points[i].index)
			return centrino_model[cpu]->op_points[i].frequency;
	}
	if (failsafe)
		return centrino_model[cpu]->op_points[i-1].frequency;
	else
		return 0;
}

/* Return the current CPU frequency in kHz */
static unsigned int get_cur_freq(unsigned int cpu)
{
	unsigned l, h;
	unsigned clock_freq;
	cpumask_t saved_mask;
	cpumask_of_cpu_ptr(new_mask, cpu);

	saved_mask = current->cpus_allowed;
	set_cpus_allowed_ptr(current, new_mask);
	if (smp_processor_id() != cpu)
		return 0;

	rdmsr(MSR_IA32_PERF_STATUS, l, h);
	clock_freq = extract_clock(l, cpu, 0);

	if (unlikely(clock_freq == 0)) {
		/*
		 * On some CPUs, we can see transient MSR values (which are
		 * not present in _PSS), while CPU is doing some automatic
		 * P-state transition (like TM2). Get the last freq set 
		 * in PERF_CTL.
		 */
		rdmsr(MSR_IA32_PERF_CTL, l, h);
		clock_freq = extract_clock(l, cpu, 1);
	}

	set_cpus_allowed_ptr(current, &saved_mask);
	return clock_freq;
}


static int centrino_cpu_init(struct cpufreq_policy *policy)
{
	struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
	unsigned freq;
	unsigned l, h;
	int ret;
	int i;

	/* Only Intel makes Enhanced Speedstep-capable CPUs */
	if (cpu->x86_vendor != X86_VENDOR_INTEL || !cpu_has(cpu, X86_FEATURE_EST))
		return -ENODEV;

	if (cpu_has(cpu, X86_FEATURE_CONSTANT_TSC))
		centrino_driver.flags |= CPUFREQ_CONST_LOOPS;

	if (policy->cpu != 0)
		return -ENODEV;

	for (i = 0; i < N_IDS; i++)
		if (centrino_verify_cpu_id(cpu, &cpu_ids[i]))
			break;

	if (i != N_IDS)
		centrino_cpu[policy->cpu] = &cpu_ids[i];

	if (!centrino_cpu[policy->cpu]) {
		dprintk("found unsupported CPU with "
		"Enhanced SpeedStep: send /proc/cpuinfo to "
		MAINTAINER "\n");
		return -ENODEV;
	}

	if (centrino_cpu_init_table(policy)) {
		return -ENODEV;
	}

	/* Check to see if Enhanced SpeedStep is enabled, and try to
	   enable it if not. */
	rdmsr(MSR_IA32_MISC_ENABLE, l, h);

	if (!(l & (1<<16))) {
		l |= (1<<16);
		dprintk("trying to enable Enhanced SpeedStep (%x)\n", l);
		wrmsr(MSR_IA32_MISC_ENABLE, l, h);

		/* check to see if it stuck */
		rdmsr(MSR_IA32_MISC_ENABLE, l, h);
		if (!(l & (1<<16))) {
			printk(KERN_INFO PFX "couldn't enable Enhanced SpeedStep\n");
			return -ENODEV;
		}
	}

	freq = get_cur_freq(policy->cpu);

	policy->cpuinfo.transition_latency = 10000; /* 10uS transition latency */
	policy->cur = freq;

	dprintk("centrino_cpu_init: cur=%dkHz\n", policy->cur);

	ret = cpufreq_frequency_table_cpuinfo(policy, centrino_model[policy->cpu]->op_points);
	if (ret)
		return (ret);

	cpufreq_frequency_table_get_attr(centrino_model[policy->cpu]->op_points, policy->cpu);

	return 0;
}

static int centrino_cpu_exit(struct cpufreq_policy *policy)
{
	unsigned int cpu = policy->cpu;

	if (!centrino_model[cpu])
		return -ENODEV;

	cpufreq_frequency_table_put_attr(cpu);

	centrino_model[cpu] = NULL;

	return 0;
}

/**
 * centrino_verify - verifies a new CPUFreq policy
 * @policy: new policy
 *
 * Limit must be within this model's frequency range at least one
 * border included.
 */
static int centrino_verify (struct cpufreq_policy *policy)
{
	return cpufreq_frequency_table_verify(policy, centrino_model[policy->cpu]->op_points);
}

/**
 * centrino_setpolicy - set a new CPUFreq policy
 * @policy: new policy
 * @target_freq: the target frequency
 * @relation: how that frequency relates to achieved frequency (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
 *
 * Sets a new CPUFreq policy.
 */
struct allmasks {
	cpumask_t		online_policy_cpus;
	cpumask_t		saved_mask;
	cpumask_t		set_mask;
	cpumask_t		covered_cpus;
};

static int centrino_target (struct cpufreq_policy *policy,
			    unsigned int target_freq,
			    unsigned int relation)
{
	unsigned int    newstate = 0;
	unsigned int	msr, oldmsr = 0, h = 0, cpu = policy->cpu;
	struct cpufreq_freqs	freqs;
	int			retval = 0;
	unsigned int		j, k, first_cpu, tmp;
	CPUMASK_ALLOC(allmasks);
	CPUMASK_VAR(online_policy_cpus, allmasks);
	CPUMASK_VAR(saved_mask, allmasks);
	CPUMASK_VAR(set_mask, allmasks);
	CPUMASK_VAR(covered_cpus, allmasks);

	if (unlikely(allmasks == NULL))
		return -ENOMEM;

	if (unlikely(centrino_model[cpu] == NULL)) {
		retval = -ENODEV;
		goto out;
	}

	if (unlikely(cpufreq_frequency_table_target(policy,
			centrino_model[cpu]->op_points,
			target_freq,
			relation,
			&newstate))) {
		retval = -EINVAL;
		goto out;
	}

#ifdef CONFIG_HOTPLUG_CPU
	/* cpufreq holds the hotplug lock, so we are safe from here on */
	cpus_and(*online_policy_cpus, cpu_online_map, policy->cpus);
#else
	*online_policy_cpus = policy->cpus;
#endif

	*saved_mask = current->cpus_allowed;
	first_cpu = 1;
	cpus_clear(*covered_cpus);
	for_each_cpu_mask_nr(j, *online_policy_cpus) {
		/*
		 * Support for SMP systems.
		 * Make sure we are running on CPU that wants to change freq
		 */
		cpus_clear(*set_mask);
		if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
			cpus_or(*set_mask, *set_mask, *online_policy_cpus);
		else
			cpu_set(j, *set_mask);

		set_cpus_allowed_ptr(current, set_mask);
		preempt_disable();
		if (unlikely(!cpu_isset(smp_processor_id(), *set_mask))) {
			dprintk("couldn't limit to CPUs in this domain\n");
			retval = -EAGAIN;
			if (first_cpu) {
				/* We haven't started the transition yet. */
				goto migrate_end;
			}
			preempt_enable();
			break;
		}

		msr = centrino_model[cpu]->op_points[newstate].index;

		if (first_cpu) {
			rdmsr(MSR_IA32_PERF_CTL, oldmsr, h);
			if (msr == (oldmsr & 0xffff)) {
				dprintk("no change needed - msr was and needs "
					"to be %x\n", oldmsr);
				retval = 0;
				goto migrate_end;
			}

			freqs.old = extract_clock(oldmsr, cpu, 0);
			freqs.new = extract_clock(msr, cpu, 0);

			dprintk("target=%dkHz old=%d new=%d msr=%04x\n",
				target_freq, freqs.old, freqs.new, msr);

			for_each_cpu_mask_nr(k, *online_policy_cpus) {
				freqs.cpu = k;
				cpufreq_notify_transition(&freqs,
					CPUFREQ_PRECHANGE);
			}

			first_cpu = 0;
			/* all but 16 LSB are reserved, treat them with care */
			oldmsr &= ~0xffff;
			msr &= 0xffff;
			oldmsr |= msr;
		}

		wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
		if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) {
			preempt_enable();
			break;
		}

		cpu_set(j, *covered_cpus);
		preempt_enable();
	}

	for_each_cpu_mask_nr(k, *online_policy_cpus) {
		freqs.cpu = k;
		cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
	}

	if (unlikely(retval)) {
		/*
		 * We have failed halfway through the frequency change.
		 * We have sent callbacks to policy->cpus and
		 * MSRs have already been written on coverd_cpus.
		 * Best effort undo..
		 */

		if (!cpus_empty(*covered_cpus)) {
			cpumask_of_cpu_ptr_declare(new_mask);

			for_each_cpu_mask_nr(j, *covered_cpus) {
				cpumask_of_cpu_ptr_next(new_mask, j);
				set_cpus_allowed_ptr(current, new_mask);
				wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
			}
		}

		tmp = freqs.new;
		freqs.new = freqs.old;
		freqs.old = tmp;
		for_each_cpu_mask_nr(j, *online_policy_cpus) {
			freqs.cpu = j;
			cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
			cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
		}
	}
	set_cpus_allowed_ptr(current, saved_mask);
	retval = 0;
	goto out;

migrate_end:
	preempt_enable();
	set_cpus_allowed_ptr(current, saved_mask);
out:
	CPUMASK_FREE(allmasks);
	return retval;
}

static struct freq_attr* centrino_attr[] = {
	&cpufreq_freq_attr_scaling_available_freqs,
	NULL,
};

static struct cpufreq_driver centrino_driver = {
	.name		= "centrino", /* should be speedstep-centrino,
					 but there's a 16 char limit */
	.init		= centrino_cpu_init,
	.exit		= centrino_cpu_exit,
	.verify		= centrino_verify,
	.target		= centrino_target,
	.get		= get_cur_freq,
	.attr           = centrino_attr,
	.owner		= THIS_MODULE,
};


/**
 * centrino_init - initializes the Enhanced SpeedStep CPUFreq driver
 *
 * Initializes the Enhanced SpeedStep support. Returns -ENODEV on
 * unsupported devices, -ENOENT if there's no voltage table for this
 * particular CPU model, -EINVAL on problems during initiatization,
 * and zero on success.
 *
 * This is quite picky.  Not only does the CPU have to advertise the
 * "est" flag in the cpuid capability flags, we look for a specific
 * CPU model and stepping, and we need to have the exact model name in
 * our voltage tables.  That is, be paranoid about not releasing
 * someone's valuable magic smoke.
 */
static int __init centrino_init(void)
{
	struct cpuinfo_x86 *cpu = &cpu_data(0);

	if (!cpu_has(cpu, X86_FEATURE_EST))
		return -ENODEV;

	return cpufreq_register_driver(&centrino_driver);
}

static void __exit centrino_exit(void)
{
	cpufreq_unregister_driver(&centrino_driver);
}

MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>");
MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors.");
MODULE_LICENSE ("GPL");

late_initcall(centrino_init);
module_exit(centrino_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium
	3	* M (part of the Centrino chipset).
	4	*
491b07c9 JF	5	* Since the original Pentium M, most new Intel CPUs support Enhanced
	6	* SpeedStep.
	7	*
1da177e4 LT	8	* Despite the "SpeedStep" in the name, this is almost entirely unlike
	9	* traditional SpeedStep.
	10	*
	11	* Modelled on speedstep.c
	12	*
	13	* Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org>
1da177e4 LT	14	*/
	15
	16	#include <linux/kernel.h>
	17	#include <linux/module.h>
	18	#include <linux/init.h>
	19	#include <linux/cpufreq.h>
4e57b681	20	#include <linux/sched.h> /* current */
1da177e4 LT	21	#include <linux/delay.h>
	22	#include <linux/compiler.h>
	23
1da177e4 LT	24	#include <asm/msr.h>
	25	#include <asm/processor.h>
	26	#include <asm/cpufeature.h>
	27
1da177e4	28	#define PFX "speedstep-centrino: "
491b07c9	29	#define MAINTAINER "cpufreq@lists.linux.org.uk"
1da177e4 LT	30
	31	#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-centrino", msg)
	32
8b9c6671	33	#define INTEL_MSR_RANGE (0xffff)
1da177e4 LT	34
	35	struct cpu_id
	36	{
	37	__u8 x86; /* CPU family */
	38	__u8 x86_model; /* model */
	39	__u8 x86_mask; /* stepping */
	40	};
	41
	42	enum {
	43	CPU_BANIAS,
	44	CPU_DOTHAN_A1,
	45	CPU_DOTHAN_A2,
	46	CPU_DOTHAN_B0,
8282864a DJ	47	CPU_MP4HT_D0,
8282864a DJ	48	CPU_MP4HT_E0,
1da177e4 LT	49	};
	50
	51	static const struct cpu_id cpu_ids[] = {
	52	[CPU_BANIAS] = { 6, 9, 5 },
	53	[CPU_DOTHAN_A1] = { 6, 13, 1 },
	54	[CPU_DOTHAN_A2] = { 6, 13, 2 },
	55	[CPU_DOTHAN_B0] = { 6, 13, 6 },
8282864a DJ	56	[CPU_MP4HT_D0] = {15, 3, 4 },
8282864a DJ	57	[CPU_MP4HT_E0] = {15, 4, 1 },
1da177e4	58	};
38e548ee	59	#define N_IDS ARRAY_SIZE(cpu_ids)
1da177e4 LT	60
	61	struct cpu_model
	62	{
	63	const struct cpu_id *cpu_id;
	64	const char *model_name;
	65	unsigned max_freq; /* max clock in kHz */
	66
	67	struct cpufreq_frequency_table op_points; / clock/voltage pairs */
	68	};
	69	static int centrino_verify_cpu_id(const struct cpuinfo_x86 c, const struct cpu_id x);
	70
	71	/* Operating points for current CPU */
	72	static struct cpu_model *centrino_model[NR_CPUS];
	73	static const struct cpu_id *centrino_cpu[NR_CPUS];
	74
	75	static struct cpufreq_driver centrino_driver;
	76
	77	#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE
	78
	79	/* Computes the correct form for IA32_PERF_CTL MSR for a particular
	80	frequency/voltage operating point; frequency in MHz, volts in mV.
	81	This is stored as "index" in the structure. */
	82	#define OP(mhz, mv) \
	83	{ \
	84	.frequency = (mhz) * 1000, \
	85	.index = (((mhz)/100) << 8) \| ((mv - 700) / 16) \
	86	}
	87
	88	/*
	89	* These voltage tables were derived from the Intel Pentium M
	90	* datasheet, document 25261202.pdf, Table 5. I have verified they
	91	* are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium
	92	* M.
	93	*/
	94
	95	/* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
	96	static struct cpufreq_frequency_table banias_900[] =
	97	{
	98	OP(600, 844),
	99	OP(800, 988),
	100	OP(900, 1004),
	101	{ .frequency = CPUFREQ_TABLE_END }
	102	};
	103
	104	/* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
	105	static struct cpufreq_frequency_table banias_1000[] =
	106	{
	107	OP(600, 844),
	108	OP(800, 972),
	109	OP(900, 988),
	110	OP(1000, 1004),
	111	{ .frequency = CPUFREQ_TABLE_END }
	112	};
	113
	114	/* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */
	115	static struct cpufreq_frequency_table banias_1100[] =
	116	{
	117	OP( 600, 956),
	118	OP( 800, 1020),
	119	OP( 900, 1100),
	120	OP(1000, 1164),
	121	OP(1100, 1180),
	122	{ .frequency = CPUFREQ_TABLE_END }
	123	};
124
125
126	/* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */
127	static struct cpufreq_frequency_table banias_1200[] =
128	{
129	OP( 600, 956),
130	OP( 800, 1004),
131	OP( 900, 1020),
132	OP(1000, 1100),
133	OP(1100, 1164),
134	OP(1200, 1180),
135	{ .frequency = CPUFREQ_TABLE_END }
136	};
137
138	/* Intel Pentium M processor 1.30GHz (Banias) */
139	static struct cpufreq_frequency_table banias_1300[] =
140	{
141	OP( 600, 956),
142	OP( 800, 1260),
143	OP(1000, 1292),
144	OP(1200, 1356),
145	OP(1300, 1388),
146	{ .frequency = CPUFREQ_TABLE_END }
147	};
148
149	/* Intel Pentium M processor 1.40GHz (Banias) */
150	static struct cpufreq_frequency_table banias_1400[] =
151	{
152	OP( 600, 956),
153	OP( 800, 1180),
154	OP(1000, 1308),
155	OP(1200, 1436),
156	OP(1400, 1484),
157	{ .frequency = CPUFREQ_TABLE_END }
158	};
159
160	/* Intel Pentium M processor 1.50GHz (Banias) */
161	static struct cpufreq_frequency_table banias_1500[] =
162	{
163	OP( 600, 956),
164	OP( 800, 1116),
165	OP(1000, 1228),
166	OP(1200, 1356),
167	OP(1400, 1452),
168	OP(1500, 1484),
169	{ .frequency = CPUFREQ_TABLE_END }
170	};
171
172	/* Intel Pentium M processor 1.60GHz (Banias) */
173	static struct cpufreq_frequency_table banias_1600[] =
174	{
175	OP( 600, 956),
176	OP( 800, 1036),
177	OP(1000, 1164),
178	OP(1200, 1276),
179	OP(1400, 1420),
180	OP(1600, 1484),
181	{ .frequency = CPUFREQ_TABLE_END }
182	};
183
184	/* Intel Pentium M processor 1.70GHz (Banias) */
185	static struct cpufreq_frequency_table banias_1700[] =
186	{
187	OP( 600, 956),
188	OP( 800, 1004),
189	OP(1000, 1116),
190	OP(1200, 1228),
191	OP(1400, 1308),
192	OP(1700, 1484),
193	{ .frequency = CPUFREQ_TABLE_END }
194	};
195	#undef OP
196
197	#define _BANIAS(cpuid, max, name) \
198	{ .cpu_id = cpuid, \
199	.model_name = "Intel(R) Pentium(R) M processor " name "MHz", \
200	.max_freq = (max)*1000, \
201	.op_points = banias_##max, \
202	}
203	#define BANIAS(max) _BANIAS(&cpu_ids[CPU_BANIAS], max, #max)
204
205	/* CPU models, their operating frequency range, and freq/voltage
206	operating points */
207	static struct cpu_model models[] =
208	{
209	_BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"),
210	BANIAS(1000),
211	BANIAS(1100),
212	BANIAS(1200),
213	BANIAS(1300),
214	BANIAS(1400),
215	BANIAS(1500),
216	BANIAS(1600),
217	BANIAS(1700),
218
219	/* NULL model_name is a wildcard */
220	{ &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL },
221	{ &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL },
222	{ &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL },
8282864a DJ	223	{ &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL },
8282864a DJ	224	{ &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL },
1da177e4 LT	225
	226	{ NULL, }
	227	};
	228	#undef _BANIAS
	229	#undef BANIAS
	230
	231	static int centrino_cpu_init_table(struct cpufreq_policy *policy)
	232	{
92cb7612	233	struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
1da177e4 LT	234	struct cpu_model *model;
	235
	236	for(model = models; model->cpu_id != NULL; model++)
	237	if (centrino_verify_cpu_id(cpu, model->cpu_id) &&
	238	(model->model_name == NULL \|\|
	239	strcmp(cpu->x86_model_id, model->model_name) == 0))
	240	break;
	241
	242	if (model->cpu_id == NULL) {
	243	/* No match at all */
8c362a5d	244	dprintk("no support for CPU model \"%s\": "
1da177e4 LT	245	"send /proc/cpuinfo to " MAINTAINER "\n",
	246	cpu->x86_model_id);
	247	return -ENOENT;
	248	}
	249
	250	if (model->op_points == NULL) {
	251	/* Matched a non-match */
8c362a5d	252	dprintk("no table support for CPU model \"%s\"\n",
1da177e4	253	cpu->x86_model_id);
68485695	254	dprintk("try using the acpi-cpufreq driver\n");
1da177e4 LT	255	return -ENOENT;
	256	}
	257
	258	centrino_model[policy->cpu] = model;
	259
	260	dprintk("found \"%s\": max frequency: %dkHz\n",
	261	model->model_name, model->max_freq);
	262
	263	return 0;
	264	}
	265
	266	#else
	267	static inline int centrino_cpu_init_table(struct cpufreq_policy *policy) { return -ENODEV; }
	268	#endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */
	269
	270	static int centrino_verify_cpu_id(const struct cpuinfo_x86 c, const struct cpu_id x)
	271	{
	272	if ((c->x86 == x->x86) &&
	273	(c->x86_model == x->x86_model) &&
	274	(c->x86_mask == x->x86_mask))
	275	return 1;
	276	return 0;
	277	}
	278
	279	/* To be called only after centrino_model is initialized */
	280	static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe)
	281	{
	282	int i;
	283
	284	/*
	285	* Extract clock in kHz from PERF_CTL value
	286	* for centrino, as some DSDTs are buggy.
	287	* Ideally, this can be done using the acpi_data structure.
	288	*/
	289	if ((centrino_cpu[cpu] == &cpu_ids[CPU_BANIAS]) \|\|
	290	(centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_A1]) \|\|
	291	(centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_B0])) {
	292	msr = (msr >> 8) & 0xff;
	293	return msr * 100000;
	294	}
	295
	296	if ((!centrino_model[cpu]) \|\| (!centrino_model[cpu]->op_points))
	297	return 0;
	298
	299	msr &= 0xffff;
	300	for (i=0;centrino_model[cpu]->op_points[i].frequency != CPUFREQ_TABLE_END; i++) {
	301	if (msr == centrino_model[cpu]->op_points[i].index)
	302	return centrino_model[cpu]->op_points[i].frequency;
	303	}
	304	if (failsafe)
	305	return centrino_model[cpu]->op_points[i-1].frequency;
	306	else
	307	return 0;
	308	}
	309
	310	/* Return the current CPU frequency in kHz */
	311	static unsigned int get_cur_freq(unsigned int cpu)
	312	{
	313	unsigned l, h;
	314	unsigned clock_freq;
	315	cpumask_t saved_mask;
65c01184	316	cpumask_of_cpu_ptr(new_mask, cpu);
1da177e4 LT	317
1da177e4 LT	318	saved_mask = current->cpus_allowed;
65c01184	319	set_cpus_allowed_ptr(current, new_mask);
1da177e4 LT	320	if (smp_processor_id() != cpu)
	321	return 0;
	322
	323	rdmsr(MSR_IA32_PERF_STATUS, l, h);
	324	clock_freq = extract_clock(l, cpu, 0);
	325
	326	if (unlikely(clock_freq == 0)) {
	327	/*
	328	* On some CPUs, we can see transient MSR values (which are
	329	* not present in _PSS), while CPU is doing some automatic
	330	* P-state transition (like TM2). Get the last freq set
	331	* in PERF_CTL.
	332	*/
	333	rdmsr(MSR_IA32_PERF_CTL, l, h);
	334	clock_freq = extract_clock(l, cpu, 1);
	335	}
	336
fc0e4748	337	set_cpus_allowed_ptr(current, &saved_mask);
1da177e4 LT	338	return clock_freq;
	339	}
	340
	341
1da177e4 LT	342	static int centrino_cpu_init(struct cpufreq_policy *policy)
1da177e4 LT	343	{
92cb7612	344	struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
1da177e4 LT	345	unsigned freq;
	346	unsigned l, h;
	347	int ret;
	348	int i;
	349
	350	/* Only Intel makes Enhanced Speedstep-capable CPUs */
	351	if (cpu->x86_vendor != X86_VENDOR_INTEL \|\| !cpu_has(cpu, X86_FEATURE_EST))
	352	return -ENODEV;
	353
8ad5496d	354	if (cpu_has(cpu, X86_FEATURE_CONSTANT_TSC))
1da177e4	355	centrino_driver.flags \|= CPUFREQ_CONST_LOOPS;
1da177e4	356
68485695 AB	357	if (policy->cpu != 0)
68485695 AB	358	return -ENODEV;
1da177e4	359
68485695 AB	360	for (i = 0; i < N_IDS; i++)
	361	if (centrino_verify_cpu_id(cpu, &cpu_ids[i]))
	362	break;
f914be79	363
68485695 AB	364	if (i != N_IDS)
68485695 AB	365	centrino_cpu[policy->cpu] = &cpu_ids[i];
f914be79	366
68485695 AB	367	if (!centrino_cpu[policy->cpu]) {
	368	dprintk("found unsupported CPU with "
	369	"Enhanced SpeedStep: send /proc/cpuinfo to "
	370	MAINTAINER "\n");
	371	return -ENODEV;
	372	}
1da177e4	373
68485695 AB	374	if (centrino_cpu_init_table(policy)) {
68485695 AB	375	return -ENODEV;
1da177e4 LT	376	}
	377
	378	/* Check to see if Enhanced SpeedStep is enabled, and try to
	379	enable it if not. */
	380	rdmsr(MSR_IA32_MISC_ENABLE, l, h);
	381
	382	if (!(l & (1<<16))) {
	383	l \|= (1<<16);
	384	dprintk("trying to enable Enhanced SpeedStep (%x)\n", l);
	385	wrmsr(MSR_IA32_MISC_ENABLE, l, h);
	386
	387	/* check to see if it stuck */
	388	rdmsr(MSR_IA32_MISC_ENABLE, l, h);
	389	if (!(l & (1<<16))) {
	390	printk(KERN_INFO PFX "couldn't enable Enhanced SpeedStep\n");
	391	return -ENODEV;
	392	}
	393	}
	394
	395	freq = get_cur_freq(policy->cpu);
	396
1da177e4 LT	397	policy->cpuinfo.transition_latency = 10000; /* 10uS transition latency */
	398	policy->cur = freq;
	399
	400	dprintk("centrino_cpu_init: cur=%dkHz\n", policy->cur);
	401
	402	ret = cpufreq_frequency_table_cpuinfo(policy, centrino_model[policy->cpu]->op_points);
	403	if (ret)
	404	return (ret);
	405
	406	cpufreq_frequency_table_get_attr(centrino_model[policy->cpu]->op_points, policy->cpu);
	407
	408	return 0;
	409	}
	410
	411	static int centrino_cpu_exit(struct cpufreq_policy *policy)
	412	{
	413	unsigned int cpu = policy->cpu;
	414
	415	if (!centrino_model[cpu])
	416	return -ENODEV;
	417
	418	cpufreq_frequency_table_put_attr(cpu);
	419
1da177e4 LT	420	centrino_model[cpu] = NULL;
	421
	422	return 0;
	423	}
	424
	425	/**
	426	* centrino_verify - verifies a new CPUFreq policy
	427	* @policy: new policy
	428	*
	429	* Limit must be within this model's frequency range at least one
	430	* border included.
	431	*/
	432	static int centrino_verify (struct cpufreq_policy *policy)
	433	{
	434	return cpufreq_frequency_table_verify(policy, centrino_model[policy->cpu]->op_points);
	435	}
	436
	437	/**
	438	* centrino_setpolicy - set a new CPUFreq policy
	439	* @policy: new policy
	440	* @target_freq: the target frequency
	441	* @relation: how that frequency relates to achieved frequency (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
	442	*
	443	* Sets a new CPUFreq policy.
	444	*/
eb53fac5 MT	445	struct allmasks {
	446	cpumask_t online_policy_cpus;
	447	cpumask_t saved_mask;
	448	cpumask_t set_mask;
	449	cpumask_t covered_cpus;
	450	};
	451
1da177e4 LT	452	static int centrino_target (struct cpufreq_policy *policy,
	453	unsigned int target_freq,
	454	unsigned int relation)
	455	{
	456	unsigned int newstate = 0;
c52851b6	457	unsigned int msr, oldmsr = 0, h = 0, cpu = policy->cpu;
1da177e4	458	struct cpufreq_freqs freqs;
c52851b6 VP	459	int retval = 0;
c52851b6 VP	460	unsigned int j, k, first_cpu, tmp;
eb53fac5 MT	461	CPUMASK_ALLOC(allmasks);
	462	CPUMASK_VAR(online_policy_cpus, allmasks);
	463	CPUMASK_VAR(saved_mask, allmasks);
	464	CPUMASK_VAR(set_mask, allmasks);
	465	CPUMASK_VAR(covered_cpus, allmasks);
	466
	467	if (unlikely(allmasks == NULL))
	468	return -ENOMEM;
	469
	470	if (unlikely(centrino_model[cpu] == NULL)) {
	471	retval = -ENODEV;
	472	goto out;
	473	}
1da177e4	474
c52851b6 VP	475	if (unlikely(cpufreq_frequency_table_target(policy,
	476	centrino_model[cpu]->op_points,
	477	target_freq,
	478	relation,
	479	&newstate))) {
eb53fac5 MT	480	retval = -EINVAL;
eb53fac5 MT	481	goto out;
1da177e4 LT	482	}
1da177e4 LT	483
7e1f19e5	484	#ifdef CONFIG_HOTPLUG_CPU
c52851b6	485	/* cpufreq holds the hotplug lock, so we are safe from here on */
eb53fac5	486	cpus_and(*online_policy_cpus, cpu_online_map, policy->cpus);
7e1f19e5	487	#else
eb53fac5	488	*online_policy_cpus = policy->cpus;
7e1f19e5	489	#endif
1da177e4	490
eb53fac5	491	*saved_mask = current->cpus_allowed;
c52851b6	492	first_cpu = 1;
eb53fac5 MT	493	cpus_clear(*covered_cpus);
eb53fac5 MT	494	for_each_cpu_mask_nr(j, *online_policy_cpus) {
c52851b6 VP	495	/*
	496	* Support for SMP systems.
	497	* Make sure we are running on CPU that wants to change freq
	498	*/
eb53fac5	499	cpus_clear(*set_mask);
c52851b6	500	if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
eb53fac5	501	cpus_or(set_mask, set_mask, *online_policy_cpus);
c52851b6	502	else
eb53fac5	503	cpu_set(j, *set_mask);
c52851b6	504
eb53fac5	505	set_cpus_allowed_ptr(current, set_mask);
e8e49190	506	preempt_disable();
eb53fac5	507	if (unlikely(!cpu_isset(smp_processor_id(), *set_mask))) {
c52851b6 VP	508	dprintk("couldn't limit to CPUs in this domain\n");
	509	retval = -EAGAIN;
	510	if (first_cpu) {
	511	/* We haven't started the transition yet. */
	512	goto migrate_end;
	513	}
e8e49190	514	preempt_enable();
c52851b6 VP	515	break;
c52851b6 VP	516	}
1da177e4	517
c52851b6 VP	518	msr = centrino_model[cpu]->op_points[newstate].index;
	519
	520	if (first_cpu) {
	521	rdmsr(MSR_IA32_PERF_CTL, oldmsr, h);
	522	if (msr == (oldmsr & 0xffff)) {
	523	dprintk("no change needed - msr was and needs "
	524	"to be %x\n", oldmsr);
	525	retval = 0;
	526	goto migrate_end;
	527	}
	528
	529	freqs.old = extract_clock(oldmsr, cpu, 0);
	530	freqs.new = extract_clock(msr, cpu, 0);
	531
	532	dprintk("target=%dkHz old=%d new=%d msr=%04x\n",
	533	target_freq, freqs.old, freqs.new, msr);
	534
eb53fac5	535	for_each_cpu_mask_nr(k, *online_policy_cpus) {
c52851b6 VP	536	freqs.cpu = k;
	537	cpufreq_notify_transition(&freqs,
	538	CPUFREQ_PRECHANGE);
	539	}
	540
	541	first_cpu = 0;
	542	/* all but 16 LSB are reserved, treat them with care */
	543	oldmsr &= ~0xffff;
	544	msr &= 0xffff;
	545	oldmsr \|= msr;
	546	}
1da177e4	547
c52851b6	548	wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
e8e49190 DJ	549	if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) {
e8e49190 DJ	550	preempt_enable();
c52851b6	551	break;
e8e49190	552	}
1da177e4	553
eb53fac5	554	cpu_set(j, *covered_cpus);
e8e49190	555	preempt_enable();
c52851b6	556	}
1da177e4	557
eb53fac5	558	for_each_cpu_mask_nr(k, *online_policy_cpus) {
c52851b6 VP	559	freqs.cpu = k;
	560	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
	561	}
1da177e4	562
c52851b6 VP	563	if (unlikely(retval)) {
	564	/*
	565	* We have failed halfway through the frequency change.
	566	* We have sent callbacks to policy->cpus and
	567	* MSRs have already been written on coverd_cpus.
	568	* Best effort undo..
	569	*/
1da177e4	570
eb53fac5	571	if (!cpus_empty(*covered_cpus)) {
65c01184 MT	572	cpumask_of_cpu_ptr_declare(new_mask);
65c01184 MT	573
eb53fac5	574	for_each_cpu_mask_nr(j, *covered_cpus) {
65c01184 MT	575	cpumask_of_cpu_ptr_next(new_mask, j);
65c01184 MT	576	set_cpus_allowed_ptr(current, new_mask);
c52851b6 VP	577	wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
	578	}
	579	}
1da177e4	580
c52851b6 VP	581	tmp = freqs.new;
	582	freqs.new = freqs.old;
	583	freqs.old = tmp;
eb53fac5	584	for_each_cpu_mask_nr(j, *online_policy_cpus) {
c52851b6 VP	585	freqs.cpu = j;
	586	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
	587	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
	588	}
	589	}
eb53fac5 MT	590	set_cpus_allowed_ptr(current, saved_mask);
	591	retval = 0;
	592	goto out;
1da177e4	593
1da177e4	594	migrate_end:
e8e49190	595	preempt_enable();
eb53fac5 MT	596	set_cpus_allowed_ptr(current, saved_mask);
	597	out:
	598	CPUMASK_FREE(allmasks);
	599	return retval;
1da177e4 LT	600	}
	601
	602	static struct freq_attr* centrino_attr[] = {
	603	&cpufreq_freq_attr_scaling_available_freqs,
	604	NULL,
	605	};
	606
	607	static struct cpufreq_driver centrino_driver = {
	608	.name = "centrino", /* should be speedstep-centrino,
	609	but there's a 16 char limit */
	610	.init = centrino_cpu_init,
	611	.exit = centrino_cpu_exit,
	612	.verify = centrino_verify,
	613	.target = centrino_target,
	614	.get = get_cur_freq,
	615	.attr = centrino_attr,
	616	.owner = THIS_MODULE,
	617	};
	618
	619
	620	/**
	621	* centrino_init - initializes the Enhanced SpeedStep CPUFreq driver
	622	*
	623	* Initializes the Enhanced SpeedStep support. Returns -ENODEV on
	624	* unsupported devices, -ENOENT if there's no voltage table for this
	625	* particular CPU model, -EINVAL on problems during initiatization,
	626	* and zero on success.
	627	*
	628	* This is quite picky. Not only does the CPU have to advertise the
	629	* "est" flag in the cpuid capability flags, we look for a specific
	630	* CPU model and stepping, and we need to have the exact model name in
	631	* our voltage tables. That is, be paranoid about not releasing
	632	* someone's valuable magic smoke.
	633	*/
	634	static int __init centrino_init(void)
	635	{
92cb7612	636	struct cpuinfo_x86 *cpu = &cpu_data(0);
1da177e4 LT	637
	638	if (!cpu_has(cpu, X86_FEATURE_EST))
	639	return -ENODEV;
	640
	641	return cpufreq_register_driver(&centrino_driver);
	642	}
	643
	644	static void __exit centrino_exit(void)
	645	{
	646	cpufreq_unregister_driver(&centrino_driver);
	647	}
	648
	649	MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>");
	650	MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors.");
	651	MODULE_LICENSE ("GPL");
	652
	653	late_initcall(centrino_init);
	654	module_exit(centrino_exit);