[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kernel / cpu / cyrix.c

#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <asm/dma.h>
#include <linux/io.h>
#include <asm/processor-cyrix.h>
#include <asm/processor-flags.h>
#include <linux/timer.h>
#include <asm/pci-direct.h>
#include <asm/tsc.h>
#include <asm/cpufeature.h>
#include <linux/sched.h>
#include <linux/sched/clock.h>

#include "cpu.h"

/*
 * Read NSC/Cyrix DEVID registers (DIR) to get more detailed info. about the CPU
 */
static void __do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
{
	unsigned char ccr2, ccr3;

	/* we test for DEVID by checking whether CCR3 is writable */
	ccr3 = getCx86(CX86_CCR3);
	setCx86(CX86_CCR3, ccr3 ^ 0x80);
	getCx86(0xc0);   /* dummy to change bus */

	if (getCx86(CX86_CCR3) == ccr3) {       /* no DEVID regs. */
		ccr2 = getCx86(CX86_CCR2);
		setCx86(CX86_CCR2, ccr2 ^ 0x04);
		getCx86(0xc0);  /* dummy */

		if (getCx86(CX86_CCR2) == ccr2) /* old Cx486SLC/DLC */
			*dir0 = 0xfd;
		else {                          /* Cx486S A step */
			setCx86(CX86_CCR2, ccr2);
			*dir0 = 0xfe;
		}
	} else {
		setCx86(CX86_CCR3, ccr3);  /* restore CCR3 */

		/* read DIR0 and DIR1 CPU registers */
		*dir0 = getCx86(CX86_DIR0);
		*dir1 = getCx86(CX86_DIR1);
	}
}

static void do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
{
	unsigned long flags;

	local_irq_save(flags);
	__do_cyrix_devid(dir0, dir1);
	local_irq_restore(flags);
}
/*
 * Cx86_dir0_msb is a HACK needed by check_cx686_cpuid/slop in bugs.h in
 * order to identify the Cyrix CPU model after we're out of setup.c
 *
 * Actually since bugs.h doesn't even reference this perhaps someone should
 * fix the documentation ???
 */
static unsigned char Cx86_dir0_msb = 0;

static const char Cx86_model[][9] = {
	"Cx486", "Cx486", "5x86 ", "6x86", "MediaGX ", "6x86MX ",
	"M II ", "Unknown"
};
static const char Cx486_name[][5] = {
	"SLC", "DLC", "SLC2", "DLC2", "SRx", "DRx",
	"SRx2", "DRx2"
};
static const char Cx486S_name[][4] = {
	"S", "S2", "Se", "S2e"
};
static const char Cx486D_name[][4] = {
	"DX", "DX2", "?", "?", "?", "DX4"
};
static char Cx86_cb[] = "?.5x Core/Bus Clock";
static const char cyrix_model_mult1[] = "12??43";
static const char cyrix_model_mult2[] = "12233445";

/*
 * Reset the slow-loop (SLOP) bit on the 686(L) which is set by some old
 * BIOSes for compatibility with DOS games.  This makes the udelay loop
 * work correctly, and improves performance.
 *
 * FIXME: our newer udelay uses the tsc. We don't need to frob with SLOP
 */

static void check_cx686_slop(struct cpuinfo_x86 *c)
{
	unsigned long flags;

	if (Cx86_dir0_msb == 3) {
		unsigned char ccr3, ccr5;

		local_irq_save(flags);
		ccr3 = getCx86(CX86_CCR3);
		setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
		ccr5 = getCx86(CX86_CCR5);
		if (ccr5 & 2)
			setCx86(CX86_CCR5, ccr5 & 0xfd);  /* reset SLOP */
		setCx86(CX86_CCR3, ccr3);                 /* disable MAPEN */
		local_irq_restore(flags);

		if (ccr5 & 2) { /* possible wrong calibration done */
			pr_info("Recalibrating delay loop with SLOP bit reset\n");
			calibrate_delay();
			c->loops_per_jiffy = loops_per_jiffy;
		}
	}
}


static void set_cx86_reorder(void)
{
	u8 ccr3;

	pr_info("Enable Memory access reorder on Cyrix/NSC processor.\n");
	ccr3 = getCx86(CX86_CCR3);
	setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */

	/* Load/Store Serialize to mem access disable (=reorder it) */
	setCx86_old(CX86_PCR0, getCx86_old(CX86_PCR0) & ~0x80);
	/* set load/store serialize from 1GB to 4GB */
	ccr3 |= 0xe0;
	setCx86(CX86_CCR3, ccr3);
}

static void set_cx86_memwb(void)
{
	pr_info("Enable Memory-Write-back mode on Cyrix/NSC processor.\n");

	/* CCR2 bit 2: unlock NW bit */
	setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) & ~0x04);
	/* set 'Not Write-through' */
	write_cr0(read_cr0() | X86_CR0_NW);
	/* CCR2 bit 2: lock NW bit and set WT1 */
	setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) | 0x14);
}

/*
 *	Configure later MediaGX and/or Geode processor.
 */

static void geode_configure(void)
{
	unsigned long flags;
	u8 ccr3;
	local_irq_save(flags);

	/* Suspend on halt power saving and enable #SUSP pin */
	setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) | 0x88);

	ccr3 = getCx86(CX86_CCR3);
	setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);	/* enable MAPEN */


	/* FPU fast, DTE cache, Mem bypass */
	setCx86_old(CX86_CCR4, getCx86_old(CX86_CCR4) | 0x38);
	setCx86(CX86_CCR3, ccr3);			/* disable MAPEN */

	set_cx86_memwb();
	set_cx86_reorder();

	local_irq_restore(flags);
}

static void early_init_cyrix(struct cpuinfo_x86 *c)
{
	unsigned char dir0, dir0_msn, dir1 = 0;

	__do_cyrix_devid(&dir0, &dir1);
	dir0_msn = dir0 >> 4; /* identifies CPU "family"   */

	switch (dir0_msn) {
	case 3: /* 6x86/6x86L */
		/* Emulate MTRRs using Cyrix's ARRs. */
		set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
		break;
	case 5: /* 6x86MX/M II */
		/* Emulate MTRRs using Cyrix's ARRs. */
		set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
		break;
	}
}

static void init_cyrix(struct cpuinfo_x86 *c)
{
	unsigned char dir0, dir0_msn, dir0_lsn, dir1 = 0;
	char *buf = c->x86_model_id;
	const char *p = NULL;

	/*
	 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
	 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
	 */
	clear_cpu_cap(c, 0*32+31);

	/* Cyrix used bit 24 in extended (AMD) CPUID for Cyrix MMX extensions */
	if (test_cpu_cap(c, 1*32+24)) {
		clear_cpu_cap(c, 1*32+24);
		set_cpu_cap(c, X86_FEATURE_CXMMX);
	}

	do_cyrix_devid(&dir0, &dir1);

	check_cx686_slop(c);

	Cx86_dir0_msb = dir0_msn = dir0 >> 4; /* identifies CPU "family"   */
	dir0_lsn = dir0 & 0xf;                /* model or clock multiplier */

	/* common case step number/rev -- exceptions handled below */
	c->x86_model = (dir1 >> 4) + 1;
	c->x86_mask = dir1 & 0xf;

	/* Now cook; the original recipe is by Channing Corn, from Cyrix.
	 * We do the same thing for each generation: we work out
	 * the model, multiplier and stepping.  Black magic included,
	 * to make the silicon step/rev numbers match the printed ones.
	 */

	switch (dir0_msn) {
		unsigned char tmp;

	case 0: /* Cx486SLC/DLC/SRx/DRx */
		p = Cx486_name[dir0_lsn & 7];
		break;

	case 1: /* Cx486S/DX/DX2/DX4 */
		p = (dir0_lsn & 8) ? Cx486D_name[dir0_lsn & 5]
			: Cx486S_name[dir0_lsn & 3];
		break;

	case 2: /* 5x86 */
		Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5];
		p = Cx86_cb+2;
		break;

	case 3: /* 6x86/6x86L */
		Cx86_cb[1] = ' ';
		Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5];
		if (dir1 > 0x21) { /* 686L */
			Cx86_cb[0] = 'L';
			p = Cx86_cb;
			(c->x86_model)++;
		} else             /* 686 */
			p = Cx86_cb+1;
		/* Emulate MTRRs using Cyrix's ARRs. */
		set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
		/* 6x86's contain this bug */
		set_cpu_bug(c, X86_BUG_COMA);
		break;

	case 4: /* MediaGX/GXm or Geode GXM/GXLV/GX1 */
#ifdef CONFIG_PCI
	{
		u32 vendor, device;
		/*
		 * It isn't really a PCI quirk directly, but the cure is the
		 * same. The MediaGX has deep magic SMM stuff that handles the
		 * SB emulation. It throws away the fifo on disable_dma() which
		 * is wrong and ruins the audio.
		 *
		 *  Bug2: VSA1 has a wrap bug so that using maximum sized DMA
		 *  causes bad things. According to NatSemi VSA2 has another
		 *  bug to do with 'hlt'. I've not seen any boards using VSA2
		 *  and X doesn't seem to support it either so who cares 8).
		 *  VSA1 we work around however.
		 */

		pr_info("Working around Cyrix MediaGX virtual DMA bugs.\n");
		isa_dma_bridge_buggy = 2;

		/* We do this before the PCI layer is running. However we
		   are safe here as we know the bridge must be a Cyrix
		   companion and must be present */
		vendor = read_pci_config_16(0, 0, 0x12, PCI_VENDOR_ID);
		device = read_pci_config_16(0, 0, 0x12, PCI_DEVICE_ID);

		/*
		 *  The 5510/5520 companion chips have a funky PIT.
		 */
		if (vendor == PCI_VENDOR_ID_CYRIX &&
			(device == PCI_DEVICE_ID_CYRIX_5510 ||
					device == PCI_DEVICE_ID_CYRIX_5520))
			mark_tsc_unstable("cyrix 5510/5520 detected");
	}
#endif
		c->x86_cache_size = 16;	/* Yep 16K integrated cache thats it */

		/* GXm supports extended cpuid levels 'ala' AMD */
		if (c->cpuid_level == 2) {
			/* Enable cxMMX extensions (GX1 Datasheet 54) */
			setCx86_old(CX86_CCR7, getCx86_old(CX86_CCR7) | 1);

			/*
			 * GXm : 0x30 ... 0x5f GXm  datasheet 51
			 * GXlv: 0x6x          GXlv datasheet 54
			 *  ?  : 0x7x
			 * GX1 : 0x8x          GX1  datasheet 56
			 */
			if ((0x30 <= dir1 && dir1 <= 0x6f) ||
					(0x80 <= dir1 && dir1 <= 0x8f))
				geode_configure();
			return;
		} else { /* MediaGX */
			Cx86_cb[2] = (dir0_lsn & 1) ? '3' : '4';
			p = Cx86_cb+2;
			c->x86_model = (dir1 & 0x20) ? 1 : 2;
		}
		break;

	case 5: /* 6x86MX/M II */
		if (dir1 > 7) {
			dir0_msn++;  /* M II */
			/* Enable MMX extensions (App note 108) */
			setCx86_old(CX86_CCR7, getCx86_old(CX86_CCR7)|1);
		} else {
			/* A 6x86MX - it has the bug. */
			set_cpu_bug(c, X86_BUG_COMA);
		}
		tmp = (!(dir0_lsn & 7) || dir0_lsn & 1) ? 2 : 0;
		Cx86_cb[tmp] = cyrix_model_mult2[dir0_lsn & 7];
		p = Cx86_cb+tmp;
		if (((dir1 & 0x0f) > 4) || ((dir1 & 0xf0) == 0x20))
			(c->x86_model)++;
		/* Emulate MTRRs using Cyrix's ARRs. */
		set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
		break;

	case 0xf:  /* Cyrix 486 without DEVID registers */
		switch (dir0_lsn) {
		case 0xd:  /* either a 486SLC or DLC w/o DEVID */
			dir0_msn = 0;
			p = Cx486_name[!!boot_cpu_has(X86_FEATURE_FPU)];
			break;

		case 0xe:  /* a 486S A step */
			dir0_msn = 0;
			p = Cx486S_name[0];
			break;
		}
		break;

	default:  /* unknown (shouldn't happen, we know everyone ;-) */
		dir0_msn = 7;
		break;
	}
	strcpy(buf, Cx86_model[dir0_msn & 7]);
	if (p)
		strcat(buf, p);
	return;
}

/*
 * Handle National Semiconductor branded processors
 */
static void init_nsc(struct cpuinfo_x86 *c)
{
	/*
	 * There may be GX1 processors in the wild that are branded
	 * NSC and not Cyrix.
	 *
	 * This function only handles the GX processor, and kicks every
	 * thing else to the Cyrix init function above - that should
	 * cover any processors that might have been branded differently
	 * after NSC acquired Cyrix.
	 *
	 * If this breaks your GX1 horribly, please e-mail
	 * info-linux@ldcmail.amd.com to tell us.
	 */

	/* Handle the GX (Formally known as the GX2) */

	if (c->x86 == 5 && c->x86_model == 5)
		cpu_detect_cache_sizes(c);
	else
		init_cyrix(c);
}

/*
 * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
 * by the fact that they preserve the flags across the division of 5/2.
 * PII and PPro exhibit this behavior too, but they have cpuid available.
 */

/*
 * Perform the Cyrix 5/2 test. A Cyrix won't change
 * the flags, while other 486 chips will.
 */
static inline int test_cyrix_52div(void)
{
	unsigned int test;

	__asm__ __volatile__(
	     "sahf\n\t"		/* clear flags (%eax = 0x0005) */
	     "div %b2\n\t"	/* divide 5 by 2 */
	     "lahf"		/* store flags into %ah */
	     : "=a" (test)
	     : "0" (5), "q" (2)
	     : "cc");

	/* AH is 0x02 on Cyrix after the divide.. */
	return (unsigned char) (test >> 8) == 0x02;
}

static void cyrix_identify(struct cpuinfo_x86 *c)
{
	/* Detect Cyrix with disabled CPUID */
	if (c->x86 == 4 && test_cyrix_52div()) {
		unsigned char dir0, dir1;

		strcpy(c->x86_vendor_id, "CyrixInstead");
		c->x86_vendor = X86_VENDOR_CYRIX;

		/* Actually enable cpuid on the older cyrix */

		/* Retrieve CPU revisions */

		do_cyrix_devid(&dir0, &dir1);

		dir0 >>= 4;

		/* Check it is an affected model */

		if (dir0 == 5 || dir0 == 3) {
			unsigned char ccr3;
			unsigned long flags;
			pr_info("Enabling CPUID on Cyrix processor.\n");
			local_irq_save(flags);
			ccr3 = getCx86(CX86_CCR3);
			/* enable MAPEN  */
			setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);
			/* enable cpuid  */
			setCx86_old(CX86_CCR4, getCx86_old(CX86_CCR4) | 0x80);
			/* disable MAPEN */
			setCx86(CX86_CCR3, ccr3);
			local_irq_restore(flags);
		}
	}
}

static const struct cpu_dev cyrix_cpu_dev = {
	.c_vendor	= "Cyrix",
	.c_ident	= { "CyrixInstead" },
	.c_early_init	= early_init_cyrix,
	.c_init		= init_cyrix,
	.c_identify	= cyrix_identify,
	.c_x86_vendor	= X86_VENDOR_CYRIX,
};

cpu_dev_register(cyrix_cpu_dev);

static const struct cpu_dev nsc_cpu_dev = {
	.c_vendor	= "NSC",
	.c_ident	= { "Geode by NSC" },
	.c_init		= init_nsc,
	.c_x86_vendor	= X86_VENDOR_NSC,
};

cpu_dev_register(nsc_cpu_dev);
Commit	Line	Data
1da177e4 LT	1	#include <linux/bitops.h>
	2	#include <linux/delay.h>
	3	#include <linux/pci.h>
	4	#include <asm/dma.h>
8bdbd962	5	#include <linux/io.h>
f25f64ed	6	#include <asm/processor-cyrix.h>
7ebad705	7	#include <asm/processor-flags.h>
8bdbd962	8	#include <linux/timer.h>
120fad72	9	#include <asm/pci-direct.h>
e8edc6e0	10	#include <asm/tsc.h>
cd4d09ec	11	#include <asm/cpufeature.h>
acb04058	12	#include <linux/sched.h>
e6017571	13	#include <linux/sched/clock.h>
1da177e4 LT	14
	15	#include "cpu.h"
	16
	17	/*
	18	* Read NSC/Cyrix DEVID registers (DIR) to get more detailed info. about the CPU
	19	*/
148f9bb8	20	static void __do_cyrix_devid(unsigned char dir0, unsigned char dir1)
1da177e4 LT	21	{
1da177e4 LT	22	unsigned char ccr2, ccr3;
adf85265	23
1da177e4	24	/* we test for DEVID by checking whether CCR3 is writable */
1da177e4 LT	25	ccr3 = getCx86(CX86_CCR3);
	26	setCx86(CX86_CCR3, ccr3 ^ 0x80);
	27	getCx86(0xc0); /* dummy to change bus */
	28
	29	if (getCx86(CX86_CCR3) == ccr3) { /* no DEVID regs. */
	30	ccr2 = getCx86(CX86_CCR2);
	31	setCx86(CX86_CCR2, ccr2 ^ 0x04);
	32	getCx86(0xc0); /* dummy */
	33
	34	if (getCx86(CX86_CCR2) == ccr2) /* old Cx486SLC/DLC */
	35	*dir0 = 0xfd;
	36	else { /* Cx486S A step */
	37	setCx86(CX86_CCR2, ccr2);
	38	*dir0 = 0xfe;
	39	}
adf85265	40	} else {
1da177e4 LT	41	setCx86(CX86_CCR3, ccr3); /* restore CCR3 */
	42
	43	/* read DIR0 and DIR1 CPU registers */
	44	*dir0 = getCx86(CX86_DIR0);
	45	*dir1 = getCx86(CX86_DIR1);
	46	}
1da177e4 LT	47	}
1da177e4 LT	48
148f9bb8	49	static void do_cyrix_devid(unsigned char dir0, unsigned char dir1)
5fef55fd YL	50	{
	51	unsigned long flags;
	52
	53	local_irq_save(flags);
	54	__do_cyrix_devid(dir0, dir1);
	55	local_irq_restore(flags);
	56	}
1da177e4 LT	57	/*
	58	* Cx86_dir0_msb is a HACK needed by check_cx686_cpuid/slop in bugs.h in
	59	* order to identify the Cyrix CPU model after we're out of setup.c
	60	*
	61	* Actually since bugs.h doesn't even reference this perhaps someone should
	62	* fix the documentation ???
	63	*/
148f9bb8	64	static unsigned char Cx86_dir0_msb = 0;
1da177e4	65
148f9bb8	66	static const char Cx86_model[][9] = {
1da177e4 LT	67	"Cx486", "Cx486", "5x86 ", "6x86", "MediaGX ", "6x86MX ",
	68	"M II ", "Unknown"
	69	};
148f9bb8	70	static const char Cx486_name[][5] = {
1da177e4 LT	71	"SLC", "DLC", "SLC2", "DLC2", "SRx", "DRx",
	72	"SRx2", "DRx2"
	73	};
148f9bb8	74	static const char Cx486S_name[][4] = {
1da177e4 LT	75	"S", "S2", "Se", "S2e"
1da177e4 LT	76	};
148f9bb8	77	static const char Cx486D_name[][4] = {
1da177e4 LT	78	"DX", "DX2", "?", "?", "?", "DX4"
1da177e4 LT	79	};
148f9bb8 PG	80	static char Cx86_cb[] = "?.5x Core/Bus Clock";
	81	static const char cyrix_model_mult1[] = "12??43";
	82	static const char cyrix_model_mult2[] = "12233445";
1da177e4 LT	83
	84	/*
	85	* Reset the slow-loop (SLOP) bit on the 686(L) which is set by some old
	86	* BIOSes for compatibility with DOS games. This makes the udelay loop
	87	* work correctly, and improves performance.
	88	*
	89	* FIXME: our newer udelay uses the tsc. We don't need to frob with SLOP
	90	*/
	91
148f9bb8	92	static void check_cx686_slop(struct cpuinfo_x86 *c)
1da177e4 LT	93	{
1da177e4 LT	94	unsigned long flags;
adf85265	95
1da177e4 LT	96	if (Cx86_dir0_msb == 3) {
	97	unsigned char ccr3, ccr5;
	98
	99	local_irq_save(flags);
	100	ccr3 = getCx86(CX86_CCR3);
db955170	101	setCx86(CX86_CCR3, (ccr3 & 0x0f) \| 0x10); /* enable MAPEN */
1da177e4 LT	102	ccr5 = getCx86(CX86_CCR5);
	103	if (ccr5 & 2)
	104	setCx86(CX86_CCR5, ccr5 & 0xfd); /* reset SLOP */
	105	setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
	106	local_irq_restore(flags);
	107
	108	if (ccr5 & 2) { /* possible wrong calibration done */
1b74dde7	109	pr_info("Recalibrating delay loop with SLOP bit reset\n");
1da177e4 LT	110	calibrate_delay();
	111	c->loops_per_jiffy = loops_per_jiffy;
	112	}
	113	}
	114	}
	115
	116
148f9bb8	117	static void set_cx86_reorder(void)
1da177e4 LT	118	{
	119	u8 ccr3;
	120
1b74dde7	121	pr_info("Enable Memory access reorder on Cyrix/NSC processor.\n");
1da177e4	122	ccr3 = getCx86(CX86_CCR3);
96de0e25	123	setCx86(CX86_CCR3, (ccr3 & 0x0f) \| 0x10); /* enable MAPEN */
1da177e4	124
96de0e25	125	/* Load/Store Serialize to mem access disable (=reorder it) */
026e2c05	126	setCx86_old(CX86_PCR0, getCx86_old(CX86_PCR0) & ~0x80);
1da177e4 LT	127	/* set load/store serialize from 1GB to 4GB */
	128	ccr3 \|= 0xe0;
	129	setCx86(CX86_CCR3, ccr3);
	130	}
	131
148f9bb8	132	static void set_cx86_memwb(void)
1da177e4	133	{
1b74dde7	134	pr_info("Enable Memory-Write-back mode on Cyrix/NSC processor.\n");
1da177e4 LT	135
1da177e4 LT	136	/* CCR2 bit 2: unlock NW bit */
026e2c05	137	setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) & ~0x04);
1da177e4	138	/* set 'Not Write-through' */
7ebad705	139	write_cr0(read_cr0() \| X86_CR0_NW);
1da177e4	140	/* CCR2 bit 2: lock NW bit and set WT1 */
026e2c05	141	setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) \| 0x14);
1da177e4 LT	142	}
1da177e4 LT	143
1da177e4 LT	144	/*
	145	* Configure later MediaGX and/or Geode processor.
	146	*/
	147
148f9bb8	148	static void geode_configure(void)
1da177e4 LT	149	{
1da177e4 LT	150	unsigned long flags;
bcde1ebb	151	u8 ccr3;
1da177e4 LT	152	local_irq_save(flags);
	153
	154	/* Suspend on halt power saving and enable #SUSP pin */
026e2c05	155	setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) \| 0x88);
1da177e4 LT	156
1da177e4 LT	157	ccr3 = getCx86(CX86_CCR3);
bcde1ebb	158	setCx86(CX86_CCR3, (ccr3 & 0x0f) \| 0x10); /* enable MAPEN */
adf85265	159
bcde1ebb TY	160
bcde1ebb TY	161	/* FPU fast, DTE cache, Mem bypass */
026e2c05	162	setCx86_old(CX86_CCR4, getCx86_old(CX86_CCR4) \| 0x38);
bcde1ebb	163	setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
adf85265	164
1da177e4	165	set_cx86_memwb();
adf85265	166	set_cx86_reorder();
adf85265	167
1da177e4 LT	168	local_irq_restore(flags);
	169	}
	170
148f9bb8	171	static void early_init_cyrix(struct cpuinfo_x86 *c)
5fef55fd YL	172	{
	173	unsigned char dir0, dir0_msn, dir1 = 0;
	174
	175	__do_cyrix_devid(&dir0, &dir1);
	176	dir0_msn = dir0 >> 4; /* identifies CPU "family" */
	177
	178	switch (dir0_msn) {
	179	case 3: /* 6x86/6x86L */
	180	/* Emulate MTRRs using Cyrix's ARRs. */
	181	set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
	182	break;
	183	case 5: /* 6x86MX/M II */
	184	/* Emulate MTRRs using Cyrix's ARRs. */
	185	set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
	186	break;
	187	}
	188	}
1da177e4	189
148f9bb8	190	static void init_cyrix(struct cpuinfo_x86 *c)
1da177e4 LT	191	{
	192	unsigned char dir0, dir0_msn, dir0_lsn, dir1 = 0;
	193	char *buf = c->x86_model_id;
	194	const char *p = NULL;
	195
adf85265 PC	196	/*
	197	* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
	198	* 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
	199	*/
1d007cd5	200	clear_cpu_cap(c, 0*32+31);
1da177e4 LT	201
1da177e4 LT	202	/* Cyrix used bit 24 in extended (AMD) CPUID for Cyrix MMX extensions */
1d007cd5 IM	203	if (test_cpu_cap(c, 1*32+24)) {
	204	clear_cpu_cap(c, 1*32+24);
	205	set_cpu_cap(c, X86_FEATURE_CXMMX);
1da177e4 LT	206	}
	207
	208	do_cyrix_devid(&dir0, &dir1);
	209
	210	check_cx686_slop(c);
	211
	212	Cx86_dir0_msb = dir0_msn = dir0 >> 4; /* identifies CPU "family" */
	213	dir0_lsn = dir0 & 0xf; /* model or clock multiplier */
	214
	215	/* common case step number/rev -- exceptions handled below */
	216	c->x86_model = (dir1 >> 4) + 1;
	217	c->x86_mask = dir1 & 0xf;
	218
	219	/* Now cook; the original recipe is by Channing Corn, from Cyrix.
	220	* We do the same thing for each generation: we work out
	221	* the model, multiplier and stepping. Black magic included,
	222	* to make the silicon step/rev numbers match the printed ones.
	223	*/
adf85265	224
1da177e4 LT	225	switch (dir0_msn) {
	226	unsigned char tmp;
	227
	228	case 0: /* Cx486SLC/DLC/SRx/DRx */
	229	p = Cx486_name[dir0_lsn & 7];
	230	break;
	231
	232	case 1: /* Cx486S/DX/DX2/DX4 */
	233	p = (dir0_lsn & 8) ? Cx486D_name[dir0_lsn & 5]
	234	: Cx486S_name[dir0_lsn & 3];
	235	break;
	236
	237	case 2: /* 5x86 */
	238	Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5];
	239	p = Cx86_cb+2;
	240	break;
	241
	242	case 3: /* 6x86/6x86L */
	243	Cx86_cb[1] = ' ';
	244	Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5];
	245	if (dir1 > 0x21) { /* 686L */
	246	Cx86_cb[0] = 'L';
	247	p = Cx86_cb;
	248	(c->x86_model)++;
	249	} else /* 686 */
	250	p = Cx86_cb+1;
	251	/* Emulate MTRRs using Cyrix's ARRs. */
1d007cd5	252	set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
1da177e4	253	/* 6x86's contain this bug */
c5b41a67	254	set_cpu_bug(c, X86_BUG_COMA);
1da177e4 LT	255	break;
	256
	257	case 4: /* MediaGX/GXm or Geode GXM/GXLV/GX1 */
	258	#ifdef CONFIG_PCI
120fad72 AC	259	{
120fad72 AC	260	u32 vendor, device;
adf85265 PC	261	/*
	262	* It isn't really a PCI quirk directly, but the cure is the
	263	* same. The MediaGX has deep magic SMM stuff that handles the
	264	* SB emulation. It throws away the fifo on disable_dma() which
	265	* is wrong and ruins the audio.
	266	*
	267	* Bug2: VSA1 has a wrap bug so that using maximum sized DMA
	268	* causes bad things. According to NatSemi VSA2 has another
	269	* bug to do with 'hlt'. I've not seen any boards using VSA2
	270	* and X doesn't seem to support it either so who cares 8).
	271	* VSA1 we work around however.
	272	*/
1da177e4	273
1b74dde7	274	pr_info("Working around Cyrix MediaGX virtual DMA bugs.\n");
1da177e4	275	isa_dma_bridge_buggy = 2;
cefc0113	276
120fad72 AC	277	/* We do this before the PCI layer is running. However we
	278	are safe here as we know the bridge must be a Cyrix
	279	companion and must be present */
	280	vendor = read_pci_config_16(0, 0, 0x12, PCI_VENDOR_ID);
	281	device = read_pci_config_16(0, 0, 0x12, PCI_DEVICE_ID);
cefc0113	282
1da177e4 LT	283	/*
1da177e4 LT	284	* The 5510/5520 companion chips have a funky PIT.
adf85265	285	*/
120fad72	286	if (vendor == PCI_VENDOR_ID_CYRIX &&
8bdbd962 AC	287	(device == PCI_DEVICE_ID_CYRIX_5510 \|\|
8bdbd962 AC	288	device == PCI_DEVICE_ID_CYRIX_5520))
5a90cf20	289	mark_tsc_unstable("cyrix 5510/5520 detected");
120fad72	290	}
cefc0113	291	#endif
adf85265	292	c->x86_cache_size = 16; /* Yep 16K integrated cache thats it */
1da177e4 LT	293
	294	/* GXm supports extended cpuid levels 'ala' AMD */
	295	if (c->cpuid_level == 2) {
	296	/* Enable cxMMX extensions (GX1 Datasheet 54) */
026e2c05	297	setCx86_old(CX86_CCR7, getCx86_old(CX86_CCR7) \| 1);
adf85265	298
2632f01a	299	/*
	300	* GXm : 0x30 ... 0x5f GXm datasheet 51
	301	* GXlv: 0x6x GXlv datasheet 54
	302	* ? : 0x7x
	303	* GX1 : 0x8x GX1 datasheet 56
	304	*/
8bdbd962 AC	305	if ((0x30 <= dir1 && dir1 <= 0x6f) \|\|
8bdbd962 AC	306	(0x80 <= dir1 && dir1 <= 0x8f))
1da177e4	307	geode_configure();
1da177e4	308	return;
adf85265	309	} else { /* MediaGX */
1da177e4 LT	310	Cx86_cb[2] = (dir0_lsn & 1) ? '3' : '4';
	311	p = Cx86_cb+2;
	312	c->x86_model = (dir1 & 0x20) ? 1 : 2;
	313	}
	314	break;
	315
adf85265 PC	316	case 5: /* 6x86MX/M II */
adf85265 PC	317	if (dir1 > 7) {
1da177e4 LT	318	dir0_msn++; /* M II */
1da177e4 LT	319	/* Enable MMX extensions (App note 108) */
026e2c05	320	setCx86_old(CX86_CCR7, getCx86_old(CX86_CCR7)\|1);
adf85265	321	} else {
c5b41a67 BP	322	/* A 6x86MX - it has the bug. */
c5b41a67 BP	323	set_cpu_bug(c, X86_BUG_COMA);
1da177e4 LT	324	}
	325	tmp = (!(dir0_lsn & 7) \|\| dir0_lsn & 1) ? 2 : 0;
	326	Cx86_cb[tmp] = cyrix_model_mult2[dir0_lsn & 7];
	327	p = Cx86_cb+tmp;
adf85265	328	if (((dir1 & 0x0f) > 4) \|\| ((dir1 & 0xf0) == 0x20))
1da177e4 LT	329	(c->x86_model)++;
1da177e4 LT	330	/* Emulate MTRRs using Cyrix's ARRs. */
1d007cd5	331	set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
1da177e4 LT	332	break;
	333
	334	case 0xf: /* Cyrix 486 without DEVID registers */
	335	switch (dir0_lsn) {
	336	case 0xd: /* either a 486SLC or DLC w/o DEVID */
	337	dir0_msn = 0;
a402a8df	338	p = Cx486_name[!!boot_cpu_has(X86_FEATURE_FPU)];
1da177e4 LT	339	break;
	340
	341	case 0xe: /* a 486S A step */
	342	dir0_msn = 0;
	343	p = Cx486S_name[0];
	344	break;
	345	}
	346	break;
	347
	348	default: /* unknown (shouldn't happen, we know everyone ;-) */
	349	dir0_msn = 7;
	350	break;
	351	}
	352	strcpy(buf, Cx86_model[dir0_msn & 7]);
adf85265 PC	353	if (p)
adf85265 PC	354	strcat(buf, p);
1da177e4 LT	355	return;
	356	}
	357
f90b8116 JC	358	/*
	359	* Handle National Semiconductor branded processors
	360	*/
148f9bb8	361	static void init_nsc(struct cpuinfo_x86 *c)
f90b8116	362	{
adf85265 PC	363	/*
adf85265 PC	364	* There may be GX1 processors in the wild that are branded
f90b8116 JC	365	* NSC and not Cyrix.
	366	*
	367	* This function only handles the GX processor, and kicks every
	368	* thing else to the Cyrix init function above - that should
	369	* cover any processors that might have been branded differently
d6e05edc	370	* after NSC acquired Cyrix.
f90b8116 JC	371	*
	372	* If this breaks your GX1 horribly, please e-mail
	373	* info-linux@ldcmail.amd.com to tell us.
	374	*/
	375
	376	/* Handle the GX (Formally known as the GX2) */
	377
	378	if (c->x86 == 5 && c->x86_model == 5)
27c13ece	379	cpu_detect_cache_sizes(c);
f90b8116 JC	380	else
	381	init_cyrix(c);
	382	}
	383
1da177e4 LT	384	/*
	385	* Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
	386	* by the fact that they preserve the flags across the division of 5/2.
	387	* PII and PPro exhibit this behavior too, but they have cpuid available.
	388	*/
adf85265	389
1da177e4 LT	390	/*
	391	* Perform the Cyrix 5/2 test. A Cyrix won't change
	392	* the flags, while other 486 chips will.
	393	*/
	394	static inline int test_cyrix_52div(void)
	395	{
	396	unsigned int test;
	397
	398	__asm__ __volatile__(
	399	"sahf\n\t" /* clear flags (%eax = 0x0005) */
	400	"div %b2\n\t" /* divide 5 by 2 */
	401	"lahf" /* store flags into %ah */
	402	: "=a" (test)
	403	: "0" (5), "q" (2)
	404	: "cc");
	405
	406	/* AH is 0x02 on Cyrix after the divide.. */
	407	return (unsigned char) (test >> 8) == 0x02;
	408	}
	409
148f9bb8	410	static void cyrix_identify(struct cpuinfo_x86 *c)
1da177e4 LT	411	{
1da177e4 LT	412	/* Detect Cyrix with disabled CPUID */
adf85265	413	if (c->x86 == 4 && test_cyrix_52div()) {
1da177e4	414	unsigned char dir0, dir1;
adf85265	415
1da177e4	416	strcpy(c->x86_vendor_id, "CyrixInstead");
adf85265 PC	417	c->x86_vendor = X86_VENDOR_CYRIX;
	418
	419	/* Actually enable cpuid on the older cyrix */
	420
	421	/* Retrieve CPU revisions */
	422
1da177e4 LT	423	do_cyrix_devid(&dir0, &dir1);
1da177e4 LT	424
adf85265 PC	425	dir0 >>= 4;
adf85265 PC	426
1da177e4	427	/* Check it is an affected model */
adf85265 PC	428
adf85265 PC	429	if (dir0 == 5 \|\| dir0 == 3) {
bcde1ebb	430	unsigned char ccr3;
1da177e4	431	unsigned long flags;
1b74dde7	432	pr_info("Enabling CPUID on Cyrix processor.\n");
1da177e4 LT	433	local_irq_save(flags);
1da177e4 LT	434	ccr3 = getCx86(CX86_CCR3);
8bdbd962 AC	435	/* enable MAPEN */
	436	setCx86(CX86_CCR3, (ccr3 & 0x0f) \| 0x10);
	437	/* enable cpuid */
	438	setCx86_old(CX86_CCR4, getCx86_old(CX86_CCR4) \| 0x80);
	439	/* disable MAPEN */
	440	setCx86(CX86_CCR3, ccr3);
1da177e4 LT	441	local_irq_restore(flags);
	442	}
	443	}
1da177e4 LT	444	}
1da177e4 LT	445
148f9bb8	446	static const struct cpu_dev cyrix_cpu_dev = {
1da177e4	447	.c_vendor = "Cyrix",
adf85265	448	.c_ident = { "CyrixInstead" },
5fef55fd	449	.c_early_init = early_init_cyrix,
1da177e4 LT	450	.c_init = init_cyrix,
1da177e4 LT	451	.c_identify = cyrix_identify,
10a434fc	452	.c_x86_vendor = X86_VENDOR_CYRIX,
1da177e4 LT	453	};
1da177e4 LT	454
10a434fc	455	cpu_dev_register(cyrix_cpu_dev);
1da177e4	456
148f9bb8	457	static const struct cpu_dev nsc_cpu_dev = {
1da177e4	458	.c_vendor = "NSC",
adf85265	459	.c_ident = { "Geode by NSC" },
f90b8116	460	.c_init = init_nsc,
10a434fc	461	.c_x86_vendor = X86_VENDOR_NSC,
1da177e4 LT	462	};
1da177e4 LT	463
10a434fc	464	cpu_dev_register(nsc_cpu_dev);