[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kernel / cpu / intel.c

#include <linux/init.h>
#include <linux/kernel.h>

#include <linux/string.h>
#include <linux/bitops.h>
#include <linux/smp.h>
#include <linux/sched.h>
#include <linux/thread_info.h>
#include <linux/module.h>
#include <linux/uaccess.h>

#include <asm/processor.h>
#include <asm/pgtable.h>
#include <asm/msr.h>
#include <asm/bugs.h>
#include <asm/cpu.h>

#ifdef CONFIG_X86_64
#include <linux/topology.h>
#include <asm/numa_64.h>
#endif

#include "cpu.h"

#ifdef CONFIG_X86_LOCAL_APIC
#include <asm/mpspec.h>
#include <asm/apic.h>
#endif

static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
{
	u64 misc_enable;

	/* Unmask CPUID levels if masked: */
	if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
		rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);

		if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
			misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
			wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
			c->cpuid_level = cpuid_eax(0);
			get_cpu_cap(c);
		}
	}

	if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
		(c->x86 == 0x6 && c->x86_model >= 0x0e))
		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);

	if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) {
		unsigned lower_word;

		wrmsr(MSR_IA32_UCODE_REV, 0, 0);
		/* Required by the SDM */
		sync_core();
		rdmsr(MSR_IA32_UCODE_REV, lower_word, c->microcode);
	}

	/*
	 * Atom erratum AAE44/AAF40/AAG38/AAH41:
	 *
	 * A race condition between speculative fetches and invalidating
	 * a large page.  This is worked around in microcode, but we
	 * need the microcode to have already been loaded... so if it is
	 * not, recommend a BIOS update and disable large pages.
	 */
	if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
	    c->microcode < 0x20e) {
		printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
		clear_cpu_cap(c, X86_FEATURE_PSE);
	}

#ifdef CONFIG_X86_64
	set_cpu_cap(c, X86_FEATURE_SYSENTER32);
#else
	/* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
	if (c->x86 == 15 && c->x86_cache_alignment == 64)
		c->x86_cache_alignment = 128;
#endif

	/* CPUID workaround for 0F33/0F34 CPU */
	if (c->x86 == 0xF && c->x86_model == 0x3
	    && (c->x86_mask == 0x3 || c->x86_mask == 0x4))
		c->x86_phys_bits = 36;

	/*
	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
	 * with P/T states and does not stop in deep C-states.
	 *
	 * It is also reliable across cores and sockets. (but not across
	 * cabinets - we turn it off in that case explicitly.)
	 */
	if (c->x86_power & (1 << 8)) {
		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
		if (!check_tsc_unstable())
			sched_clock_stable = 1;
	}

	/*
	 * There is a known erratum on Pentium III and Core Solo
	 * and Core Duo CPUs.
	 * " Page with PAT set to WC while associated MTRR is UC
	 *   may consolidate to UC "
	 * Because of this erratum, it is better to stick with
	 * setting WC in MTRR rather than using PAT on these CPUs.
	 *
	 * Enable PAT WC only on P4, Core 2 or later CPUs.
	 */
	if (c->x86 == 6 && c->x86_model < 15)
		clear_cpu_cap(c, X86_FEATURE_PAT);

#ifdef CONFIG_KMEMCHECK
	/*
	 * P4s have a "fast strings" feature which causes single-
	 * stepping REP instructions to only generate a #DB on
	 * cache-line boundaries.
	 *
	 * Ingo Molnar reported a Pentium D (model 6) and a Xeon
	 * (model 2) with the same problem.
	 */
	if (c->x86 == 15) {
		rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);

		if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) {
			printk(KERN_INFO "kmemcheck: Disabling fast string operations\n");

			misc_enable &= ~MSR_IA32_MISC_ENABLE_FAST_STRING;
			wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
		}
	}
#endif

	/*
	 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
	 * clear the fast string and enhanced fast string CPU capabilities.
	 */
	if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
		rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
		if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
			printk(KERN_INFO "Disabled fast string operations\n");
			setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
			setup_clear_cpu_cap(X86_FEATURE_ERMS);
		}
	}
}

#ifdef CONFIG_X86_32
/*
 *	Early probe support logic for ppro memory erratum #50
 *
 *	This is called before we do cpu ident work
 */

int __cpuinit ppro_with_ram_bug(void)
{
	/* Uses data from early_cpu_detect now */
	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
	    boot_cpu_data.x86 == 6 &&
	    boot_cpu_data.x86_model == 1 &&
	    boot_cpu_data.x86_mask < 8) {
		printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
		return 1;
	}
	return 0;
}

#ifdef CONFIG_X86_F00F_BUG
static void __cpuinit trap_init_f00f_bug(void)
{
	__set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);

	/*
	 * Update the IDT descriptor and reload the IDT so that
	 * it uses the read-only mapped virtual address.
	 */
	idt_descr.address = fix_to_virt(FIX_F00F_IDT);
	load_idt(&idt_descr);
}
#endif

static void __cpuinit intel_smp_check(struct cpuinfo_x86 *c)
{
	/* calling is from identify_secondary_cpu() ? */
	if (!c->cpu_index)
		return;

	/*
	 * Mask B, Pentium, but not Pentium MMX
	 */
	if (c->x86 == 5 &&
	    c->x86_mask >= 1 && c->x86_mask <= 4 &&
	    c->x86_model <= 3) {
		/*
		 * Remember we have B step Pentia with bugs
		 */
		WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
				    "with B stepping processors.\n");
	}
}

static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
{
	unsigned long lo, hi;

#ifdef CONFIG_X86_F00F_BUG
	/*
	 * All current models of Pentium and Pentium with MMX technology CPUs
	 * have the F0 0F bug, which lets nonprivileged users lock up the
	 * system.
	 * Note that the workaround only should be initialized once...
	 */
	c->f00f_bug = 0;
	if (!paravirt_enabled() && c->x86 == 5) {
		static int f00f_workaround_enabled;

		c->f00f_bug = 1;
		if (!f00f_workaround_enabled) {
			trap_init_f00f_bug();
			printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
			f00f_workaround_enabled = 1;
		}
	}
#endif

	/*
	 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
	 * model 3 mask 3
	 */
	if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
		clear_cpu_cap(c, X86_FEATURE_SEP);

	/*
	 * P4 Xeon errata 037 workaround.
	 * Hardware prefetcher may cause stale data to be loaded into the cache.
	 */
	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
		rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
		if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) {
			printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
			printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
			lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE;
			wrmsr(MSR_IA32_MISC_ENABLE, lo, hi);
		}
	}

	/*
	 * See if we have a good local APIC by checking for buggy Pentia,
	 * i.e. all B steppings and the C2 stepping of P54C when using their
	 * integrated APIC (see 11AP erratum in "Pentium Processor
	 * Specification Update").
	 */
	if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
	    (c->x86_mask < 0x6 || c->x86_mask == 0xb))
		set_cpu_cap(c, X86_FEATURE_11AP);


#ifdef CONFIG_X86_INTEL_USERCOPY
	/*
	 * Set up the preferred alignment for movsl bulk memory moves
	 */
	switch (c->x86) {
	case 4:		/* 486: untested */
		break;
	case 5:		/* Old Pentia: untested */
		break;
	case 6:		/* PII/PIII only like movsl with 8-byte alignment */
		movsl_mask.mask = 7;
		break;
	case 15:	/* P4 is OK down to 8-byte alignment */
		movsl_mask.mask = 7;
		break;
	}
#endif

#ifdef CONFIG_X86_NUMAQ
	numaq_tsc_disable();
#endif

	intel_smp_check(c);
}
#else
static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
{
}
#endif

static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
{
#ifdef CONFIG_NUMA
	unsigned node;
	int cpu = smp_processor_id();

	/* Don't do the funky fallback heuristics the AMD version employs
	   for now. */
	node = numa_cpu_node(cpu);
	if (node == NUMA_NO_NODE || !node_online(node)) {
		/* reuse the value from init_cpu_to_node() */
		node = cpu_to_node(cpu);
	}
	numa_set_node(cpu, node);
#endif
}

/*
 * find out the number of processor cores on the die
 */
static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
{
	unsigned int eax, ebx, ecx, edx;

	if (c->cpuid_level < 4)
		return 1;

	/* Intel has a non-standard dependency on %ecx for this CPUID level. */
	cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
	if (eax & 0x1f)
		return (eax >> 26) + 1;
	else
		return 1;
}

static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
{
	/* Intel VMX MSR indicated features */
#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW	0x00200000
#define X86_VMX_FEATURE_PROC_CTLS_VNMI		0x00400000
#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS	0x80000000
#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC	0x00000001
#define X86_VMX_FEATURE_PROC_CTLS2_EPT		0x00000002
#define X86_VMX_FEATURE_PROC_CTLS2_VPID		0x00000020

	u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;

	clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
	clear_cpu_cap(c, X86_FEATURE_VNMI);
	clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
	clear_cpu_cap(c, X86_FEATURE_EPT);
	clear_cpu_cap(c, X86_FEATURE_VPID);

	rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
	msr_ctl = vmx_msr_high | vmx_msr_low;
	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
		set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
		set_cpu_cap(c, X86_FEATURE_VNMI);
	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
		rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
		      vmx_msr_low, vmx_msr_high);
		msr_ctl2 = vmx_msr_high | vmx_msr_low;
		if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
		    (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
			set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
		if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
			set_cpu_cap(c, X86_FEATURE_EPT);
		if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
			set_cpu_cap(c, X86_FEATURE_VPID);
	}
}

static void __cpuinit init_intel(struct cpuinfo_x86 *c)
{
	unsigned int l2 = 0;

	early_init_intel(c);

	intel_workarounds(c);

	/*
	 * Detect the extended topology information if available. This
	 * will reinitialise the initial_apicid which will be used
	 * in init_intel_cacheinfo()
	 */
	detect_extended_topology(c);

	l2 = init_intel_cacheinfo(c);
	if (c->cpuid_level > 9) {
		unsigned eax = cpuid_eax(10);
		/* Check for version and the number of counters */
		if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
			set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
	}

	if (cpu_has_xmm2)
		set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
	if (cpu_has_ds) {
		unsigned int l1;
		rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
		if (!(l1 & (1<<11)))
			set_cpu_cap(c, X86_FEATURE_BTS);
		if (!(l1 & (1<<12)))
			set_cpu_cap(c, X86_FEATURE_PEBS);
	}

	if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush)
		set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR);

#ifdef CONFIG_X86_64
	if (c->x86 == 15)
		c->x86_cache_alignment = c->x86_clflush_size * 2;
	if (c->x86 == 6)
		set_cpu_cap(c, X86_FEATURE_REP_GOOD);
#else
	/*
	 * Names for the Pentium II/Celeron processors
	 * detectable only by also checking the cache size.
	 * Dixon is NOT a Celeron.
	 */
	if (c->x86 == 6) {
		char *p = NULL;

		switch (c->x86_model) {
		case 5:
			if (l2 == 0)
				p = "Celeron (Covington)";
			else if (l2 == 256)
				p = "Mobile Pentium II (Dixon)";
			break;

		case 6:
			if (l2 == 128)
				p = "Celeron (Mendocino)";
			else if (c->x86_mask == 0 || c->x86_mask == 5)
				p = "Celeron-A";
			break;

		case 8:
			if (l2 == 128)
				p = "Celeron (Coppermine)";
			break;
		}

		if (p)
			strcpy(c->x86_model_id, p);
	}

	if (c->x86 == 15)
		set_cpu_cap(c, X86_FEATURE_P4);
	if (c->x86 == 6)
		set_cpu_cap(c, X86_FEATURE_P3);
#endif

	if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
		/*
		 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
		 * detection.
		 */
		c->x86_max_cores = intel_num_cpu_cores(c);
#ifdef CONFIG_X86_32
		detect_ht(c);
#endif
	}

	/* Work around errata */
	srat_detect_node(c);

	if (cpu_has(c, X86_FEATURE_VMX))
		detect_vmx_virtcap(c);

	/*
	 * Initialize MSR_IA32_ENERGY_PERF_BIAS if BIOS did not.
	 * x86_energy_perf_policy(8) is available to change it at run-time
	 */
	if (cpu_has(c, X86_FEATURE_EPB)) {
		u64 epb;

		rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
		if ((epb & 0xF) == ENERGY_PERF_BIAS_PERFORMANCE) {
			printk_once(KERN_WARNING "ENERGY_PERF_BIAS:"
				" Set to 'normal', was 'performance'\n"
				"ENERGY_PERF_BIAS: View and update with"
				" x86_energy_perf_policy(8)\n");
			epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL;
			wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
		}
	}
}

#ifdef CONFIG_X86_32
static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
{
	/*
	 * Intel PIII Tualatin. This comes in two flavours.
	 * One has 256kb of cache, the other 512. We have no way
	 * to determine which, so we use a boottime override
	 * for the 512kb model, and assume 256 otherwise.
	 */
	if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
		size = 256;
	return size;
}
#endif

static const struct cpu_dev __cpuinitconst intel_cpu_dev = {
	.c_vendor	= "Intel",
	.c_ident	= { "GenuineIntel" },
#ifdef CONFIG_X86_32
	.c_models = {
		{ .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
		  {
			  [0] = "486 DX-25/33",
			  [1] = "486 DX-50",
			  [2] = "486 SX",
			  [3] = "486 DX/2",
			  [4] = "486 SL",
			  [5] = "486 SX/2",
			  [7] = "486 DX/2-WB",
			  [8] = "486 DX/4",
			  [9] = "486 DX/4-WB"
		  }
		},
		{ .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
		  {
			  [0] = "Pentium 60/66 A-step",
			  [1] = "Pentium 60/66",
			  [2] = "Pentium 75 - 200",
			  [3] = "OverDrive PODP5V83",
			  [4] = "Pentium MMX",
			  [7] = "Mobile Pentium 75 - 200",
			  [8] = "Mobile Pentium MMX"
		  }
		},
		{ .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
		  {
			  [0] = "Pentium Pro A-step",
			  [1] = "Pentium Pro",
			  [3] = "Pentium II (Klamath)",
			  [4] = "Pentium II (Deschutes)",
			  [5] = "Pentium II (Deschutes)",
			  [6] = "Mobile Pentium II",
			  [7] = "Pentium III (Katmai)",
			  [8] = "Pentium III (Coppermine)",
			  [10] = "Pentium III (Cascades)",
			  [11] = "Pentium III (Tualatin)",
		  }
		},
		{ .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
		  {
			  [0] = "Pentium 4 (Unknown)",
			  [1] = "Pentium 4 (Willamette)",
			  [2] = "Pentium 4 (Northwood)",
			  [4] = "Pentium 4 (Foster)",
			  [5] = "Pentium 4 (Foster)",
		  }
		},
	},
	.c_size_cache	= intel_size_cache,
#endif
	.c_early_init   = early_init_intel,
	.c_init		= init_intel,
	.c_x86_vendor	= X86_VENDOR_INTEL,
};

cpu_dev_register(intel_cpu_dev);
Commit	Line	Data
1da177e4 LT	1	#include <linux/init.h>
	2	#include <linux/kernel.h>
	3
	4	#include <linux/string.h>
	5	#include <linux/bitops.h>
	6	#include <linux/smp.h>
83ce4009	7	#include <linux/sched.h>
1da177e4	8	#include <linux/thread_info.h>
53e86b91	9	#include <linux/module.h>
8bdbd962	10	#include <linux/uaccess.h>
1da177e4 LT	11
1da177e4 LT	12	#include <asm/processor.h>
d72b1b4f	13	#include <asm/pgtable.h>
1da177e4	14	#include <asm/msr.h>
73bdb73f	15	#include <asm/bugs.h>
1f442d70	16	#include <asm/cpu.h>
1da177e4	17
185f3b9d	18	#ifdef CONFIG_X86_64
8bdbd962	19	#include <linux/topology.h>
185f3b9d YL	20	#include <asm/numa_64.h>
	21	#endif
	22
1da177e4 LT	23	#include "cpu.h"
	24
	25	#ifdef CONFIG_X86_LOCAL_APIC
	26	#include <asm/mpspec.h>
	27	#include <asm/apic.h>
1da177e4 LT	28	#endif
1da177e4 LT	29
03ae5768	30	static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
1da177e4	31	{
161ec53c FY	32	u64 misc_enable;
161ec53c FY	33
99fb4d34	34	/* Unmask CPUID levels if masked: */
30a0fb94	35	if (c->x86 > 6 \|\| (c->x86 == 6 && c->x86_model >= 0xd)) {
99fb4d34 IM	36	rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
	37
	38	if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
	39	misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
	40	wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
	41	c->cpuid_level = cpuid_eax(0);
d900329e	42	get_cpu_cap(c);
99fb4d34	43	}
066941bd PA	44	}
066941bd PA	45
2b16a235 AK	46	if ((c->x86 == 0xf && c->x86_model >= 0x03) \|\|
	47	(c->x86 == 0x6 && c->x86_model >= 0x0e))
	48	set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
185f3b9d	49
506ed6b5 AK	50	if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) {
	51	unsigned lower_word;
	52
	53	wrmsr(MSR_IA32_UCODE_REV, 0, 0);
	54	/* Required by the SDM */
	55	sync_core();
	56	rdmsr(MSR_IA32_UCODE_REV, lower_word, c->microcode);
	57	}
	58
7a0fc404 PA	59	/*
	60	* Atom erratum AAE44/AAF40/AAG38/AAH41:
	61	*
	62	* A race condition between speculative fetches and invalidating
	63	* a large page. This is worked around in microcode, but we
	64	* need the microcode to have already been loaded... so if it is
	65	* not, recommend a BIOS update and disable large pages.
	66	*/
30963c0a AK	67	if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
	68	c->microcode < 0x20e) {
	69	printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
	70	clear_cpu_cap(c, X86_FEATURE_PSE);
7a0fc404 PA	71	}
7a0fc404 PA	72
185f3b9d YL	73	#ifdef CONFIG_X86_64
	74	set_cpu_cap(c, X86_FEATURE_SYSENTER32);
	75	#else
	76	/* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
	77	if (c->x86 == 15 && c->x86_cache_alignment == 64)
	78	c->x86_cache_alignment = 128;
	79	#endif
40fb1715	80
13c6c532 JB	81	/* CPUID workaround for 0F33/0F34 CPU */
	82	if (c->x86 == 0xF && c->x86_model == 0x3
	83	&& (c->x86_mask == 0x3 \|\| c->x86_mask == 0x4))
	84	c->x86_phys_bits = 36;
	85
40fb1715 VP	86	/*
40fb1715 VP	87	* c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
83ce4009 IM	88	* with P/T states and does not stop in deep C-states.
	89	*
	90	* It is also reliable across cores and sockets. (but not across
	91	* cabinets - we turn it off in that case explicitly.)
40fb1715 VP	92	*/
	93	if (c->x86_power & (1 << 8)) {
	94	set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
	95	set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
14be1f74 DS	96	if (!check_tsc_unstable())
14be1f74 DS	97	sched_clock_stable = 1;
40fb1715 VP	98	}
40fb1715 VP	99
75a04811 PA	100	/*
	101	* There is a known erratum on Pentium III and Core Solo
	102	* and Core Duo CPUs.
	103	* " Page with PAT set to WC while associated MTRR is UC
	104	* may consolidate to UC "
	105	* Because of this erratum, it is better to stick with
	106	* setting WC in MTRR rather than using PAT on these CPUs.
	107	*
	108	* Enable PAT WC only on P4, Core 2 or later CPUs.
	109	*/
	110	if (c->x86 == 6 && c->x86_model < 15)
	111	clear_cpu_cap(c, X86_FEATURE_PAT);
f8561296 VN	112
	113	#ifdef CONFIG_KMEMCHECK
	114	/*
	115	* P4s have a "fast strings" feature which causes single-
	116	* stepping REP instructions to only generate a #DB on
	117	* cache-line boundaries.
	118	*
	119	* Ingo Molnar reported a Pentium D (model 6) and a Xeon
	120	* (model 2) with the same problem.
	121	*/
	122	if (c->x86 == 15) {
f8561296 VN	123	rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
	124
	125	if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) {
	126	printk(KERN_INFO "kmemcheck: Disabling fast string operations\n");
	127
	128	misc_enable &= ~MSR_IA32_MISC_ENABLE_FAST_STRING;
	129	wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
	130	}
	131	}
	132	#endif
161ec53c FY	133
	134	/*
	135	* If fast string is not enabled in IA32_MISC_ENABLE for any reason,
	136	* clear the fast string and enhanced fast string CPU capabilities.
	137	*/
	138	if (c->x86 > 6 \|\| (c->x86 == 6 && c->x86_model >= 0xd)) {
	139	rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
	140	if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
	141	printk(KERN_INFO "Disabled fast string operations\n");
	142	setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
	143	setup_clear_cpu_cap(X86_FEATURE_ERMS);
	144	}
	145	}
1da177e4 LT	146	}
1da177e4 LT	147
185f3b9d	148	#ifdef CONFIG_X86_32
1da177e4 LT	149	/*
	150	* Early probe support logic for ppro memory erratum #50
	151	*
	152	* This is called before we do cpu ident work
	153	*/
65eb6b43	154
3bc9b76b	155	int __cpuinit ppro_with_ram_bug(void)
1da177e4 LT	156	{
	157	/* Uses data from early_cpu_detect now */
	158	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
	159	boot_cpu_data.x86 == 6 &&
	160	boot_cpu_data.x86_model == 1 &&
	161	boot_cpu_data.x86_mask < 8) {
	162	printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
	163	return 1;
	164	}
	165	return 0;
	166	}
65eb6b43	167
4052704d YL	168	#ifdef CONFIG_X86_F00F_BUG
	169	static void __cpuinit trap_init_f00f_bug(void)
	170	{
	171	__set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
1da177e4	172
4052704d YL	173	/*
	174	* Update the IDT descriptor and reload the IDT so that
	175	* it uses the read-only mapped virtual address.
	176	*/
	177	idt_descr.address = fix_to_virt(FIX_F00F_IDT);
	178	load_idt(&idt_descr);
	179	}
	180	#endif
	181
1f442d70 YL	182	static void __cpuinit intel_smp_check(struct cpuinfo_x86 *c)
1f442d70 YL	183	{
1f442d70	184	/* calling is from identify_secondary_cpu() ? */
f6e9456c	185	if (!c->cpu_index)
1f442d70 YL	186	return;
	187
	188	/*
	189	* Mask B, Pentium, but not Pentium MMX
	190	*/
	191	if (c->x86 == 5 &&
	192	c->x86_mask >= 1 && c->x86_mask <= 4 &&
	193	c->x86_model <= 3) {
	194	/*
	195	* Remember we have B step Pentia with bugs
	196	*/
	197	WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
	198	"with B stepping processors.\n");
	199	}
1f442d70 YL	200	}
1f442d70 YL	201
4052704d	202	static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
1da177e4 LT	203	{
	204	unsigned long lo, hi;
	205
4052704d YL	206	#ifdef CONFIG_X86_F00F_BUG
	207	/*
	208	* All current models of Pentium and Pentium with MMX technology CPUs
8bdbd962 AC	209	* have the F0 0F bug, which lets nonprivileged users lock up the
8bdbd962 AC	210	* system.
4052704d YL	211	* Note that the workaround only should be initialized once...
	212	*/
	213	c->f00f_bug = 0;
	214	if (!paravirt_enabled() && c->x86 == 5) {
	215	static int f00f_workaround_enabled;
	216
	217	c->f00f_bug = 1;
	218	if (!f00f_workaround_enabled) {
	219	trap_init_f00f_bug();
	220	printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
	221	f00f_workaround_enabled = 1;
	222	}
	223	}
	224	#endif
	225
	226	/*
	227	* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
	228	* model 3 mask 3
	229	*/
	230	if ((c->x86<<8 \| c->x86_model<<4 \| c->x86_mask) < 0x633)
	231	clear_cpu_cap(c, X86_FEATURE_SEP);
	232
	233	/*
	234	* P4 Xeon errata 037 workaround.
	235	* Hardware prefetcher may cause stale data to be loaded into the cache.
	236	*/
1da177e4	237	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
65eb6b43	238	rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
ecab22aa	239	if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) {
1da177e4 LT	240	printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
1da177e4 LT	241	printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
ecab22aa	242	lo \|= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE;
8bdbd962	243	wrmsr(MSR_IA32_MISC_ENABLE, lo, hi);
1da177e4 LT	244	}
1da177e4 LT	245	}
1da177e4	246
4052704d YL	247	/*
	248	* See if we have a good local APIC by checking for buggy Pentia,
	249	* i.e. all B steppings and the C2 stepping of P54C when using their
	250	* integrated APIC (see 11AP erratum in "Pentium Processor
	251	* Specification Update").
	252	*/
	253	if (cpu_has_apic && (c->x86<<8 \| c->x86_model<<4) == 0x520 &&
	254	(c->x86_mask < 0x6 \|\| c->x86_mask == 0xb))
	255	set_cpu_cap(c, X86_FEATURE_11AP);
185f3b9d	256
185f3b9d	257
4052704d	258	#ifdef CONFIG_X86_INTEL_USERCOPY
185f3b9d	259	/*
4052704d	260	* Set up the preferred alignment for movsl bulk memory moves
185f3b9d	261	*/
4052704d YL	262	switch (c->x86) {
	263	case 4: /* 486: untested */
	264	break;
	265	case 5: /* Old Pentia: untested */
	266	break;
	267	case 6: /* PII/PIII only like movsl with 8-byte alignment */
	268	movsl_mask.mask = 7;
	269	break;
	270	case 15: /* P4 is OK down to 8-byte alignment */
	271	movsl_mask.mask = 7;
	272	break;
	273	}
185f3b9d	274	#endif
4052704d YL	275
	276	#ifdef CONFIG_X86_NUMAQ
	277	numaq_tsc_disable();
	278	#endif
1f442d70 YL	279
1f442d70 YL	280	intel_smp_check(c);
4052704d YL	281	}
	282	#else
	283	static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
	284	{
	285	}
185f3b9d YL	286	#endif
185f3b9d YL	287
2759c328	288	static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
185f3b9d	289	{
645a7919	290	#ifdef CONFIG_NUMA
185f3b9d YL	291	unsigned node;
185f3b9d YL	292	int cpu = smp_processor_id();
185f3b9d YL	293
	294	/* Don't do the funky fallback heuristics the AMD version employs
	295	for now. */
bbc9e2f4	296	node = numa_cpu_node(cpu);
50f2d7f6	297	if (node == NUMA_NO_NODE \|\| !node_online(node)) {
d9c2d5ac YL	298	/* reuse the value from init_cpu_to_node() */
	299	node = cpu_to_node(cpu);
	300	}
185f3b9d	301	numa_set_node(cpu, node);
185f3b9d YL	302	#endif
	303	}
	304
3dd9d514 AK	305	/*
	306	* find out the number of processor cores on the die
	307	*/
f69feff7	308	static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
3dd9d514	309	{
f2ab4461	310	unsigned int eax, ebx, ecx, edx;
3dd9d514 AK	311
	312	if (c->cpuid_level < 4)
	313	return 1;
	314
f2ab4461 ZA	315	/* Intel has a non-standard dependency on %ecx for this CPUID level. */
f2ab4461 ZA	316	cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
3dd9d514	317	if (eax & 0x1f)
8bdbd962	318	return (eax >> 26) + 1;
3dd9d514 AK	319	else
	320	return 1;
	321	}
	322
e38e05a8 SY	323	static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
	324	{
	325	/* Intel VMX MSR indicated features */
	326	#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
	327	#define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
	328	#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
	329	#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
	330	#define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
	331	#define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
	332
	333	u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
	334
	335	clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
	336	clear_cpu_cap(c, X86_FEATURE_VNMI);
	337	clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
	338	clear_cpu_cap(c, X86_FEATURE_EPT);
	339	clear_cpu_cap(c, X86_FEATURE_VPID);
	340
	341	rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
	342	msr_ctl = vmx_msr_high \| vmx_msr_low;
	343	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
	344	set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
	345	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
	346	set_cpu_cap(c, X86_FEATURE_VNMI);
	347	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
	348	rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
	349	vmx_msr_low, vmx_msr_high);
	350	msr_ctl2 = vmx_msr_high \| vmx_msr_low;
	351	if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
	352	(msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
	353	set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
	354	if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
	355	set_cpu_cap(c, X86_FEATURE_EPT);
	356	if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
	357	set_cpu_cap(c, X86_FEATURE_VPID);
	358	}
	359	}
	360
3bc9b76b	361	static void __cpuinit init_intel(struct cpuinfo_x86 *c)
1da177e4 LT	362	{
1da177e4 LT	363	unsigned int l2 = 0;
1da177e4	364
2b16a235 AK	365	early_init_intel(c);
2b16a235 AK	366
4052704d	367	intel_workarounds(c);
1da177e4	368
345077cd SS	369	/*
	370	* Detect the extended topology information if available. This
	371	* will reinitialise the initial_apicid which will be used
	372	* in init_intel_cacheinfo()
	373	*/
	374	detect_extended_topology(c);
	375
1da177e4	376	l2 = init_intel_cacheinfo(c);
65eb6b43	377	if (c->cpuid_level > 9) {
0080e667 VP	378	unsigned eax = cpuid_eax(10);
	379	/* Check for version and the number of counters */
	380	if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
d0e95ebd	381	set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
0080e667	382	}
1da177e4	383
4052704d YL	384	if (cpu_has_xmm2)
	385	set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
	386	if (cpu_has_ds) {
	387	unsigned int l1;
	388	rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
	389	if (!(l1 & (1<<11)))
	390	set_cpu_cap(c, X86_FEATURE_BTS);
	391	if (!(l1 & (1<<12)))
	392	set_cpu_cap(c, X86_FEATURE_PEBS);
4052704d	393	}
1da177e4	394
e736ad54 PV	395	if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush)
	396	set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR);
	397
4052704d YL	398	#ifdef CONFIG_X86_64
	399	if (c->x86 == 15)
	400	c->x86_cache_alignment = c->x86_clflush_size * 2;
	401	if (c->x86 == 6)
	402	set_cpu_cap(c, X86_FEATURE_REP_GOOD);
	403	#else
65eb6b43 PC	404	/*
	405	* Names for the Pentium II/Celeron processors
	406	* detectable only by also checking the cache size.
	407	* Dixon is NOT a Celeron.
	408	*/
1da177e4	409	if (c->x86 == 6) {
4052704d YL	410	char *p = NULL;
4052704d YL	411
1da177e4 LT	412	switch (c->x86_model) {
1da177e4 LT	413	case 5:
865be7a8 OZ	414	if (l2 == 0)
	415	p = "Celeron (Covington)";
	416	else if (l2 == 256)
	417	p = "Mobile Pentium II (Dixon)";
1da177e4	418	break;
65eb6b43	419
1da177e4 LT	420	case 6:
	421	if (l2 == 128)
	422	p = "Celeron (Mendocino)";
	423	else if (c->x86_mask == 0 \|\| c->x86_mask == 5)
	424	p = "Celeron-A";
	425	break;
65eb6b43	426
1da177e4 LT	427	case 8:
	428	if (l2 == 128)
	429	p = "Celeron (Coppermine)";
	430	break;
	431	}
1da177e4	432
4052704d YL	433	if (p)
4052704d YL	434	strcpy(c->x86_model_id, p);
1da177e4	435	}
1da177e4	436
185f3b9d YL	437	if (c->x86 == 15)
	438	set_cpu_cap(c, X86_FEATURE_P4);
	439	if (c->x86 == 6)
	440	set_cpu_cap(c, X86_FEATURE_P3);
f4166c54	441	#endif
185f3b9d	442
185f3b9d YL	443	if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
	444	/*
	445	* let's use the legacy cpuid vector 0x1 and 0x4 for topology
	446	* detection.
	447	*/
	448	c->x86_max_cores = intel_num_cpu_cores(c);
	449	#ifdef CONFIG_X86_32
	450	detect_ht(c);
	451	#endif
	452	}
	453
	454	/* Work around errata */
2759c328	455	srat_detect_node(c);
e38e05a8 SY	456
	457	if (cpu_has(c, X86_FEATURE_VMX))
	458	detect_vmx_virtcap(c);
abe48b10 LB	459
	460	/*
	461	* Initialize MSR_IA32_ENERGY_PERF_BIAS if BIOS did not.
	462	* x86_energy_perf_policy(8) is available to change it at run-time
	463	*/
	464	if (cpu_has(c, X86_FEATURE_EPB)) {
	465	u64 epb;
	466
	467	rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
17edf2d7 LB	468	if ((epb & 0xF) == ENERGY_PERF_BIAS_PERFORMANCE) {
	469	printk_once(KERN_WARNING "ENERGY_PERF_BIAS:"
	470	" Set to 'normal', was 'performance'\n"
	471	"ENERGY_PERF_BIAS: View and update with"
	472	" x86_energy_perf_policy(8)\n");
abe48b10 LB	473	epb = (epb & ~0xF) \| ENERGY_PERF_BIAS_NORMAL;
	474	wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
	475	}
	476	}
42ed458a	477	}
1da177e4	478
185f3b9d	479	#ifdef CONFIG_X86_32
65eb6b43	480	static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
1da177e4	481	{
65eb6b43 PC	482	/*
65eb6b43 PC	483	* Intel PIII Tualatin. This comes in two flavours.
1da177e4 LT	484	* One has 256kb of cache, the other 512. We have no way
	485	* to determine which, so we use a boottime override
	486	* for the 512kb model, and assume 256 otherwise.
	487	*/
	488	if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
	489	size = 256;
	490	return size;
	491	}
185f3b9d	492	#endif
1da177e4	493
02dde8b4	494	static const struct cpu_dev __cpuinitconst intel_cpu_dev = {
1da177e4	495	.c_vendor = "Intel",
65eb6b43	496	.c_ident = { "GenuineIntel" },
185f3b9d	497	#ifdef CONFIG_X86_32
1da177e4	498	.c_models = {
65eb6b43 PC	499	{ .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
	500	{
	501	[0] = "486 DX-25/33",
	502	[1] = "486 DX-50",
	503	[2] = "486 SX",
	504	[3] = "486 DX/2",
	505	[4] = "486 SL",
	506	[5] = "486 SX/2",
	507	[7] = "486 DX/2-WB",
	508	[8] = "486 DX/4",
1da177e4 LT	509	[9] = "486 DX/4-WB"
	510	}
	511	},
	512	{ .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
65eb6b43 PC	513	{
	514	[0] = "Pentium 60/66 A-step",
	515	[1] = "Pentium 60/66",
1da177e4	516	[2] = "Pentium 75 - 200",
65eb6b43	517	[3] = "OverDrive PODP5V83",
1da177e4	518	[4] = "Pentium MMX",
65eb6b43	519	[7] = "Mobile Pentium 75 - 200",
1da177e4 LT	520	[8] = "Mobile Pentium MMX"
	521	}
	522	},
	523	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
65eb6b43	524	{
1da177e4	525	[0] = "Pentium Pro A-step",
65eb6b43 PC	526	[1] = "Pentium Pro",
	527	[3] = "Pentium II (Klamath)",
	528	[4] = "Pentium II (Deschutes)",
	529	[5] = "Pentium II (Deschutes)",
1da177e4	530	[6] = "Mobile Pentium II",
65eb6b43 PC	531	[7] = "Pentium III (Katmai)",
65eb6b43 PC	532	[8] = "Pentium III (Coppermine)",
1da177e4 LT	533	[10] = "Pentium III (Cascades)",
	534	[11] = "Pentium III (Tualatin)",
	535	}
	536	},
	537	{ .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
	538	{
	539	[0] = "Pentium 4 (Unknown)",
	540	[1] = "Pentium 4 (Willamette)",
	541	[2] = "Pentium 4 (Northwood)",
	542	[4] = "Pentium 4 (Foster)",
	543	[5] = "Pentium 4 (Foster)",
	544	}
	545	},
	546	},
185f3b9d YL	547	.c_size_cache = intel_size_cache,
185f3b9d YL	548	#endif
03ae5768	549	.c_early_init = early_init_intel,
1da177e4	550	.c_init = init_intel,
10a434fc	551	.c_x86_vendor = X86_VENDOR_INTEL,
1da177e4 LT	552	};
1da177e4 LT	553
10a434fc	554	cpu_dev_register(intel_cpu_dev);
1da177e4	555