[mirror_ubuntu-artful-kernel.git] / arch / x86 / kernel / cpu / intel.c

#include <linux/init.h>
#include <linux/kernel.h>

#include <linux/string.h>
#include <linux/bitops.h>
#include <linux/smp.h>
#include <linux/thread_info.h>
#include <linux/module.h>

#include <asm/processor.h>
#include <asm/pgtable.h>
#include <asm/msr.h>
#include <asm/uaccess.h>
#include <asm/ptrace.h>
#include <asm/ds.h>
#include <asm/bugs.h>

#include "cpu.h"

#ifdef CONFIG_X86_LOCAL_APIC
#include <asm/mpspec.h>
#include <asm/apic.h>
#include <mach_apic.h>
#endif

static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
{
	/* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
	if (c->x86 == 15 && c->x86_cache_alignment == 64)
		c->x86_cache_alignment = 128;
	if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
		(c->x86 == 0x6 && c->x86_model >= 0x0e))
		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
}

/*
 *	Early probe support logic for ppro memory erratum #50
 *
 *	This is called before we do cpu ident work
 */

int __cpuinit ppro_with_ram_bug(void)
{
	/* Uses data from early_cpu_detect now */
	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
	    boot_cpu_data.x86 == 6 &&
	    boot_cpu_data.x86_model == 1 &&
	    boot_cpu_data.x86_mask < 8) {
		printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
		return 1;
	}
	return 0;
}


/*
 * P4 Xeon errata 037 workaround.
 * Hardware prefetcher may cause stale data to be loaded into the cache.
 */
static void __cpuinit Intel_errata_workarounds(struct cpuinfo_x86 *c)
{
	unsigned long lo, hi;

	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
		rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
		if ((lo & (1<<9)) == 0) {
			printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
			printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
			lo |= (1<<9);	/* Disable hw prefetching */
			wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
		}
	}
}


/*
 * find out the number of processor cores on the die
 */
static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
{
	unsigned int eax, ebx, ecx, edx;

	if (c->cpuid_level < 4)
		return 1;

	/* Intel has a non-standard dependency on %ecx for this CPUID level. */
	cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
	if (eax & 0x1f)
		return ((eax >> 26) + 1);
	else
		return 1;
}

#ifdef CONFIG_X86_F00F_BUG
static void __cpuinit trap_init_f00f_bug(void)
{
	__set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);

	/*
	 * Update the IDT descriptor and reload the IDT so that
	 * it uses the read-only mapped virtual address.
	 */
	idt_descr.address = fix_to_virt(FIX_F00F_IDT);
	load_idt(&idt_descr);
}
#endif

static void __cpuinit init_intel(struct cpuinfo_x86 *c)
{
	unsigned int l2 = 0;
	char *p = NULL;

	early_init_intel(c);

#ifdef CONFIG_X86_F00F_BUG
	/*
	 * All current models of Pentium and Pentium with MMX technology CPUs
	 * have the F0 0F bug, which lets nonprivileged users lock up the system.
	 * Note that the workaround only should be initialized once...
	 */
	c->f00f_bug = 0;
	if (!paravirt_enabled() && c->x86 == 5) {
		static int f00f_workaround_enabled;

		c->f00f_bug = 1;
		if (!f00f_workaround_enabled) {
			trap_init_f00f_bug();
			printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
			f00f_workaround_enabled = 1;
		}
	}
#endif

	l2 = init_intel_cacheinfo(c);
	if (c->cpuid_level > 9) {
		unsigned eax = cpuid_eax(10);
		/* Check for version and the number of counters */
		if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
			set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
	}

	/* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */
	if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
		clear_cpu_cap(c, X86_FEATURE_SEP);

	/*
	 * Names for the Pentium II/Celeron processors
	 * detectable only by also checking the cache size.
	 * Dixon is NOT a Celeron.
	 */
	if (c->x86 == 6) {
		switch (c->x86_model) {
		case 5:
			if (c->x86_mask == 0) {
				if (l2 == 0)
					p = "Celeron (Covington)";
				else if (l2 == 256)
					p = "Mobile Pentium II (Dixon)";
			}
			break;

		case 6:
			if (l2 == 128)
				p = "Celeron (Mendocino)";
			else if (c->x86_mask == 0 || c->x86_mask == 5)
				p = "Celeron-A";
			break;

		case 8:
			if (l2 == 128)
				p = "Celeron (Coppermine)";
			break;
		}
	}

	if (p)
		strcpy(c->x86_model_id, p);

	detect_extended_topology(c);

	if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
		/*
		 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
		 * detection.
		 */
		c->x86_max_cores = intel_num_cpu_cores(c);
		detect_ht(c);
	}

	/* Work around errata */
	Intel_errata_workarounds(c);

#ifdef CONFIG_X86_INTEL_USERCOPY
	/*
	 * Set up the preferred alignment for movsl bulk memory moves
	 */
	switch (c->x86) {
	case 4:		/* 486: untested */
		break;
	case 5:		/* Old Pentia: untested */
		break;
	case 6:		/* PII/PIII only like movsl with 8-byte alignment */
		movsl_mask.mask = 7;
		break;
	case 15:	/* P4 is OK down to 8-byte alignment */
		movsl_mask.mask = 7;
		break;
	}
#endif

	if (cpu_has_xmm2)
		set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
	if (c->x86 == 15)
		set_cpu_cap(c, X86_FEATURE_P4);
	if (c->x86 == 6)
		set_cpu_cap(c, X86_FEATURE_P3);
	if (cpu_has_ds) {
		unsigned int l1;
		rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
		if (!(l1 & (1<<11)))
			set_cpu_cap(c, X86_FEATURE_BTS);
		if (!(l1 & (1<<12)))
			set_cpu_cap(c, X86_FEATURE_PEBS);
		ds_init_intel(c);
	}

	if (cpu_has_bts)
		ptrace_bts_init_intel(c);

	/*
	 * See if we have a good local APIC by checking for buggy Pentia,
	 * i.e. all B steppings and the C2 stepping of P54C when using their
	 * integrated APIC (see 11AP erratum in "Pentium Processor
	 * Specification Update").
	 */
	if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
	    (c->x86_mask < 0x6 || c->x86_mask == 0xb))
		set_cpu_cap(c, X86_FEATURE_11AP);

#ifdef CONFIG_X86_NUMAQ
	numaq_tsc_disable();
#endif
}

static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
{
	/*
	 * Intel PIII Tualatin. This comes in two flavours.
	 * One has 256kb of cache, the other 512. We have no way
	 * to determine which, so we use a boottime override
	 * for the 512kb model, and assume 256 otherwise.
	 */
	if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
		size = 256;
	return size;
}

static struct cpu_dev intel_cpu_dev __cpuinitdata = {
	.c_vendor	= "Intel",
	.c_ident	= { "GenuineIntel" },
	.c_models = {
		{ .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
		  {
			  [0] = "486 DX-25/33",
			  [1] = "486 DX-50",
			  [2] = "486 SX",
			  [3] = "486 DX/2",
			  [4] = "486 SL",
			  [5] = "486 SX/2",
			  [7] = "486 DX/2-WB",
			  [8] = "486 DX/4",
			  [9] = "486 DX/4-WB"
		  }
		},
		{ .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
		  {
			  [0] = "Pentium 60/66 A-step",
			  [1] = "Pentium 60/66",
			  [2] = "Pentium 75 - 200",
			  [3] = "OverDrive PODP5V83",
			  [4] = "Pentium MMX",
			  [7] = "Mobile Pentium 75 - 200",
			  [8] = "Mobile Pentium MMX"
		  }
		},
		{ .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
		  {
			  [0] = "Pentium Pro A-step",
			  [1] = "Pentium Pro",
			  [3] = "Pentium II (Klamath)",
			  [4] = "Pentium II (Deschutes)",
			  [5] = "Pentium II (Deschutes)",
			  [6] = "Mobile Pentium II",
			  [7] = "Pentium III (Katmai)",
			  [8] = "Pentium III (Coppermine)",
			  [10] = "Pentium III (Cascades)",
			  [11] = "Pentium III (Tualatin)",
		  }
		},
		{ .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
		  {
			  [0] = "Pentium 4 (Unknown)",
			  [1] = "Pentium 4 (Willamette)",
			  [2] = "Pentium 4 (Northwood)",
			  [4] = "Pentium 4 (Foster)",
			  [5] = "Pentium 4 (Foster)",
		  }
		},
	},
	.c_early_init   = early_init_intel,
	.c_init		= init_intel,
	.c_size_cache	= intel_size_cache,
	.c_x86_vendor	= X86_VENDOR_INTEL,
};

cpu_dev_register(intel_cpu_dev);

/* arch_initcall(intel_cpu_init); */
Commit	Line	Data
1da177e4 LT	1	#include <linux/init.h>
	2	#include <linux/kernel.h>
	3
	4	#include <linux/string.h>
	5	#include <linux/bitops.h>
	6	#include <linux/smp.h>
	7	#include <linux/thread_info.h>
53e86b91	8	#include <linux/module.h>
1da177e4 LT	9
1da177e4 LT	10	#include <asm/processor.h>
d72b1b4f	11	#include <asm/pgtable.h>
1da177e4 LT	12	#include <asm/msr.h>
1da177e4 LT	13	#include <asm/uaccess.h>
eee3af4a MM	14	#include <asm/ptrace.h>
eee3af4a MM	15	#include <asm/ds.h>
73bdb73f	16	#include <asm/bugs.h>
1da177e4 LT	17
	18	#include "cpu.h"
	19
	20	#ifdef CONFIG_X86_LOCAL_APIC
	21	#include <asm/mpspec.h>
	22	#include <asm/apic.h>
	23	#include <mach_apic.h>
	24	#endif
	25
03ae5768	26	static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
1da177e4	27	{
1da177e4 LT	28	/* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
	29	if (c->x86 == 15 && c->x86_cache_alignment == 64)
	30	c->x86_cache_alignment = 128;
2b16a235 AK	31	if ((c->x86 == 0xf && c->x86_model >= 0x03) \|\|
	32	(c->x86 == 0x6 && c->x86_model >= 0x0e))
	33	set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
1da177e4 LT	34	}
	35
	36	/*
	37	* Early probe support logic for ppro memory erratum #50
	38	*
	39	* This is called before we do cpu ident work
	40	*/
65eb6b43	41
3bc9b76b	42	int __cpuinit ppro_with_ram_bug(void)
1da177e4 LT	43	{
	44	/* Uses data from early_cpu_detect now */
	45	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
	46	boot_cpu_data.x86 == 6 &&
	47	boot_cpu_data.x86_model == 1 &&
	48	boot_cpu_data.x86_mask < 8) {
	49	printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
	50	return 1;
	51	}
	52	return 0;
	53	}
65eb6b43	54
1da177e4 LT	55
	56	/*
	57	* P4 Xeon errata 037 workaround.
	58	* Hardware prefetcher may cause stale data to be loaded into the cache.
	59	*/
3bc9b76b	60	static void __cpuinit Intel_errata_workarounds(struct cpuinfo_x86 *c)
1da177e4 LT	61	{
	62	unsigned long lo, hi;
	63
	64	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
65eb6b43	65	rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
1da177e4 LT	66	if ((lo & (1<<9)) == 0) {
	67	printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
	68	printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
	69	lo \|= (1<<9); /* Disable hw prefetching */
	70	wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
	71	}
	72	}
	73	}
	74
	75
3dd9d514 AK	76	/*
	77	* find out the number of processor cores on the die
	78	*/
f69feff7	79	static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
3dd9d514	80	{
f2ab4461	81	unsigned int eax, ebx, ecx, edx;
3dd9d514 AK	82
	83	if (c->cpuid_level < 4)
	84	return 1;
	85
f2ab4461 ZA	86	/* Intel has a non-standard dependency on %ecx for this CPUID level. */
f2ab4461 ZA	87	cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
3dd9d514 AK	88	if (eax & 0x1f)
	89	return ((eax >> 26) + 1);
	90	else
	91	return 1;
	92	}
	93
d72b1b4f SR	94	#ifdef CONFIG_X86_F00F_BUG
	95	static void __cpuinit trap_init_f00f_bug(void)
	96	{
	97	__set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
	98
	99	/*
	100	* Update the IDT descriptor and reload the IDT so that
	101	* it uses the read-only mapped virtual address.
	102	*/
	103	idt_descr.address = fix_to_virt(FIX_F00F_IDT);
	104	load_idt(&idt_descr);
	105	}
	106	#endif
	107
3bc9b76b	108	static void __cpuinit init_intel(struct cpuinfo_x86 *c)
1da177e4 LT	109	{
	110	unsigned int l2 = 0;
	111	char *p = NULL;
	112
2b16a235 AK	113	early_init_intel(c);
2b16a235 AK	114
1da177e4 LT	115	#ifdef CONFIG_X86_F00F_BUG
	116	/*
	117	* All current models of Pentium and Pentium with MMX technology CPUs
	118	* have the F0 0F bug, which lets nonprivileged users lock up the system.
	119	* Note that the workaround only should be initialized once...
	120	*/
	121	c->f00f_bug = 0;
4f205fd4	122	if (!paravirt_enabled() && c->x86 == 5) {
65eb6b43	123	static int f00f_workaround_enabled;
1da177e4 LT	124
1da177e4 LT	125	c->f00f_bug = 1;
65eb6b43	126	if (!f00f_workaround_enabled) {
1da177e4 LT	127	trap_init_f00f_bug();
	128	printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
	129	f00f_workaround_enabled = 1;
	130	}
	131	}
	132	#endif
	133
1da177e4	134	l2 = init_intel_cacheinfo(c);
65eb6b43	135	if (c->cpuid_level > 9) {
0080e667 VP	136	unsigned eax = cpuid_eax(10);
	137	/* Check for version and the number of counters */
	138	if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
d0e95ebd	139	set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
0080e667	140	}
1da177e4 LT	141
	142	/* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */
	143	if ((c->x86<<8 \| c->x86_model<<4 \| c->x86_mask) < 0x633)
d0e95ebd	144	clear_cpu_cap(c, X86_FEATURE_SEP);
1da177e4	145
65eb6b43 PC	146	/*
	147	* Names for the Pentium II/Celeron processors
	148	* detectable only by also checking the cache size.
	149	* Dixon is NOT a Celeron.
	150	*/
1da177e4 LT	151	if (c->x86 == 6) {
	152	switch (c->x86_model) {
	153	case 5:
	154	if (c->x86_mask == 0) {
	155	if (l2 == 0)
	156	p = "Celeron (Covington)";
	157	else if (l2 == 256)
	158	p = "Mobile Pentium II (Dixon)";
	159	}
	160	break;
65eb6b43	161
1da177e4 LT	162	case 6:
	163	if (l2 == 128)
	164	p = "Celeron (Mendocino)";
	165	else if (c->x86_mask == 0 \|\| c->x86_mask == 5)
	166	p = "Celeron-A";
	167	break;
65eb6b43	168
1da177e4 LT	169	case 8:
	170	if (l2 == 128)
	171	p = "Celeron (Coppermine)";
	172	break;
	173	}
	174	}
	175
65eb6b43	176	if (p)
1da177e4	177	strcpy(c->x86_model_id, p);
65eb6b43	178
bbb65d2d SS	179	detect_extended_topology(c);
	180
	181	if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
	182	/*
	183	* let's use the legacy cpuid vector 0x1 and 0x4 for topology
	184	* detection.
	185	*/
f69feff7	186	c->x86_max_cores = intel_num_cpu_cores(c);
bbb65d2d SS	187	detect_ht(c);
bbb65d2d SS	188	}
1da177e4 LT	189
	190	/* Work around errata */
	191	Intel_errata_workarounds(c);
	192
	193	#ifdef CONFIG_X86_INTEL_USERCOPY
	194	/*
	195	* Set up the preferred alignment for movsl bulk memory moves
	196	*/
	197	switch (c->x86) {
	198	case 4: /* 486: untested */
	199	break;
	200	case 5: /* Old Pentia: untested */
	201	break;
	202	case 6: /* PII/PIII only like movsl with 8-byte alignment */
	203	movsl_mask.mask = 7;
	204	break;
	205	case 15: /* P4 is OK down to 8-byte alignment */
	206	movsl_mask.mask = 7;
	207	break;
	208	}
	209	#endif
	210
6d5f718a	211	if (cpu_has_xmm2)
d0e95ebd	212	set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
f69feff7	213	if (c->x86 == 15)
d0e95ebd	214	set_cpu_cap(c, X86_FEATURE_P4);
65eb6b43	215	if (c->x86 == 6)
d0e95ebd	216	set_cpu_cap(c, X86_FEATURE_P3);
42ed458a SE	217	if (cpu_has_ds) {
	218	unsigned int l1;
	219	rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
538f188e	220	if (!(l1 & (1<<11)))
d0e95ebd	221	set_cpu_cap(c, X86_FEATURE_BTS);
42ed458a	222	if (!(l1 & (1<<12)))
d0e95ebd	223	set_cpu_cap(c, X86_FEATURE_PEBS);
93fa7636	224	ds_init_intel(c);
42ed458a	225	}
eee3af4a MM	226
eee3af4a MM	227	if (cpu_has_bts)
93fa7636	228	ptrace_bts_init_intel(c);
3d88cca7	229
593f4a78 MR	230	/*
	231	* See if we have a good local APIC by checking for buggy Pentia,
	232	* i.e. all B steppings and the C2 stepping of P54C when using their
	233	* integrated APIC (see 11AP erratum in "Pentium Processor
	234	* Specification Update").
	235	*/
	236	if (cpu_has_apic && (c->x86<<8 \| c->x86_model<<4) == 0x520 &&
	237	(c->x86_mask < 0x6 \|\| c->x86_mask == 0xb))
	238	set_cpu_cap(c, X86_FEATURE_11AP);
	239
3d88cca7 YL	240	#ifdef CONFIG_X86_NUMAQ
	241	numaq_tsc_disable();
	242	#endif
42ed458a	243	}
1da177e4	244
65eb6b43	245	static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
1da177e4	246	{
65eb6b43 PC	247	/*
65eb6b43 PC	248	* Intel PIII Tualatin. This comes in two flavours.
1da177e4 LT	249	* One has 256kb of cache, the other 512. We have no way
	250	* to determine which, so we use a boottime override
	251	* for the 512kb model, and assume 256 otherwise.
	252	*/
	253	if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
	254	size = 256;
	255	return size;
	256	}
	257
3bc9b76b	258	static struct cpu_dev intel_cpu_dev __cpuinitdata = {
1da177e4	259	.c_vendor = "Intel",
65eb6b43	260	.c_ident = { "GenuineIntel" },
1da177e4	261	.c_models = {
65eb6b43 PC	262	{ .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
	263	{
	264	[0] = "486 DX-25/33",
	265	[1] = "486 DX-50",
	266	[2] = "486 SX",
	267	[3] = "486 DX/2",
	268	[4] = "486 SL",
	269	[5] = "486 SX/2",
	270	[7] = "486 DX/2-WB",
	271	[8] = "486 DX/4",
1da177e4 LT	272	[9] = "486 DX/4-WB"
	273	}
	274	},
	275	{ .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
65eb6b43 PC	276	{
	277	[0] = "Pentium 60/66 A-step",
	278	[1] = "Pentium 60/66",
1da177e4	279	[2] = "Pentium 75 - 200",
65eb6b43	280	[3] = "OverDrive PODP5V83",
1da177e4	281	[4] = "Pentium MMX",
65eb6b43	282	[7] = "Mobile Pentium 75 - 200",
1da177e4 LT	283	[8] = "Mobile Pentium MMX"
	284	}
	285	},
	286	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
65eb6b43	287	{
1da177e4	288	[0] = "Pentium Pro A-step",
65eb6b43 PC	289	[1] = "Pentium Pro",
	290	[3] = "Pentium II (Klamath)",
	291	[4] = "Pentium II (Deschutes)",
	292	[5] = "Pentium II (Deschutes)",
1da177e4	293	[6] = "Mobile Pentium II",
65eb6b43 PC	294	[7] = "Pentium III (Katmai)",
65eb6b43 PC	295	[8] = "Pentium III (Coppermine)",
1da177e4 LT	296	[10] = "Pentium III (Cascades)",
	297	[11] = "Pentium III (Tualatin)",
	298	}
	299	},
	300	{ .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
	301	{
	302	[0] = "Pentium 4 (Unknown)",
	303	[1] = "Pentium 4 (Willamette)",
	304	[2] = "Pentium 4 (Northwood)",
	305	[4] = "Pentium 4 (Foster)",
	306	[5] = "Pentium 4 (Foster)",
	307	}
	308	},
	309	},
03ae5768	310	.c_early_init = early_init_intel,
1da177e4	311	.c_init = init_intel,
1da177e4	312	.c_size_cache = intel_size_cache,
10a434fc	313	.c_x86_vendor = X86_VENDOR_INTEL,
1da177e4 LT	314	};
1da177e4 LT	315
10a434fc	316	cpu_dev_register(intel_cpu_dev);
1da177e4	317
65eb6b43	318	/* arch_initcall(intel_cpu_init); */
1da177e4	319