]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | #include <linux/init.h> |
2 | #include <linux/kernel.h> | |
3 | ||
4 | #include <linux/string.h> | |
5 | #include <linux/bitops.h> | |
6 | #include <linux/smp.h> | |
7 | #include <linux/thread_info.h> | |
53e86b91 | 8 | #include <linux/module.h> |
1da177e4 LT |
9 | |
10 | #include <asm/processor.h> | |
d72b1b4f | 11 | #include <asm/pgtable.h> |
1da177e4 LT |
12 | #include <asm/msr.h> |
13 | #include <asm/uaccess.h> | |
eee3af4a MM |
14 | #include <asm/ptrace.h> |
15 | #include <asm/ds.h> | |
73bdb73f | 16 | #include <asm/bugs.h> |
1da177e4 | 17 | |
185f3b9d YL |
18 | #ifdef CONFIG_X86_64 |
19 | #include <asm/topology.h> | |
20 | #include <asm/numa_64.h> | |
21 | #endif | |
22 | ||
1da177e4 LT |
23 | #include "cpu.h" |
24 | ||
25 | #ifdef CONFIG_X86_LOCAL_APIC | |
26 | #include <asm/mpspec.h> | |
27 | #include <asm/apic.h> | |
28 | #include <mach_apic.h> | |
29 | #endif | |
30 | ||
03ae5768 | 31 | static void __cpuinit early_init_intel(struct cpuinfo_x86 *c) |
1da177e4 | 32 | { |
2b16a235 AK |
33 | if ((c->x86 == 0xf && c->x86_model >= 0x03) || |
34 | (c->x86 == 0x6 && c->x86_model >= 0x0e)) | |
35 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); | |
185f3b9d YL |
36 | |
37 | #ifdef CONFIG_X86_64 | |
38 | set_cpu_cap(c, X86_FEATURE_SYSENTER32); | |
39 | #else | |
40 | /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ | |
41 | if (c->x86 == 15 && c->x86_cache_alignment == 64) | |
42 | c->x86_cache_alignment = 128; | |
43 | #endif | |
1da177e4 LT |
44 | } |
45 | ||
185f3b9d | 46 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
47 | /* |
48 | * Early probe support logic for ppro memory erratum #50 | |
49 | * | |
50 | * This is called before we do cpu ident work | |
51 | */ | |
65eb6b43 | 52 | |
3bc9b76b | 53 | int __cpuinit ppro_with_ram_bug(void) |
1da177e4 LT |
54 | { |
55 | /* Uses data from early_cpu_detect now */ | |
56 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
57 | boot_cpu_data.x86 == 6 && | |
58 | boot_cpu_data.x86_model == 1 && | |
59 | boot_cpu_data.x86_mask < 8) { | |
60 | printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n"); | |
61 | return 1; | |
62 | } | |
63 | return 0; | |
64 | } | |
65eb6b43 | 65 | |
1da177e4 LT |
66 | |
67 | /* | |
68 | * P4 Xeon errata 037 workaround. | |
69 | * Hardware prefetcher may cause stale data to be loaded into the cache. | |
70 | */ | |
3bc9b76b | 71 | static void __cpuinit Intel_errata_workarounds(struct cpuinfo_x86 *c) |
1da177e4 LT |
72 | { |
73 | unsigned long lo, hi; | |
74 | ||
75 | if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) { | |
65eb6b43 | 76 | rdmsr(MSR_IA32_MISC_ENABLE, lo, hi); |
1da177e4 LT |
77 | if ((lo & (1<<9)) == 0) { |
78 | printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n"); | |
79 | printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n"); | |
80 | lo |= (1<<9); /* Disable hw prefetching */ | |
81 | wrmsr (MSR_IA32_MISC_ENABLE, lo, hi); | |
82 | } | |
83 | } | |
84 | } | |
85 | ||
86 | ||
185f3b9d YL |
87 | |
88 | #ifdef CONFIG_X86_F00F_BUG | |
89 | static void __cpuinit trap_init_f00f_bug(void) | |
90 | { | |
91 | __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO); | |
92 | ||
93 | /* | |
94 | * Update the IDT descriptor and reload the IDT so that | |
95 | * it uses the read-only mapped virtual address. | |
96 | */ | |
97 | idt_descr.address = fix_to_virt(FIX_F00F_IDT); | |
98 | load_idt(&idt_descr); | |
99 | } | |
100 | #endif | |
101 | #endif | |
102 | ||
103 | static void __cpuinit srat_detect_node(void) | |
104 | { | |
105 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) | |
106 | unsigned node; | |
107 | int cpu = smp_processor_id(); | |
108 | int apicid = hard_smp_processor_id(); | |
109 | ||
110 | /* Don't do the funky fallback heuristics the AMD version employs | |
111 | for now. */ | |
112 | node = apicid_to_node[apicid]; | |
113 | if (node == NUMA_NO_NODE || !node_online(node)) | |
114 | node = first_node(node_online_map); | |
115 | numa_set_node(cpu, node); | |
116 | ||
117 | printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node); | |
118 | #endif | |
119 | } | |
120 | ||
3dd9d514 AK |
121 | /* |
122 | * find out the number of processor cores on the die | |
123 | */ | |
f69feff7 | 124 | static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c) |
3dd9d514 | 125 | { |
f2ab4461 | 126 | unsigned int eax, ebx, ecx, edx; |
3dd9d514 AK |
127 | |
128 | if (c->cpuid_level < 4) | |
129 | return 1; | |
130 | ||
f2ab4461 ZA |
131 | /* Intel has a non-standard dependency on %ecx for this CPUID level. */ |
132 | cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); | |
3dd9d514 AK |
133 | if (eax & 0x1f) |
134 | return ((eax >> 26) + 1); | |
135 | else | |
136 | return 1; | |
137 | } | |
138 | ||
3bc9b76b | 139 | static void __cpuinit init_intel(struct cpuinfo_x86 *c) |
1da177e4 LT |
140 | { |
141 | unsigned int l2 = 0; | |
142 | char *p = NULL; | |
143 | ||
2b16a235 AK |
144 | early_init_intel(c); |
145 | ||
1da177e4 LT |
146 | #ifdef CONFIG_X86_F00F_BUG |
147 | /* | |
148 | * All current models of Pentium and Pentium with MMX technology CPUs | |
149 | * have the F0 0F bug, which lets nonprivileged users lock up the system. | |
150 | * Note that the workaround only should be initialized once... | |
151 | */ | |
152 | c->f00f_bug = 0; | |
4f205fd4 | 153 | if (!paravirt_enabled() && c->x86 == 5) { |
65eb6b43 | 154 | static int f00f_workaround_enabled; |
1da177e4 LT |
155 | |
156 | c->f00f_bug = 1; | |
65eb6b43 | 157 | if (!f00f_workaround_enabled) { |
1da177e4 LT |
158 | trap_init_f00f_bug(); |
159 | printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n"); | |
160 | f00f_workaround_enabled = 1; | |
161 | } | |
162 | } | |
163 | #endif | |
164 | ||
1da177e4 | 165 | l2 = init_intel_cacheinfo(c); |
65eb6b43 | 166 | if (c->cpuid_level > 9) { |
0080e667 VP |
167 | unsigned eax = cpuid_eax(10); |
168 | /* Check for version and the number of counters */ | |
169 | if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) | |
d0e95ebd | 170 | set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); |
0080e667 | 171 | } |
1da177e4 | 172 | |
185f3b9d | 173 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
174 | /* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */ |
175 | if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633) | |
d0e95ebd | 176 | clear_cpu_cap(c, X86_FEATURE_SEP); |
1da177e4 | 177 | |
65eb6b43 PC |
178 | /* |
179 | * Names for the Pentium II/Celeron processors | |
180 | * detectable only by also checking the cache size. | |
181 | * Dixon is NOT a Celeron. | |
182 | */ | |
1da177e4 LT |
183 | if (c->x86 == 6) { |
184 | switch (c->x86_model) { | |
185 | case 5: | |
186 | if (c->x86_mask == 0) { | |
187 | if (l2 == 0) | |
188 | p = "Celeron (Covington)"; | |
189 | else if (l2 == 256) | |
190 | p = "Mobile Pentium II (Dixon)"; | |
191 | } | |
192 | break; | |
65eb6b43 | 193 | |
1da177e4 LT |
194 | case 6: |
195 | if (l2 == 128) | |
196 | p = "Celeron (Mendocino)"; | |
197 | else if (c->x86_mask == 0 || c->x86_mask == 5) | |
198 | p = "Celeron-A"; | |
199 | break; | |
65eb6b43 | 200 | |
1da177e4 LT |
201 | case 8: |
202 | if (l2 == 128) | |
203 | p = "Celeron (Coppermine)"; | |
204 | break; | |
205 | } | |
206 | } | |
207 | ||
65eb6b43 | 208 | if (p) |
1da177e4 | 209 | strcpy(c->x86_model_id, p); |
65eb6b43 | 210 | |
1da177e4 LT |
211 | Intel_errata_workarounds(c); |
212 | ||
213 | #ifdef CONFIG_X86_INTEL_USERCOPY | |
214 | /* | |
215 | * Set up the preferred alignment for movsl bulk memory moves | |
216 | */ | |
217 | switch (c->x86) { | |
218 | case 4: /* 486: untested */ | |
219 | break; | |
220 | case 5: /* Old Pentia: untested */ | |
221 | break; | |
222 | case 6: /* PII/PIII only like movsl with 8-byte alignment */ | |
223 | movsl_mask.mask = 7; | |
224 | break; | |
225 | case 15: /* P4 is OK down to 8-byte alignment */ | |
226 | movsl_mask.mask = 7; | |
227 | break; | |
228 | } | |
185f3b9d YL |
229 | #endif |
230 | ||
1da177e4 LT |
231 | #endif |
232 | ||
6d5f718a | 233 | if (cpu_has_xmm2) |
d0e95ebd | 234 | set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); |
42ed458a SE |
235 | if (cpu_has_ds) { |
236 | unsigned int l1; | |
237 | rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); | |
538f188e | 238 | if (!(l1 & (1<<11))) |
d0e95ebd | 239 | set_cpu_cap(c, X86_FEATURE_BTS); |
42ed458a | 240 | if (!(l1 & (1<<12))) |
d0e95ebd | 241 | set_cpu_cap(c, X86_FEATURE_PEBS); |
93fa7636 | 242 | ds_init_intel(c); |
42ed458a | 243 | } |
eee3af4a | 244 | |
185f3b9d YL |
245 | #ifdef CONFIG_X86_64 |
246 | if (c->x86 == 15) | |
247 | c->x86_cache_alignment = c->x86_clflush_size * 2; | |
248 | if (c->x86 == 6) | |
249 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); | |
250 | #else | |
251 | if (c->x86 == 15) | |
252 | set_cpu_cap(c, X86_FEATURE_P4); | |
253 | if (c->x86 == 6) | |
254 | set_cpu_cap(c, X86_FEATURE_P3); | |
255 | ||
eee3af4a | 256 | if (cpu_has_bts) |
93fa7636 | 257 | ptrace_bts_init_intel(c); |
3d88cca7 | 258 | |
593f4a78 MR |
259 | /* |
260 | * See if we have a good local APIC by checking for buggy Pentia, | |
261 | * i.e. all B steppings and the C2 stepping of P54C when using their | |
262 | * integrated APIC (see 11AP erratum in "Pentium Processor | |
263 | * Specification Update"). | |
264 | */ | |
265 | if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 && | |
266 | (c->x86_mask < 0x6 || c->x86_mask == 0xb)) | |
267 | set_cpu_cap(c, X86_FEATURE_11AP); | |
268 | ||
3d88cca7 YL |
269 | #ifdef CONFIG_X86_NUMAQ |
270 | numaq_tsc_disable(); | |
271 | #endif | |
185f3b9d YL |
272 | #endif |
273 | ||
274 | detect_extended_topology(c); | |
275 | if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) { | |
276 | /* | |
277 | * let's use the legacy cpuid vector 0x1 and 0x4 for topology | |
278 | * detection. | |
279 | */ | |
280 | c->x86_max_cores = intel_num_cpu_cores(c); | |
281 | #ifdef CONFIG_X86_32 | |
282 | detect_ht(c); | |
283 | #endif | |
284 | } | |
285 | ||
286 | /* Work around errata */ | |
287 | srat_detect_node(); | |
42ed458a | 288 | } |
1da177e4 | 289 | |
185f3b9d | 290 | #ifdef CONFIG_X86_32 |
65eb6b43 | 291 | static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) |
1da177e4 | 292 | { |
65eb6b43 PC |
293 | /* |
294 | * Intel PIII Tualatin. This comes in two flavours. | |
1da177e4 LT |
295 | * One has 256kb of cache, the other 512. We have no way |
296 | * to determine which, so we use a boottime override | |
297 | * for the 512kb model, and assume 256 otherwise. | |
298 | */ | |
299 | if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) | |
300 | size = 256; | |
301 | return size; | |
302 | } | |
185f3b9d | 303 | #endif |
1da177e4 | 304 | |
3bc9b76b | 305 | static struct cpu_dev intel_cpu_dev __cpuinitdata = { |
1da177e4 | 306 | .c_vendor = "Intel", |
65eb6b43 | 307 | .c_ident = { "GenuineIntel" }, |
185f3b9d | 308 | #ifdef CONFIG_X86_32 |
1da177e4 | 309 | .c_models = { |
65eb6b43 PC |
310 | { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names = |
311 | { | |
312 | [0] = "486 DX-25/33", | |
313 | [1] = "486 DX-50", | |
314 | [2] = "486 SX", | |
315 | [3] = "486 DX/2", | |
316 | [4] = "486 SL", | |
317 | [5] = "486 SX/2", | |
318 | [7] = "486 DX/2-WB", | |
319 | [8] = "486 DX/4", | |
1da177e4 LT |
320 | [9] = "486 DX/4-WB" |
321 | } | |
322 | }, | |
323 | { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names = | |
65eb6b43 PC |
324 | { |
325 | [0] = "Pentium 60/66 A-step", | |
326 | [1] = "Pentium 60/66", | |
1da177e4 | 327 | [2] = "Pentium 75 - 200", |
65eb6b43 | 328 | [3] = "OverDrive PODP5V83", |
1da177e4 | 329 | [4] = "Pentium MMX", |
65eb6b43 | 330 | [7] = "Mobile Pentium 75 - 200", |
1da177e4 LT |
331 | [8] = "Mobile Pentium MMX" |
332 | } | |
333 | }, | |
334 | { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names = | |
65eb6b43 | 335 | { |
1da177e4 | 336 | [0] = "Pentium Pro A-step", |
65eb6b43 PC |
337 | [1] = "Pentium Pro", |
338 | [3] = "Pentium II (Klamath)", | |
339 | [4] = "Pentium II (Deschutes)", | |
340 | [5] = "Pentium II (Deschutes)", | |
1da177e4 | 341 | [6] = "Mobile Pentium II", |
65eb6b43 PC |
342 | [7] = "Pentium III (Katmai)", |
343 | [8] = "Pentium III (Coppermine)", | |
1da177e4 LT |
344 | [10] = "Pentium III (Cascades)", |
345 | [11] = "Pentium III (Tualatin)", | |
346 | } | |
347 | }, | |
348 | { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names = | |
349 | { | |
350 | [0] = "Pentium 4 (Unknown)", | |
351 | [1] = "Pentium 4 (Willamette)", | |
352 | [2] = "Pentium 4 (Northwood)", | |
353 | [4] = "Pentium 4 (Foster)", | |
354 | [5] = "Pentium 4 (Foster)", | |
355 | } | |
356 | }, | |
357 | }, | |
185f3b9d YL |
358 | .c_size_cache = intel_size_cache, |
359 | #endif | |
03ae5768 | 360 | .c_early_init = early_init_intel, |
1da177e4 | 361 | .c_init = init_intel, |
10a434fc | 362 | .c_x86_vendor = X86_VENDOR_INTEL, |
1da177e4 LT |
363 | }; |
364 | ||
10a434fc | 365 | cpu_dev_register(intel_cpu_dev); |
1da177e4 | 366 |